WIP: device tree MVP

2026-11-13 19:11:37 +08:00 · 2022-01-06 17:20:17 -05:00
parent 07d75d85cf
commit 1f39b42525
1395 changed files with 68755 additions and 0 deletions
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+# SPDX-License-Identifier: Apache-2.0
+
+description: Cortex-M DTCM (Data Tightly Coupled Memory)
+
+compatible: "arm,dtcm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cortex-M ITCM (Instruction Tightly Coupled Memory)
+
+compatible: "arm,itcm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM Serial Configuration Control (SCC)
+
+compatible: "arm,scc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,52 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM SSC (Synchronous Serial Controller) controller
+
+compatible: "atmel,sam-ssc"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      description: |
+        PIO pin configuration for RF, RK, RD, TF, TK, & TD signals.
+        We expect that the phandles will reference pinctrl nodes.
+        These nodes will have a nodelabel that matches the Atmel SoC HAL
+        defines and be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the SSC on SAME7x would be
+           pinctrl-0 = <&pd24b_ssc_rf &pa22a_ssc_rk &pa10c_ssc_rd
+                        &pb0d_ssc_tf &pb1d_ssc_tk &pb5d_ssc_td>;
+
+      required: true
+
+    dmas:
+      required: true
+      description: |
+        TX & RX dma specifiers.  Each specifier will have a phandle
+        reference to the dma controller, the channel number, and peripheral
+        trigger source.
+
+        For example dmas for TX, RX would look like
+           dmas = <&xdmac 22 DMA_PERID_SSC_TX>, <&xdmac 23 DMA_PERID_SSC_RX>;
+
+    dma-names:
+      required: true
+      description: |
+        This should be "tx" and "rx" to match the dmas property.
+
+        For example
+           dma-names = "tx", "rx";
@@ -0,0 +1,10 @@
+description: |
+    For locating the Device ID (serial number) on Atmel SAM0 devices
+
+compatible: "atmel,sam0-id"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,15 @@
+description: Atmel SAM0 multi-protocol (UART, SPI, I2C) SERCOM unit
+
+compatible: "atmel,sam0-sercom"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
@@ -0,0 +1,19 @@
+# Copyright (c) 2020, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAMD2x Power Manger (PM)
+
+compatible: "atmel,samd2x-pm"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+clock-cells:
+  - offset
+  - bit
@@ -0,0 +1,13 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Nordic DPPIC (Distributed Programmable Peripheral Interconnect Controller)
+
+compatible: "nordic,nrf-dppic"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic EGU (Event Generator Unit)
+
+compatible: "nordic,nrf-egu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
@@ -0,0 +1,9 @@
+description: Nordic FICR (Factory Information Configuration Registers)
+
+compatible: "nordic,nrf-ficr"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,15 @@
+# Copyright (c) 2019 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic KMU (Key Management Unit)
+
+compatible: "nordic,nrf-kmu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
@@ -0,0 +1,12 @@
+description: Nordic SPU (System Protection Unit)
+
+compatible: "nordic,nrf-spu"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
@@ -0,0 +1,9 @@
+description: Nordic UICR (User Information Configuration Registers)
+
+compatible: "nordic,nrf-uicr"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX DTCM (Data Tightly Coupled Memory)
+
+compatible: "nxp,imx-dtcm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,28 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX Enhanced Periodic Interrupt Timer (EPIT)
+
+compatible: "nxp,imx-epit"
+
+include: base.yaml
+
+properties:
+  reg:
+      required: true
+
+  interrupts:
+      required: true
+
+  label:
+      required: true
+
+  prescaler:
+     type: int
+     required: true
+     description: Set the EPIT prescaler between 0 and 4095
+
+  rdc:
+     type: int
+     required: true
+     description: Set the RDC permission for this peripheral
@@ -0,0 +1,12 @@
+# Copyright (c) 2018, Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX ITCM (Instruction Tightly Coupled Memory)
+
+compatible: "nxp,imx-itcm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true
@@ -0,0 +1,23 @@
+# Copyright (c) 2018, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: i.MX Messaging Unit
+
+compatible: "nxp,imx-mu"
+
+include: base.yaml
+
+properties:
+  reg:
+      required: true
+
+  interrupts:
+      required: true
+
+  label:
+      required: true
+
+  rdc:
+     type: int
+     required: true
+     description: Set the RDC permission for this peripheral
@@ -0,0 +1,29 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis FTM
+
+compatible: "nxp,kinetis-ftm"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    prescaler:
+      type: int
+      required: true
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+        - 16
+        - 32
+        - 64
+        - 128
+      description: Input clock prescaler
@@ -0,0 +1,25 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis KE1xF System Integration Module (SIM) IP node
+
+compatible: "nxp,kinetis-ke1xf-sim"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    clkout-source:
+      type: int
+      required: false
+      description: clkout clock source
+
+    clkout-divider:
+      type: int
+      required: false
+      description: clkout divider
@@ -0,0 +1,21 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis Multipurpose Clock generator (MCG) IP node
+
+compatible: "nxp,kinetis-mcg"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - name
@@ -0,0 +1,22 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis PCC (Peripheral Clock Controller) IP node
+
+compatible: "nxp,kinetis-pcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    "#clock-cells":
+      const: 2
+
+clock-cells:
+  - name
+  - ip-source
@@ -0,0 +1,26 @@
+# Copyright (c) 2019-2021 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis SCG (System Clock Generator) IP node
+
+compatible: "nxp,kinetis-scg"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    sosc-mode:
+      type: int
+      description: system oscillator mode
+      required: false
+
+    "#clock-cells":
+      const: 1
+
+clock-cells:
+  - name
@@ -0,0 +1,45 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis System Integration Module (SIM) IP node
+
+compatible: "nxp,kinetis-sim"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    label:
+      required: true
+
+    pllfll-select:
+      type: int
+      required: true
+      description: pll/fll selection for clock system
+
+    er32k-select:
+      type: int
+      required: true
+      description: er32k selection for clock system
+
+    clkout-source:
+      type: int
+      required: false
+      description: clkout clock source
+
+    clkout-divider:
+      type: int
+      required: false
+      description: clkout divider
+
+    "#clock-cells":
+      type: int
+      required: false
+      const: 3
+
+clock-cells:
+  - name
+  - offset
+  - bits
@@ -0,0 +1,15 @@
+# Copyright (c) 2020 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: LPC Flexcomm node
+
+compatible: "nxp,lpc-flexcomm"
+
+include: base.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 CCM (Core Coupled Memory)
+
+compatible: "st,stm32-ccm"
+
+include: [base.yaml, mem-region.yaml]
+
+properties:
+    reg:
+      required: true