WIP: device tree MVP

2026-11-14 17:41:36 +08:00 · 2022-01-06 17:20:17 -05:00
parent 07d75d85cf
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+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for ADC controllers
+
+include: base.yaml
+
+properties:
+    label:
+      required: true
+
+    "#io-channel-cells":
+      type: int
+      required: true
@@ -0,0 +1,34 @@
+# Copyright (C) 2019 Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ADC channels exposed on Arduino Uno (R3) headers.
+
+    The Arduino Uno layout provides a 6-pin Analog Input header.  This
+    has analog input signals labeled from A0 at the top through A5 at
+    the bottom.
+
+    This binding provides a nexus mapping for these pins where parent
+    pins 0 through 5 correspond to A0 through A5.
+
+compatible: "arduino,uno-adc"
+
+include: base.yaml
+
+properties:
+    io-channel-map:
+      type: compound
+      required: true
+
+    io-channel-map-mask:
+      type: compound
+      required: false
+
+    io-channel-map-pass-thru:
+      type: compound
+      required: false
+
+    "#io-channel-cells":
+      type: int
+      required: true
+      description: Number of items to expect in an ADC specifier
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+description: Atmel SAM family AFEC
+
+compatible: "atmel,sam-afec"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    peripheral-id:
+      type: int
+      description: peripheral ID
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+    pinctrl-0:
+      type: phandles
+      required: true
+      description: |
+        PIO pin configuration for ADTRG signal.  We expect that
+        the phandles will reference pinctrl nodes.  These nodes will
+        have a nodelabel that matches the Atmel SoC HAL defines and
+        be of the form p<port><pin><periph>_<inst>_<signal>.
+
+        For example the I2C on SAME7x would be
+           pinctrl-0 = <&pa8b_afec0_adtrg>;
+
+io-channel-cells:
+    - input
@@ -0,0 +1,48 @@
+# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 family ADC
+
+compatible: "atmel,sam0-adc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clocks:
+      required: true
+
+    clock-names:
+      required: true
+
+    gclk:
+      type: int
+      required: true
+      description: generic clock generator source
+
+    prescaler:
+      type: int
+      required: true
+      description: clock prescaler divisor applied to the generic clock
+
+    "#io-channel-cells":
+      const: 1
+
+    calib-offset:
+      type: int
+      required: false
+      description: |
+        bit position offset in NVM SW Calib for start of ADC0 BIASCOMP field.
+        This property is expected to be set on SAM{D,E}5x family of SoCs.
+        For ADC0 this should be 0, and for ADC1 this should be 14.
+      enum:
+        - 0
+        - 14
+
+io-channel-cells:
+    - input
@@ -0,0 +1,16 @@
+# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE it8xxx2 ADC
+
+compatible: "ite,it8xxx2-adc"
+
+include: adc-controller.yaml
+
+properties:
+    interrupts:
+      required: true
+
+    pinctrl-0:
+      type: phandles
+      required: true
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+description: Microchip MCP3204
+
+compatible: "microchip,mcp3204"
+
+include: microchip,mcp320x-base.yaml
@@ -0,0 +1,5 @@
+description: Microchip MCP3208
+
+compatible: "microchip,mcp3208"
+
+include: microchip,mcp320x-base.yaml
@@ -0,0 +1,10 @@
+# Common fields for Microchip MCP3204/MCP3208
+
+include: [adc-controller.yaml, spi-device.yaml]
+
+properties:
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - channel
@@ -0,0 +1,48 @@
+# Copyright (c) 2019, Intel Corporation
+# Copyright (c) 2021, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC ADC
+
+compatible: "microchip,xec-adc-v2"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+    girqs:
+      type: array
+      required: true
+      description: Array of pairs of GIRQ number and bit position
+
+    pcrs:
+      type: array
+      required: true
+      description: ADC PCR register index and bit position
+
+    "#girq-cells":
+      type: int
+      const: 2
+
+    "#pcr-cells":
+      type: int
+      const: 2
+
+io-channel-cells:
+    - input
+
+girq-cells:
+    - girqnum
+    - bitpos
+
+pcr-cells:
+    - regidx
+    - bitpos
@@ -0,0 +1,26 @@
+# Copyright (c) 2019, Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip XEC ADC
+
+compatible: "microchip,xec-adc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+    clktime:
+      type: int
+      required: true
+      description: ADC clock high & low time count value <1:255>
+
+io-channel-cells:
+    - input
@@ -0,0 +1,21 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: nRF ADC node
+
+compatible: "nordic,nrf-adc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
@@ -0,0 +1,21 @@
+# Copyright (c) 2018, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic Semiconductor nRF family SAADC node
+
+compatible: "nordic,nrf-saadc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
@@ -0,0 +1,41 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP Kinetis ADC12
+
+compatible: "nxp,kinetis-adc12"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    clk-source:
+      type: int
+      required: true
+      description: converter clock source
+
+    clk-divider:
+      type: int
+      required: true
+      description: clock divider for the converter
+
+    alternate-voltage-reference:
+      type: boolean
+      required: false
+      description: use alternate voltage reference source
+
+    sample-time:
+      type: int
+      required: true
+      description: sample time in clock cycles
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
@@ -0,0 +1,63 @@
+# Copyright (c) 2017, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: Kinetis ADC16
+
+compatible: "nxp,kinetis-adc16"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    channel-mux-b:
+      type: boolean
+      required: false
+      description: |
+        Use alternate set (b instead of a) of ADC channels
+
+    interrupts:
+      required: true
+
+    periodic-trigger:
+      type: boolean
+      required: false
+      description: if periodic trigger enabled
+
+    "#io-channel-cells":
+      const: 1
+
+    clk-source:
+      type: int
+      required: false
+      description: use alternate clock reference source
+
+    long-sample:
+      type: int
+      required: false
+      enum:
+        - 0
+        - 1
+        - 2
+        - 3
+        - 4
+      description: long sample mode
+
+    continuous-convert:
+      type: boolean
+      required: false
+      description: If use continuous convert
+
+    high-speed:
+      type: boolean
+      required: false
+      description: If use high speed
+
+    hw-trigger-src:
+      type: int
+      required: false
+      description: hardware trigger source (See ADCxTRGSEL field in user manual for more details)
+
+io-channel-cells:
+    - input
@@ -0,0 +1,31 @@
+# Copyright (c) 2019 Vestas Wind Systems A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCUA 12B1MSPS SAR ADC
+
+compatible: "nxp,mcux-12b1msps-sar"
+
+include: adc-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clk-divider:
+    type: int
+    required: true
+    description: clock divider for the converter
+
+  sample-period-mode:
+    type: int
+    required: true
+    description: sample period mode
+
+  "#io-channel-cells":
+    const: 1
+
+io-channel-cells:
+  - input
@@ -0,0 +1,31 @@
+# Copyright (c) 2018, Endre Karlson
+# Copyright (c) 2018, Song Qiang <songqiang1304521@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST STM32 family ADC
+
+compatible: "st,stm32-adc"
+
+include: [adc-controller.yaml, pinctrl-device.yaml]
+
+properties:
+    reg:
+      required: true
+
+    clocks:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+    pinctrl-0:
+      required: true
+
+    pinctrl-names:
+      required: true
+
+io-channel-cells:
+    - input
@@ -0,0 +1,21 @@
+# Copyright (c) 2021 Pavlo Hamov <pasha.gamov@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: cc32xx ADC node
+
+compatible: "ti,cc32xx-adc"
+
+include: adc-controller.yaml
+
+properties:
+    reg:
+      required: true
+
+    interrupts:
+      required: true
+
+    "#io-channel-cells":
+      const: 1
+
+io-channel-cells:
+    - input
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+description: Texas Instruments LMP90077 AFE binding
+
+compatible: "ti,lmp90077"
+
+include: ti,lmp90xxx-base.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90078 AFE binding
+
+compatible: "ti,lmp90078"
+
+include: ti,lmp90xxx-current.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90079 AFE binding
+
+compatible: "ti,lmp90079"
+
+include: ti,lmp90xxx-base.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90080 AFE binding
+
+compatible: "ti,lmp90080"
+
+include: ti,lmp90xxx-current.yaml
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+description: Texas Instruments LMP90097 AFE binding
+
+compatible: "ti,lmp90097"
+
+include: ti,lmp90xxx-base.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90098 AFE binding
+
+compatible: "ti,lmp90098"
+
+include: ti,lmp90xxx-current.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90099 AFE binding
+
+compatible: "ti,lmp90099"
+
+include: ti,lmp90xxx-base.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments LMP90100 AFE binding
+
+compatible: "ti,lmp90100"
+
+include: ti,lmp90xxx-current.yaml
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+# Common fields for Texas Instruments LMP90xxx AFEs
+
+include: [adc-controller.yaml, spi-device.yaml]
+
+bus: lmp90xxx
+
+properties:
+    drdyb-gpios:
+      type: phandle-array
+      required: false
+      description: Data Ready Bar
+
+    "#io-channel-cells":
+      const: 2
+
+io-channel-cells:
+    - positive
+    - negative
@@ -0,0 +1,9 @@
+# Common fields for Texas Instruments LMP90xxx AFEs with current sources
+
+include: ti,lmp90xxx-base.yaml
+
+properties:
+    rtd-current:
+      type: int
+      required: false
+      description: RTD current in microampere
@@ -0,0 +1,40 @@
+# Copyright (c) 2019, Peter Bigot Consulting, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Description for a voltage divider, with optional ability to measure
+    resistance of the upper leg.
+
+compatible: "voltage-divider"
+
+include: base.yaml
+
+properties:
+    io-channels:
+      required: true
+      description: |
+        Channels available with this divider configuration.
+
+    output-ohms:
+      type: int
+      required: true
+      description: |
+        Resistance of the lower leg of the voltage divider
+
+    full-ohms:
+      type: int
+      required: false
+      description: |
+        Resistance of the full path through the voltage divider.
+
+        If absent or zero the driver assumes that the upper leg is a
+        resistance-based sensor.
+
+    power-gpios:
+      type: phandle-array
+      required: false
+      description: |
+        Control power to the voltage divider inputs.
+
+        If present the corresponding GPIO must be set to an active level
+        to enable the divider input.
@@ -0,0 +1,46 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Zephyr ADC Emulator
+
+compatible: "zephyr,adc-emul"
+
+include: adc-controller.yaml
+
+properties:
+    nchannels:
+        type: int
+        required: true
+        description: Number of emulated ADC channels. Should be in 1-32 range.
+
+    ref-internal-mv:
+        type: int
+        required: false
+        default: 0
+        description:
+          Internal reference voltage in mV. If not provided or set to zero,
+          channel setup with ADC_REF_INTERNAL will fail.
+
+    ref-vdd-mv:
+        type: int
+        required: false
+        default: 0
+        description:
+          VDD reference voltage in mV. If not provided or set to zero,
+          channel setup with ADC_REF_VDD_X will fail.
+
+    ref-external0-mv:
+        type: int
+        required: false
+        default: 0
+        description:
+          External 0 reference voltage in mV. If not provided or set to zero,
+          channel setup with ADC_REF_EXTERNAL0 will fail.
+
+    ref-external1-mv:
+        type: int
+        required: false
+        default: 0
+        description:
+          External 1 reference voltage in mV. If not provided or set to zero,
+          channel setup with ADC_REF_EXTERNAL1 will fail.