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WIP: device tree MVP
This commit is contained in:
Daniel Agar
@@ -0,0 +1,14 @@
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# Copyright (c) 2017, NXP
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# SPDX-License-Identifier: Apache-2.0
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# Common fields for ADC controllers
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include: base.yaml
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properties:
|
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label:
|
||||
required: true
|
||||
|
||||
"#io-channel-cells":
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||||
type: int
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||||
required: true
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||||
@@ -0,0 +1,34 @@
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# Copyright (C) 2019 Peter Bigot Consulting, LLC
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# SPDX-License-Identifier: Apache-2.0
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||||
description: |
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||||
ADC channels exposed on Arduino Uno (R3) headers.
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||||
The Arduino Uno layout provides a 6-pin Analog Input header. This
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has analog input signals labeled from A0 at the top through A5 at
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the bottom.
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This binding provides a nexus mapping for these pins where parent
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pins 0 through 5 correspond to A0 through A5.
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compatible: "arduino,uno-adc"
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include: base.yaml
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properties:
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io-channel-map:
|
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type: compound
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||||
required: true
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||||
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||||
io-channel-map-mask:
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||||
type: compound
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||||
required: false
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||||
|
||||
io-channel-map-pass-thru:
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||||
type: compound
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||||
required: false
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||||
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||||
"#io-channel-cells":
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type: int
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||||
required: true
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||||
description: Number of items to expect in an ADC specifier
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@@ -0,0 +1,35 @@
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description: Atmel SAM family AFEC
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|
||||
compatible: "atmel,sam-afec"
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||||
|
||||
include: adc-controller.yaml
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properties:
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reg:
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required: true
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||||
|
||||
interrupts:
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||||
required: true
|
||||
|
||||
peripheral-id:
|
||||
type: int
|
||||
description: peripheral ID
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||||
required: true
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||||
|
||||
"#io-channel-cells":
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||||
const: 1
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||||
|
||||
pinctrl-0:
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type: phandles
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||||
required: true
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||||
description: |
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||||
PIO pin configuration for ADTRG signal. We expect that
|
||||
the phandles will reference pinctrl nodes. These nodes will
|
||||
have a nodelabel that matches the Atmel SoC HAL defines and
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be of the form p<port><pin><periph>_<inst>_<signal>.
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||||
|
||||
For example the I2C on SAME7x would be
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||||
pinctrl-0 = <&pa8b_afec0_adtrg>;
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||||
|
||||
io-channel-cells:
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- input
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||||
@@ -0,0 +1,48 @@
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# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
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# SPDX-License-Identifier: Apache-2.0
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||||
description: Atmel SAM0 family ADC
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compatible: "atmel,sam0-adc"
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include: adc-controller.yaml
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properties:
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reg:
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required: true
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|
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interrupts:
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required: true
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|
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clocks:
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required: true
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||||
|
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clock-names:
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||||
required: true
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||||
|
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gclk:
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type: int
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required: true
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description: generic clock generator source
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|
||||
prescaler:
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||||
type: int
|
||||
required: true
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description: clock prescaler divisor applied to the generic clock
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|
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"#io-channel-cells":
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const: 1
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|
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calib-offset:
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type: int
|
||||
required: false
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||||
description: |
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||||
bit position offset in NVM SW Calib for start of ADC0 BIASCOMP field.
|
||||
This property is expected to be set on SAM{D,E}5x family of SoCs.
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||||
For ADC0 this should be 0, and for ADC1 this should be 14.
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||||
enum:
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||||
- 0
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||||
- 14
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||||
|
||||
io-channel-cells:
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- input
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@@ -0,0 +1,16 @@
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# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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||||
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description: ITE it8xxx2 ADC
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compatible: "ite,it8xxx2-adc"
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|
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include: adc-controller.yaml
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||||
|
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properties:
|
||||
interrupts:
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||||
required: true
|
||||
|
||||
pinctrl-0:
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||||
type: phandles
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||||
required: true
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Microchip MCP3204
|
||||
|
||||
compatible: "microchip,mcp3204"
|
||||
|
||||
include: microchip,mcp320x-base.yaml
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Microchip MCP3208
|
||||
|
||||
compatible: "microchip,mcp3208"
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||||
|
||||
include: microchip,mcp320x-base.yaml
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||||
@@ -0,0 +1,10 @@
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||||
# Common fields for Microchip MCP3204/MCP3208
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||||
|
||||
include: [adc-controller.yaml, spi-device.yaml]
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||||
|
||||
properties:
|
||||
"#io-channel-cells":
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const: 1
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||||
|
||||
io-channel-cells:
|
||||
- channel
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||||
@@ -0,0 +1,48 @@
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# Copyright (c) 2019, Intel Corporation
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# Copyright (c) 2021, Microchip Technology Inc.
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# SPDX-License-Identifier: Apache-2.0
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||||
|
||||
description: Microchip XEC ADC
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|
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compatible: "microchip,xec-adc-v2"
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include: adc-controller.yaml
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|
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properties:
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reg:
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||||
required: true
|
||||
|
||||
interrupts:
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required: true
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|
||||
"#io-channel-cells":
|
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const: 1
|
||||
|
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girqs:
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type: array
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||||
required: true
|
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description: Array of pairs of GIRQ number and bit position
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||||
|
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pcrs:
|
||||
type: array
|
||||
required: true
|
||||
description: ADC PCR register index and bit position
|
||||
|
||||
"#girq-cells":
|
||||
type: int
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||||
const: 2
|
||||
|
||||
"#pcr-cells":
|
||||
type: int
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||||
const: 2
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||||
|
||||
io-channel-cells:
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||||
- input
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||||
|
||||
girq-cells:
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- girqnum
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- bitpos
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|
||||
pcr-cells:
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- regidx
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||||
- bitpos
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||||
@@ -0,0 +1,26 @@
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||||
# Copyright (c) 2019, Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip XEC ADC
|
||||
|
||||
compatible: "microchip,xec-adc"
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||||
|
||||
include: adc-controller.yaml
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||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
clktime:
|
||||
type: int
|
||||
required: true
|
||||
description: ADC clock high & low time count value <1:255>
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (c) 2018, Nordic Semiconductor ASA
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||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: nRF ADC node
|
||||
|
||||
compatible: "nordic,nrf-adc"
|
||||
|
||||
include: adc-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (c) 2018, Nordic Semiconductor ASA
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||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nordic Semiconductor nRF family SAADC node
|
||||
|
||||
compatible: "nordic,nrf-saadc"
|
||||
|
||||
include: adc-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
@@ -0,0 +1,41 @@
|
||||
# Copyright (c) 2019 Vestas Wind Systems A/S
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP Kinetis ADC12
|
||||
|
||||
compatible: "nxp,kinetis-adc12"
|
||||
|
||||
include: adc-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clk-source:
|
||||
type: int
|
||||
required: true
|
||||
description: converter clock source
|
||||
|
||||
clk-divider:
|
||||
type: int
|
||||
required: true
|
||||
description: clock divider for the converter
|
||||
|
||||
alternate-voltage-reference:
|
||||
type: boolean
|
||||
required: false
|
||||
description: use alternate voltage reference source
|
||||
|
||||
sample-time:
|
||||
type: int
|
||||
required: true
|
||||
description: sample time in clock cycles
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
@@ -0,0 +1,63 @@
|
||||
# Copyright (c) 2017, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Kinetis ADC16
|
||||
|
||||
compatible: "nxp,kinetis-adc16"
|
||||
|
||||
include: adc-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
channel-mux-b:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Use alternate set (b instead of a) of ADC channels
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
periodic-trigger:
|
||||
type: boolean
|
||||
required: false
|
||||
description: if periodic trigger enabled
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
clk-source:
|
||||
type: int
|
||||
required: false
|
||||
description: use alternate clock reference source
|
||||
|
||||
long-sample:
|
||||
type: int
|
||||
required: false
|
||||
enum:
|
||||
- 0
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
- 4
|
||||
description: long sample mode
|
||||
|
||||
continuous-convert:
|
||||
type: boolean
|
||||
required: false
|
||||
description: If use continuous convert
|
||||
|
||||
high-speed:
|
||||
type: boolean
|
||||
required: false
|
||||
description: If use high speed
|
||||
|
||||
hw-trigger-src:
|
||||
type: int
|
||||
required: false
|
||||
description: hardware trigger source (See ADCxTRGSEL field in user manual for more details)
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
@@ -0,0 +1,31 @@
|
||||
# Copyright (c) 2019 Vestas Wind Systems A/S
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP MCUA 12B1MSPS SAR ADC
|
||||
|
||||
compatible: "nxp,mcux-12b1msps-sar"
|
||||
|
||||
include: adc-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clk-divider:
|
||||
type: int
|
||||
required: true
|
||||
description: clock divider for the converter
|
||||
|
||||
sample-period-mode:
|
||||
type: int
|
||||
required: true
|
||||
description: sample period mode
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
@@ -0,0 +1,31 @@
|
||||
# Copyright (c) 2018, Endre Karlson
|
||||
# Copyright (c) 2018, Song Qiang <songqiang1304521@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ST STM32 family ADC
|
||||
|
||||
compatible: "st,stm32-adc"
|
||||
|
||||
include: [adc-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
pinctrl-0:
|
||||
required: true
|
||||
|
||||
pinctrl-names:
|
||||
required: true
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (c) 2021 Pavlo Hamov <pasha.gamov@gmail.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: cc32xx ADC node
|
||||
|
||||
compatible: "ti,cc32xx-adc"
|
||||
|
||||
include: adc-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 1
|
||||
|
||||
io-channel-cells:
|
||||
- input
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Texas Instruments LMP90077 AFE binding
|
||||
|
||||
compatible: "ti,lmp90077"
|
||||
|
||||
include: ti,lmp90xxx-base.yaml
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Texas Instruments LMP90078 AFE binding
|
||||
|
||||
compatible: "ti,lmp90078"
|
||||
|
||||
include: ti,lmp90xxx-current.yaml
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Texas Instruments LMP90079 AFE binding
|
||||
|
||||
compatible: "ti,lmp90079"
|
||||
|
||||
include: ti,lmp90xxx-base.yaml
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Texas Instruments LMP90080 AFE binding
|
||||
|
||||
compatible: "ti,lmp90080"
|
||||
|
||||
include: ti,lmp90xxx-current.yaml
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Texas Instruments LMP90097 AFE binding
|
||||
|
||||
compatible: "ti,lmp90097"
|
||||
|
||||
include: ti,lmp90xxx-base.yaml
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Texas Instruments LMP90098 AFE binding
|
||||
|
||||
compatible: "ti,lmp90098"
|
||||
|
||||
include: ti,lmp90xxx-current.yaml
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Texas Instruments LMP90099 AFE binding
|
||||
|
||||
compatible: "ti,lmp90099"
|
||||
|
||||
include: ti,lmp90xxx-base.yaml
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Texas Instruments LMP90100 AFE binding
|
||||
|
||||
compatible: "ti,lmp90100"
|
||||
|
||||
include: ti,lmp90xxx-current.yaml
|
||||
@@ -0,0 +1,18 @@
|
||||
# Common fields for Texas Instruments LMP90xxx AFEs
|
||||
|
||||
include: [adc-controller.yaml, spi-device.yaml]
|
||||
|
||||
bus: lmp90xxx
|
||||
|
||||
properties:
|
||||
drdyb-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: Data Ready Bar
|
||||
|
||||
"#io-channel-cells":
|
||||
const: 2
|
||||
|
||||
io-channel-cells:
|
||||
- positive
|
||||
- negative
|
||||
@@ -0,0 +1,9 @@
|
||||
# Common fields for Texas Instruments LMP90xxx AFEs with current sources
|
||||
|
||||
include: ti,lmp90xxx-base.yaml
|
||||
|
||||
properties:
|
||||
rtd-current:
|
||||
type: int
|
||||
required: false
|
||||
description: RTD current in microampere
|
||||
@@ -0,0 +1,40 @@
|
||||
# Copyright (c) 2019, Peter Bigot Consulting, LLC
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Description for a voltage divider, with optional ability to measure
|
||||
resistance of the upper leg.
|
||||
|
||||
compatible: "voltage-divider"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
io-channels:
|
||||
required: true
|
||||
description: |
|
||||
Channels available with this divider configuration.
|
||||
|
||||
output-ohms:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Resistance of the lower leg of the voltage divider
|
||||
|
||||
full-ohms:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
Resistance of the full path through the voltage divider.
|
||||
|
||||
If absent or zero the driver assumes that the upper leg is a
|
||||
resistance-based sensor.
|
||||
|
||||
power-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
Control power to the voltage divider inputs.
|
||||
|
||||
If present the corresponding GPIO must be set to an active level
|
||||
to enable the divider input.
|
||||
@@ -0,0 +1,46 @@
|
||||
# Copyright 2021 Google LLC
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Zephyr ADC Emulator
|
||||
|
||||
compatible: "zephyr,adc-emul"
|
||||
|
||||
include: adc-controller.yaml
|
||||
|
||||
properties:
|
||||
nchannels:
|
||||
type: int
|
||||
required: true
|
||||
description: Number of emulated ADC channels. Should be in 1-32 range.
|
||||
|
||||
ref-internal-mv:
|
||||
type: int
|
||||
required: false
|
||||
default: 0
|
||||
description:
|
||||
Internal reference voltage in mV. If not provided or set to zero,
|
||||
channel setup with ADC_REF_INTERNAL will fail.
|
||||
|
||||
ref-vdd-mv:
|
||||
type: int
|
||||
required: false
|
||||
default: 0
|
||||
description:
|
||||
VDD reference voltage in mV. If not provided or set to zero,
|
||||
channel setup with ADC_REF_VDD_X will fail.
|
||||
|
||||
ref-external0-mv:
|
||||
type: int
|
||||
required: false
|
||||
default: 0
|
||||
description:
|
||||
External 0 reference voltage in mV. If not provided or set to zero,
|
||||
channel setup with ADC_REF_EXTERNAL0 will fail.
|
||||
|
||||
ref-external1-mv:
|
||||
type: int
|
||||
required: false
|
||||
default: 0
|
||||
description:
|
||||
External 1 reference voltage in mV. If not provided or set to zero,
|
||||
channel setup with ADC_REF_EXTERNAL1 will fail.
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2017, synopsy
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ARC DCCM
|
||||
|
||||
compatible: "arc,dccm"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2017, synopsys
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ARC ICCM
|
||||
|
||||
compatible: "arc,iccm"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,11 @@
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Cortex-M DTCM (Data Tightly Coupled Memory)
|
||||
|
||||
compatible: "arm,dtcm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,11 @@
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Cortex-M ITCM (Instruction Tightly Coupled Memory)
|
||||
|
||||
compatible: "arm,itcm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2018, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ARM Serial Configuration Control (SCC)
|
||||
|
||||
compatible: "arm,scc"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,52 @@
|
||||
# Copyright (c) 2020, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Atmel SAM SSC (Synchronous Serial Controller) controller
|
||||
|
||||
compatible: "atmel,sam-ssc"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
peripheral-id:
|
||||
type: int
|
||||
description: peripheral ID
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
type: phandles
|
||||
description: |
|
||||
PIO pin configuration for RF, RK, RD, TF, TK, & TD signals.
|
||||
We expect that the phandles will reference pinctrl nodes.
|
||||
These nodes will have a nodelabel that matches the Atmel SoC HAL
|
||||
defines and be of the form p<port><pin><periph>_<inst>_<signal>.
|
||||
|
||||
For example the SSC on SAME7x would be
|
||||
pinctrl-0 = <&pd24b_ssc_rf &pa22a_ssc_rk &pa10c_ssc_rd
|
||||
&pb0d_ssc_tf &pb1d_ssc_tk &pb5d_ssc_td>;
|
||||
|
||||
required: true
|
||||
|
||||
dmas:
|
||||
required: true
|
||||
description: |
|
||||
TX & RX dma specifiers. Each specifier will have a phandle
|
||||
reference to the dma controller, the channel number, and peripheral
|
||||
trigger source.
|
||||
|
||||
For example dmas for TX, RX would look like
|
||||
dmas = <&xdmac 22 DMA_PERID_SSC_TX>, <&xdmac 23 DMA_PERID_SSC_RX>;
|
||||
|
||||
dma-names:
|
||||
required: true
|
||||
description: |
|
||||
This should be "tx" and "rx" to match the dmas property.
|
||||
|
||||
For example
|
||||
dma-names = "tx", "rx";
|
||||
@@ -0,0 +1,10 @@
|
||||
description: |
|
||||
For locating the Device ID (serial number) on Atmel SAM0 devices
|
||||
|
||||
compatible: "atmel,sam0-id"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,15 @@
|
||||
description: Atmel SAM0 multi-protocol (UART, SPI, I2C) SERCOM unit
|
||||
|
||||
compatible: "atmel,sam0-sercom"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2020, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Atmel SAMD2x Power Manger (PM)
|
||||
|
||||
compatible: "atmel,samd2x-pm"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
|
||||
clock-cells:
|
||||
- offset
|
||||
- bit
|
||||
@@ -0,0 +1,13 @@
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nordic DPPIC (Distributed Programmable Peripheral Interconnect Controller)
|
||||
|
||||
compatible: "nordic,nrf-dppic"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nordic EGU (Event Generator Unit)
|
||||
|
||||
compatible: "nordic,nrf-egu"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,9 @@
|
||||
description: Nordic FICR (Factory Information Configuration Registers)
|
||||
|
||||
compatible: "nordic,nrf-ficr"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nordic KMU (Key Management Unit)
|
||||
|
||||
compatible: "nordic,nrf-kmu"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
description: Nordic SPU (System Protection Unit)
|
||||
|
||||
compatible: "nordic,nrf-spu"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,9 @@
|
||||
description: Nordic UICR (User Information Configuration Registers)
|
||||
|
||||
compatible: "nordic,nrf-uicr"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2018, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX DTCM (Data Tightly Coupled Memory)
|
||||
|
||||
compatible: "nxp,imx-dtcm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,28 @@
|
||||
# Copyright (c) 2018, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX Enhanced Periodic Interrupt Timer (EPIT)
|
||||
|
||||
compatible: "nxp,imx-epit"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
prescaler:
|
||||
type: int
|
||||
required: true
|
||||
description: Set the EPIT prescaler between 0 and 4095
|
||||
|
||||
rdc:
|
||||
type: int
|
||||
required: true
|
||||
description: Set the RDC permission for this peripheral
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2018, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX ITCM (Instruction Tightly Coupled Memory)
|
||||
|
||||
compatible: "nxp,imx-itcm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,23 @@
|
||||
# Copyright (c) 2018, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX Messaging Unit
|
||||
|
||||
compatible: "nxp,imx-mu"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
rdc:
|
||||
type: int
|
||||
required: true
|
||||
description: Set the RDC permission for this peripheral
|
||||
@@ -0,0 +1,29 @@
|
||||
# Copyright (c) 2017, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Kinetis FTM
|
||||
|
||||
compatible: "nxp,kinetis-ftm"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
prescaler:
|
||||
type: int
|
||||
required: true
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 4
|
||||
- 8
|
||||
- 16
|
||||
- 32
|
||||
- 64
|
||||
- 128
|
||||
description: Input clock prescaler
|
||||
@@ -0,0 +1,25 @@
|
||||
# Copyright (c) 2017, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Kinetis KE1xF System Integration Module (SIM) IP node
|
||||
|
||||
compatible: "nxp,kinetis-ke1xf-sim"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
clkout-source:
|
||||
type: int
|
||||
required: false
|
||||
description: clkout clock source
|
||||
|
||||
clkout-divider:
|
||||
type: int
|
||||
required: false
|
||||
description: clkout divider
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (c) 2019 Vestas Wind Systems A/S
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP Kinetis Multipurpose Clock generator (MCG) IP node
|
||||
|
||||
compatible: "nxp,kinetis-mcg"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clock-cells:
|
||||
- name
|
||||
@@ -0,0 +1,22 @@
|
||||
# Copyright (c) 2019 Vestas Wind Systems A/S
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP Kinetis PCC (Peripheral Clock Controller) IP node
|
||||
|
||||
compatible: "nxp,kinetis-pcc"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
|
||||
clock-cells:
|
||||
- name
|
||||
- ip-source
|
||||
@@ -0,0 +1,26 @@
|
||||
# Copyright (c) 2019-2021 Vestas Wind Systems A/S
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP Kinetis SCG (System Clock Generator) IP node
|
||||
|
||||
compatible: "nxp,kinetis-scg"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
sosc-mode:
|
||||
type: int
|
||||
description: system oscillator mode
|
||||
required: false
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clock-cells:
|
||||
- name
|
||||
@@ -0,0 +1,45 @@
|
||||
# Copyright (c) 2017, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Kinetis System Integration Module (SIM) IP node
|
||||
|
||||
compatible: "nxp,kinetis-sim"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
pllfll-select:
|
||||
type: int
|
||||
required: true
|
||||
description: pll/fll selection for clock system
|
||||
|
||||
er32k-select:
|
||||
type: int
|
||||
required: true
|
||||
description: er32k selection for clock system
|
||||
|
||||
clkout-source:
|
||||
type: int
|
||||
required: false
|
||||
description: clkout clock source
|
||||
|
||||
clkout-divider:
|
||||
type: int
|
||||
required: false
|
||||
description: clkout divider
|
||||
|
||||
"#clock-cells":
|
||||
type: int
|
||||
required: false
|
||||
const: 3
|
||||
|
||||
clock-cells:
|
||||
- name
|
||||
- offset
|
||||
- bits
|
||||
@@ -0,0 +1,15 @@
|
||||
# Copyright (c) 2020 NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC Flexcomm node
|
||||
|
||||
compatible: "nxp,lpc-flexcomm"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,11 @@
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STM32 CCM (Core Coupled Memory)
|
||||
|
||||
compatible: "st,stm32-ccm"
|
||||
|
||||
include: [base.yaml, mem-region.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2020 Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Intel Digital PDM Microphone (DMIC) node
|
||||
|
||||
compatible: "intel,dmic"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,52 @@
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nordic PDM (Pulse Density Modulation interface)
|
||||
|
||||
compatible: "nordic,nrf-pdm"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clk-pin:
|
||||
type: int
|
||||
required: true
|
||||
description: CLK pin
|
||||
|
||||
din-pin:
|
||||
type: int
|
||||
required: true
|
||||
description: DIN pin
|
||||
|
||||
clock-source:
|
||||
type: string
|
||||
required: false
|
||||
default: "PCLK32M_HFXO"
|
||||
description: |
|
||||
Clock source to be used by the PDM peripheral. The following options
|
||||
are available:
|
||||
- "PCLK32M": 32 MHz peripheral clock, synchronous to HFCLK
|
||||
- "PCLK32M_HFXO": PCLK32M running off the 32 MHz crystal oscillator
|
||||
(HFXO) for better clock accuracy and jitter performance
|
||||
- "ACLK": Audio PLL clock with configurable frequency (frequency for
|
||||
this clock must be set via the "hfclkaudio-frequency" property
|
||||
in the "nordic,nrf-clock" node); this clock source is only available
|
||||
in the nRF53 Series SoCs and it requires the use of HFXO
|
||||
enum:
|
||||
- "PCLK32M"
|
||||
- "PCLK32M_HFXO"
|
||||
- "ACLK"
|
||||
|
||||
queue-size:
|
||||
type: int
|
||||
required: false
|
||||
default: 4
|
||||
description: |
|
||||
Size of the queue of received audio data blocks to be used
|
||||
by the driver.
|
||||
@@ -0,0 +1,12 @@
|
||||
# Copyright (c) 2018 STMicroelectronics
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STMicroelectronics MPXXDTYY digital PDM microphone family
|
||||
|
||||
compatible: "st,mpxxdtyy"
|
||||
|
||||
include: i2s-device.yaml
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,13 @@
|
||||
# Copyright (c) 2018, Intel Corporation
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Texas Instruments TLV320DAC310x Audio DAC
|
||||
|
||||
compatible: "ti,tlv320dac"
|
||||
|
||||
include: i2c-device.yaml
|
||||
|
||||
properties:
|
||||
reset-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
@@ -0,0 +1,110 @@
|
||||
# Common fields for all devices
|
||||
|
||||
include: [pm.yaml]
|
||||
|
||||
properties:
|
||||
status:
|
||||
type: string
|
||||
required: false
|
||||
description: indicates the operational status of a device
|
||||
enum:
|
||||
- "ok" # Deprecated form
|
||||
- "okay"
|
||||
- "disabled"
|
||||
- "reserved"
|
||||
- "fail"
|
||||
- "fail-sss"
|
||||
|
||||
compatible:
|
||||
type: string-array
|
||||
required: true
|
||||
description: compatible strings
|
||||
|
||||
reg:
|
||||
type: array
|
||||
description: register space
|
||||
required: false
|
||||
|
||||
reg-names:
|
||||
type: string-array
|
||||
description: name of each register space
|
||||
required: false
|
||||
|
||||
interrupts:
|
||||
type: array
|
||||
required: false
|
||||
description: interrupts for device
|
||||
|
||||
# Does not follow the 'type: phandle-array' scheme, but gets type-checked
|
||||
# by the code. Declare it here just so that other bindings can make it
|
||||
# 'required: true' easily if they want to.
|
||||
interrupts-extended:
|
||||
type: compound
|
||||
required: false
|
||||
description: extended interrupt specifier for device
|
||||
|
||||
interrupt-names:
|
||||
type: string-array
|
||||
required: false
|
||||
description: name of each interrupt
|
||||
|
||||
interrupt-parent:
|
||||
type: phandle
|
||||
required: false
|
||||
description: phandle to interrupt controller node
|
||||
|
||||
label:
|
||||
type: string
|
||||
required: false
|
||||
description: Human readable string describing the device (used as device_get_binding() argument)
|
||||
|
||||
clocks:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: Clock gate information
|
||||
|
||||
clock-names:
|
||||
type: string-array
|
||||
required: false
|
||||
description: name of each clock
|
||||
|
||||
"#address-cells":
|
||||
type: int
|
||||
required: false
|
||||
description: number of address cells in reg property
|
||||
|
||||
"#size-cells":
|
||||
type: int
|
||||
required: false
|
||||
description: number of size cells in reg property
|
||||
|
||||
dmas:
|
||||
required: false
|
||||
type: phandle-array
|
||||
description: DMA channels specifiers
|
||||
|
||||
dma-names:
|
||||
required: false
|
||||
type: string-array
|
||||
description: Provided names of DMA channel specifiers
|
||||
|
||||
io-channels:
|
||||
required: false
|
||||
type: phandle-array
|
||||
description: IO channels specifiers
|
||||
|
||||
io-channel-names:
|
||||
required: false
|
||||
type: string-array
|
||||
description: Provided names of IO channel specifiers
|
||||
|
||||
mboxes:
|
||||
required: false
|
||||
type: phandle-array
|
||||
description: mailbox / IPM channels specifiers
|
||||
specifier-space: mbox
|
||||
|
||||
mbox-names:
|
||||
required: false
|
||||
type: string-array
|
||||
description: Provided names of mailbox / IPM channel specifiers
|
||||
@@ -0,0 +1,13 @@
|
||||
# Copyright (c) 2021, CSIRO
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
# Common fields for devices resulting in linker memory regions
|
||||
|
||||
properties:
|
||||
zephyr,memory-region:
|
||||
type: string
|
||||
required: false
|
||||
description: |
|
||||
Signify that this node should result in a dedicated linker script
|
||||
memory region in the final executable. The region address and size
|
||||
is taken from the <reg> property, while the name is the value of
|
||||
this property.
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (c) 2021 Intel Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Properties for Power Management (PM)
|
||||
|
||||
properties:
|
||||
wakeup-source:
|
||||
required: false
|
||||
type: boolean
|
||||
description: |
|
||||
Property to identify that a device can be used as wake up source.
|
||||
|
||||
When this property is provided a specific flag is set into the
|
||||
device that tells the system that the device is capable of
|
||||
wake up the system.
|
||||
|
||||
Wake up capable devices are disabled (interruptions will not wake up
|
||||
the system) by default but they can be enabled at runtime if necessary.
|
||||
@@ -0,0 +1,33 @@
|
||||
# Copyright (c) 2020, Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Properties for nodes with controllable power supplies.
|
||||
|
||||
properties:
|
||||
supply-gpios:
|
||||
type: phandle-array
|
||||
required: false
|
||||
description: |
|
||||
GPIO specifier that controls power to the device.
|
||||
|
||||
This property should be provided when the device has a dedicated
|
||||
switch that controls power to the device. The supply state is
|
||||
entirely the responsibility of the device driver.
|
||||
|
||||
Contrast with vin-supply.
|
||||
|
||||
vin-supply:
|
||||
type: phandle
|
||||
required: false
|
||||
description: |
|
||||
Reference to the regulator that controls power to the device.
|
||||
The referenced devicetree node must have a regulator compatible.
|
||||
|
||||
This property should be provided when device power is supplied
|
||||
by a shared regulator. The supply state is dependent on the
|
||||
request status of all devices fed by the regulator.
|
||||
|
||||
Contrast with supply-gpios. If both properties are provided
|
||||
then the regulator must be requested before the supply GPIOS is
|
||||
set to an active state, and the supply GPIOS must be set to an
|
||||
inactive state before releasing the regulator.
|
||||
@@ -0,0 +1,34 @@
|
||||
# Copyright (c) 2019 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Configures SPI slave settings for a Bluetooth controller that uses
|
||||
Zephyr's Bluetooth Host Controller Interface SPI (HCI SPI) driver.
|
||||
|
||||
A node defined via devicetree overlay should look like this:
|
||||
|
||||
&myspi {
|
||||
bt-hci@0 {
|
||||
compatible = "zephyr,bt-hci-spi-slave";
|
||||
reg = <0>;
|
||||
irq-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
|
||||
};
|
||||
};
|
||||
|
||||
The bt-hci@0 node configures an HCI SPI slave on SPI slave
|
||||
interface myspi.
|
||||
|
||||
The host interrupt GPIO is set to gpio1 pin 2 via irq-gpios. The
|
||||
GPIO flags are just for example and may be different depending on
|
||||
hardware.
|
||||
|
||||
compatible: "zephyr,bt-hci-spi-slave"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
on-bus: spi
|
||||
|
||||
properties:
|
||||
irq-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2018, I-SENSE group of ICCS
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Bluetooth module that uses Zephyr's Bluetooth Host Controller Interface SPI
|
||||
driver (e.g. nRF51822)
|
||||
|
||||
compatible: "zephyr,bt-hci-spi"
|
||||
|
||||
include: spi-device.yaml
|
||||
|
||||
properties:
|
||||
irq-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
|
||||
reset-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
@@ -0,0 +1,28 @@
|
||||
description: Bosch m_can CAN-FD controller base
|
||||
|
||||
compatible: "bosch,m-can-base"
|
||||
|
||||
properties:
|
||||
std-filter-elements:
|
||||
type: int
|
||||
required: true
|
||||
|
||||
ext-filter-elements:
|
||||
type: int
|
||||
required: true
|
||||
|
||||
rx-fifo0-elements:
|
||||
type: int
|
||||
required: true
|
||||
|
||||
rx-fifo1-elements:
|
||||
type: int
|
||||
required: true
|
||||
|
||||
rx-buffer-elements:
|
||||
type: int
|
||||
required: true
|
||||
|
||||
tx-buffer-elements:
|
||||
type: int
|
||||
required: true
|
||||
@@ -0,0 +1,12 @@
|
||||
description: Bosch m_can CAN-FD controller
|
||||
|
||||
compatible: "bosch,m-can"
|
||||
|
||||
include: can-fd-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
@@ -0,0 +1,36 @@
|
||||
# Common fields for CAN controllers
|
||||
|
||||
include: base.yaml
|
||||
|
||||
bus: can
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
bus-speed:
|
||||
type: int
|
||||
required: true
|
||||
description: bus speed in Baud/s
|
||||
sjw:
|
||||
type: int
|
||||
required: true
|
||||
description: Resynchronization jump width (ISO 11898-1)
|
||||
prop-seg:
|
||||
type: int
|
||||
required: false
|
||||
description: Time quantums of propagation segment (ISO 11898-1)
|
||||
phase-seg1:
|
||||
type: int
|
||||
required: false
|
||||
description: Time quantums of phase buffer 1 segment (ISO 11898-1)
|
||||
phase-seg2:
|
||||
type: int
|
||||
required: false
|
||||
description: Time quantums of phase buffer 2 segment (ISO 11898-1)
|
||||
sample-point:
|
||||
type: int
|
||||
required: false
|
||||
description: >
|
||||
Sample point in permille.
|
||||
This param is required if segments are not given.
|
||||
If the sample point is given, the segments are ignored.
|
||||
@@ -0,0 +1,14 @@
|
||||
# Copyright (c) 2018 Alexander Wachter
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for CAN devices
|
||||
|
||||
include: base.yaml
|
||||
|
||||
on-bus: can
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
label:
|
||||
required: true
|
||||
@@ -0,0 +1,36 @@
|
||||
# Common fields for CAN-FD controllers
|
||||
|
||||
include: can-controller.yaml
|
||||
|
||||
properties:
|
||||
bus-speed-data:
|
||||
type: int
|
||||
required: true
|
||||
description: data phase bus speed in Baud/s
|
||||
sjw-data:
|
||||
type: int
|
||||
required: true
|
||||
description: Resynchronization jump width for the data phase. (ISO11898-1:2015)
|
||||
prop-seg-data:
|
||||
type: int
|
||||
required: false
|
||||
description: Time quantums of propagation segment for the data phase. (ISO11898-1:2015)
|
||||
phase-seg1-data:
|
||||
type: int
|
||||
required: false
|
||||
description: Time quantums of phase buffer 1 segment for the data phase. (ISO11898-1:2015)
|
||||
phase-seg2-data:
|
||||
type: int
|
||||
required: false
|
||||
description: Time quantums of phase buffer 2 segment for the data phase. (ISO11898-1:2015)
|
||||
sample-point-data:
|
||||
type: int
|
||||
required: false
|
||||
description: >
|
||||
Sample point in permille for the data phase.
|
||||
This param is required if segments are not given.
|
||||
If the sample point is given, the segments are ignored.
|
||||
tx-delay-comp-offset:
|
||||
type: int
|
||||
required: false
|
||||
default: 0
|
||||
@@ -0,0 +1,26 @@
|
||||
# Copyright (c) 2019 Karsten Koenig
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: MCP2515 SPI CAN controller
|
||||
|
||||
compatible: "microchip,mcp2515"
|
||||
|
||||
include: [spi-device.yaml, can-controller.yaml]
|
||||
|
||||
properties:
|
||||
osc-freq:
|
||||
type: int
|
||||
required: true
|
||||
description: Frequency of the external oscillator
|
||||
int-gpios:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: |
|
||||
Interrupt pin.
|
||||
|
||||
This pin signals active low when produced by the controller. The
|
||||
property value should ensure the flags properly describe the signal
|
||||
that is presented to the driver.
|
||||
reg:
|
||||
type: array
|
||||
required: true
|
||||
@@ -0,0 +1,23 @@
|
||||
# Copyright (c) 2019 Vestas Wind Systems A/S
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: NXP FlexCAN controller
|
||||
|
||||
compatible: "nxp,kinetis-flexcan"
|
||||
|
||||
include: can-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
clk-source:
|
||||
type: int
|
||||
required: true
|
||||
description: CAN engine clock source
|
||||
@@ -0,0 +1,15 @@
|
||||
description: Renesas R-Car CAN controller
|
||||
|
||||
compatible: "renesas,rcar-can"
|
||||
|
||||
include: can-controller.yaml
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
@@ -0,0 +1,26 @@
|
||||
description: STM32 CAN controller
|
||||
|
||||
compatible: "st,stm32-can"
|
||||
|
||||
include: [can-controller.yaml, pinctrl-device.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
pinctrl-0:
|
||||
required: true
|
||||
|
||||
pinctrl-names:
|
||||
required: true
|
||||
|
||||
master-can-reg:
|
||||
type: int
|
||||
required: false
|
||||
description: master can reg when different from current instance
|
||||
@@ -0,0 +1,5 @@
|
||||
description: Bosch m_can CAN-FD controller
|
||||
|
||||
compatible: "st,stm32-fdcan"
|
||||
|
||||
include: ["bosch,m-can.yaml", "pinctrl-device.yaml"]
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (c) 2020, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Atmel SAMD2x Generic Clock Controller (GCLK)
|
||||
|
||||
compatible: "atmel,samd2x-gclk"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clock-cells:
|
||||
- clkctrl_id
|
||||
@@ -0,0 +1,18 @@
|
||||
# Copyright (c) 2020, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Atmel SAMD5x Generic Clock Controller (GCLK)
|
||||
|
||||
compatible: "atmel,samd5x-gclk"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clock-cells:
|
||||
- periph_ch
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2020, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Atmel SAMD5x Generic Clock Controller (MCLK)
|
||||
|
||||
compatible: "atmel,samd5x-mclk"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
|
||||
clock-cells:
|
||||
- offset
|
||||
- bit
|
||||
@@ -0,0 +1,10 @@
|
||||
# Copyright (c) 2019, Linaro Limited
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
# Common fields for clock controllers
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
type: int
|
||||
required: true
|
||||
description: Number of items to expect in a Clock specifier
|
||||
@@ -0,0 +1,31 @@
|
||||
# Copyright (c) 2020, Mohamed ElShahawi
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: ESP32 RTC (Power & Clock Controller Module) Module
|
||||
|
||||
compatible: "espressif,esp32-rtc"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
xtal-freq:
|
||||
type: int
|
||||
required: true
|
||||
description: Value of the external XTAL connected to ESP32.
|
||||
|
||||
xtal-div:
|
||||
type: int
|
||||
required: false
|
||||
description: Divisor value for XTAL Clock, CPU_CLK = XTAL_FREQ / xtal-div
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clock-cells:
|
||||
- offset # Index of the peripheral in esp32 modules list (Check esp32_clock.h)
|
||||
@@ -0,0 +1,27 @@
|
||||
# Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Generic fixed-rate clock provider
|
||||
|
||||
compatible: "fixed-clock"
|
||||
|
||||
include: clock-controller.yaml
|
||||
|
||||
properties:
|
||||
label:
|
||||
type: string
|
||||
required: false
|
||||
description: Human readable string describing the device (used as device_get_binding() argument)
|
||||
|
||||
clock-frequency:
|
||||
type: int
|
||||
description: output clock frequency (Hz)
|
||||
required: true
|
||||
|
||||
clocks:
|
||||
type: array
|
||||
required: false
|
||||
description: input clock source
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
@@ -0,0 +1,24 @@
|
||||
# Copyright (c) 2021 Prevas A/S
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Generic fixed factor clock provider
|
||||
|
||||
compatible: "fixed-factor-clock"
|
||||
|
||||
include: clock-controller.yaml
|
||||
|
||||
properties:
|
||||
clock-div:
|
||||
type: int
|
||||
description: fixed clock divider
|
||||
|
||||
clock-mult:
|
||||
type: int
|
||||
description: fixed clock multiplier
|
||||
|
||||
clocks:
|
||||
type: phandle-array
|
||||
description: input clock source
|
||||
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
@@ -0,0 +1,93 @@
|
||||
# Copyright (c) 2020 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
description: |
|
||||
LiteX Mixed Mode Clock Manager
|
||||
Common clock driver with MMCM unit for dynamic reconfiguration
|
||||
of up to 7 clock outputs with ability to change frequency, duty
|
||||
cycle and phase offset
|
||||
|
||||
compatible: "litex,clk"
|
||||
|
||||
clock-cells:
|
||||
- id
|
||||
|
||||
properties:
|
||||
|
||||
reg:
|
||||
description: Base address and lengths of the register space
|
||||
|
||||
"#clock-cells":
|
||||
required: true
|
||||
const: 1
|
||||
|
||||
clock-output-names:
|
||||
required: true
|
||||
type: string-array
|
||||
description: |
|
||||
List of strings of clock output signal names indexed
|
||||
by the first cell in the clock specifier.
|
||||
|
||||
litex,lock-timeout:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
Number of ms to wait for MMCM to assert LOCK signal
|
||||
litex,drdy-timeout:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
Number of ms to wait for MMCM to assert DRDY signal
|
||||
litex,sys-clock-frequency:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
System clock frequency
|
||||
litex,divclk-divide-min:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
minimal global divider
|
||||
litex,divclk-divide-max:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
maximal global divider
|
||||
litex,clkfbout-mult-min:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
minimal global multiplier
|
||||
litex,clkfbout-mult-max:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
maximal global multiplier
|
||||
litex,vco-freq-min:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
minimal frequency after global divider and multiplier
|
||||
litex,vco-freq-max:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
maximal frequency after global divider and multiplier
|
||||
litex,clkout-divide-min:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
minimal clock output divider
|
||||
litex,clkout-divide-max:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
maximal clock output divider
|
||||
litex,vco-margin:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
tolerancy for vco frequency
|
||||
const: 0
|
||||
@@ -0,0 +1,67 @@
|
||||
# Copyright (c) 2020 Antmicro <www.antmicro.com>
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
include: base.yaml
|
||||
|
||||
description: |
|
||||
LiteX Mixed Mode Clock Manager clock output binding
|
||||
|
||||
compatible: "litex,clkout"
|
||||
|
||||
properties:
|
||||
|
||||
"#clock-cells":
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
Number of cells in a clock specifier;
|
||||
Typically 0 for nodes with a single clock output
|
||||
and 1 for nodes with multiple clock outputs.
|
||||
const: 1
|
||||
|
||||
clock-output-names:
|
||||
required: true
|
||||
type: string
|
||||
description: |
|
||||
string of clock output signal name.
|
||||
|
||||
litex,clock-frequency:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
default frequency in Hz for clock output
|
||||
|
||||
litex,clock-phase:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
default phase offset given in degrees
|
||||
|
||||
litex,clock-duty-num:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
default duty cycle numerator value
|
||||
|
||||
litex,clock-duty-den:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
default duty cycle denominator value
|
||||
|
||||
litex,clock-margin:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
clock output margin coefficient
|
||||
|
||||
litex,clock-margin-exp:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
exponent for clkout margin
|
||||
effective clkout margin shall be
|
||||
margin * 10^(-exponent) * 100%
|
||||
|
||||
clock-cells:
|
||||
- id
|
||||
@@ -0,0 +1,52 @@
|
||||
# Copyright (c) 2021, Microchip Technology Inc.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Microchip XEC Power Clock Reset and VBAT register (PCR)
|
||||
|
||||
compatible: "microchip,xec-pcr"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
core-clock-div:
|
||||
type: int
|
||||
required: true
|
||||
description: Divide 96 MHz PLL clock to produce Cortex-M4 core clock
|
||||
|
||||
slow-clock-div:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
PWM and TACH clock domain divided down from 48 MHz AHB clock. The
|
||||
default value is 480 for 100 kHz.
|
||||
|
||||
pll-32k-src:
|
||||
type: int
|
||||
required: true
|
||||
description: 32 KHz clock source for PLL
|
||||
|
||||
periph-32k-src:
|
||||
type: int
|
||||
required: true
|
||||
description: 32 KHz clock source for peripherals
|
||||
|
||||
xtal-single-ended:
|
||||
type: boolean
|
||||
required: false
|
||||
description: Use single ended crystal connection to XTAL2 pin.
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
|
||||
clock-cells:
|
||||
- regidx
|
||||
- bitpos
|
||||
@@ -0,0 +1,27 @@
|
||||
# Copyright (c) 2018 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Nordic nRF clock control node
|
||||
|
||||
compatible: "nordic,nrf-clock"
|
||||
|
||||
include: base.yaml
|
||||
|
||||
properties:
|
||||
label:
|
||||
required: true
|
||||
|
||||
reg:
|
||||
required: true
|
||||
|
||||
interrupts:
|
||||
required: true
|
||||
|
||||
hfclkaudio-frequency:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
Frequency of the HFCLKAUDIO clock in Hz. Adjustable with 3.3 ppm
|
||||
resolution in two frequency bands - 11.176 MHz to 11.402 MHz, and
|
||||
12.165 MHz to 12.411 MHz (refer to the relevant Product Specification).
|
||||
The HFCLKAUDIO clock is only available in the nRF53 Series SoCs.
|
||||
@@ -0,0 +1,224 @@
|
||||
# Copyright (c) 2020 Nuvoton Technology Corporation.
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Nuvoton, NPCX PCC (Power and Clock Controller) node.
|
||||
Besides power management, this node is also in charge of configuring the
|
||||
Oscillator Frequency Multiplier Clock (OFMCLK), which is derived from
|
||||
High-Frequency Clock Generator (HFCG), is the source clock of Cortex-M4 core
|
||||
and most of NPCX hardware modules.
|
||||
|
||||
Here is an example of configuring OFMCLK and the other clock sources derived
|
||||
from it in board dts file.
|
||||
&pcc {
|
||||
clock-frequency = <DT_FREQ_M(100)>; /* OFMCLK runs at 100MHz */
|
||||
core-prescaler = <5>; /* CORE_CLK runs at 20MHz */
|
||||
apb1-prescaler = <5>; /* APB1_CLK runs at 20MHz */
|
||||
apb2-prescaler = <5>; /* APB2_CLK runs at 20MHz */
|
||||
apb3-prescaler = <5>; /* APB3_CLK runs at 20MHz */
|
||||
};
|
||||
|
||||
compatible: "nuvoton,npcx-pcc"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
clock-frequency:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
Default frequency in Hz for HFCG output clock (OFMCLK). Currently,
|
||||
only the following values are allowed:
|
||||
100000000, 100 MHz
|
||||
96000000, 96 MHz
|
||||
90000000, 90 MHz
|
||||
80000000, 80 MHz
|
||||
66000000, 66 MHz
|
||||
50000000, 50 MHz
|
||||
48000000, 48 MHz
|
||||
40000000, 40 MHz (default value after reset)
|
||||
33000000, 33 MHz
|
||||
enum:
|
||||
- 100000000
|
||||
- 96000000
|
||||
- 90000000
|
||||
- 80000000
|
||||
- 66000000
|
||||
- 50000000
|
||||
- 48000000
|
||||
- 40000000
|
||||
- 33000000
|
||||
|
||||
core-prescaler:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Core clock prescaler (FPRED). It sets the Core frequency, CORE_CLK, by
|
||||
dividing OFMCLK(MCLK) and needs to meet the following requirements.
|
||||
- CORE_CLK must be set to 4MHz <= CORE_CLK <= 100MHz.
|
||||
= Only the following values are allowed:
|
||||
1, CORE_CLK = OFMCLK
|
||||
2, CORE_CLK = OFMCLK / 2
|
||||
3, CORE_CLK = OFMCLK / 3
|
||||
4, CORE_CLK = OFMCLK / 4
|
||||
5, CORE_CLK = OFMCLK / 5
|
||||
6, CORE_CLK = OFMCLK / 6
|
||||
7, CORE_CLK = OFMCLK / 7
|
||||
8, CORE_CLK = OFMCLK / 8
|
||||
9, CORE_CLK = OFMCLK / 9
|
||||
10, CORE_CLK = OFMCLK / 10
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
- 4
|
||||
- 5
|
||||
- 6
|
||||
- 7
|
||||
- 8
|
||||
- 9
|
||||
- 10
|
||||
|
||||
apb1-prescaler:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
APB1 prescaler. It sets the APB1 bus frequency, APB1_CLK, by dividing
|
||||
OFMCLK(MCLK) and needs to meet the following requirements.
|
||||
- APB1_CLK must be set to 4MHz <= APB1_CLK <= 50MHz.
|
||||
- APB1_CLK must be an integer division (including 1) of CORE_CLK.
|
||||
= Only the following values are allowed:
|
||||
1, APB1_CLK = OFMCLK
|
||||
2, APB1_CLK = OFMCLK / 2
|
||||
3, APB1_CLK = OFMCLK / 3
|
||||
4, APB1_CLK = OFMCLK / 4
|
||||
5, APB1_CLK = OFMCLK / 5
|
||||
6, APB1_CLK = OFMCLK / 6
|
||||
7, APB1_CLK = OFMCLK / 7
|
||||
8, APB1_CLK = OFMCLK / 8
|
||||
9, APB1_CLK = OFMCLK / 9
|
||||
10, APB1_CLK = OFMCLK / 10
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
- 4
|
||||
- 5
|
||||
- 6
|
||||
- 7
|
||||
- 8
|
||||
- 9
|
||||
- 10
|
||||
|
||||
apb2-prescaler:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
APB2 prescaler. It sets the APB2 bus frequency, APB2_CLK, by dividing
|
||||
OFMCLK(MCLK) and needs to meet the following requirements.
|
||||
- APB2_CLK must be set to 8MHz <= APB2_CLK <= 50MHz.
|
||||
- APB2_CLK must be an integer division (including 1) of CORE_CLK.
|
||||
= Only the following values are allowed:
|
||||
1, APB2_CLK = OFMCLK
|
||||
2, APB2_CLK = OFMCLK / 2
|
||||
3, APB2_CLK = OFMCLK / 3
|
||||
4, APB2_CLK = OFMCLK / 4
|
||||
5, APB2_CLK = OFMCLK / 5
|
||||
6, APB2_CLK = OFMCLK / 6
|
||||
7, APB2_CLK = OFMCLK / 7
|
||||
8, APB2_CLK = OFMCLK / 8
|
||||
9, APB2_CLK = OFMCLK / 9
|
||||
10, APB2_CLK = OFMCLK / 10
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
- 4
|
||||
- 5
|
||||
- 6
|
||||
- 7
|
||||
- 8
|
||||
- 9
|
||||
- 10
|
||||
|
||||
apb3-prescaler:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
APB3 prescaler. It sets the APB3 bus frequency, APB3_CLK, by dividing
|
||||
OFMCLK(MCLK) and needs to meet the following requirements.
|
||||
- APB3_CLK must be set to 12.5MHz <= APB3_CLK <= 50MHz.
|
||||
- APB3_CLK must be an integer division (including 1) of CORE_CLK.
|
||||
= Only the following values are allowed:
|
||||
1, APB3_CLK = OFMCLK
|
||||
2, APB3_CLK = OFMCLK / 2
|
||||
3, APB3_CLK = OFMCLK / 3
|
||||
4, APB3_CLK = OFMCLK / 4
|
||||
5, APB3_CLK = OFMCLK / 5
|
||||
6, APB3_CLK = OFMCLK / 6
|
||||
7, APB3_CLK = OFMCLK / 7
|
||||
8, APB3_CLK = OFMCLK / 8
|
||||
9, APB3_CLK = OFMCLK / 9
|
||||
10, APB3_CLK = OFMCLK / 10
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
- 4
|
||||
- 5
|
||||
- 6
|
||||
- 7
|
||||
- 8
|
||||
- 9
|
||||
- 10
|
||||
|
||||
apb4-prescaler:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
APB4 prescaler. It sets the APB4 bus frequency, APB4_CLK, by dividing
|
||||
OFMCLK(MCLK) and needs to meet the following requirements.
|
||||
- APB4_CLK must be set to 8MHz <= APB4_CLK <= 50MHz.
|
||||
- APB4_CLK must be an integer division (including 1) of CORE_CLK.
|
||||
= Only the following values are allowed:
|
||||
1, APB4_CLK = OFMCLK
|
||||
2, APB4_CLK = OFMCLK / 2
|
||||
3, APB4_CLK = OFMCLK / 3
|
||||
4, APB4_CLK = OFMCLK / 4
|
||||
5, APB4_CLK = OFMCLK / 5
|
||||
6, APB4_CLK = OFMCLK / 6
|
||||
7, APB4_CLK = OFMCLK / 7
|
||||
8, APB4_CLK = OFMCLK / 8
|
||||
9, APB4_CLK = OFMCLK / 9
|
||||
10, APB4_CLK = OFMCLK / 10
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 3
|
||||
- 4
|
||||
- 5
|
||||
- 6
|
||||
- 7
|
||||
- 8
|
||||
- 9
|
||||
- 10
|
||||
|
||||
ram-pd-depth:
|
||||
required: false
|
||||
type: int
|
||||
enum:
|
||||
- 12
|
||||
- 15
|
||||
description: |
|
||||
Valid bit-depth of RAM block Power-Down control (RAM_PD) registers.
|
||||
Each bit in RAM_PDn can power down the relevant RAM block by setting
|
||||
itself to 1 for better power consumption and this valid bit-depth
|
||||
varies in different NPCX series.
|
||||
|
||||
clock-cells:
|
||||
- bus
|
||||
- ctl
|
||||
- bit
|
||||
@@ -0,0 +1,38 @@
|
||||
# Copyright (c) 2021, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX ANATOP (Analog Clock Controller Module) IP node
|
||||
|
||||
compatible: "nxp,imx-anatop"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
type: int
|
||||
const: 4
|
||||
required: true
|
||||
description: Number of items to expect in a clock specifier
|
||||
|
||||
"#pll-clock-cells":
|
||||
type: int
|
||||
const: 3
|
||||
required: true
|
||||
description: Number of items to expect in a PLL specifier
|
||||
|
||||
clock-cells:
|
||||
- name
|
||||
- offset
|
||||
- bits
|
||||
- value
|
||||
|
||||
pll-clock-cells:
|
||||
- offset
|
||||
- bits
|
||||
- value
|
||||
@@ -0,0 +1,23 @@
|
||||
# Copyright (c) 2021, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX CCM Rev2 (Clock Controller Module) IP node
|
||||
|
||||
compatible: "nxp,imx-ccm-rev2"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 3
|
||||
|
||||
clock-cells:
|
||||
- name
|
||||
- offset
|
||||
- bits
|
||||
@@ -0,0 +1,23 @@
|
||||
# Copyright (c) 2017, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: i.MX CCM (Clock Controller Module) IP node
|
||||
|
||||
compatible: "nxp,imx-ccm"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 3
|
||||
|
||||
clock-cells:
|
||||
- name
|
||||
- offset
|
||||
- bits
|
||||
@@ -0,0 +1,21 @@
|
||||
# Copyright (c) 2020, NXP
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC SYSCON & CLKCTL IP node
|
||||
|
||||
compatible: "nxp,lpc-syscon"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clock-cells:
|
||||
- name
|
||||
@@ -0,0 +1,31 @@
|
||||
# Copyright (c) 2020, Seagate
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: LPC11U6X clock controller node
|
||||
|
||||
compatible: "nxp,lpc11u6x-syscon"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
label:
|
||||
required: true
|
||||
|
||||
pinmuxs:
|
||||
type: phandle-array
|
||||
required: true
|
||||
description: system oscillator pinmux configuration
|
||||
|
||||
pinmux-names:
|
||||
type: string-array
|
||||
required: false
|
||||
description: system oscillator pins names
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clock-cells:
|
||||
- clkid
|
||||
@@ -0,0 +1,19 @@
|
||||
# Copyright (c) 2020, IoT.bzh
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: Renesas Clock Pulse Generator / Module Standby and Software Reset
|
||||
|
||||
compatible: "renesas,rcar-cpg-mssr"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
|
||||
clock-cells:
|
||||
- domain
|
||||
- module
|
||||
@@ -0,0 +1,16 @@
|
||||
# Copyright (c) 2021, Linaro ltd
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STM32 HSE Clock
|
||||
|
||||
compatible: "st,stm32-hse-clock"
|
||||
|
||||
include: [fixed-clock.yaml]
|
||||
|
||||
properties:
|
||||
hse-bypass:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
HSE crystal oscillator bypass
|
||||
Set to the property to by-pass the oscillator with an external clock.
|
||||
@@ -0,0 +1,36 @@
|
||||
# Copyright (c) 2021, Linaro ltd
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: STM32 MSI Clock
|
||||
|
||||
compatible: "st,stm32-msi-clock"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
msi-range:
|
||||
required: true
|
||||
type: int
|
||||
default: 6
|
||||
description: |
|
||||
MSI clock ranges
|
||||
enum:
|
||||
- 0 # range 0 around 100 kHz
|
||||
- 1 # range 1 around 200 kHz
|
||||
- 2 # range 2 around 400 kHz
|
||||
- 3 # range 3 around 800 kHz
|
||||
- 4 # range 4 around 1M Hz
|
||||
- 5 # range 5 around 2 MHz
|
||||
- 6 # range 6 around 4 MHz (reset value)
|
||||
- 7 # range 7 around 8 MHz
|
||||
- 8 # range 8 around 16 MHz
|
||||
- 9 # range 9 around 24 MHz
|
||||
- 10 # range 10 around 32 MHz
|
||||
- 11 # range 11 around 48 MHz
|
||||
|
||||
msi-pll-mode:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
MSI clock PLL enable
|
||||
Enables the PLL part of the MSI clock source.
|
||||
@@ -0,0 +1,96 @@
|
||||
# Copyright (c) 2021, Linaro ltd
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
STM32 Reset and Clock controller node.
|
||||
This node is in charge of system clock ('SYSCLK') source selection and controlling
|
||||
clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
|
||||
|
||||
Configuring STM32 Reset and Clock controller node:
|
||||
|
||||
System clock source should be selected amongst the clock nodes available in "clocks"
|
||||
node (typically 'clk_hse, clk_hsi', 'pll', ...).
|
||||
As part of this node configuration, SYSCLK frequency should also be defined, using
|
||||
"clock-frequency" property.
|
||||
Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
|
||||
prescaler properties.
|
||||
Here is an example of correctly configured rcc node:
|
||||
&rcc {
|
||||
clocks = <&pll>; /* Set pll as SYSCLK source */
|
||||
clock-frequency = <DT_FREQ_M(80)>; /* SYSCLK runs at 80MHz */
|
||||
ahb-prescaler = <1>;
|
||||
apb1-presacler = <1>;
|
||||
apb2-presacler = <1>;
|
||||
}
|
||||
|
||||
Specifying a gated clock:
|
||||
|
||||
To specify a gated clock, a peripheral should define a "clocks" property encoded
|
||||
in the following way:
|
||||
... {
|
||||
...
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
|
||||
...
|
||||
}
|
||||
After the phandle referring to rcc node, the first index specifies the registers of
|
||||
the bus controlling the peripheral and the second index specifies the bit used to
|
||||
control the peripheral clock in that bus register.
|
||||
|
||||
compatible: "st,stm32-rcc"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
reg:
|
||||
required: true
|
||||
|
||||
"#clock-cells":
|
||||
const: 2
|
||||
|
||||
clock-frequency:
|
||||
required: true
|
||||
type: int
|
||||
description: |
|
||||
default frequency in Hz for clock output
|
||||
|
||||
ahb-prescaler:
|
||||
type: int
|
||||
required: true
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 4
|
||||
- 8
|
||||
- 16
|
||||
- 64
|
||||
- 128
|
||||
- 256
|
||||
- 512
|
||||
description: |
|
||||
AHB prescaler. Sets a HCLK frequency (feeding Cortex-M Systick)
|
||||
lower than SYSCLK frequency (actual core frequency).
|
||||
The HCLK clocks CPU, AHB, memories and DMA.
|
||||
|
||||
apb1-prescaler:
|
||||
type: int
|
||||
required: true
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 4
|
||||
- 8
|
||||
- 16
|
||||
|
||||
apb2-prescaler:
|
||||
type: int
|
||||
required: true
|
||||
enum:
|
||||
- 1
|
||||
- 2
|
||||
- 4
|
||||
- 8
|
||||
- 16
|
||||
|
||||
clock-cells:
|
||||
- bus
|
||||
- bits
|
||||
@@ -0,0 +1,40 @@
|
||||
# Copyright (c) 2021, Linaro ltd
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Main PLL node binding for STM32F0 and STM32F3 devices.
|
||||
|
||||
Takes one of clk_hse or clk_hsi as input clock.
|
||||
|
||||
Note: Some STM32F0 SoC variants (STM32072 for instance) may also support HSI48
|
||||
as input clock. This case is not supported yet.
|
||||
|
||||
Frequency calculation for output clock is as follows:
|
||||
|
||||
f(PLLCLK) = f(PLLIN) x PLLMUL --> SYSCLK (System Clock)
|
||||
|
||||
with, depending on the case:
|
||||
If input_clk = clk_hse
|
||||
f(PLLIN) = f(input_clk) / PREDIV
|
||||
If input_clk = clk_hsi
|
||||
On STM32F3, STM32F03x, STM32F05x, STM32F030x4, STM32F030x6 and STM32F030x8
|
||||
f(PLLIN) = f(input_clk) / 2
|
||||
On STM32F04x, STM32F07x, STM32F09x, STM32F070x6, STM32F070xB and STM32F030xC
|
||||
f(PLLIN) = f(input_clk) / PREDIV
|
||||
|
||||
The PLL output frequency must be set in range 16-48MHz
|
||||
|
||||
compatible: "st,stm32f0-pll-clock"
|
||||
|
||||
include:
|
||||
- name: st,stm32f105-pll-clock.yaml
|
||||
property-blocklist:
|
||||
- mul
|
||||
|
||||
properties:
|
||||
mul:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
PLL multiplication factor for output clock
|
||||
Valid range: 2 - 16
|
||||
@@ -0,0 +1,13 @@
|
||||
# Copyright (c) 2021, Linaro ltd
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
STM32F0 and G0 Reset and Clock controller node.
|
||||
For more description confere st,stm32-rcc.yaml
|
||||
|
||||
compatible: "st,stm32f0-rcc"
|
||||
|
||||
include:
|
||||
- name: st,stm32-rcc.yaml
|
||||
property-blocklist:
|
||||
- apb2-prescaler
|
||||
@@ -0,0 +1,47 @@
|
||||
# Copyright (c) 2021, Linaro ltd
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
description: |
|
||||
Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
|
||||
|
||||
Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
|
||||
as input clock.
|
||||
|
||||
Up to 2 output clocks could be supported and for each output clock, the
|
||||
frequency can be computed with the following formula:
|
||||
|
||||
f(PLLCLK) = f(input clk) x PLLMUL --> SYSCLK (System Clock)
|
||||
f(USBCLK) = f(PLLCLK) / USBPRE --> USB
|
||||
|
||||
The PLL output frequency must not exceed 72 MHz.
|
||||
|
||||
|
||||
compatible: "st,stm32f1-pll-clock"
|
||||
|
||||
include: [clock-controller.yaml, base.yaml]
|
||||
|
||||
properties:
|
||||
"#clock-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
required: true
|
||||
|
||||
mul:
|
||||
type: int
|
||||
required: true
|
||||
description: |
|
||||
Main PLL multiplication factor for VCO
|
||||
Valid range: 2 - 16
|
||||
|
||||
xtpre:
|
||||
type: boolean
|
||||
required: false
|
||||
description: |
|
||||
Otpional HSE divider for PLL entry
|
||||
|
||||
usbpre:
|
||||
type: int
|
||||
required: false
|
||||
description: |
|
||||
Otpional HSE divider for PLL entry
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user