mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-11-14 21:11:36 +08:00
WIP: device tree MVP
This commit is contained in:
Daniel Agar
@@ -0,0 +1,390 @@
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/*
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* Copyright (c) 2017 RnDity Sp. z o.o.
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* Copyright (c) 2019 Centaur Analytics, Inc
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv6-m.dtsi>
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#include <dt-bindings/clock/stm32_clock.h>
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#include <dt-bindings/i2c/i2c.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/pwm/pwm.h>
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#include <freq.h>
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/ {
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chosen {
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zephyr,flash-controller = &flash;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m0";
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reg = <0>;
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};
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};
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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clocks {
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clk_hse: clk-hse {
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#clock-cells = <0>;
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compatible = "st,stm32-hse-clock";
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status = "disabled";
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};
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clk_hsi: clk-hsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(8)>;
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status = "disabled";
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};
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clk_lse: clk-lse {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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status = "disabled";
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};
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clk_lsi: clk-lsi {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_K(40)>;
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status = "disabled";
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};
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pll: pll {
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#clock-cells = <0>;
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compatible = "st,stm32f0-pll-clock";
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status = "disabled";
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};
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};
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soc {
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flash: flash-controller@40022000 {
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compatible = "st,stm32-flash-controller", "st,stm32f0-flash-controller";
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label = "FLASH_CTRL";
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reg = <0x40022000 0x400>;
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interrupts = <3 0>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
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#address-cells = <1>;
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#size-cells = <1>;
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flash0: flash@8000000 {
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compatible = "st,stm32-nv-flash", "soc-nv-flash";
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label = "FLASH_STM32";
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write-block-size = <2>;
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/* maximum erase time for a 2K sector */
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max-erase-time = <40>;
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};
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};
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rcc: rcc@40021000 {
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compatible = "st,stm32f0-rcc";
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#clock-cells = <2>;
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reg = <0x40021000 0x400>;
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};
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exti: interrupt-controller@40010400 {
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compatible = "st,stm32-exti";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0x40010400 0x400>;
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};
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pinctrl: pin-controller@48000000 {
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compatible = "st,stm32-pinctrl";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x48000000 0x1800>;
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gpioa: gpio@48000000 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
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label = "GPIOA";
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};
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gpiob: gpio@48000400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
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label = "GPIOB";
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};
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gpioc: gpio@48000800 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
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label = "GPIOC";
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};
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gpiod: gpio@48000c00 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48000c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
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label = "GPIOD";
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};
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gpiof: gpio@48001400 {
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compatible = "st,stm32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x48001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
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label = "GPIOF";
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};
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};
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usart1: serial@40013800 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40013800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
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interrupts = <27 0>;
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status = "disabled";
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label = "UART_1";
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};
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usart2: serial@40004400 {
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compatible = "st,stm32-usart", "st,stm32-uart";
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reg = <0x40004400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
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interrupts = <28 0>;
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status = "disabled";
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label = "UART_2";
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};
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i2c1: i2c@40005400 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
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interrupts = <23 0>;
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interrupt-names = "combined";
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status = "disabled";
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label= "I2C_1";
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};
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i2c2: i2c@40005800 {
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compatible = "st,stm32-i2c-v2";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40005800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
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interrupts = <24 0>;
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interrupt-names = "combined";
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status = "disabled";
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label= "I2C_2";
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};
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spi1: spi@40013000 {
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compatible = "st,stm32-spi-fifo", "st,stm32-spi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40013000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;
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interrupts = <25 3>;
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status = "disabled";
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label = "SPI_1";
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};
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rtc: rtc@40002800 {
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compatible = "st,stm32-rtc";
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reg = <0x40002800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
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interrupts = <2 0>;
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prescaler = <32768>;
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status = "disabled";
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label = "RTC_0";
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};
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iwdg: watchdog@40003000 {
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compatible = "st,stm32-watchdog";
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reg = <0x40003000 0x400>;
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label = "IWDG";
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};
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wwdg: watchdog@40002c00 {
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compatible = "st,stm32-window-watchdog";
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reg = <0x40002C00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
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label = "WWDG";
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interrupts = <0 2>;
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status = "disabled";
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};
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timers1: timers@40012c00 {
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compatible = "st,stm32-timers";
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reg = <0x40012c00 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
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interrupts = <13 0>, <14 0>;
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interrupt-names = "brk_up_trg_com", "cc";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_1";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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label = "PWM_1";
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#pwm-cells = <3>;
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};
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};
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timers3: timers@40000400 {
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compatible = "st,stm32-timers";
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reg = <0x40000400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
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interrupts = <16 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_3";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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label = "PWM_3";
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#pwm-cells = <3>;
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};
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};
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timers6: timers@40001000 {
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compatible = "st,stm32-timers";
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reg = <0x40001000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
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interrupts = <17 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_6";
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};
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timers7: timers@40001400 {
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compatible = "st,stm32-timers";
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reg = <0x40001400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
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interrupts = <18 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_7";
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};
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timers14: timers@40002000 {
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compatible = "st,stm32-timers";
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reg = <0x40002000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
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interrupts = <19 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_14";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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label = "PWM_14";
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#pwm-cells = <3>;
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};
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};
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timers15: timers@40014000 {
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compatible = "st,stm32-timers";
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reg = <0x40014000 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
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interrupts = <20 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_15";
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pwm {
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compatible = "st,stm32-pwm";
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status = "disabled";
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label = "PWM_15";
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#pwm-cells = <3>;
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};
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};
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timers16: timers@40014400 {
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compatible = "st,stm32-timers";
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reg = <0x40014400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
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interrupts = <21 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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label = "TIMERS_16";
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||||
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pwm {
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||||
compatible = "st,stm32-pwm";
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status = "disabled";
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label = "PWM_16";
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#pwm-cells = <3>;
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};
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};
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timers17: timers@40014800 {
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compatible = "st,stm32-timers";
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reg = <0x40014800 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
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interrupts = <22 0>;
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interrupt-names = "global";
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st,prescaler = <0>;
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status = "disabled";
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||||
label = "TIMERS_17";
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pwm {
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||||
compatible = "st,stm32-pwm";
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status = "disabled";
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||||
label = "PWM_17";
|
||||
#pwm-cells = <3>;
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};
|
||||
};
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adc1: adc@40012400 {
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compatible = "st,stm32-adc";
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reg = <0x40012400 0x400>;
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clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
|
||||
interrupts = <12 0>;
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status = "disabled";
|
||||
label = "ADC_1";
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||||
#io-channel-cells = <1>;
|
||||
};
|
||||
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||||
dma1: dma@40020000 {
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||||
compatible = "st,stm32-dma-v2bis";
|
||||
#dma-cells = <2>;
|
||||
reg = <0x40020000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
|
||||
interrupts = <9 0 10 0 10 0 11 0 11 0>;
|
||||
status = "disabled";
|
||||
label = "DMA_1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <2>;
|
||||
};
|
||||
@@ -0,0 +1,17 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f0/stm32f0.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
erase-block-size = <1024>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f0/stm32f030.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(4)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(16)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <mem.h>
|
||||
#include <st/f0/stm32f030.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(8)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <26 3>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,75 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Intel Corporation.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f0/stm32f030.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(32)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <26 3>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
/*
|
||||
* USARTs 3-6 share the same IRQ on stm32f030Xc devices. This
|
||||
* configuration is not currently supported, so at most one of
|
||||
* these may be enabled at a time. Enabling more than one will
|
||||
* result in a build failure.
|
||||
*/
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
|
||||
interrupts = <29 0>;
|
||||
status = "disabled";
|
||||
label = "UART_3";
|
||||
};
|
||||
|
||||
usart4: serial@40004c00 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
interrupts = <29 0>;
|
||||
status = "disabled";
|
||||
label = "UART_4";
|
||||
};
|
||||
|
||||
usart5: serial@40005000 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
||||
interrupts = <29 0>;
|
||||
status = "disabled";
|
||||
label = "UART_5";
|
||||
};
|
||||
|
||||
usart6: serial@40011400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40011400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
|
||||
interrupts = <29 0>;
|
||||
status = "disabled";
|
||||
label = "UART_6";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f0/stm32f0.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
erase-block-size = <1024>;
|
||||
};
|
||||
};
|
||||
timers2: timers@40000000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
||||
interrupts = <15 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_2";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_2";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f0/stm32f031.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(4)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(32)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Nathan Tsoi <nathan@vertile.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f0/stm32f0.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
erase-block-size = <1024>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <mem.h>
|
||||
#include <st/f0/stm32f051.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(8)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,47 @@
|
||||
/*
|
||||
* Copyright (c) 2018 qianfan Zhao
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f0/stm32f0.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
erase-block-size = <2048>;
|
||||
};
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <26 3>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
usb: usb@40005c00 {
|
||||
compatible = "st,stm32-usb";
|
||||
reg = <0x40005c00 0x400>;
|
||||
interrupts = <31 0>;
|
||||
interrupt-names = "usb";
|
||||
num-bidir-endpoints = <8>;
|
||||
ram-size = <1024>;
|
||||
phys = <&usb_fs_phy>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
||||
status = "disabled";
|
||||
label= "USB";
|
||||
};
|
||||
};
|
||||
|
||||
usb_fs_phy: usbphy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "USB_FS_PHY";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <mem.h>
|
||||
#include <st/f0/stm32f070.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(16)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* Copyright (c) 2017 BayLibre, SAS
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f0/stm32f0.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
erase-block-size = <2048>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@48000000 {
|
||||
|
||||
gpioe: gpio@48001000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
|
||||
label = "GPIOE";
|
||||
};
|
||||
};
|
||||
|
||||
timers2: timers@40000000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
||||
interrupts = <15 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_2";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_2";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <26 3>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
usb: usb@40005c00 {
|
||||
compatible = "st,stm32-usb";
|
||||
reg = <0x40005c00 0x400>;
|
||||
interrupts = <31 0>;
|
||||
interrupt-names = "usb";
|
||||
num-bidir-endpoints = <8>;
|
||||
ram-size = <1024>;
|
||||
phys = <&usb_fs_phy>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
||||
status = "disabled";
|
||||
label= "USB";
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006400 0x400>;
|
||||
interrupts = <30 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
|
||||
status = "disabled";
|
||||
label = "CAN_1";
|
||||
bus-speed = <250000>;
|
||||
sjw = <1>;
|
||||
prop-seg = <0>;
|
||||
phase-seg1 = <5>;
|
||||
phase-seg2 = <6>;
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dma1: dma@40020000 {
|
||||
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_fs_phy: usbphy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "USB_FS_PHY";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <mem.h>
|
||||
#include <st/f0/stm32f072.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(16)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,81 @@
|
||||
/*
|
||||
* Copyright (c) Bobby Noelte
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f0/stm32f0.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
erase-block-size = <2048>;
|
||||
};
|
||||
};
|
||||
|
||||
timers2: timers@40000000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
||||
interrupts = <15 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_2";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_2";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <26 3>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@48000000 {
|
||||
|
||||
gpioe: gpio@48001000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
|
||||
label = "GPIOE";
|
||||
};
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dma1: dma@40020000 {
|
||||
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
|
||||
};
|
||||
|
||||
dma2: dma@40020400 {
|
||||
compatible = "st,stm32-dma-v2bis";
|
||||
#dma-cells = <2>;
|
||||
reg = <0x40020400 0x400>;
|
||||
interrupts = <10 0 10 0 11 0 11 0 11 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <mem.h>
|
||||
#include <st/f0/stm32f091.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(32)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2019 The Chromium OS Authors
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
#include <mem.h>
|
||||
#include <st/f0/stm32f091.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(32)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,333 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
* Copyright (c) 2019 Centaur Analytics, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include <dt-bindings/clock/stm32_clock.h>
|
||||
#include <dt-bindings/i2c/i2c.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <freq.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
zephyr,flash-controller = &flash;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m3";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32-hse-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_M(8)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_K(40)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pll: pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32f1-pll-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
|
||||
flash: flash-controller@40022000 {
|
||||
compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
|
||||
label = "FLASH_CTRL";
|
||||
reg = <0x40022000 0x400>;
|
||||
interrupts = <3 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0: flash@8000000 {
|
||||
compatible = "st,stm32-nv-flash", "soc-nv-flash";
|
||||
label = "FLASH_STM32";
|
||||
|
||||
write-block-size = <2>;
|
||||
/* maximum erase time for a 2K sector */
|
||||
max-erase-time = <40>;
|
||||
};
|
||||
};
|
||||
|
||||
rcc: rcc@40021000 {
|
||||
compatible = "st,stm32-rcc";
|
||||
#clock-cells = <2>;
|
||||
reg = <0x40021000 0x400>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@40010400 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x40010400 0x400>;
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@40010800 {
|
||||
compatible = "st,stm32f1-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40010800 0x1C00>;
|
||||
|
||||
gpioa: gpio@40010800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40010800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000005>;
|
||||
label = "GPIOA";
|
||||
};
|
||||
|
||||
gpiob: gpio@40010c00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40010c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000009>;
|
||||
label = "GPIOB";
|
||||
};
|
||||
|
||||
gpioc: gpio@40011000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40011000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000011>;
|
||||
label = "GPIOC";
|
||||
};
|
||||
|
||||
gpiod: gpio@40011400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40011400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000021>;
|
||||
label = "GPIOD";
|
||||
};
|
||||
|
||||
gpioe: gpio@40011800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40011800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000041>;
|
||||
label = "GPIOE";
|
||||
};
|
||||
};
|
||||
|
||||
usart1: serial@40013800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40013800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
|
||||
interrupts = <37 0>;
|
||||
status = "disabled";
|
||||
label = "UART_1";
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
|
||||
interrupts = <38 0>;
|
||||
status = "disabled";
|
||||
label = "UART_2";
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
|
||||
interrupts = <39 0>;
|
||||
status = "disabled";
|
||||
label = "UART_3";
|
||||
};
|
||||
|
||||
i2c1: i2c@40005400 {
|
||||
compatible = "st,stm32-i2c-v1";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
|
||||
interrupts = <31 0>, <32 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_1";
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32-i2c-v1";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
|
||||
interrupts = <33 0>, <34 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_2";
|
||||
};
|
||||
|
||||
spi1: spi@40013000 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
|
||||
interrupts = <35 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_1";
|
||||
};
|
||||
|
||||
iwdg: watchdog@40003000 {
|
||||
compatible = "st,stm32-watchdog";
|
||||
reg = <0x40003000 0x400>;
|
||||
label = "IWDG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wwdg: watchdog@40002c00 {
|
||||
compatible = "st,stm32-window-watchdog";
|
||||
reg = <0x40002C00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
|
||||
label = "WWDG";
|
||||
interrupts = <0 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timers1: timers@40012c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40012c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
|
||||
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_1";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_1";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers2: timers@40000000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
||||
interrupts = <28 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_2";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_2";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers3: timers@40000400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
|
||||
interrupts = <29 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_3";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_3";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers4: timers@40000800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
||||
interrupts = <30 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_4";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_4";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
adc1: adc@40012400 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x40012400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
|
||||
interrupts = <18 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dma1: dma@40020000 {
|
||||
compatible = "st,stm32-dma-v2bis";
|
||||
#dma-cells = <2>;
|
||||
reg = <0x40020000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
|
||||
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
|
||||
status = "disabled";
|
||||
label = "DMA_1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <4>;
|
||||
};
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Jonas Eriksson, Up to Code AB
|
||||
*
|
||||
* SoC device tree include for STM32F100xB SoCs
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f1.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(8)>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
/delete-node/ pll;
|
||||
|
||||
pll: pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32f100-pll-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(128)>;
|
||||
erase-block-size = <DT_SIZE_K(1)>;
|
||||
};
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Jonas Eriksson, Up to Code AB
|
||||
*
|
||||
* SoC device tree include for STM32F100xE SoCs
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f100Xb.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(32)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
||||
interrupts = <51 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_3";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,67 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f1.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(20)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(64)>;
|
||||
erase-block-size = <DT_SIZE_K(1)>;
|
||||
};
|
||||
};
|
||||
|
||||
/* spi2 is present on all STM32F103x8 SoCs except
|
||||
* STM32F103T8. Delete node in stm32f103t8.dtsi.
|
||||
*/
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
usb: usb@40005c00 {
|
||||
compatible = "st,stm32-usb";
|
||||
reg = <0x40005c00 0x400>;
|
||||
interrupts = <20 0>;
|
||||
interrupt-names = "usb";
|
||||
num-bidir-endpoints = <8>;
|
||||
ram-size = <512>;
|
||||
status = "disabled";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
||||
phys = <&usb_fs_phy>;
|
||||
label= "USB";
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006400 0x400>;
|
||||
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
|
||||
status = "disabled";
|
||||
label = "CAN_1";
|
||||
};
|
||||
};
|
||||
|
||||
usb_fs_phy: usbphy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "USB_FS_PHY";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (c) 2017 I-SENSE group of ICCS
|
||||
*
|
||||
* SoC device tree include for STM32F103xB SoCs
|
||||
* where 'x' is replaced for specific SoCs like {C,R,T,V}
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f103X8.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(128)>;
|
||||
erase-block-size = <DT_SIZE_K(1)>;
|
||||
};
|
||||
};
|
||||
|
||||
/* spi2 is present on all STM32F103xB SoCs except
|
||||
* STM32F103TB. Delete node in stm32f103tb.dtsi.
|
||||
*/
|
||||
};
|
||||
|
||||
};
|
||||
@@ -0,0 +1,166 @@
|
||||
/*
|
||||
* Copyright (c) 2017 I-SENSE group of ICCS
|
||||
*
|
||||
* SoC device tree include for STM32F103xC SoCs
|
||||
* where 'x' is replaced for specific SoCs like {R,V,Z}
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f103Xb.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(48)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(256)>;
|
||||
erase-block-size = <DT_SIZE_K(2)>;
|
||||
};
|
||||
};
|
||||
|
||||
uart4: serial@40004c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
interrupts = <52 0>;
|
||||
status = "disabled";
|
||||
label = "UART_4";
|
||||
};
|
||||
|
||||
uart5: serial@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
||||
interrupts = <53 0>;
|
||||
status = "disabled";
|
||||
label = "UART_5";
|
||||
};
|
||||
|
||||
timers5: timers@40000c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
||||
interrupts = <50 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_5";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_5";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers6: timers@40001000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
||||
interrupts = <54 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_6";
|
||||
};
|
||||
|
||||
timers7: timers@40001400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
||||
interrupts = <55 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_7";
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0X40003c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
||||
interrupts = <51 5>;
|
||||
label = "SPI_3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@40010800 {
|
||||
reg = <0x40010800 0x2000>;
|
||||
|
||||
gpiof: gpio@40011c00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40011c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000081>;
|
||||
label = "GPIOF";
|
||||
};
|
||||
|
||||
gpiog: gpio@40012000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40012000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000101>;
|
||||
label = "GPIOG";
|
||||
};
|
||||
};
|
||||
|
||||
adc2: adc@40012800 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x40012800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
|
||||
/* Shares vector with ADC1 */
|
||||
interrupts = <18 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_2";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
adc3: adc@40013c00 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x40013c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
|
||||
interrupts = <47 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_3";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
timers8: timers@40013400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40013400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
|
||||
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_8";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_8";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
dma2: dma@40020400 {
|
||||
compatible = "st,stm32-dma-v2bis";
|
||||
#dma-cells = <2>;
|
||||
reg = <0x40020400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
|
||||
interrupts = < 56 0 57 0 58 0 59 0 60 0>;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Teltonika
|
||||
*
|
||||
* SoC device tree include for STM32F103xD SoCs
|
||||
* where 'x' is replaced for specific SoCs like {R,V,Z}
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f103Xc.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(384)>;
|
||||
erase-block-size = <DT_SIZE_K(2)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2017 I-SENSE group of ICCS
|
||||
*
|
||||
* SoC device tree include for STM32F103xE SoCs
|
||||
* where 'x' is replaced for specific SoCs like {R,V,Z}
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f103Xd.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
erase-block-size = <DT_SIZE_K(2)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,141 @@
|
||||
/* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Copyright (c) 2020 Google, LLC
|
||||
*
|
||||
* SoC device tree include for STM32F103xG SoCs
|
||||
* where 'x' is replaced for specific SoCs like {R,V,Z}
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f103Xe.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(96)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
/* Note that there are actually two banks of
|
||||
* flash (512KB each) and two flash controllers.
|
||||
* This matters if you're doing in-application
|
||||
* flash programming and you need the
|
||||
* read-while-write capabilities, but is
|
||||
* otherwise a non-issue.
|
||||
*/
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
erase-block-size = <DT_SIZE_K(2)>;
|
||||
};
|
||||
};
|
||||
|
||||
timers9: timers@40014c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
|
||||
/* Shared with TIM1_BRK */
|
||||
interrupts = <24 0>;
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_9";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_9";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers10: timers@40015000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40015000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
||||
/* Shared with TIM1_UP */
|
||||
interrupts = <25 0>;
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_10";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_10";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers11: timers@40015400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40015400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
|
||||
/* Shared with TIM1_TRG_COM */
|
||||
interrupts = <26 0>;
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_11";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_11";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers12: timers@40001800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
|
||||
/* Shared with TIM8_BRK */
|
||||
interrupts = <43 0>;
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_12";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_12";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers13: timers@40001c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
|
||||
/* Shared with TIM8_UP */
|
||||
interrupts = <44 0>;
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_13";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_13";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers14: timers@40002000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40002000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
|
||||
/* Shared with TIM8_TRG_COM */
|
||||
interrupts = <45 0>;
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_14";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_14";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,141 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Argentum Systems Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f1/stm32f1.dtsi>
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
/delete-node/ pll;
|
||||
|
||||
pll: pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32f105-pll-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pll2: pll2 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32f105-pll2-clock";
|
||||
clocks = <&clk_hse>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
erase-block-size = <DT_SIZE_K(2)>;
|
||||
};
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006400 0x400>;
|
||||
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
|
||||
status = "disabled";
|
||||
label = "CAN_1";
|
||||
bus-speed = <250000>;
|
||||
sjw = <1>;
|
||||
prop-seg = <0>;
|
||||
phase-seg1 = <5>;
|
||||
phase-seg2 = <6>;
|
||||
};
|
||||
|
||||
can2: can@40006800 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006800 0x400>;
|
||||
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
|
||||
status = "disabled";
|
||||
label = "CAN_2";
|
||||
bus-speed = <250000>;
|
||||
sjw = <1>;
|
||||
prop-seg = <0>;
|
||||
phase-seg1 = <5>;
|
||||
phase-seg2 = <6>;
|
||||
};
|
||||
|
||||
uart4: serial@40004c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
interrupts = <52 0>;
|
||||
status = "disabled";
|
||||
label = "UART_4";
|
||||
};
|
||||
|
||||
uart5: serial@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
||||
interrupts = <53 0>;
|
||||
status = "disabled";
|
||||
label = "UART_5";
|
||||
};
|
||||
|
||||
timers5: timers@40000c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
||||
interrupts = <50 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_5";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_5";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers6: timers@40001000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
||||
interrupts = <54 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_6";
|
||||
};
|
||||
|
||||
timers7: timers@40001400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
||||
interrupts = <55 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_7";
|
||||
};
|
||||
|
||||
usbotg_fs: usb@50000000 {
|
||||
compatible = "st,stm32-otgfs";
|
||||
reg = <0x50000000 0x40000>;
|
||||
interrupts = <67 0>;
|
||||
interrupt-names = "otgfs";
|
||||
num-bidir-endpoints = <4>;
|
||||
ram-size = <1280>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00001000>;
|
||||
phys = <&otgfs_phy>;
|
||||
status = "disabled";
|
||||
label = "OTGFS";
|
||||
};
|
||||
};
|
||||
|
||||
otgfs_phy: otgfs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "OTGFS_PHY";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Argentum Systems Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f105.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2017 I-SENSE group of ICCS
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f1/stm32f105.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
dma2: dma@40020400 {
|
||||
compatible = "st,stm32-dma-v2bis";
|
||||
#dma-cells = <2>;
|
||||
reg = <0x40020400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
|
||||
interrupts = <56 0 57 0 58 0 59 0 60 0>;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f1/stm32f107.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,570 @@
|
||||
/*
|
||||
* Copyright (c) 2018 qianfan Zhao
|
||||
* Copyright (c) 2019 Centaur Analytics, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include <dt-bindings/clock/stm32_clock.h>
|
||||
#include <dt-bindings/i2c/i2c.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <freq.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
zephyr,entropy = &rng;
|
||||
zephyr,flash-controller = &flash;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m3";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32-hse-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_M(16)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_K(32)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pll: pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32f2-pll-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
flash: flash-controller@40023c00 {
|
||||
compatible = "st,stm32-flash-controller", "st,stm32f2-flash-controller";
|
||||
label = "FLASH_CTRL";
|
||||
reg = <0x40023c00 0x400>;
|
||||
interrupts = <4 0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0: flash@8000000 {
|
||||
compatible = "st,stm32-nv-flash", "soc-nv-flash";
|
||||
label = "FLASH_STM32";
|
||||
|
||||
write-block-size = <1>;
|
||||
/* maximum erase time(ms) for a 128K sector */
|
||||
max-erase-time = <4000>;
|
||||
};
|
||||
};
|
||||
|
||||
rcc: rcc@40023800 {
|
||||
compatible = "st,stm32-rcc";
|
||||
#clock-cells = <2>;
|
||||
reg = <0x40023800 0x400>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@40013c00 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x40013c00 0x400>;
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@40020000 {
|
||||
compatible = "st,stm32-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40020000 0x2000>;
|
||||
|
||||
gpioa: gpio@40020000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
|
||||
label = "GPIOA";
|
||||
};
|
||||
|
||||
gpiob: gpio@40020400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
|
||||
label = "GPIOB";
|
||||
};
|
||||
|
||||
gpioc: gpio@40020800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
|
||||
label = "GPIOC";
|
||||
};
|
||||
|
||||
gpiod: gpio@40020c00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
|
||||
label = "GPIOD";
|
||||
};
|
||||
|
||||
gpioe: gpio@40021000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
|
||||
label = "GPIOE";
|
||||
};
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
|
||||
label = "GPIOF";
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
|
||||
label = "GPIOG";
|
||||
};
|
||||
|
||||
gpioh: gpio@40021c00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
|
||||
label = "GPIOH";
|
||||
};
|
||||
|
||||
gpioi: gpio@40022000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
|
||||
label = "GPIOI";
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc@40002800 {
|
||||
compatible = "st,stm32-rtc";
|
||||
reg = <0x40002800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
|
||||
interrupts = <41 0>;
|
||||
prescaler = <32768>;
|
||||
status = "disabled";
|
||||
label = "RTC_0";
|
||||
};
|
||||
|
||||
iwdg: watchdog@40003000 {
|
||||
compatible = "st,stm32-watchdog";
|
||||
reg = <0x40003000 0x400>;
|
||||
label = "IWDG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wwdg: watchdog@40002c00 {
|
||||
compatible = "st,stm32-window-watchdog";
|
||||
reg = <0x40002C00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
|
||||
label = "WWDG";
|
||||
interrupts = <0 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@40011000 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
|
||||
interrupts = <37 0>;
|
||||
status = "disabled";
|
||||
label = "UART_1";
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
|
||||
interrupts = <38 0>;
|
||||
status = "disabled";
|
||||
label = "UART_2";
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
|
||||
interrupts = <39 0>;
|
||||
status = "disabled";
|
||||
label = "UART_3";
|
||||
};
|
||||
|
||||
usart6: serial@40011400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40011400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
|
||||
interrupts = <71 0>;
|
||||
status = "disabled";
|
||||
label = "UART_6";
|
||||
};
|
||||
|
||||
uart4: serial@40004c00 {
|
||||
compatible ="st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
interrupts = <52 0>;
|
||||
status = "disabled";
|
||||
label = "UART_4";
|
||||
};
|
||||
|
||||
uart5: serial@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
||||
interrupts = <53 0>;
|
||||
status = "disabled";
|
||||
label = "UART_5";
|
||||
};
|
||||
|
||||
spi1: spi@40013000 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
|
||||
interrupts = <35 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_1";
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
||||
interrupts = <51 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_3";
|
||||
};
|
||||
|
||||
i2c1: i2c@40005400 {
|
||||
compatible = "st,stm32-i2c-v1";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
|
||||
interrupts = <31 0>, <32 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_1";
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32-i2c-v1";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
|
||||
interrupts = <33 0>, <34 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_2";
|
||||
};
|
||||
|
||||
i2c3: i2c@40005c00 {
|
||||
compatible = "st,stm32-i2c-v1";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
||||
interrupts = <72 0>, <73 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_3";
|
||||
};
|
||||
|
||||
usbotg_fs: usb@50000000 {
|
||||
compatible = "st,stm32-otgfs";
|
||||
reg = <0x50000000 0x40000>;
|
||||
interrupts = <67 0>;
|
||||
interrupt-names = "otgfs";
|
||||
num-bidir-endpoints = <4>;
|
||||
ram-size = <1280>;
|
||||
maximum-speed = "full-speed";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
|
||||
phys = <&otgfs_phy>;
|
||||
status = "disabled";
|
||||
label = "OTGFS";
|
||||
};
|
||||
|
||||
adc1: adc@40012000 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x40012000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
|
||||
interrupts = <18 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dma1: dma@40026000 {
|
||||
compatible = "st,stm32-dma-v1";
|
||||
#dma-cells = <4>;
|
||||
reg = <0x40026000 0x400>;
|
||||
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
|
||||
status = "disabled";
|
||||
label = "DMA_1";
|
||||
};
|
||||
|
||||
dma2: dma@40026400 {
|
||||
compatible = "st,stm32-dma-v1";
|
||||
#dma-cells = <4>;
|
||||
reg = <0x40026400 0x400>;
|
||||
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
|
||||
st,mem2mem;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
timers1: timers@40010000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
|
||||
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_1";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_1";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers2: timers@40000000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
||||
interrupts = <28 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_2";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_2";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers3: timers@40000400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
|
||||
interrupts = <29 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_3";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_3";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers4: timers@40000800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
||||
interrupts = <30 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_4";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_4";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers5: timers@40000c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
||||
interrupts = <50 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_5";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_5";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers8: timers@40010400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
|
||||
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_8";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_8";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers9: timers@40014000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
|
||||
interrupts = <24 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_9";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_9";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers12: timers@40001800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
|
||||
interrupts = <43 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_12";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_12";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
rng: rng@50060800 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x50060800 0x400>;
|
||||
interrupts = <80 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
|
||||
status = "disabled";
|
||||
label = "RNG";
|
||||
};
|
||||
|
||||
backup_sram: memory@40024000 {
|
||||
compatible = "st,stm32-backup-sram";
|
||||
reg = <0x40024000 DT_SIZE_K(4)>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
||||
label = "BACKUP_SRAM";
|
||||
zephyr,memory-region = "BACKUP_SRAM";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
otgfs_phy: otgfs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "OTGFS_PHY";
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <4>;
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Manuel Forcen <manuforcen@gmail.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f2/stm32f2.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2018 qianfan Zhao
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f2/stm32f2.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
mac: ethernet@40028000 {
|
||||
compatible = "st,stm32-ethernet";
|
||||
reg = <0x40028000 0x8000>;
|
||||
label = "ETH_0";
|
||||
interrupts = <61 0>;
|
||||
clock-names = "stmmaceth", "mac-clk-tx",
|
||||
"mac-clk-rx", "mac-clk-ptp";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f2/stm32f207.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f2/stm32f207.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,413 @@
|
||||
/*
|
||||
* Copyright (c) 2017 I-SENSE group of ICCS
|
||||
* Copyright (c) 2019 Centaur Analytics, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include <dt-bindings/clock/stm32_clock.h>
|
||||
#include <dt-bindings/i2c/i2c.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <freq.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
zephyr,flash-controller = &flash;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m4f";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
};
|
||||
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32-hse-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_M(8)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_K(40)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pll: pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32f0-pll-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
flash: flash-controller@40022000 {
|
||||
compatible = "st,stm32-flash-controller", "st,stm32f3-flash-controller";
|
||||
label = "FLASH_CTRL";
|
||||
reg = <0x40022000 0x400>;
|
||||
interrupts = <4 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0: flash@8000000 {
|
||||
compatible = "st,stm32-nv-flash", "soc-nv-flash";
|
||||
label = "FLASH_STM32";
|
||||
|
||||
write-block-size = <2>;
|
||||
erase-block-size = <2048>;
|
||||
/* maximum erase time for a 2K sector */
|
||||
max-erase-time = <40>;
|
||||
};
|
||||
};
|
||||
|
||||
rcc: rcc@40021000 {
|
||||
compatible = "st,stm32-rcc";
|
||||
#clock-cells = <2>;
|
||||
reg = <0x40021000 0x400>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@40010400 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x40010400 0x400>;
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@48000000 {
|
||||
compatible = "st,stm32-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x48000000 0x1800>;
|
||||
|
||||
gpioa: gpio@48000000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
|
||||
label = "GPIOA";
|
||||
};
|
||||
|
||||
gpiob: gpio@48000400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48000400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
||||
label = "GPIOB";
|
||||
};
|
||||
|
||||
gpioc: gpio@48000800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48000800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
|
||||
label = "GPIOC";
|
||||
};
|
||||
|
||||
gpiod: gpio@48000c00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
|
||||
label = "GPIOD";
|
||||
};
|
||||
|
||||
gpiof: gpio@48001400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
|
||||
label = "GPIOF";
|
||||
};
|
||||
};
|
||||
|
||||
iwdg: watchdog@40003000 {
|
||||
compatible = "st,stm32-watchdog";
|
||||
reg = <0x40003000 0x400>;
|
||||
label = "IWDG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wwdg: watchdog@40002c00 {
|
||||
compatible = "st,stm32-window-watchdog";
|
||||
reg = <0x40002C00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
|
||||
label = "WWDG";
|
||||
interrupts = <0 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@40013800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40013800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
|
||||
interrupts = <37 0>;
|
||||
status = "disabled";
|
||||
label = "UART_1";
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
|
||||
interrupts = <38 0>;
|
||||
status = "disabled";
|
||||
label = "UART_2";
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
|
||||
interrupts = <39 0>;
|
||||
status = "disabled";
|
||||
label = "UART_3";
|
||||
};
|
||||
|
||||
uart4: serial@40004c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
interrupts = <52 0>;
|
||||
status = "disabled";
|
||||
label = "UART_4";
|
||||
};
|
||||
|
||||
i2c1: i2c@40005400 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
|
||||
interrupts = <31 0>, <32 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_1";
|
||||
};
|
||||
|
||||
spi1: spi@40013000 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
|
||||
interrupts = <35 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_1";
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
usb: usb@40005c00 {
|
||||
compatible = "st,stm32-usb";
|
||||
reg = <0x40005c00 0x400>;
|
||||
interrupts = <20 0>;
|
||||
interrupt-names = "usb";
|
||||
num-bidir-endpoints = <8>;
|
||||
ram-size = <512>;
|
||||
phys = <&usb_fs_phy>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
||||
status = "disabled";
|
||||
label= "USB";
|
||||
};
|
||||
|
||||
timers2: timers@40000000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
||||
interrupts = <28 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_2";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_2";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers3: timers@40000400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
|
||||
interrupts = <29 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_3";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_3";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers6: timers@40001000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
||||
interrupts = <54 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_6";
|
||||
};
|
||||
|
||||
timers7: timers@40001400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
||||
interrupts = <55 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_7";
|
||||
};
|
||||
|
||||
timers15: timers@40014000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
|
||||
interrupts = <24 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_15";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_15";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers16: timers@40014400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
|
||||
interrupts = <25 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_16";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_16";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers17: timers@40014800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
|
||||
interrupts = <26 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_17";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_17";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc@40002800 {
|
||||
compatible = "st,stm32-rtc";
|
||||
reg = <0x40002800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
|
||||
interrupts = <41 0>;
|
||||
prescaler = <32768>;
|
||||
status = "disabled";
|
||||
label = "RTC_0";
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006400 0x400>;
|
||||
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
|
||||
status = "disabled";
|
||||
label = "CAN_1";
|
||||
bus-speed = <125000>;
|
||||
sjw = <1>;
|
||||
prop-seg = <0>;
|
||||
phase-seg1 = <5>;
|
||||
phase-seg2 = <6>;
|
||||
};
|
||||
|
||||
dma1: dma@40020000 {
|
||||
compatible = "st,stm32-dma-v2bis";
|
||||
#dma-cells = <2>;
|
||||
reg = <0x40020000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
|
||||
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
|
||||
status = "disabled";
|
||||
label = "DMA_1";
|
||||
};
|
||||
};
|
||||
|
||||
usb_fs_phy: usbphy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "USB_FS_PHY";
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <4>;
|
||||
};
|
||||
@@ -0,0 +1,92 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Seitz & Associates
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f3/stm32f3.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
usb: usb@40005c00 {
|
||||
/* Remap USB_LP IRQ to enable use with CAN_1 */
|
||||
interrupts = <75 0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
|
||||
interrupts = <33 0>, <34 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_2";
|
||||
};
|
||||
|
||||
i2c3: i2c@40007800 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40007800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
|
||||
interrupts = <72 0>, <73 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_3";
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0X40003c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
||||
interrupts = <51 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_3";
|
||||
};
|
||||
|
||||
timers1: timers@40012c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40012c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
|
||||
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_1";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_1";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
adc1: adc@50000000 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x50000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
||||
interrupts = <18 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Seitz & Associates
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f3/stm32f302.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(16)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/delete-node/ &spi1;
|
||||
@@ -0,0 +1,134 @@
|
||||
/*
|
||||
* Copyright (c) 2017 I-SENSE group of ICCS
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f3/stm32f3.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
usb: usb@40005c00 {
|
||||
/* Remap USB_LP IRQ to enable use with CAN_1 */
|
||||
interrupts = <75 0>;
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
|
||||
interrupts = <33 0>, <34 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_2";
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@48000000 {
|
||||
|
||||
gpioe: gpio@48001000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
|
||||
label = "GPIOE";
|
||||
};
|
||||
};
|
||||
|
||||
timers1: timers@40012c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40012c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
|
||||
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_1";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_1";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers4: timers@40000800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
||||
interrupts = <30 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_4";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_4";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers8: timers@40013400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40013400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
|
||||
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_8";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_8";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers20: timers@40015000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40015000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
||||
interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_20";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_20";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
adc1: adc@50000000 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x50000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
||||
interrupts = <18 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
|
||||
* Fabian Paschke <fabian.paschke@eas.iis.fraunhofer.de>
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f3/stm32f303.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(8)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(12)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
};
|
||||
|
||||
dac2: dac@40009800 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40009800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_2";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f3/stm32f303.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(8)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(40)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
|
||||
dma2: dma@40020400 {
|
||||
compatible = "st,stm32-dma-v2bis";
|
||||
#dma-cells = <2>;
|
||||
reg = <0x40020400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
|
||||
interrupts = <56 0 57 0 58 0 59 0 60 0>;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,38 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Paul M. Bendixen
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f3/stm32f303.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(16)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
|
||||
dma2: dma@40020400 {
|
||||
compatible = "st,stm32-dma-v2bis";
|
||||
#dma-cells = <2>;
|
||||
reg = <0x40020400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
|
||||
interrupts = <56 0 57 0 58 0 59 0 60 0>;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,41 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f3/stm32f3.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
timers1: timers@40012c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40012c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
|
||||
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_1";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_1";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
adc1: adc@50000000 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x50000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
||||
interrupts = <18 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/delete-node/ &usb;
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f3/stm32f334.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(4)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(12)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
};
|
||||
|
||||
dac2: dac@40009800 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40009800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_2";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,194 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f3/stm32f3.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@48000000 {
|
||||
gpioe: gpio@48001000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x48001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
|
||||
label = "GPIOE";
|
||||
};
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
|
||||
interrupts = <33 0>, <34 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_2";
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
||||
interrupts = <51 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_3";
|
||||
};
|
||||
|
||||
timers4: timers@40000800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
||||
interrupts = <30 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_4";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_4";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers5: timers@40000c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
||||
interrupts = <50 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_5";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_5";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers12: timers@40001800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
|
||||
interrupts = <43 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_12";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_12";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers13: timers@40001c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
|
||||
interrupts = <44 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_13";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_13";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers14: timers@40002000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40002000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
|
||||
interrupts = <45 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_14";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_14";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers18: timers@40009c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40009c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
|
||||
interrupts = <27 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_18";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_18";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers19: timers@40015c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40015c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
|
||||
interrupts = <78 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_19";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_19";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
adc1: adc@40012400 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x40012400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
|
||||
interrupts = <18 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,40 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f3/stm32f373.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(32)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40022000 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
|
||||
dma2: dma@40020400 {
|
||||
compatible = "st,stm32-dma-v2bis";
|
||||
reg = <0x40020400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
|
||||
interrupts = <56 0 57 0 58 0 59 0 60 0>;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
|
||||
dac2: dac@40009800 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40009800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_2";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,526 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
* Copyright (c) 2019 Centaur Analytics, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include <dt-bindings/clock/stm32_clock.h>
|
||||
#include <dt-bindings/i2c/i2c.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <freq.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
zephyr,flash-controller = &flash;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m4f";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32-hse-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_M(16)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_K(32)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pll: pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32f4-pll-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
flash: flash-controller@40023c00 {
|
||||
compatible = "st,stm32-flash-controller", "st,stm32f4-flash-controller";
|
||||
label = "FLASH_CTRL";
|
||||
reg = <0x40023c00 0x400>;
|
||||
interrupts = <4 0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0: flash@8000000 {
|
||||
compatible = "st,stm32-nv-flash", "soc-nv-flash";
|
||||
label = "FLASH_STM32";
|
||||
|
||||
write-block-size = <1>;
|
||||
/* maximum erase time (ms) for a 128K sector */
|
||||
max-erase-time = <4000>;
|
||||
};
|
||||
};
|
||||
|
||||
rcc: rcc@40023800 {
|
||||
compatible = "st,stm32-rcc";
|
||||
#clock-cells = <2>;
|
||||
reg = <0x40023800 0x400>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@40013c00 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x40013c00 0x400>;
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@40020000 {
|
||||
compatible = "st,stm32-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40020000 0x2000>;
|
||||
|
||||
gpioa: gpio@40020000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
|
||||
label = "GPIOA";
|
||||
};
|
||||
|
||||
gpiob: gpio@40020400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
|
||||
label = "GPIOB";
|
||||
};
|
||||
|
||||
gpioc: gpio@40020800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
|
||||
label = "GPIOC";
|
||||
};
|
||||
|
||||
gpiod: gpio@40020c00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
|
||||
label = "GPIOD";
|
||||
};
|
||||
|
||||
gpioe: gpio@40021000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
|
||||
label = "GPIOE";
|
||||
};
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
|
||||
label = "GPIOF";
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
|
||||
label = "GPIOG";
|
||||
};
|
||||
|
||||
gpioh: gpio@40021c00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
|
||||
label = "GPIOH";
|
||||
};
|
||||
};
|
||||
|
||||
iwdg: watchdog@40003000 {
|
||||
compatible = "st,stm32-watchdog";
|
||||
reg = <0x40003000 0x400>;
|
||||
label = "IWDG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wwdg: watchdog@40002c00 {
|
||||
compatible = "st,stm32-window-watchdog";
|
||||
reg = <0x40002C00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
|
||||
label = "WWDG";
|
||||
interrupts = <0 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@40011000 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
|
||||
interrupts = <37 0>;
|
||||
status = "disabled";
|
||||
label = "UART_1";
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
|
||||
interrupts = <38 0>;
|
||||
status = "disabled";
|
||||
label = "UART_2";
|
||||
};
|
||||
|
||||
usart6: serial@40011400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40011400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
|
||||
interrupts = <71 0>;
|
||||
status = "disabled";
|
||||
label = "UART_6";
|
||||
};
|
||||
|
||||
i2c1: i2c@40005400 {
|
||||
compatible = "st,stm32-i2c-v1";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
|
||||
interrupts = <31 0>, <32 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_1";
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32-i2c-v1";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
|
||||
interrupts = <33 0>, <34 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_2";
|
||||
};
|
||||
|
||||
i2c3: i2c@40005c00 {
|
||||
compatible = "st,stm32-i2c-v1";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
||||
interrupts = <72 0>, <73 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label= "I2C_3";
|
||||
};
|
||||
|
||||
spi1: spi@40013000 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
|
||||
interrupts = <35 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_1";
|
||||
};
|
||||
|
||||
usbotg_fs: usb@50000000 {
|
||||
compatible = "st,stm32-otgfs";
|
||||
reg = <0x50000000 0x40000>;
|
||||
interrupts = <67 0>;
|
||||
interrupt-names = "otgfs";
|
||||
num-bidir-endpoints = <4>;
|
||||
ram-size = <1280>;
|
||||
maximum-speed = "full-speed";
|
||||
phys = <&otgfs_phy>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
|
||||
status = "disabled";
|
||||
label= "OTGFS";
|
||||
};
|
||||
|
||||
timers1: timers@40010000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
|
||||
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_1";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_1";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers2: timers@40000000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
||||
interrupts = <28 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_2";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_2";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_2";
|
||||
};
|
||||
};
|
||||
|
||||
timers3: timers@40000400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
|
||||
interrupts = <29 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_3";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_3";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_3";
|
||||
};
|
||||
};
|
||||
|
||||
timers4: timers@40000800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
||||
interrupts = <30 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_4";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_4";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_4";
|
||||
};
|
||||
};
|
||||
|
||||
timers5: timers@40000c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
||||
interrupts = <50 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_5";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_5";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_5";
|
||||
};
|
||||
};
|
||||
|
||||
timers9: timers@40014000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
|
||||
interrupts = <24 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_9";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_9";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_9";
|
||||
};
|
||||
};
|
||||
|
||||
timers10: timers@40014400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
|
||||
interrupts = <25 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_10";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_10";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_10";
|
||||
};
|
||||
};
|
||||
|
||||
timers11: timers@40014800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
|
||||
interrupts = <26 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_11";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_11";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_11";
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc@40002800 {
|
||||
compatible = "st,stm32-rtc";
|
||||
reg = <0x40002800 0x400>;
|
||||
interrupts = <41 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
|
||||
prescaler = <32768>;
|
||||
status = "disabled";
|
||||
label = "RTC_0";
|
||||
};
|
||||
|
||||
adc1: adc@40012000 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x40012000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
|
||||
interrupts = <18 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dma1: dma@40026000 {
|
||||
compatible = "st,stm32-dma-v1";
|
||||
#dma-cells = <4>;
|
||||
reg = <0x40026000 0x400>;
|
||||
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
|
||||
status = "disabled";
|
||||
label = "DMA_1";
|
||||
};
|
||||
|
||||
dma2: dma@40026400 {
|
||||
compatible = "st,stm32-dma-v1";
|
||||
#dma-cells = <4>;
|
||||
reg = <0x40026400 0x400>;
|
||||
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
|
||||
st,mem2mem;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
};
|
||||
|
||||
otgfs_phy: otgfs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "OTGFS_PHY";
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <4>;
|
||||
};
|
||||
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f4.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
||||
interrupts = <51 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_3";
|
||||
};
|
||||
|
||||
spi4: spi@40013400 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
|
||||
interrupts = <84 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_4";
|
||||
};
|
||||
|
||||
i2s2: i2s@40003800 {
|
||||
compatible = "st,stm32-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
dmas = <&dma1 4 0 0x400 0x3
|
||||
&dma1 3 0 0x400 0x3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
label = "I2S_2";
|
||||
};
|
||||
|
||||
i2s3: i2s@40003c00 {
|
||||
compatible = "st,stm32-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
||||
interrupts = <51 5>;
|
||||
dmas = <&dma1 5 0 0x400 0x3
|
||||
&dma1 0 0 0x400 0x3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
label = "I2S_3";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Linumiz
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f401.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(64)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f401.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(96)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,275 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f401.dtsi>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
zephyr,entropy = &rng;
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl: pin-controller@40020000 {
|
||||
reg = <0x40020000 0x2400>;
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
|
||||
label = "GPIOF";
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
|
||||
label = "GPIOG";
|
||||
};
|
||||
|
||||
gpioi: gpio@40022000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
|
||||
label = "GPIOI";
|
||||
};
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
|
||||
interrupts = <39 0>;
|
||||
status = "disabled";
|
||||
label = "UART_3";
|
||||
};
|
||||
|
||||
uart4: serial@40004c00 {
|
||||
compatible ="st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
interrupts = <52 0>;
|
||||
status = "disabled";
|
||||
label = "UART_4";
|
||||
};
|
||||
|
||||
uart5: serial@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
||||
interrupts = <53 0>;
|
||||
status = "disabled";
|
||||
label = "UART_5";
|
||||
};
|
||||
|
||||
timers6: timers@40001000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
||||
interrupts = <54 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_6";
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_6";
|
||||
};
|
||||
};
|
||||
|
||||
timers7: timers@40001400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
||||
interrupts = <55 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_7";
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_7";
|
||||
};
|
||||
};
|
||||
|
||||
timers8: timers@40010400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
|
||||
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_8";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_8";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers12: timers@40001800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
|
||||
interrupts = <43 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_12";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_12";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_12";
|
||||
};
|
||||
};
|
||||
|
||||
timers13: timers@40001c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
|
||||
interrupts = <44 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_13";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_13";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_13";
|
||||
};
|
||||
};
|
||||
|
||||
timers14: timers@40002000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40002000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
|
||||
interrupts = <45 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_14";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_14";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_14";
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_hs: usb@40040000 {
|
||||
compatible = "st,stm32-otghs";
|
||||
reg = <0x40040000 0x40000>;
|
||||
interrupts = <77 0>, <74 0>, <75 0>;
|
||||
interrupt-names = "otghs", "ep1_out", "ep1_in";
|
||||
num-bidir-endpoints = <6>;
|
||||
ram-size = <4096>;
|
||||
maximum-speed = "full-speed";
|
||||
phys = <&otghs_fs_phy>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label= "OTGHS";
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006400 0x400>;
|
||||
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
|
||||
status = "disabled";
|
||||
label = "CAN_1";
|
||||
bus-speed = <125000>;
|
||||
sjw = <1>;
|
||||
prop-seg = <0>;
|
||||
phase-seg1 = <5>;
|
||||
phase-seg2 = <6>;
|
||||
};
|
||||
|
||||
can2: can@40006800 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006800 0x400>;
|
||||
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
|
||||
master-can-reg = <0x40006400>;
|
||||
status = "disabled";
|
||||
label = "CAN_2";
|
||||
bus-speed = <125000>;
|
||||
sjw = <1>;
|
||||
prop-seg = <0>;
|
||||
phase-seg1 = <5>;
|
||||
phase-seg2 = <6>;
|
||||
};
|
||||
|
||||
rng: rng@50060800 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x50060800 0x400>;
|
||||
interrupts = <80 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
|
||||
status = "disabled";
|
||||
label = "RNG";
|
||||
};
|
||||
|
||||
backup_sram: memory@40024000 {
|
||||
compatible = "st,stm32-backup-sram";
|
||||
reg = <0x40024000 DT_SIZE_K(4)>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
||||
label = "BACKUP_SRAM";
|
||||
zephyr,memory-region = "BACKUP_SRAM";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
otghs_fs_phy: otghs_fs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "OTGHS_FS_PHY";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f405.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,25 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f405.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
mac: ethernet@40028000 {
|
||||
compatible = "st,stm32-ethernet";
|
||||
reg = <0x40028000 0x8000>;
|
||||
label = "ETH_0";
|
||||
interrupts = <61 0>;
|
||||
clock-names = "stmmaceth", "mac-clk-tx",
|
||||
"mac-clk-rx", "mac-clk-ptp";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Intel Corporation
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f407.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f407.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,103 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Hans Unzner
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f4.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
spi5: spi@40015000 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
||||
interrupts = <85 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_5";
|
||||
};
|
||||
|
||||
i2s1: i2s@40013000 {
|
||||
compatible = "st,stm32-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
|
||||
interrupts = <35 5>;
|
||||
dmas = <&dma2 3 3 0x400 0x3
|
||||
&dma2 2 3 0x400 0x3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
label = "I2S_1";
|
||||
};
|
||||
|
||||
i2s2: i2s@40003800 {
|
||||
compatible = "st,stm32-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
dmas = <&dma1 4 0 0x400 0x3
|
||||
&dma1 3 0 0x400 0x3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
label = "I2S_2";
|
||||
};
|
||||
|
||||
i2s5: i2s@40015000 {
|
||||
compatible = "st,stm32-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
||||
interrupts = <85 5>;
|
||||
dmas = <&dma2 6 7 0x400 0x3
|
||||
&dma2 5 7 0x400 0x3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
label = "I2S_5";
|
||||
};
|
||||
|
||||
timers6: timers@40001000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
||||
interrupts = <54 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_6";
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_6";
|
||||
};
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Hans Unzner
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f410.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(32)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,64 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f401.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
spi5: spi@40015000 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
||||
interrupts = <85 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_5";
|
||||
};
|
||||
|
||||
i2s1: i2s@40013000 {
|
||||
compatible = "st,stm32-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
|
||||
interrupts = <35 5>;
|
||||
dmas = <&dma2 3 3 0x400 0x3
|
||||
&dma2 2 3 0x400 0x3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
label = "I2S_1";
|
||||
};
|
||||
|
||||
i2s4: i2s@40013400 {
|
||||
compatible = "st,stm32-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
|
||||
interrupts = <84 5>;
|
||||
dmas = <&dma2 1 4 0x400 0x3
|
||||
&dma2 0 4 0x400 0x3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
label = "I2S_4";
|
||||
};
|
||||
|
||||
i2s5: i2s@40015000 {
|
||||
compatible = "st,stm32-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
||||
interrupts = <85 5>;
|
||||
dmas = <&dma2 6 7 0x400 0x3
|
||||
&dma2 5 7 0x400 0x3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
label = "I2S_5";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f411.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,194 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Florian Vaussard, HEIG-VD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f411.dtsi>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
zephyr,entropy = &rng;
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl: pin-controller@40020000 {
|
||||
reg = <0x40020000 0x1c00>;
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
|
||||
label = "GPIOF";
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
|
||||
label = "GPIOG";
|
||||
};
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
|
||||
interrupts = <39 0>;
|
||||
status = "disabled";
|
||||
label = "UART_3";
|
||||
};
|
||||
|
||||
timers6: timers@40001000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
||||
interrupts = <54 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_6";
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_6";
|
||||
};
|
||||
};
|
||||
|
||||
timers7: timers@40001400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
||||
interrupts = <55 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_7";
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_7";
|
||||
};
|
||||
};
|
||||
|
||||
timers8: timers@40010400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
|
||||
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_8";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_8";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers12: timers@40001800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
|
||||
interrupts = <43 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_12";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_12";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_12";
|
||||
};
|
||||
};
|
||||
|
||||
timers13: timers@40001c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
|
||||
interrupts = <44 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_13";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_13";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_13";
|
||||
};
|
||||
};
|
||||
|
||||
timers14: timers@40002000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40002000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
|
||||
interrupts = <45 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_14";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_14";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
counter {
|
||||
compatible = "st,stm32-counter";
|
||||
status = "disabled";
|
||||
label = "COUNTER_14";
|
||||
};
|
||||
};
|
||||
|
||||
rng: rng@50060800 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x50060800 0x400>;
|
||||
interrupts = <80 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
|
||||
status = "disabled";
|
||||
label = "RNG";
|
||||
};
|
||||
|
||||
usbotg_fs: usb@50000000 {
|
||||
num-bidir-endpoints = <6>;
|
||||
};
|
||||
|
||||
quadspi: quadspi@a0001000 {
|
||||
compatible = "st,stm32-qspi";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
reg = <0xa0001000 0x400>;
|
||||
interrupts = <92 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000002>;
|
||||
status = "disabled";
|
||||
label = "QUADSPI";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f412.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f412.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(256)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,74 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Florian Vaussard, HEIG-VD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f412.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
uart4: serial@40004c00 {
|
||||
compatible ="st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
interrupts = <52 0>;
|
||||
status = "disabled";
|
||||
label = "UART_4";
|
||||
};
|
||||
|
||||
uart5: serial@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
||||
interrupts = <53 0>;
|
||||
status = "disabled";
|
||||
label = "UART_5";
|
||||
};
|
||||
|
||||
uart7: serial@40007800 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
|
||||
interrupts = <82 0>;
|
||||
status = "disabled";
|
||||
label = "UART_7";
|
||||
};
|
||||
|
||||
uart8: serial@40007c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
|
||||
interrupts = <83 0>;
|
||||
status = "disabled";
|
||||
label = "UART_8";
|
||||
};
|
||||
|
||||
uart9: serial@40011800 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40011800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
|
||||
interrupts = <88 0>;
|
||||
status = "disabled";
|
||||
label = "UART_9";
|
||||
};
|
||||
|
||||
uart10: serial@40011c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40011c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
|
||||
interrupts = <89 0>;
|
||||
status = "disabled";
|
||||
label = "UART_10";
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f413.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(320)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f413.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(320)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1536)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (c) 2019, Kwon Tae-young <tykwon@m2i.co.kr>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f405.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp: cryp@50060000 {
|
||||
compatible = "st,stm32-cryp";
|
||||
reg = <0x50060000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
|
||||
interrupts = <79 0>;
|
||||
status = "disabled";
|
||||
label = "CRYP";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2019, Kwon Tae-young <tykwon@m2i.co.kr>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f415.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f407.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
cryp: cryp@50060000 {
|
||||
compatible = "st,stm32-cryp";
|
||||
reg = <0x50060000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
|
||||
interrupts = <79 0>;
|
||||
status = "disabled";
|
||||
label = "CRYP";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f417.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f417.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,107 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f407.dtsi>
|
||||
#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@40020000 {
|
||||
reg = <0x40020000 0x2C00>;
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
|
||||
label = "GPIOJ";
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
|
||||
label = "GPIOK";
|
||||
};
|
||||
};
|
||||
|
||||
uart7: serial@40007800 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
|
||||
interrupts = <82 0>;
|
||||
status = "disabled";
|
||||
label = "UART_7";
|
||||
};
|
||||
|
||||
uart8: serial@40007c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
|
||||
interrupts = <83 0>;
|
||||
status = "disabled";
|
||||
label = "UART_8";
|
||||
};
|
||||
|
||||
spi4: spi@40013400 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
|
||||
interrupts = <84 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_4";
|
||||
};
|
||||
|
||||
/* spi5 is present on all STM32F429XX SoCs except
|
||||
* STM32F429vX SoCs. Delete node in stm32f429vX.dtsi.
|
||||
*/
|
||||
spi5: spi@40015000 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
||||
interrupts = <85 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_5";
|
||||
};
|
||||
|
||||
/* spi6 is present on all STM32F429XX SoCs except
|
||||
* STM32F429vX SoCs. Delete node in stm32f429vX.dtsi.
|
||||
*/
|
||||
spi6: spi@40015400 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
|
||||
interrupts = <86 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_6";
|
||||
};
|
||||
|
||||
fmc: memory-controller@a0000000 {
|
||||
compatible = "st,stm32-fmc";
|
||||
reg = <0xa0000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
|
||||
label = "STM32_FMC";
|
||||
status = "disabled";
|
||||
|
||||
sdram: sdram {
|
||||
compatible = "st,stm32-fmc-sdram";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
label = "STM32_FMC_SDRAM";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f427.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(192)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(2048)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,11 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f427.dtsi>
|
||||
|
||||
/delete-node/ &spi5;
|
||||
|
||||
/delete-node/ &spi6;
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f427vX.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(192)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(2048)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* Copyright (c) 2017, 2020 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f427.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f429.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(192)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(2048)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Daniel Wagenknecht
|
||||
*
|
||||
* Document the usage of /delete-node/ for device tree nodes
|
||||
* that are missing on on only a small subset of SoCs of a given group
|
||||
* of SoCs.
|
||||
* Don't remove this file even if none of the SoCs currently
|
||||
* implemented in zephyr use it.
|
||||
*
|
||||
* spi5 and spi6 are present on all STM32F429XX SoCs except
|
||||
* STM32F429vX SoCs, so they are defined in stm32f429.dtsi and deleted
|
||||
* here.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f429.dtsi>
|
||||
|
||||
/delete-node/ &spi5;
|
||||
|
||||
/delete-node/ &spi6;
|
||||
@@ -0,0 +1,29 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f429vX.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(192)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(2048)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@@ -0,0 +1,113 @@
|
||||
/*
|
||||
* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f407.dtsi>
|
||||
#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
pinctrl: pin-controller@40020000 {
|
||||
reg = <0x40020000 0x2C00>;
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
|
||||
label = "GPIOJ";
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
|
||||
label = "GPIOK";
|
||||
};
|
||||
};
|
||||
|
||||
uart7: serial@40007800 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
|
||||
interrupts = <82 0>;
|
||||
status = "disabled";
|
||||
label = "UART_7";
|
||||
};
|
||||
|
||||
uart8: serial@40007c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
|
||||
interrupts = <83 0>;
|
||||
status = "disabled";
|
||||
label = "UART_8";
|
||||
};
|
||||
|
||||
spi4: spi@40013400 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013400 0x400>;
|
||||
interrupts = <84 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_4";
|
||||
};
|
||||
|
||||
/* spi5 is present on all STM32F437XX SoCs except
|
||||
* STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
|
||||
*/
|
||||
spi5: spi@40015000 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015000 0x400>;
|
||||
interrupts = <85 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_5";
|
||||
};
|
||||
|
||||
/* spi6 is present on all STM32F437XX SoCs except
|
||||
* STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
|
||||
*/
|
||||
spi6: spi@40015400 {
|
||||
compatible = "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015400 0x400>;
|
||||
interrupts = <86 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_6";
|
||||
};
|
||||
|
||||
fmc: memory-controller@a0000000 {
|
||||
compatible = "st,stm32-fmc";
|
||||
reg = <0xa0000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
|
||||
label = "STM32_FMC";
|
||||
status = "disabled";
|
||||
|
||||
sdram: sdram {
|
||||
compatible = "st,stm32-fmc-sdram";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
label = "STM32_FMC_SDRAM";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
cryp: cryp@50060000 {
|
||||
compatible = "st,stm32-cryp";
|
||||
reg = <0x50060000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
|
||||
interrupts = <79 0>;
|
||||
status = "disabled";
|
||||
label = "CRYP";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f437.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(192)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(2048)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,11 @@
|
||||
/*
|
||||
* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f437.dtsi>
|
||||
|
||||
/delete-node/ &spi5;
|
||||
|
||||
/delete-node/ &spi6;
|
||||
@@ -0,0 +1,142 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Philémon Jaermann
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f401.dtsi>
|
||||
#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
i2s1: i2s@40013000 {
|
||||
compatible = "st,stm32-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
|
||||
interrupts = <35 5>;
|
||||
dmas = <&dma2 3 3 0x400 0x3
|
||||
&dma2 2 3 0x400 0x3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
label = "I2S_1";
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
|
||||
interrupts = <39 0>;
|
||||
status = "disabled";
|
||||
label = "UART_3";
|
||||
};
|
||||
|
||||
uart4: serial@40004c00 {
|
||||
compatible ="st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
interrupts = <52 0>;
|
||||
status = "disabled";
|
||||
label = "UART_4";
|
||||
};
|
||||
|
||||
uart5: serial@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
||||
interrupts = <53 0>;
|
||||
status = "disabled";
|
||||
label = "UART_5";
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006400 0x400>;
|
||||
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
|
||||
status = "disabled";
|
||||
label = "CAN_1";
|
||||
bus-speed = <125000>;
|
||||
sjw = <1>;
|
||||
prop-seg = <0>;
|
||||
phase-seg1 = <5>;
|
||||
phase-seg2 = <6>;
|
||||
};
|
||||
|
||||
can2: can@40006800 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006800 0x400>;
|
||||
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
|
||||
master-can-reg = <0x40006400>;
|
||||
status = "disabled";
|
||||
label = "CAN_2";
|
||||
bus-speed = <125000>;
|
||||
sjw = <1>;
|
||||
prop-seg = <0>;
|
||||
phase-seg1 = <5>;
|
||||
phase-seg2 = <6>;
|
||||
};
|
||||
|
||||
usbotg_fs: usb@50000000 {
|
||||
num-bidir-endpoints = <6>;
|
||||
};
|
||||
|
||||
usbotg_hs: usb@40040000 {
|
||||
compatible = "st,stm32-otghs";
|
||||
reg = <0x40040000 0x40000>;
|
||||
interrupts = <77 0>, <74 0>, <75 0>;
|
||||
interrupt-names = "otghs", "ep1_out", "ep1_in";
|
||||
num-bidir-endpoints = <9>;
|
||||
ram-size = <4096>;
|
||||
maximum-speed = "full-speed";
|
||||
phys = <&otghs_fs_phy>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label= "OTGHS";
|
||||
};
|
||||
|
||||
backup_sram: memory@40024000 {
|
||||
compatible = "st,stm32-backup-sram";
|
||||
reg = <0x40024000 DT_SIZE_K(4)>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
||||
label = "BACKUP_SRAM";
|
||||
zephyr,memory-region = "BACKUP_SRAM";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
fmc: memory-controller@a0000000 {
|
||||
compatible = "st,stm32-fmc";
|
||||
reg = <0xa0000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
|
||||
label = "STM32_FMC";
|
||||
status = "disabled";
|
||||
|
||||
sdram: sdram {
|
||||
compatible = "st,stm32-fmc-sdram";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
label = "STM32_FMC_SDRAM";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
otghs_fs_phy: otghs_fs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "OTGHS_FS_PHY";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f446.dtsi>
|
||||
|
||||
/ {
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (c) 2017 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f4/stm32f429.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
usbotg_fs: usb@50000000 {
|
||||
num-bidir-endpoints = <6>;
|
||||
};
|
||||
|
||||
usbotg_hs: usb@40040000 {
|
||||
num-bidir-endpoints = <9>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f4/stm32f469.dtsi>
|
||||
|
||||
/ {
|
||||
ccm0: memory@10000000 {
|
||||
compatible = "st,stm32-ccm";
|
||||
reg = <0x10000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "CCM";
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
reg = <0x20000000 DT_SIZE_K(320)>;
|
||||
};
|
||||
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(2048)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,775 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Yurii Hamann
|
||||
* Copyright (c) 2019 Centaur Analytics, Inc
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv7-m.dtsi>
|
||||
#include <dt-bindings/clock/stm32_clock.h>
|
||||
#include <dt-bindings/i2c/i2c.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
|
||||
#include <freq.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
zephyr,entropy = &rng;
|
||||
zephyr,flash-controller = &flash;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m7";
|
||||
reg = <0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
mpu: mpu@e000ed90 {
|
||||
compatible = "arm,armv7m-mpu";
|
||||
reg = <0xe000ed90 0x40>;
|
||||
arm,num-mpu-regions = <8>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32-hse-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_M(16)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_K(32)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pll: pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32f7-pll-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
fmc: memory-controller@a0000000 {
|
||||
compatible = "st,stm32-fmc";
|
||||
reg = <0xa0000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
|
||||
label = "STM32_FMC";
|
||||
status = "disabled";
|
||||
|
||||
sdram: sdram {
|
||||
compatible = "st,stm32-fmc-sdram";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
label = "STM32_FMC_SDRAM";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
flash: flash-controller@40023c00 {
|
||||
compatible = "st,stm32-flash-controller", "st,stm32f7-flash-controller";
|
||||
label = "FLASH_CTRL";
|
||||
reg = <0x40023c00 0x400>;
|
||||
interrupts = <4 0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0: flash@8000000 {
|
||||
compatible = "st,stm32-nv-flash", "soc-nv-flash";
|
||||
label = "FLASH_STM32";
|
||||
|
||||
write-block-size = <1>;
|
||||
/* maximum erase time (ms) for a 256K sector */
|
||||
max-erase-time = <4000>;
|
||||
};
|
||||
};
|
||||
|
||||
rcc: rcc@40023800 {
|
||||
compatible = "st,stm32-rcc";
|
||||
#clock-cells = <2>;
|
||||
reg = <0x40023800 0x400>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@40013c00 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x40013c00 0x400>;
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@40020000 {
|
||||
compatible = "st,stm32-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x40020000 0x2400>;
|
||||
|
||||
gpioa: gpio@40020000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
|
||||
label = "GPIOA";
|
||||
};
|
||||
|
||||
gpiob: gpio@40020400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
|
||||
label = "GPIOB";
|
||||
};
|
||||
|
||||
gpioc: gpio@40020800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
|
||||
label = "GPIOC";
|
||||
};
|
||||
|
||||
gpiod: gpio@40020C00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40020C00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
|
||||
label = "GPIOD";
|
||||
};
|
||||
|
||||
gpioe: gpio@40021000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
|
||||
label = "GPIOE";
|
||||
};
|
||||
|
||||
gpiof: gpio@40021400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
|
||||
label = "GPIOF";
|
||||
};
|
||||
|
||||
gpiog: gpio@40021800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
|
||||
label = "GPIOG";
|
||||
};
|
||||
|
||||
gpioh: gpio@40021C00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40021C00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
|
||||
label = "GPIOH";
|
||||
};
|
||||
|
||||
gpioi: gpio@40022000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
|
||||
label = "GPIOI";
|
||||
};
|
||||
};
|
||||
|
||||
iwdg: watchdog@40003000 {
|
||||
compatible = "st,stm32-watchdog";
|
||||
reg = <0x40003000 0x400>;
|
||||
label = "IWDG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wwdg: watchdog@40002c00 {
|
||||
compatible = "st,stm32-window-watchdog";
|
||||
reg = <0x40002C00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
|
||||
label = "WWDG";
|
||||
interrupts = <0 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@40011000 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40011000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
|
||||
interrupts = <37 0>;
|
||||
status = "disabled";
|
||||
label = "UART_1";
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
|
||||
interrupts = <38 0>;
|
||||
status = "disabled";
|
||||
label = "UART_2";
|
||||
};
|
||||
|
||||
usart3: serial@40004800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
|
||||
interrupts = <39 0>;
|
||||
status = "disabled";
|
||||
label = "UART_3";
|
||||
};
|
||||
|
||||
uart4: serial@40004c00 {
|
||||
compatible ="st,stm32-uart";
|
||||
reg = <0x40004c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
|
||||
interrupts = <52 0>;
|
||||
status = "disabled";
|
||||
label = "UART_4";
|
||||
};
|
||||
|
||||
uart5: serial@40005000 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40005000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
|
||||
interrupts = <53 0>;
|
||||
status = "disabled";
|
||||
label = "UART_5";
|
||||
};
|
||||
|
||||
usart6: serial@40011400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40011400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
|
||||
interrupts = <71 0>;
|
||||
status = "disabled";
|
||||
label = "UART_6";
|
||||
};
|
||||
|
||||
uart7: serial@40007800 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
|
||||
interrupts = <82 0>;
|
||||
status = "disabled";
|
||||
label = "UART_7";
|
||||
};
|
||||
|
||||
uart8: serial@40007c00 {
|
||||
compatible = "st,stm32-uart";
|
||||
reg = <0x40007c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
|
||||
interrupts = <83 0>;
|
||||
status = "disabled";
|
||||
label = "UART_8";
|
||||
};
|
||||
|
||||
i2c1: i2c@40005400 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
|
||||
interrupts = <31 0>, <32 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label = "I2C_1";
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
|
||||
interrupts = <33 0>, <34 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label = "I2C_2";
|
||||
};
|
||||
|
||||
i2c3: i2c@40005c00 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
|
||||
interrupts = <72 0>, <73 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label = "I2C_3";
|
||||
};
|
||||
|
||||
spi1: spi@40013000 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
|
||||
interrupts = <35 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_1";
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <36 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
spi3: spi@40003c00 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
|
||||
interrupts = <51 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_3";
|
||||
};
|
||||
|
||||
spi4: spi@40013400 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
|
||||
interrupts = <84 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_4";
|
||||
};
|
||||
|
||||
spi5: spi@40015000 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
||||
interrupts = <85 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_5";
|
||||
};
|
||||
|
||||
can1: can@40006400 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006400 0x400>;
|
||||
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
|
||||
status = "disabled";
|
||||
label = "CAN_1";
|
||||
};
|
||||
|
||||
timers1: timers@40010000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
|
||||
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_1";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_1";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers2: timers@40000000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
|
||||
interrupts = <28 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_2";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_2";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers3: timers@40000400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
|
||||
interrupts = <29 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_3";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_3";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers4: timers@40000800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
|
||||
interrupts = <30 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_4";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_4";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers5: timers@40000c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
|
||||
interrupts = <50 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_5";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_5";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers6: timers@40001000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
|
||||
interrupts = <54 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_6";
|
||||
};
|
||||
|
||||
timers7: timers@40001400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
|
||||
interrupts = <55 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_7";
|
||||
};
|
||||
|
||||
timers8: timers@40010400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40010400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
|
||||
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
|
||||
interrupt-names = "brk", "up", "trgcom", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_8";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_8";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers9: timers@40014000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
|
||||
interrupts = <24 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_9";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_9";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers10: timers@40014400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
|
||||
interrupts = <25 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_10";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_10";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers11: timers@40014800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
|
||||
interrupts = <26 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_11";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_11";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers12: timers@40001800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
|
||||
interrupts = <43 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_12";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_12";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers13: timers@40001c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40001c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
|
||||
interrupts = <44 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_13";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_13";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers14: timers@40002000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40002000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
|
||||
interrupts = <45 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_14";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_14";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg_fs: usb@50000000 {
|
||||
compatible = "st,stm32-otgfs";
|
||||
reg = <0x50000000 0x40000>;
|
||||
interrupts = <67 0>;
|
||||
interrupt-names = "otgfs";
|
||||
num-bidir-endpoints = <6>;
|
||||
ram-size = <1280>;
|
||||
maximum-speed = "full-speed";
|
||||
phys = <&otgfs_phy>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
|
||||
status = "disabled";
|
||||
label = "OTGFS";
|
||||
};
|
||||
|
||||
usbotg_hs: usb@40040000 {
|
||||
compatible = "st,stm32-otghs";
|
||||
reg = <0x40040000 0x40000>;
|
||||
interrupts = <77 0>, <74 0>, <75 0>;
|
||||
interrupt-names = "otghs", "ep1_out", "ep1_in";
|
||||
num-bidir-endpoints = <9>;
|
||||
ram-size = <4096>;
|
||||
maximum-speed = "full-speed";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
|
||||
phys = <&otghs_fs_phy>;
|
||||
status = "disabled";
|
||||
label= "OTGHS";
|
||||
};
|
||||
|
||||
rtc: rtc@40002800 {
|
||||
compatible = "st,stm32-rtc";
|
||||
reg = <0x40002800 0x300>;
|
||||
interrupts = <41 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
|
||||
prescaler = <32768>;
|
||||
status = "disabled";
|
||||
label = "RTC_0";
|
||||
};
|
||||
|
||||
adc1: adc@40012000 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x40012000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
|
||||
interrupts = <18 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dac1: dac@40007400 {
|
||||
compatible = "st,stm32-dac";
|
||||
reg = <0x40007400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
|
||||
status = "disabled";
|
||||
label = "DAC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dma1: dma@40026000 {
|
||||
compatible = "st,stm32-dma-v1";
|
||||
#dma-cells = <4>;
|
||||
reg = <0x40026000 0x400>;
|
||||
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
|
||||
status = "disabled";
|
||||
label = "DMA_1";
|
||||
};
|
||||
|
||||
dma2: dma@40026400 {
|
||||
compatible = "st,stm32-dma-v1";
|
||||
#dma-cells = <4>;
|
||||
reg = <0x40026400 0x400>;
|
||||
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
|
||||
st,mem2mem;
|
||||
status = "disabled";
|
||||
label = "DMA_2";
|
||||
};
|
||||
|
||||
rng: rng@50060800 {
|
||||
compatible = "st,stm32-rng";
|
||||
reg = <0x50060800 0x400>;
|
||||
interrupts = <80 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
|
||||
status = "disabled";
|
||||
label = "RNG";
|
||||
};
|
||||
|
||||
sdmmc1: sdmmc@40012c00 {
|
||||
compatible = "st,stm32-sdmmc";
|
||||
reg = <0x40012c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
|
||||
interrupts = <49 0>;
|
||||
status = "disabled";
|
||||
label = "SDMMC_1";
|
||||
};
|
||||
|
||||
backup_sram: memory@40024000 {
|
||||
compatible = "st,stm32-backup-sram";
|
||||
reg = <0x40024000 DT_SIZE_K(4)>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
|
||||
label = "BACKUP_SRAM";
|
||||
zephyr,memory-region = "BACKUP_SRAM";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
quadspi: quadspi@a0001000 {
|
||||
compatible = "st,stm32-qspi";
|
||||
#address-cells = <0x1>;
|
||||
#size-cells = <0x0>;
|
||||
reg = <0xa0001000 0x34>;
|
||||
interrupts = <92 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x2>;
|
||||
status = "disabled";
|
||||
label = "QUADSPI";
|
||||
};
|
||||
};
|
||||
|
||||
otghs_fs_phy: otghs_fs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "OTGHS_FS_PHY";
|
||||
};
|
||||
|
||||
otgfs_phy: otgfs_phy {
|
||||
compatible = "usb-nop-xceiv";
|
||||
#phy-cells = <0>;
|
||||
label = "OTGFS_PHY";
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <4>;
|
||||
};
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Aurelien Jarno
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f7/stm32f7.dtsi>
|
||||
|
||||
/ {
|
||||
/* 64KB DTCM @ 0x20000000, 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00 */
|
||||
|
||||
sram0: memory@20010000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x20010000 DT_SIZE_K(192)>;
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
||||
soc {
|
||||
usbphyc: usbphyc@40017c00 {
|
||||
compatible = "st,stm32-usbphyc";
|
||||
reg = <0x40017c00 0x400>;
|
||||
#phy-cells = <0>;
|
||||
label = "USBPHYC";
|
||||
};
|
||||
|
||||
usbotg_hs: usb@40040000 {
|
||||
phys = <&usbphyc>;
|
||||
maximum-speed = "high-speed";
|
||||
};
|
||||
|
||||
sdmmc2: sdmmc@40011c00 {
|
||||
compatible = "st,stm32-sdmmc";
|
||||
reg = <0x40011c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
|
||||
interrupts = <103 0>;
|
||||
status = "disabled";
|
||||
label = "SDMMC_2";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/delete-node/ &otghs_fs_phy;
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f7/stm32f723.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,94 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Kwon Tae-young <tykwon@m2i.co.kr>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f7/stm32f7.dtsi>
|
||||
|
||||
/ {
|
||||
/* 64KB DTCM @ 20000000, 240KB SRAM1 @ 20010000, 16KB SRAM2 @ 2004C000 */
|
||||
|
||||
sram0: memory@20010000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x20010000 DT_SIZE_K(256)>;
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(64)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl: pin-controller@40020000 {
|
||||
reg = <0x40020000 0x2C00>;
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
|
||||
label = "GPIOJ";
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
|
||||
label = "GPIOK";
|
||||
};
|
||||
};
|
||||
|
||||
i2c4: i2c@40006000 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40006000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
|
||||
interrupts = <95 0>, <96 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label = "I2C_4";
|
||||
};
|
||||
|
||||
spi6: spi@40015400 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
|
||||
interrupts = <86 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_6";
|
||||
};
|
||||
|
||||
can2: can@40006800 {
|
||||
compatible = "st,stm32-can";
|
||||
reg = <0x40006800 0x400>;
|
||||
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
|
||||
interrupt-names = "TX", "RX0", "RX1", "SCE";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
|
||||
status = "disabled";
|
||||
label = "CAN_2";
|
||||
};
|
||||
|
||||
mac: ethernet@40028000 {
|
||||
compatible = "st,stm32-ethernet";
|
||||
reg = <0x40028000 0x8000>;
|
||||
label = "ETH_0";
|
||||
interrupts = <61 0>;
|
||||
clock-names = "stmmaceth", "mac-clk-tx",
|
||||
"mac-clk-rx", "mac-clk-ptp";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Kwon Tae-young <tykwon@m2i.co.kr>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f7/stm32f745.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(512)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2020 Kwon Tae-young <tykwon@m2i.co.kr>
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f7/stm32f745.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,7 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Yurii Hamann
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f7/stm32f745.dtsi>
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f7/stm32f746.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,7 @@
|
||||
/*
|
||||
* Copyright (c) 2018 AJ Palmer
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f7/stm32f746.dtsi>
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2018 AJ Palmer
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f7/stm32f756.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(1024)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c) 2021 Daniel Agar
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f7/stm32f7.dtsi>
|
||||
|
||||
/ {
|
||||
/* 128KB DTCM @ 20000000, 368KB SRAM1 @ 20020000,
|
||||
* 16KB SRAM2 @ 2007C000
|
||||
*/
|
||||
|
||||
sram0: memory@20020000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x20020000 DT_SIZE_K(384)>;
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl: pin-controller@40020000 {
|
||||
reg = <0x40020000 0x2C00>;
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
|
||||
label = "GPIOJ";
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
|
||||
label = "GPIOK";
|
||||
};
|
||||
};
|
||||
|
||||
i2c4: i2c@40006000 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40006000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
|
||||
interrupts = <95 0>, <96 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label = "I2C_4";
|
||||
};
|
||||
|
||||
spi6: spi@40015400 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
|
||||
interrupts = <86 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_6";
|
||||
};
|
||||
|
||||
mac: ethernet@40028000 {
|
||||
compatible = "st,stm32-ethernet";
|
||||
reg = <0x40028000 0x8000>;
|
||||
label = "ETH_0";
|
||||
interrupts = <61 0>;
|
||||
clock-names = "stmmaceth", "mac-clk-tx",
|
||||
"mac-clk-rx", "mac-clk-ptp";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc2: sdmmc@40011c00 {
|
||||
compatible = "st,stm32-sdmmc";
|
||||
reg = <0x40011c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
|
||||
interrupts = <103 0>;
|
||||
status = "disabled";
|
||||
label = "SDMMC_2";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,95 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Roland Ma
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f7/stm32f7.dtsi>
|
||||
|
||||
/ {
|
||||
/* 128KB DTCM @ 20000000, 368KB SRAM1 @ 20020000,
|
||||
* 16KB SRAM2 @ 2007C000
|
||||
*/
|
||||
|
||||
sram0: memory@20020000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x20020000 DT_SIZE_K(384)>;
|
||||
};
|
||||
|
||||
dtcm: memory@20000000 {
|
||||
compatible = "arm,dtcm";
|
||||
reg = <0x20000000 DT_SIZE_K(128)>;
|
||||
zephyr,memory-region = "DTCM";
|
||||
};
|
||||
|
||||
soc {
|
||||
pinctrl: pin-controller@40020000 {
|
||||
reg = <0x40020000 0x2C00>;
|
||||
|
||||
gpioj: gpio@40022400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
|
||||
label = "GPIOJ";
|
||||
};
|
||||
|
||||
gpiok: gpio@40022800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x40022800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
|
||||
label = "GPIOK";
|
||||
};
|
||||
};
|
||||
|
||||
i2c4: i2c@40006000 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40006000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x01000000>;
|
||||
interrupts = <95 0>, <96 0>;
|
||||
interrupt-names = "event", "error";
|
||||
status = "disabled";
|
||||
label = "I2C_4";
|
||||
};
|
||||
|
||||
spi6: spi@40015400 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40015400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
|
||||
interrupts = <86 5>;
|
||||
status = "disabled";
|
||||
label = "SPI_6";
|
||||
};
|
||||
|
||||
mac: ethernet@40028000 {
|
||||
compatible = "st,stm32-ethernet";
|
||||
reg = <0x40028000 0x8000>;
|
||||
label = "ETH_0";
|
||||
interrupts = <61 0>;
|
||||
clock-names = "stmmaceth", "mac-clk-tx",
|
||||
"mac-clk-rx", "mac-clk-ptp";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
|
||||
<&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdmmc2: sdmmc@40011c00 {
|
||||
compatible = "st,stm32-sdmmc";
|
||||
reg = <0x40011c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
|
||||
interrupts = <103 0>;
|
||||
status = "disabled";
|
||||
label = "SDMMC_2";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Roland Ma
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f7/stm32f767.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(2048)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,7 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Yurii Hamann
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <st/f7/stm32f767.dtsi>
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* Copyright (c) 2018 Linaro Limited
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <st/f7/stm32f769.dtsi>
|
||||
|
||||
/ {
|
||||
soc {
|
||||
flash-controller@40023c00 {
|
||||
flash0: flash@8000000 {
|
||||
reg = <0x08000000 DT_SIZE_K(2048)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
@@ -0,0 +1,393 @@
|
||||
/*
|
||||
* Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
|
||||
* Copyright (c) 2019 ST Microelectronics
|
||||
* Copyright (c) 2019 Centaur Analytics, Inc
|
||||
* Copyright (C) 2020 Framework Computer LLC <ktl@frame.work>
|
||||
* Copyright (c) 2021 G-Technologies Sdn. Bhd.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <arm/armv6-m.dtsi>
|
||||
#include <dt-bindings/clock/stm32_clock.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/i2c/i2c.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <freq.h>
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
zephyr,flash-controller = &flash;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-m0+";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sram0: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
};
|
||||
|
||||
clocks {
|
||||
clk_hse: clk-hse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32-hse-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_hsi: clk-hsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_M(16)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lse: clk-lse {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clk_lsi: clk-lsi {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <DT_FREQ_K(32)>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pll: pll {
|
||||
#clock-cells = <0>;
|
||||
compatible = "st,stm32g0-pll-clock";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
flash: flash-controller@40022000 {
|
||||
compatible = "st,stm32-flash-controller", "st,stm32g0-flash-controller";
|
||||
label = "FLASH_CTRL";
|
||||
reg = <0x40022000 0x400>;
|
||||
interrupts = <3 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
flash0: flash@8000000 {
|
||||
compatible = "st,stm32-nv-flash", "soc-nv-flash";
|
||||
label = "FLASH_STM32";
|
||||
|
||||
write-block-size = <8>;
|
||||
erase-block-size = <2048>;
|
||||
/* maximum erase time(ms) for a 2K sector */
|
||||
max-erase-time = <40>;
|
||||
};
|
||||
};
|
||||
|
||||
rcc: rcc@40021000 {
|
||||
compatible = "st,stm32f0-rcc";
|
||||
#clock-cells = <2>;
|
||||
reg = <0x40021000 0x400>;
|
||||
};
|
||||
|
||||
exti: interrupt-controller@40021800 {
|
||||
compatible = "st,stm32-exti";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x40021800 0x400>;
|
||||
};
|
||||
|
||||
pinctrl: pin-controller@50000000 {
|
||||
compatible = "st,stm32-pinctrl";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x50000000 0x2000>;
|
||||
|
||||
gpioa: gpio@50000000 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x50000000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000001>;
|
||||
label = "GPIOA";
|
||||
};
|
||||
|
||||
gpiob: gpio@50000400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x50000400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000002>;
|
||||
label = "GPIOB";
|
||||
};
|
||||
|
||||
gpioc: gpio@50000800 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x50000800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000004>;
|
||||
label = "GPIOC";
|
||||
};
|
||||
|
||||
gpiod: gpio@50000c00 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x50000c00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000008>;
|
||||
label = "GPIOD";
|
||||
};
|
||||
|
||||
gpiof: gpio@50001400 {
|
||||
compatible = "st,stm32-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x50001400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_IOP 0x00000020>;
|
||||
label = "GPIOF";
|
||||
};
|
||||
};
|
||||
|
||||
rtc: rtc@40002800 {
|
||||
compatible = "st,stm32-rtc";
|
||||
reg = <0x40002800 0x400>;
|
||||
interrupts = <2 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>;
|
||||
prescaler = <32768>;
|
||||
status = "disabled";
|
||||
label = "RTC_0";
|
||||
};
|
||||
|
||||
iwdg: watchdog@40003000 {
|
||||
compatible = "st,stm32-watchdog";
|
||||
reg = <0x40003000 0x400>;
|
||||
label = "IWDG";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wwdg: watchdog@40002c00 {
|
||||
compatible = "st,stm32-window-watchdog";
|
||||
reg = <0x40002C00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
|
||||
label = "WWDG";
|
||||
interrupts = <0 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usart1: serial@40013800 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40013800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
|
||||
interrupts = <27 0>;
|
||||
status = "disabled";
|
||||
label = "UART_1";
|
||||
};
|
||||
|
||||
usart2: serial@40004400 {
|
||||
compatible = "st,stm32-usart", "st,stm32-uart";
|
||||
reg = <0x40004400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
|
||||
interrupts = <28 0>;
|
||||
status = "disabled";
|
||||
label = "UART_2";
|
||||
};
|
||||
|
||||
lptim1: timers@40007c00 {
|
||||
compatible = "st,stm32-lptim";
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40007c00 0x400>;
|
||||
interrupts = <17 1>;
|
||||
interrupt-names = "wakeup";
|
||||
status = "disabled";
|
||||
label = "LPTIM_1";
|
||||
};
|
||||
|
||||
timers1: timers@40012c00 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40012C00 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
|
||||
interrupts = <13 0>, <14 0>;
|
||||
interrupt-names = "brk_up_trg_com", "cc";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_1";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_1";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers3: timers@40000400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40000400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
|
||||
interrupts = <16 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_3";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_3";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers14: timers@40002000 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40002000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
|
||||
interrupts = <19 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_14";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_14";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers16: timers@40014400 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
|
||||
interrupts = <21 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_16";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_16";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
timers17: timers@40014800 {
|
||||
compatible = "st,stm32-timers";
|
||||
reg = <0x40014800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
|
||||
interrupts = <22 0>;
|
||||
interrupt-names = "global";
|
||||
st,prescaler = <0>;
|
||||
status = "disabled";
|
||||
label = "TIMERS_17";
|
||||
|
||||
pwm {
|
||||
compatible = "st,stm32-pwm";
|
||||
status = "disabled";
|
||||
label = "PWM_17";
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c1: i2c@40005400 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
|
||||
interrupts = <23 0>;
|
||||
interrupt-names = "combined";
|
||||
status = "disabled";
|
||||
label = "I2C_1";
|
||||
};
|
||||
|
||||
i2c2: i2c@40005800 {
|
||||
compatible = "st,stm32-i2c-v2";
|
||||
clock-frequency = <I2C_BITRATE_STANDARD>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40005800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
|
||||
interrupts = <24 0>;
|
||||
interrupt-names = "combined";
|
||||
status = "disabled";
|
||||
label = "I2C_2";
|
||||
};
|
||||
|
||||
spi1: spi@40013000 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40013000 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
|
||||
interrupts = <25 0>;
|
||||
status = "disabled";
|
||||
label = "SPI_1";
|
||||
};
|
||||
|
||||
spi2: spi@40003800 {
|
||||
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x40003800 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
|
||||
interrupts = <26 0>;
|
||||
status = "disabled";
|
||||
label = "SPI_2";
|
||||
};
|
||||
|
||||
adc1: adc@40012400 {
|
||||
compatible = "st,stm32-adc";
|
||||
reg = <0x40012400 0x400>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
|
||||
interrupts = <12 0>;
|
||||
status = "disabled";
|
||||
label = "ADC_1";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
dma1: dma@40020000 {
|
||||
compatible = "st,stm32-dma-v2";
|
||||
#dma-cells = <3>;
|
||||
reg = <0x40020000 0x400>;
|
||||
interrupts = <9 0 10 0 10 0 11 0 11 0>;
|
||||
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
|
||||
dma-requests = <5>;
|
||||
dma-offset = <0>;
|
||||
status = "disabled";
|
||||
label = "DMA_1";
|
||||
};
|
||||
|
||||
/* DMAMUX clock is enabled as long as DMA1 or DMA2 is enabled */
|
||||
dmamux1: dmamux@40020800 {
|
||||
compatible = "st,stm32-dmamux";
|
||||
#dma-cells = <3>;
|
||||
reg = <0x40020800 0x800>;
|
||||
interrupts = <11 0>;
|
||||
dma-channels = <5>;
|
||||
dma-generators = <4>;
|
||||
dma-requests= <49>;
|
||||
status = "disabled";
|
||||
label = "DMAMUX_1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&nvic {
|
||||
arm,num-irq-priority-bits = <2>;
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user