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WIP: device tree MVP

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This commit is contained in:
Daniel Agar
2022-01-06 17:20:17 -05:00
parent 07d75d85cf
commit 1f39b42525
1395 changed files with 68755 additions and 0 deletions
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dts/Kconfig
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# SPDX-License-Identifier: Apache-2.0
config HAS_DTS
bool
help
This option specifies that the target platform supports device tree
configuration.
config HAS_DTS_GPIO
bool
depends on HAS_DTS
help
This option specifies that the target platform supports device tree
configuration for GPIO.
config HAS_DTS_WDT
bool
depends on HAS_DTS
help
This option specifies that the target platform supports device tree
configuration for WDT.
dts/arm/armv6-m.dtsi
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/* SPDX-License-Identifier: Apache-2.0 */
#include "skeleton.dtsi"
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&nvic>;
ranges;
nvic: interrupt-controller@e000e100 {
#address-cells = <1>;
compatible = "arm,v6m-nvic";
reg = <0xe000e100 0xc00>;
interrupt-controller;
#interrupt-cells = <2>;
};
systick: timer@e000e010 {
compatible = "arm,armv6m-systick";
reg = <0xe000e010 0x10>;
};
};
};
dts/arm/armv7-a.dtsi
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/*
* Copyright (c) 2018 Lexmark International, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
};
};
dts/arm/armv7-m.dtsi
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/* SPDX-License-Identifier: Apache-2.0 */
#include "skeleton.dtsi"
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&nvic>;
ranges;
nvic: interrupt-controller@e000e100 {
#address-cells = <1>;
compatible = "arm,v7m-nvic";
reg = <0xe000e100 0xc00>;
interrupt-controller;
#interrupt-cells = <2>;
};
systick: timer@e000e010 {
compatible = "arm,armv7m-systick";
reg = <0xe000e010 0x10>;
};
};
};
dts/arm/armv7-r.dtsi
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/*
* Copyright (c) 2018 Lexmark International, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "skeleton.dtsi"
/ {
soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
ranges;
};
};
dts/arm/nxp/nxp_k66.dtsi
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/*
* Copyright (c) 2020 DENX Software Engineering GmbH
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <nxp/nxp_k6x.dtsi>
&flash0 {
reg = <0x00000000 DT_SIZE_M(2)>;
};
/ {
soc {
lpuart0: lpuart@400c4000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x400c4000 0x14>;
interrupts = <86 0>;
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1038 20>;
label = "LPUART_0";
status = "disabled";
};
flexcan1: can@400a4000 {
compatible = "nxp,kinetis-flexcan";
reg = <0x400a4000 0x1000>;
interrupts = <94 0>, <95 0>, <96 0>, <97 0>, <98 0>, <99 0>;
interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning",
"rx-warning", "wake-up";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 4>;
clk-source = <1>;
label = "CAN_1";
sjw = <1>;
prop-seg = <1>;
phase-seg1 = <3>;
phase-seg2 = <2>;
status = "disabled";
};
};
};
dts/arm/nxp/nxp_k6x.dtsi
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/* SPDX-License-Identifier: Apache-2.0 */
#include <mem.h>
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/kinetis_sim.h>
#include <dt-bindings/clock/kinetis_mcg.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/i2c/i2c.h>
/ {
aliases {
watchdog0 = &wdog;
};
chosen {
zephyr,entropy = &rnga;
zephyr,flash-controller = &ftfe;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
/* The on-chip SRAM is split into SRAM_L and SRAM_U regions that form a
* contiguous block in the memory map, however misaligned accesses
* across the 0x2000_0000 boundary are not supported in the Arm
* Cortex-M4 architecture. For clarity and to avoid the temptation for
* someone to extend sram0 without solving this issue, we define two
* separate memory nodes here and only use the upper one for now. A
* potential solution has been proposed in binutils:
* https://sourceware.org/ml/binutils/2017-02/msg00250.html
*/
sram_l: memory@1fff0000 {
compatible = "mmio-sram";
reg = <0x1fff0000 DT_SIZE_K(64)>;
};
sram0: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(192)>;
};
temp0: temp0 {
compatible = "nxp,kinetis-temperature";
io-channels = <&adc0 26>, <&adc0 27>;
io-channel-names = "SENSOR", "BANDGAP";
bandgap-voltage = <1000000>;
vtemp25 = <716000>;
sensor-slope-cold = <1620>;
sensor-slope-hot = <1620>;
label = "TEMP0";
status = "disabled";
};
temp1: temp1 {
compatible = "nxp,kinetis-temperature";
io-channels = <&adc1 26>, <&adc1 27>;
io-channel-names = "SENSOR", "BANDGAP";
bandgap-voltage = <1000000>;
vtemp25 = <716000>;
sensor-slope-cold = <1620>;
sensor-slope-hot = <1620>;
label = "TEMP1";
status = "disabled";
};
soc {
mpu: mpu@4000d000 {
compatible = "nxp,k64f-mpu";
reg = <0x4000d000 0x824>;
status = "disabled";
};
mcg: clock-controller@40064000 {
compatible = "nxp,kinetis-mcg";
reg = <0x40064000 0xd>;
label = "MCG";
#clock-cells = <1>;
};
osc: clock-controller@40065000 {
compatible = "nxp,k64f-osc";
reg = <0x40065000 0x4>;
enable-external-reference;
};
rtc: rtc@4003d000 {
compatible = "nxp,kinetis-rtc";
reg = <0x4003d000 0x1000>;
interrupts = <46 0>, <47 0>;
interrupt-names = "alarm", "seconds";
clock-frequency = <32768>;
prescaler = <32768>;
label = "RTC_0";
};
sim: sim@40047000 {
compatible = "nxp,kinetis-sim";
reg = <0x40047000 0x1060>;
label = "SIM";
#clock-cells = <3>;
core_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <1>;
#clock-cells = <0>;
};
bus_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <2>;
#clock-cells = <0>;
};
flexbus_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <3>;
#clock-cells = <0>;
};
flash_clk {
compatible = "fixed-factor-clock";
clocks = <&mcg KINETIS_MCG_OUT_CLK>;
clock-div = <5>;
#clock-cells = <0>;
};
};
ftfe: flash-controller@40020000 {
compatible = "nxp,kinetis-ftfe";
label = "FLASH_CTRL";
reg = <0x40020000 0x18>;
interrupts = <18 0>, <19 0>;
interrupt-names = "command-complete", "read-collision";
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@0 {
compatible = "soc-nv-flash";
label = "MCUX_FLASH";
reg = <0 DT_SIZE_M(1)>;
erase-block-size = <4096>;
write-block-size = <8>;
};
};
i2c0: i2c@40066000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40066000 0x1000>;
interrupts = <24 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 6>;
label = "I2C_0";
status = "disabled";
};
i2c1: i2c@40067000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40067000 0x1000>;
interrupts = <25 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 7>;
label = "I2C_1";
status = "disabled";
};
i2c2: i2c@400e6000 {
compatible = "nxp,kinetis-i2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x400e6000 0x1000>;
interrupts = <74 0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 6>;
label = "I2C_2";
status = "disabled";
};
uart0: uart@4006a000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006a000 0x1000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 10>;
label = "UART_0";
status = "disabled";
};
uart1: uart@4006b000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006b000 0x1000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0x1034 11>;
label = "UART_1";
status = "disabled";
};
uart2: uart@4006c000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006c000 0x1000>;
interrupts = <35 0>, <36 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 12>;
label = "UART_2";
status = "disabled";
};
uart3: uart@4006d000 {
compatible = "nxp,kinetis-uart";
reg = <0x4006d000 0x1000>;
interrupts = <37 0>, <38 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1034 13>;
label = "UART_3";
status = "disabled";
};
uart4: uart@400ea000 {
compatible = "nxp,kinetis-uart";
reg = <0x400ea000 0x1000>;
interrupts = <66 0>, <67 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 10>;
label = "UART_4";
status = "disabled";
};
uart5: uart@400eb000 {
compatible = "nxp,kinetis-uart";
reg = <0x400eb000 0x1000>;
interrupts = <68 0>, <69 0>;
interrupt-names = "status", "error";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1028 11>;
label = "UART_5";
status = "disabled";
};
porta: pinmux@40049000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x40049000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 9>;
};
portb: pinmux@4004a000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004a000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 10>;
};
portc: pinmux@4004b000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004b000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 11>;
};
portd: pinmux@4004c000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004c000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 12>;
};
porte: pinmux@4004d000 {
compatible = "nxp,kinetis-pinmux";
reg = <0x4004d000 0xd0>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1038 13>;
};
gpioa: gpio@400ff000 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff000 0x40>;
interrupts = <59 2>;
label = "GPIO_0";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&porta>;
};
gpiob: gpio@400ff040 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff040 0x40>;
interrupts = <60 2>;
label = "GPIO_1";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portb>;
};
gpioc: gpio@400ff080 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff080 0x40>;
interrupts = <61 2>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portc>;
};
gpiod: gpio@400ff0c0 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff0c0 0x40>;
interrupts = <62 2>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&portd>;
};
gpioe: gpio@400ff100 {
compatible = "nxp,kinetis-gpio";
status = "disabled";
reg = <0x400ff100 0x40>;
interrupts = <63 2>;
label = "GPIO_4";
gpio-controller;
#gpio-cells = <2>;
nxp,kinetis-port = <&porte>;
};
spi0: spi@4002c000 {
compatible = "nxp,kinetis-dspi";
reg = <0x4002c000 0x88>;
interrupts = <26 3>;
label = "SPI_0";
dmas = <&edma0 0 14>, <&edma0 0 15>;
dma-names = "rx", "tx";
rx-fifo-size = <4>;
tx-fifo-size = <4>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 12>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@4002d000 {
compatible = "nxp,kinetis-dspi";
reg = <0x4002d000 0x88>;
interrupts = <27 3>;
label = "SPI_1";
dmas = <&edma0 0 16>, <&edma0 0 16>;
dma-names = "rx", "tx";
rx-fifo-size = <1>;
tx-fifo-size = <1>;
nxp,rx-tx-chn-share;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 13>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi2: spi@400ac000 {
compatible = "nxp,kinetis-dspi";
reg = <0x400ac000 0x88>;
interrupts = <65 3>;
label = "SPI_2";
dmas = <&edma0 0 17>, <&edma0 0 17>;
dma-names = "rx", "tx";
rx-fifo-size = <1>;
tx-fifo-size = <1>;
nxp,rx-tx-chn-share;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x1030 12>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
wdog: watchdog@40052000 {
compatible = "nxp,kinetis-wdog";
reg = <0x40052000 16>;
interrupts = <22 0>;
clocks = <&sim KINETIS_SIM_LPO_CLK 0 0>;
label = "WDT_0";
};
ftm0: ftm@40038000{
compatible = "nxp,kinetis-ftm";
reg = <0x40038000 0x98>;
interrupts = <42 0>;
clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
prescaler = <16>;
label = "FTM_0";
status = "disabled";
};
ftm1: ftm@40039000{
compatible = "nxp,kinetis-ftm";
reg = <0x40039000 0x98>;
interrupts = <43 0>;
clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
prescaler = <16>;
label = "FTM_1";
status = "disabled";
};
ftm2: ftm@4003a000{
compatible = "nxp,kinetis-ftm";
reg = <0x4003a000 0x98>;
interrupts = <44 0>;
clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
prescaler = <16>;
label = "FTM_2";
status = "disabled";
};
ftm3: ftm@400b9000{
compatible = "nxp,kinetis-ftm";
reg = <0x400b9000 0x98>;
interrupts = <71 0>;
clocks = <&mcg KINETIS_MCG_FIXED_FREQ_CLK>;
prescaler = <16>;
label = "FTM_3";
status = "disabled";
};
adc0: adc@4003b000{
compatible = "nxp,kinetis-adc16";
reg = <0x4003b000 0x70>;
clocks = <&sim KINETIS_SIM_SIM_SOPT7 0 0xF>,
<&sim KINETIS_SIM_SIM_SOPT7 7 0x80>;
dmas = <&edma0 0 40>;
dma-names = "adc0";
clk-source = <0>;
interrupts = <39 0>;
label = "ADC_0";
status = "disabled";
#io-channel-cells = <1>;
};
adc1: adc@400bb000{
compatible = "nxp,kinetis-adc16";
reg = <0x400bb000 0x70>;
clocks = <&sim KINETIS_SIM_SIM_SOPT7 8 0xF00>,
<&sim KINETIS_SIM_SIM_SOPT7 15 0x8000>;
dmas = <&edma0 0 41>;
dma-names = "adc1";
clk-source = <0>;
interrupts = <73 0>;
label = "ADC_1";
status = "disabled";
#io-channel-cells = <1>;
};
dac0: dac@400cc000 {
compatible = "nxp,kinetis-dac";
reg = <0x400cc000 0x1000>;
interrupts = <56 0>;
voltage-reference = <1>;
label = "DAC_0";
status = "disabled";
#io-channel-cells = <1>;
};
dac1: dac@400cd000 {
compatible = "nxp,kinetis-dac";
reg = <0x400cd000 0x1000>;
interrupts = <72 0>;
voltage-reference = <1>;
label = "DAC_1";
status = "disabled";
#io-channel-cells = <1>;
};
usbotg: usbd@40072000 {
compatible = "nxp,kinetis-usbd";
reg = <0x40072000 0x1000>;
interrupts = <53 1>;
interrupt-names = "usb_otg";
num-bidir-endpoints = <16>;
status = "disabled";
label = "USBD";
};
enet: ethernet@400c0000 {
compatible = "nxp,kinetis-ethernet";
reg = <0x400c0000 0x620>;
interrupts = <83 0>, <84 0>, <85 0>;
interrupt-names = "TX", "RX", "ERR";
status = "disabled";
label = "ETH_0";
clocks = <&sim KINETIS_SIM_CORESYS_CLK 0 0>;
ptp {
compatible = "nxp,kinetis-ptp";
status = "disabled";
interrupts = <82 0>;
interrupt-names = "IEEE1588_TMR";
};
};
rnga: random@40029000 {
compatible = "nxp,kinetis-rnga";
reg = <0x40029000 0x1000>;
status = "okay";
interrupts = <23 0>;
label = "RNGA";
};
flexcan0: can@40024000 {
compatible = "nxp,kinetis-flexcan";
reg = <0x40024000 0x1000>;
interrupts = <75 0>, <76 0>, <77 0>, <78 0>, <79 0>, <80 0>;
interrupt-names = "mb-0-15", "bus-off", "error", "tx-warning", "rx-warning", "wake-up";
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103C 4>;
clk-source = <1>;
label = "CAN_0";
sjw = <1>;
sample-point = <875>;
status = "disabled";
};
edma0: dma-controller@40008000 {
#dma-cells = <2>;
compatible = "nxp,mcux-edma";
dma-channels = <16>;
dma-requests = <64>;
nxp,mem2mem;
reg = <0x40008000 0x1000>,
<0x40021000 0x1000>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>,
<8 0>, <9 0>, <10 0>, <11 0>,
<12 0>, <13 0>, <14 0>, <15 0>,
<16 0>;
clocks = <&sim KINETIS_SIM_DMA_CLK 0x1040 0x00000002>,
<&sim KINETIS_SIM_DMAMUX_CLK 0x103C 0x00000002>;
status = "disabled";
label = "DMA_0";
};
pit0: pit@40037000 {
compatible = "nxp,kinetis-pit";
reg = <0x40037000 0x1000>;
clocks = <&sim KINETIS_SIM_BUS_CLK 0x103c 23>;
interrupts = <48 0>, <49 0>, <50 0>, <51 0>;
status = "disabled";
pit-channel = <0>;
pit-period = <1000000>;
clock-frequency = <60000000>;
label = "PIT0";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
dts/arm/nxp/nxp_rt1060.dtsi
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/*
* Copyright (c) 2019, Linaro
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/nxp_rt.dtsi>
/* i.MX rt1060 has two continuous on-chip RAM, one is part of the
* FlexRAM mapped at 0x20280000 (vs 0x20280000 on rt1050) and is
* configurable (256KB by defaults), the other one is dedicated 512KB
* ram (OCRAM2) mapped at 0x20200000. In order to have a continuous
* region, we describe them in one 768Kb unique node.
*/
&ocram {
compatible = "mmio-sram";
reg = <0x20200000 DT_SIZE_K(768)>;
};
/* i.MX rt1060 has a second Ethernet controller. */
/ {
soc {
enet2: ethernet@402d4000 {
compatible = "nxp,kinetis-ethernet";
reg = <0x402D4000 0x628>;
interrupts = <152 0>;
interrupt-names = "COMMON";
status = "disabled";
label = "ETH_1";
ptp {
compatible = "nxp,kinetis-ptp";
status = "disabled";
interrupts = <153 0>;
interrupt-names = "IEEE1588_TMR";
};
};
};
};
dts/arm/nxp/nxp_rt1064.dtsi
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/*
* Copyright (c) 2019, Linaro
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/nxp_rt1060.dtsi>
&flexspi2 {
reg = <0x402a4000 0x4000>, <0x70000000 DT_SIZE_M(4)>;
/* WINBOND */
w25q32jvwj0: w25q32jvwj@0 {
compatible = "nxp,imx-flexspi-nor";
size = <33554432>;
label = "W25Q32JVWJ0";
reg = <0>;
spi-max-frequency = <133000000>;
status = "okay";
jedec-id = [ef 40 16];
erase-block-size = <4096>;
write-block-size = <1>;
};
};
dts/arm/nxp/nxp_rt1160_cm4.dtsi
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/*
* Copyright (c) 2021, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/nxp_rt11xx.dtsi>
/ {
cpus {
/delete-node/ cpu@0;
};
/*
* SRAM0 & SRAM1 are available only to the M4 core. EDMA_LPSR interrupts are connected
* to the M4 core alone, hence this EDMA controller has been designated M4 only.
* GPIO's 9, 11 are available to both M4 and M7 cores, however the GPIO interrupts are
* only accesssible to the M4.
*
* Refer to Chapter 3 of the Reference Manual
*/
soc {
sram0: memory@1ffe0000 {
compatible = "mmio-sram";
reg = <0x1ffe0000 DT_SIZE_K(128)>;
};
sram1: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(128)>;
};
/*
* M4 uses different addresses from the M7 core for GPIO2 and
* GPIO3, see pg. 1364 of RT1160 ref manual for example
*/
gpio2: gpio@40130000 {
compatible = "nxp,imx-gpio";
reg = <0x40130000 0x4000>;
interrupts = <102 0>, <103 0>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
};
gpio3: gpio@40134000 {
compatible = "nxp,imx-gpio";
reg = <0x40134000 0x4000>;
interrupts = <104 0>, <105 0>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
};
edma_lpsr0: dma-controller@40c14000 {
#dma-cells = <2>;
compatible = "nxp,mcux-edma";
dma-channels = <32>;
dma-requests = <208>;
nxp,mem2mem;
nxp,a_on;
reg = <0x40c14000 0x4000>,
<0x40c18000 0x4000>;
clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
status = "disabled";
label = "DMA_0";
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>,
<8 0>, <9 0>, <10 0>, <11 0>,
<12 0>, <13 0>, <14 0>, <15 0>,
<16 0>;
};
};
};
&gpio9 {
interrupts = <99 0>;
};
&gpio11 {
/* GPIO 7-11 share the same interrupt on the CM4 */
interrupts = <99 0>;
status = "disabled";
};
dts/arm/nxp/nxp_rt1160_cm7.dtsi
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/*
* Copyright (c) 2021, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/nxp_rt11xx.dtsi>
/ {
cpus {
/delete-node/ cpu@1;
};
/*
* ITCM & DTCM are available only to the M7 core. EDMA interrupts are connected
* to the M7 core alone, hence this EDMA controller has been designated M7 only.
* GPIO 6 is available to both M4 and M7 cores, however the GPIO interrupt is
* only accesssible to the M7.
*
* Refer to Chapter 3 of the Reference Manual
*/
soc {
flexram: flexram@40028000 {
reg = <0x40028000 0x4000>;
interrupts = <50 0>;
#address-cells = <1>;
#size-cells = <1>;
itcm: itcm@0 {
compatible = "nxp,imx-itcm";
reg = <0x00000000 DT_SIZE_K(256)>;
};
dtcm: dtcm@20000000 {
compatible = "nxp,imx-dtcm";
reg = <0x20000000 DT_SIZE_K(256)>;
};
};
/*
* M7 uses different addresses from the M4 core for GPIO2 and
* GPIO3, see pg. 1460 of RT1160 ref manual for example
*/
gpio2: gpio@42008000 {
compatible = "nxp,imx-gpio";
reg = <0x42008000 0x4000>;
interrupts = <102 0>, <103 0>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
};
gpio3: gpio@4200c000 {
compatible = "nxp,imx-gpio";
reg = <0x4200c000 0x4000>;
interrupts = <104 0>, <105 0>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
};
edma0: dma-controller@40070000 {
#dma-cells = <2>;
compatible = "nxp,mcux-edma";
dma-channels = <32>;
dma-requests = <208>;
nxp,mem2mem;
nxp,a_on;
reg = <0x40070000 0x4000>,
<0x40074000 0x4000>;
clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
status = "disabled";
label = "DMA_0";
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>,
<8 0>, <9 0>, <10 0>, <11 0>,
<12 0>, <13 0>, <14 0>, <15 0>,
<16 0>;
};
};
};
&gpio6 {
interrupts = <61 0>, <62 0>;
};
dts/arm/nxp/nxp_rt1170_cm4.dtsi
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/*
* Copyright (c) 2021, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/nxp_rt11xx.dtsi>
/ {
cpus {
/delete-node/ cpu@0;
};
/*
* SRAM0 & SRAM1 are available only to the M4 core. EDMA_LPSR interrupts are connected
* to the M4 core alone, hence this EDMA controller has been designated M4 only.
* GPIO's 9, 11 are available to both M4 and M7 cores, however the GPIO interrupts are
* only accesssible to the M4.
*
* Refer to Chapter 3 of the Reference Manual
*/
soc {
sram0: memory@1ffe0000 {
compatible = "mmio-sram";
reg = <0x1ffe0000 DT_SIZE_K(128)>;
};
sram1: memory@20000000 {
compatible = "mmio-sram";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "SRAM1";
};
/*
* M4 uses different addresses from the M7 core for GPIO2 and
* GPIO3, see pg. 1410 of RT1170 ref manual for example
*/
gpio2: gpio@40130000 {
compatible = "nxp,imx-gpio";
reg = <0x40130000 0x4000>;
interrupts = <102 0>, <103 0>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
};
gpio3: gpio@40134000 {
compatible = "nxp,imx-gpio";
reg = <0x40134000 0x4000>;
interrupts = <104 0>, <105 0>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
};
edma_lpsr0: dma-controller@40c14000 {
#dma-cells = <2>;
compatible = "nxp,mcux-edma";
dma-channels = <32>;
dma-requests = <208>;
nxp,mem2mem;
nxp,a_on;
reg = <0x40c14000 0x4000>,
<0x40c18000 0x4000>;
clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
status = "disabled";
label = "DMA_0";
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>,
<8 0>, <9 0>, <10 0>, <11 0>,
<12 0>, <13 0>, <14 0>, <15 0>,
<16 0>;
};
};
};
&gpio9 {
interrupts = <99 0>;
};
&gpio11 {
/* GPIO 7-11 share the same interrupt on the CM4 */
interrupts = <99 0>;
status = "disabled";
};
dts/arm/nxp/nxp_rt1170_cm7.dtsi
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/*
* Copyright (c) 2021, NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/nxp_rt11xx.dtsi>
/ {
cpus {
/delete-node/ cpu@1;
};
/*
* ITCM & DTCM are available only to the M7 core. EDMA interrupts are connected
* to the M7 core alone, hence this EDMA controller has been designated M7 only.
* GPIO 6 is available to both M4 and M7 cores, however the GPIO interrupt is
* only accesssible to the M7.
*
* Refer to Chapter 3 of the Reference Manual
*/
soc {
flexram: flexram@40028000 {
reg = <0x40028000 0x4000>;
interrupts = <50 0>;
#address-cells = <1>;
#size-cells = <1>;
itcm: itcm@0 {
compatible = "nxp,imx-itcm";
reg = <0x00000000 DT_SIZE_K(256)>;
zephyr,memory-region = "ITCM";
};
dtcm: dtcm@20000000 {
compatible = "nxp,imx-dtcm";
reg = <0x20000000 DT_SIZE_K(256)>;
zephyr,memory-region = "DTCM";
};
};
/*
* M7 uses different addresses from the M4 core for GPIO2 and
* GPIO3, see pg. 1460 of RT1170 ref manual for example
*/
gpio2: gpio@42008000 {
compatible = "nxp,imx-gpio";
reg = <0x42008000 0x4000>;
interrupts = <102 0>, <103 0>;
label = "GPIO_2";
gpio-controller;
#gpio-cells = <2>;
};
gpio3: gpio@4200c000 {
compatible = "nxp,imx-gpio";
reg = <0x4200c000 0x4000>;
interrupts = <104 0>, <105 0>;
label = "GPIO_3";
gpio-controller;
#gpio-cells = <2>;
};
edma0: dma-controller@40070000 {
#dma-cells = <2>;
compatible = "nxp,mcux-edma";
dma-channels = <32>;
dma-requests = <208>;
nxp,mem2mem;
nxp,a_on;
reg = <0x40070000 0x4000>,
<0x40074000 0x4000>;
clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
status = "disabled";
label = "DMA_0";
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>,
<8 0>, <9 0>, <10 0>, <11 0>,
<12 0>, <13 0>, <14 0>, <15 0>,
<16 0>;
};
};
};
&gpio6 {
interrupts = <61 0>, <62 0>;
};
dts/arm/st/f0/stm32f0.dtsi
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/*
* Copyright (c) 2017 RnDity Sp. z o.o.
* Copyright (c) 2019 Centaur Analytics, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv6-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <freq.h>
/ {
chosen {
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m0";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "st,stm32-hse-clock";
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(8)>;
status = "disabled";
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(40)>;
status = "disabled";
};
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32f0-pll-clock";
status = "disabled";
};
};
soc {
flash: flash-controller@40022000 {
compatible = "st,stm32-flash-controller", "st,stm32f0-flash-controller";
label = "FLASH_CTRL";
reg = <0x40022000 0x400>;
interrupts = <3 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
label = "FLASH_STM32";
write-block-size = <2>;
/* maximum erase time for a 2K sector */
max-erase-time = <40>;
};
};
rcc: rcc@40021000 {
compatible = "st,stm32f0-rcc";
#clock-cells = <2>;
reg = <0x40021000 0x400>;
};
exti: interrupt-controller@40010400 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x40010400 0x400>;
};
pinctrl: pin-controller@48000000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x48000000 0x1800>;
gpioa: gpio@48000000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
label = "GPIOA";
};
gpiob: gpio@48000400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "GPIOB";
};
gpioc: gpio@48000800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
label = "GPIOC";
};
gpiod: gpio@48000c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
label = "GPIOD";
};
gpiof: gpio@48001400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
label = "GPIOF";
};
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00004000>;
interrupts = <27 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <28 0>;
status = "disabled";
label = "UART_2";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <23 0>;
interrupt-names = "combined";
status = "disabled";
label= "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <24 0>;
interrupt-names = "combined";
status = "disabled";
label= "I2C_2";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00001000>;
interrupts = <25 3>;
status = "disabled";
label = "SPI_1";
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
interrupts = <2 0>;
prescaler = <32768>;
status = "disabled";
label = "RTC_0";
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
label = "IWDG";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 2>;
status = "disabled";
};
timers1: timers@40012c00 {
compatible = "st,stm32-timers";
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000800>;
interrupts = <13 0>, <14 0>;
interrupt-names = "brk_up_trg_com", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_1";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_1";
#pwm-cells = <3>;
};
};
timers3: timers@40000400 {
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
interrupts = <16 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_3";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_3";
#pwm-cells = <3>;
};
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
interrupts = <17 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_6";
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
interrupts = <18 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_7";
};
timers14: timers@40002000 {
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
interrupts = <19 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_14";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_14";
#pwm-cells = <3>;
};
};
timers15: timers@40014000 {
compatible = "st,stm32-timers";
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00010000>;
interrupts = <20 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_15";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_15";
#pwm-cells = <3>;
};
};
timers16: timers@40014400 {
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00020000>;
interrupts = <21 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_16";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_16";
#pwm-cells = <3>;
};
};
timers17: timers@40014800 {
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00040000>;
interrupts = <22 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_17";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_17";
#pwm-cells = <3>;
};
};
adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>;
interrupts = <12 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <9 0 10 0 10 0 11 0 11 0>;
status = "disabled";
label = "DMA_1";
};
};
};
&nvic {
arm,num-irq-priority-bits = <2>;
};
dts/arm/st/f0/stm32f030.dtsi
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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f0/stm32f0.dtsi>
/ {
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
erase-block-size = <1024>;
};
};
};
};
dts/arm/st/f0/stm32f030X4.dtsi
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/*
* Copyright (c) 2019 Antony Pavlov <antonynpavlov@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f0/stm32f030.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(4)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(16)>;
};
};
};
};
dts/arm/st/f0/stm32f030X8.dtsi
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/*
* Copyright (c) 2018 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f0/stm32f030.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(8)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(64)>;
};
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
};
};
dts/arm/st/f0/stm32f030Xc.dtsi
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/*
* Copyright (c) 2018 Intel Corporation.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f0/stm32f030.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(256)>;
};
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
/*
* USARTs 3-6 share the same IRQ on stm32f030Xc devices. This
* configuration is not currently supported, so at most one of
* these may be enabled at a time. Enabling more than one will
* result in a build failure.
*/
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <29 0>;
status = "disabled";
label = "UART_3";
};
usart4: serial@40004c00 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <29 0>;
status = "disabled";
label = "UART_4";
};
usart5: serial@40005000 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <29 0>;
status = "disabled";
label = "UART_5";
};
usart6: serial@40011400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000020>;
interrupts = <29 0>;
status = "disabled";
label = "UART_6";
};
};
};
dts/arm/st/f0/stm32f031.dtsi
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/*
* Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f0/stm32f0.dtsi>
/ {
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
erase-block-size = <1024>;
};
};
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
interrupts = <15 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_2";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_2";
#pwm-cells = <3>;
};
};
};
};
dts/arm/st/f0/stm32f031X6.dtsi
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/*
* Copyright (c) 2021 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f0/stm32f031.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(4)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(32)>;
};
};
};
};
dts/arm/st/f0/stm32f051.dtsi
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/*
* Copyright (c) 2018 Nathan Tsoi <nathan@vertile.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f0/stm32f0.dtsi>
/ {
soc {
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
flash-controller@40022000 {
flash0: flash@8000000 {
erase-block-size = <1024>;
};
};
};
};
dts/arm/st/f0/stm32f051X8.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f0/stm32f051.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(8)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(64)>;
};
};
};
};
dts/arm/st/f0/stm32f070.dtsi
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/*
* Copyright (c) 2018 qianfan Zhao
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f0/stm32f0.dtsi>
/ {
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
erase-block-size = <2048>;
};
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
usb: usb@40005c00 {
compatible = "st,stm32-usb";
reg = <0x40005c00 0x400>;
interrupts = <31 0>;
interrupt-names = "usb";
num-bidir-endpoints = <8>;
ram-size = <1024>;
phys = <&usb_fs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
status = "disabled";
label= "USB";
};
};
usb_fs_phy: usbphy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "USB_FS_PHY";
};
};
dts/arm/st/f0/stm32f070Xb.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f0/stm32f070.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
};
};
};
};
dts/arm/st/f0/stm32f072.dtsi
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/*
* Copyright (c) 2017 BayLibre, SAS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f0/stm32f0.dtsi>
/ {
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
erase-block-size = <2048>;
};
};
pinctrl: pin-controller@48000000 {
gpioe: gpio@48001000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
label = "GPIOE";
};
};
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
interrupts = <15 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_2";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_2";
#pwm-cells = <3>;
};
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
usb: usb@40005c00 {
compatible = "st,stm32-usb";
reg = <0x40005c00 0x400>;
interrupts = <31 0>;
interrupt-names = "usb";
num-bidir-endpoints = <8>;
ram-size = <1024>;
phys = <&usb_fs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
status = "disabled";
label= "USB";
};
can1: can@40006400 {
compatible = "st,stm32-can";
reg = <0x40006400 0x400>;
interrupts = <30 0>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
bus-speed = <250000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
dma1: dma@40020000 {
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
};
};
usb_fs_phy: usbphy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "USB_FS_PHY";
};
};
dts/arm/st/f0/stm32f072Xb.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f0/stm32f072.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
};
};
};
};
dts/arm/st/f0/stm32f091.dtsi
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/*
* Copyright (c) Bobby Noelte
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f0/stm32f0.dtsi>
/ {
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
erase-block-size = <2048>;
};
};
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
interrupts = <15 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_2";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_2";
#pwm-cells = <3>;
};
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <26 3>;
status = "disabled";
label = "SPI_2";
};
pinctrl: pin-controller@48000000 {
gpioe: gpio@48001000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
label = "GPIOE";
};
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
dma1: dma@40020000 {
interrupts = <9 0 10 0 10 0 11 0 11 0 11 0 11 0>;
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
interrupts = <10 0 10 0 11 0 11 0 11 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
status = "disabled";
label = "DMA_2";
};
};
};
dts/arm/st/f0/stm32f091Xc.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f0/stm32f091.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(256)>;
};
};
};
};
dts/arm/st/f0/stm32f098Xc.dtsi
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/*
* Copyright (c) 2019 The Chromium OS Authors
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f0/stm32f091.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(256)>;
};
};
};
};
dts/arm/st/f1/stm32f1.dtsi
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/*
* Copyright (c) 2017 Linaro Limited
* Copyright (c) 2019 Centaur Analytics, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <freq.h>
/ {
chosen {
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "st,stm32-hse-clock";
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(8)>;
status = "disabled";
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(40)>;
status = "disabled";
};
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32f1-pll-clock";
status = "disabled";
};
};
soc {
flash: flash-controller@40022000 {
compatible = "st,stm32-flash-controller", "st,stm32f1-flash-controller";
label = "FLASH_CTRL";
reg = <0x40022000 0x400>;
interrupts = <3 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
label = "FLASH_STM32";
write-block-size = <2>;
/* maximum erase time for a 2K sector */
max-erase-time = <40>;
};
};
rcc: rcc@40021000 {
compatible = "st,stm32-rcc";
#clock-cells = <2>;
reg = <0x40021000 0x400>;
};
exti: interrupt-controller@40010400 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x40010400 0x400>;
};
pinctrl: pin-controller@40010800 {
compatible = "st,stm32f1-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40010800 0x1C00>;
gpioa: gpio@40010800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40010800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000005>;
label = "GPIOA";
};
gpiob: gpio@40010c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40010c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000009>;
label = "GPIOB";
};
gpioc: gpio@40011000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000011>;
label = "GPIOC";
};
gpiod: gpio@40011400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000021>;
label = "GPIOD";
};
gpioe: gpio@40011800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40011800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000041>;
label = "GPIOE";
};
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
status = "disabled";
label = "SPI_1";
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
label = "IWDG";
status = "disabled";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
timers1: timers@40012c00 {
compatible = "st,stm32-timers";
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_1";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_1";
#pwm-cells = <3>;
};
};
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
interrupts = <28 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_2";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_2";
#pwm-cells = <3>;
};
};
timers3: timers@40000400 {
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_3";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_3";
#pwm-cells = <3>;
};
};
timers4: timers@40000800 {
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_4";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_4";
#pwm-cells = <3>;
};
};
adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
status = "disabled";
label = "DMA_1";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
dts/arm/st/f1/stm32f100Xb.dtsi
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/*
* Copyright (c) 2020 Jonas Eriksson, Up to Code AB
*
* SoC device tree include for STM32F100xB SoCs
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f1/stm32f1.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(8)>;
};
clocks {
/delete-node/ pll;
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32f100-pll-clock";
status = "disabled";
};
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
erase-block-size = <DT_SIZE_K(1)>;
};
};
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
};
};
dts/arm/st/f1/stm32f100Xe.dtsi
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/*
* Copyright (c) 2020 Jonas Eriksson, Up to Code AB
*
* SoC device tree include for STM32F100xE SoCs
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f1/stm32f100Xb.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
};
};
dts/arm/st/f1/stm32f103X8.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f1/stm32f1.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(20)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(64)>;
erase-block-size = <DT_SIZE_K(1)>;
};
};
/* spi2 is present on all STM32F103x8 SoCs except
* STM32F103T8. Delete node in stm32f103t8.dtsi.
*/
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
usb: usb@40005c00 {
compatible = "st,stm32-usb";
reg = <0x40005c00 0x400>;
interrupts = <20 0>;
interrupt-names = "usb";
num-bidir-endpoints = <8>;
ram-size = <512>;
status = "disabled";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
phys = <&usb_fs_phy>;
label= "USB";
};
can1: can@40006400 {
compatible = "st,stm32-can";
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
};
};
usb_fs_phy: usbphy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "USB_FS_PHY";
};
};
dts/arm/st/f1/stm32f103Xb.dtsi
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/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SoC device tree include for STM32F103xB SoCs
* where 'x' is replaced for specific SoCs like {C,R,T,V}
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f1/stm32f103X8.dtsi>
/ {
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
erase-block-size = <DT_SIZE_K(1)>;
};
};
/* spi2 is present on all STM32F103xB SoCs except
* STM32F103TB. Delete node in stm32f103tb.dtsi.
*/
};
};
dts/arm/st/f1/stm32f103Xc.dtsi
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/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SoC device tree include for STM32F103xC SoCs
* where 'x' is replaced for specific SoCs like {R,V,Z}
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f1/stm32f103Xb.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(48)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(256)>;
erase-block-size = <DT_SIZE_K(2)>;
};
};
uart4: serial@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
timers5: timers@40000c00 {
compatible = "st,stm32-timers";
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_5";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_5";
#pwm-cells = <3>;
};
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_6";
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_7";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0X40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
label = "SPI_3";
status = "disabled";
};
pinctrl: pin-controller@40010800 {
reg = <0x40010800 0x2000>;
gpiof: gpio@40011c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000081>;
label = "GPIOF";
};
gpiog: gpio@40012000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40012000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000101>;
label = "GPIOG";
};
};
adc2: adc@40012800 {
compatible = "st,stm32-adc";
reg = <0x40012800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
/* Shares vector with ADC1 */
interrupts = <18 0>;
status = "disabled";
label = "ADC_2";
#io-channel-cells = <1>;
};
adc3: adc@40013c00 {
compatible = "st,stm32-adc";
reg = <0x40013c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00008000>;
interrupts = <47 0>;
status = "disabled";
label = "ADC_3";
#io-channel-cells = <1>;
};
timers8: timers@40013400 {
compatible = "st,stm32-timers";
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_8";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_8";
#pwm-cells = <3>;
};
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = < 56 0 57 0 58 0 59 0 60 0>;
status = "disabled";
label = "DMA_2";
};
};
};
dts/arm/st/f1/stm32f103Xd.dtsi
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/*
* Copyright (c) 2021 Teltonika
*
* SoC device tree include for STM32F103xD SoCs
* where 'x' is replaced for specific SoCs like {R,V,Z}
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f1/stm32f103Xc.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(64)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(384)>;
erase-block-size = <DT_SIZE_K(2)>;
};
};
};
};
dts/arm/st/f1/stm32f103Xe.dtsi
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/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SoC device tree include for STM32F103xE SoCs
* where 'x' is replaced for specific SoCs like {R,V,Z}
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f1/stm32f103Xd.dtsi>
/ {
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
erase-block-size = <DT_SIZE_K(2)>;
};
};
};
};
dts/arm/st/f1/stm32f103Xg.dtsi
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/* SPDX-License-Identifier: Apache-2.0
*
* Copyright (c) 2020 Google, LLC
*
* SoC device tree include for STM32F103xG SoCs
* where 'x' is replaced for specific SoCs like {R,V,Z}
*/
#include <mem.h>
#include <st/f1/stm32f103Xe.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(96)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
/* Note that there are actually two banks of
* flash (512KB each) and two flash controllers.
* This matters if you're doing in-application
* flash programming and you need the
* read-while-write capabilities, but is
* otherwise a non-issue.
*/
reg = <0x08000000 DT_SIZE_K(1024)>;
erase-block-size = <DT_SIZE_K(2)>;
};
};
timers9: timers@40014c00 {
compatible = "st,stm32-timers";
reg = <0x40014c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
/* Shared with TIM1_BRK */
interrupts = <24 0>;
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_9";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_9";
#pwm-cells = <3>;
};
};
timers10: timers@40015000 {
compatible = "st,stm32-timers";
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
/* Shared with TIM1_UP */
interrupts = <25 0>;
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_10";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_10";
#pwm-cells = <3>;
};
};
timers11: timers@40015400 {
compatible = "st,stm32-timers";
reg = <0x40015400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
/* Shared with TIM1_TRG_COM */
interrupts = <26 0>;
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_11";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_11";
#pwm-cells = <3>;
};
};
timers12: timers@40001800 {
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
/* Shared with TIM8_BRK */
interrupts = <43 0>;
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_12";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_12";
#pwm-cells = <3>;
};
};
timers13: timers@40001c00 {
compatible = "st,stm32-timers";
reg = <0x40001c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
/* Shared with TIM8_UP */
interrupts = <44 0>;
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_13";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_13";
#pwm-cells = <3>;
};
};
timers14: timers@40002000 {
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
/* Shared with TIM8_TRG_COM */
interrupts = <45 0>;
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_14";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_14";
#pwm-cells = <3>;
};
};
};
};
dts/arm/st/f1/stm32f105.dtsi
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/*
* Copyright (c) 2019 Argentum Systems Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f1/stm32f1.dtsi>
/ {
clocks {
/delete-node/ pll;
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32f105-pll-clock";
status = "disabled";
};
pll2: pll2 {
#clock-cells = <0>;
compatible = "st,stm32f105-pll2-clock";
clocks = <&clk_hse>;
status = "disabled";
};
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
erase-block-size = <DT_SIZE_K(2)>;
};
};
can1: can@40006400 {
compatible = "st,stm32-can";
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
bus-speed = <250000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
can2: can@40006800 {
compatible = "st,stm32-can";
reg = <0x40006800 0x400>;
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
status = "disabled";
label = "CAN_2";
bus-speed = <250000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
uart4: serial@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
timers5: timers@40000c00 {
compatible = "st,stm32-timers";
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_5";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_5";
#pwm-cells = <3>;
};
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_6";
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_7";
};
usbotg_fs: usb@50000000 {
compatible = "st,stm32-otgfs";
reg = <0x50000000 0x40000>;
interrupts = <67 0>;
interrupt-names = "otgfs";
num-bidir-endpoints = <4>;
ram-size = <1280>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00001000>;
phys = <&otgfs_phy>;
status = "disabled";
label = "OTGFS";
};
};
otgfs_phy: otgfs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "OTGFS_PHY";
};
};
dts/arm/st/f1/stm32f105Xc.dtsi
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/*
* Copyright (c) 2019 Argentum Systems Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f1/stm32f105.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(64)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(256)>;
};
};
};
};
dts/arm/st/f1/stm32f107.dtsi
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/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f1/stm32f105.dtsi>
/ {
soc {
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
status = "disabled";
label = "DMA_2";
};
};
};
dts/arm/st/f1/stm32f107Xc.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f1/stm32f107.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(64)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(256)>;
};
};
};
};
dts/arm/st/f2/stm32f2.dtsi
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/*
* Copyright (c) 2018 qianfan Zhao
* Copyright (c) 2019 Centaur Analytics, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <freq.h>
/ {
chosen {
zephyr,entropy = &rng;
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m3";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "st,stm32-hse-clock";
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(16)>;
status = "disabled";
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(32)>;
status = "disabled";
};
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32f2-pll-clock";
status = "disabled";
};
};
soc {
flash: flash-controller@40023c00 {
compatible = "st,stm32-flash-controller", "st,stm32f2-flash-controller";
label = "FLASH_CTRL";
reg = <0x40023c00 0x400>;
interrupts = <4 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
label = "FLASH_STM32";
write-block-size = <1>;
/* maximum erase time(ms) for a 128K sector */
max-erase-time = <4000>;
};
};
rcc: rcc@40023800 {
compatible = "st,stm32-rcc";
#clock-cells = <2>;
reg = <0x40023800 0x400>;
};
exti: interrupt-controller@40013c00 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x40013c00 0x400>;
};
pinctrl: pin-controller@40020000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40020000 0x2000>;
gpioa: gpio@40020000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
label = "GPIOA";
};
gpiob: gpio@40020400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
label = "GPIOB";
};
gpioc: gpio@40020800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
label = "GPIOC";
};
gpiod: gpio@40020c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
label = "GPIOD";
};
gpioe: gpio@40021000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
label = "GPIOE";
};
gpiof: gpio@40021400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
label = "GPIOF";
};
gpiog: gpio@40021800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
label = "GPIOG";
};
gpioh: gpio@40021c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
label = "GPIOH";
};
gpioi: gpio@40022000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
label = "GPIOI";
};
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
interrupts = <41 0>;
prescaler = <32768>;
status = "disabled";
label = "RTC_0";
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
label = "IWDG";
status = "disabled";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
usart6: serial@40011400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
interrupts = <71 0>;
status = "disabled";
label = "UART_6";
};
uart4: serial@40004c00 {
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
status = "disabled";
label = "SPI_1";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
i2c3: i2c@40005c00 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
interrupts = <72 0>, <73 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_3";
};
usbotg_fs: usb@50000000 {
compatible = "st,stm32-otgfs";
reg = <0x50000000 0x40000>;
interrupts = <67 0>;
interrupt-names = "otgfs";
num-bidir-endpoints = <4>;
ram-size = <1280>;
maximum-speed = "full-speed";
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
phys = <&otgfs_phy>;
status = "disabled";
label = "OTGFS";
};
adc1: adc@40012000 {
compatible = "st,stm32-adc";
reg = <0x40012000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
dma1: dma@40026000 {
compatible = "st,stm32-dma-v1";
#dma-cells = <4>;
reg = <0x40026000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
status = "disabled";
label = "DMA_1";
};
dma2: dma@40026400 {
compatible = "st,stm32-dma-v1";
#dma-cells = <4>;
reg = <0x40026400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
timers1: timers@40010000 {
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_1";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_1";
#pwm-cells = <3>;
};
};
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
interrupts = <28 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_2";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_2";
#pwm-cells = <3>;
};
};
timers3: timers@40000400 {
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_3";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_3";
#pwm-cells = <3>;
};
};
timers4: timers@40000800 {
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_4";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_4";
#pwm-cells = <3>;
};
};
timers5: timers@40000c00 {
compatible = "st,stm32-timers";
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_5";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_5";
#pwm-cells = <3>;
};
};
timers8: timers@40010400 {
compatible = "st,stm32-timers";
reg = <0x40010400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_8";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_8";
#pwm-cells = <3>;
};
};
timers9: timers@40014000 {
compatible = "st,stm32-timers";
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
interrupts = <24 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_9";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_9";
#pwm-cells = <3>;
};
};
timers12: timers@40001800 {
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
interrupts = <43 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_12";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_12";
#pwm-cells = <3>;
};
};
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
interrupts = <80 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
status = "disabled";
label = "RNG";
};
backup_sram: memory@40024000 {
compatible = "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "BACKUP_SRAM";
zephyr,memory-region = "BACKUP_SRAM";
status = "disabled";
};
};
otgfs_phy: otgfs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "OTGFS_PHY";
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
dts/arm/st/f2/stm32f205Xe.dtsi
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/*
* Copyright (c) 2021 Manuel Forcen <manuforcen@gmail.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f2/stm32f2.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};
dts/arm/st/f2/stm32f207.dtsi
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/*
* Copyright (c) 2018 qianfan Zhao
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f2/stm32f2.dtsi>
/ {
soc {
mac: ethernet@40028000 {
compatible = "st,stm32-ethernet";
reg = <0x40028000 0x8000>;
label = "ETH_0";
interrupts = <61 0>;
clock-names = "stmmaceth", "mac-clk-tx",
"mac-clk-rx", "mac-clk-ptp";
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
<&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
<&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
<&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
status = "disabled";
};
};
};
dts/arm/st/f2/stm32f207Xe.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f2/stm32f207.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};
dts/arm/st/f2/stm32f207Xg.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f2/stm32f207.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(1024)>;
};
};
};
};
dts/arm/st/f3/stm32f3.dtsi
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/*
* Copyright (c) 2017 I-SENSE group of ICCS
* Copyright (c) 2019 Centaur Analytics, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <freq.h>
/ {
chosen {
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "st,stm32-hse-clock";
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(8)>;
status = "disabled";
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(40)>;
status = "disabled";
};
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32f0-pll-clock";
status = "disabled";
};
};
soc {
flash: flash-controller@40022000 {
compatible = "st,stm32-flash-controller", "st,stm32f3-flash-controller";
label = "FLASH_CTRL";
reg = <0x40022000 0x400>;
interrupts = <4 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
label = "FLASH_STM32";
write-block-size = <2>;
erase-block-size = <2048>;
/* maximum erase time for a 2K sector */
max-erase-time = <40>;
};
};
rcc: rcc@40021000 {
compatible = "st,stm32-rcc";
#clock-cells = <2>;
reg = <0x40021000 0x400>;
};
exti: interrupt-controller@40010400 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x40010400 0x400>;
};
pinctrl: pin-controller@48000000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x48000000 0x1800>;
gpioa: gpio@48000000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00020000>;
label = "GPIOA";
};
gpiob: gpio@48000400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "GPIOB";
};
gpioc: gpio@48000800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00080000>;
label = "GPIOC";
};
gpiod: gpio@48000c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00100000>;
label = "GPIOD";
};
gpiof: gpio@48001400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00400000>;
label = "GPIOF";
};
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
label = "IWDG";
status = "disabled";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40013800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40013800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00004000>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
uart4: serial@40004c00 {
compatible = "st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
status = "disabled";
label = "SPI_1";
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
usb: usb@40005c00 {
compatible = "st,stm32-usb";
reg = <0x40005c00 0x400>;
interrupts = <20 0>;
interrupt-names = "usb";
num-bidir-endpoints = <8>;
ram-size = <512>;
phys = <&usb_fs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
status = "disabled";
label= "USB";
};
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
interrupts = <28 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_2";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_2";
#pwm-cells = <3>;
};
};
timers3: timers@40000400 {
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_3";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_3";
#pwm-cells = <3>;
};
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_6";
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_7";
};
timers15: timers@40014000 {
compatible = "st,stm32-timers";
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
interrupts = <24 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_15";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_15";
#pwm-cells = <3>;
};
};
timers16: timers@40014400 {
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
interrupts = <25 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_16";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_16";
#pwm-cells = <3>;
};
};
timers17: timers@40014800 {
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
interrupts = <26 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_17";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_17";
#pwm-cells = <3>;
};
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
interrupts = <41 0>;
prescaler = <32768>;
status = "disabled";
label = "RTC_0";
};
can1: can@40006400 {
compatible = "st,stm32-can";
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
bus-speed = <125000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
dma1: dma@40020000 {
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x1>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0>;
status = "disabled";
label = "DMA_1";
};
};
usb_fs_phy: usbphy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "USB_FS_PHY";
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
dts/arm/st/f3/stm32f302.dtsi
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/*
* Copyright (c) 2018 Seitz & Associates
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f3/stm32f3.dtsi>
/ {
soc {
usb: usb@40005c00 {
/* Remap USB_LP IRQ to enable use with CAN_1 */
interrupts = <75 0>;
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
i2c3: i2c@40007800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
interrupts = <72 0>, <73 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_3";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0X40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
timers1: timers@40012c00 {
compatible = "st,stm32-timers";
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_1";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_1";
#pwm-cells = <3>;
};
};
adc1: adc@50000000 {
compatible = "st,stm32-adc";
reg = <0x50000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
};
};
dts/arm/st/f3/stm32f302X8.dtsi
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/*
* Copyright (c) 2018 Seitz & Associates
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f3/stm32f302.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(16)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(64)>;
};
};
};
};
/delete-node/ &spi1;
dts/arm/st/f3/stm32f303.dtsi
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/*
* Copyright (c) 2017 I-SENSE group of ICCS
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f3/stm32f3.dtsi>
/ {
soc {
usb: usb@40005c00 {
/* Remap USB_LP IRQ to enable use with CAN_1 */
interrupts = <75 0>;
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
pinctrl: pin-controller@48000000 {
gpioe: gpio@48001000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
label = "GPIOE";
};
};
timers1: timers@40012c00 {
compatible = "st,stm32-timers";
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_1";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_1";
#pwm-cells = <3>;
};
};
timers4: timers@40000800 {
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_4";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_4";
#pwm-cells = <3>;
};
};
timers8: timers@40013400 {
compatible = "st,stm32-timers";
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_8";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_8";
#pwm-cells = <3>;
};
};
timers20: timers@40015000 {
compatible = "st,stm32-timers";
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
interrupts = <77 0>, <78 0>, <79 0>, <80 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_20";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_20";
#pwm-cells = <3>;
};
};
adc1: adc@50000000 {
compatible = "st,stm32-adc";
reg = <0x50000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
};
};
dts/arm/st/f3/stm32f303X8.dtsi
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/*
* Copyright (c) 2020 Sebastian Schwabe <sebastian.schwabe@mailbox.tu-dresden.de>
* Fabian Paschke <fabian.paschke@eas.iis.fraunhofer.de>
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f3/stm32f303.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(8)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(12)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(64)>;
};
};
dac2: dac@40009800 {
compatible = "st,stm32-dac";
reg = <0x40009800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
status = "disabled";
label = "DAC_2";
#io-channel-cells = <1>;
};
};
};
dts/arm/st/f3/stm32f303Xc.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f3/stm32f303.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(8)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(40)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(256)>;
};
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
status = "disabled";
label = "DMA_2";
};
};
};
dts/arm/st/f3/stm32f303Xe.dtsi
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/*
* Copyright (c) 2020 Paul M. Bendixen
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f3/stm32f303.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(16)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(64)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2bis";
#dma-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
status = "disabled";
label = "DMA_2";
};
};
};
dts/arm/st/f3/stm32f334.dtsi
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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f3/stm32f3.dtsi>
/ {
soc {
timers1: timers@40012c00 {
compatible = "st,stm32-timers";
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_1";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_1";
#pwm-cells = <3>;
};
};
adc1: adc@50000000 {
compatible = "st,stm32-adc";
reg = <0x50000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
};
};
/delete-node/ &usb;
dts/arm/st/f3/stm32f334X8.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f3/stm32f334.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(4)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(12)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(64)>;
};
};
dac2: dac@40009800 {
compatible = "st,stm32-dac";
reg = <0x40009800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
status = "disabled";
label = "DAC_2";
#io-channel-cells = <1>;
};
};
};
dts/arm/st/f3/stm32f373.dtsi
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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f3/stm32f3.dtsi>
/ {
soc {
pinctrl: pin-controller@48000000 {
gpioe: gpio@48001000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x48001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00200000>;
label = "GPIOE";
};
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
timers4: timers@40000800 {
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_4";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_4";
#pwm-cells = <3>;
};
};
timers5: timers@40000c00 {
compatible = "st,stm32-timers";
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_5";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_5";
#pwm-cells = <3>;
};
};
timers12: timers@40001800 {
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
interrupts = <43 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_12";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_12";
#pwm-cells = <3>;
};
};
timers13: timers@40001c00 {
compatible = "st,stm32-timers";
reg = <0x40001c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
interrupts = <44 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_13";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_13";
#pwm-cells = <3>;
};
};
timers14: timers@40002000 {
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
interrupts = <45 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_14";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_14";
#pwm-cells = <3>;
};
};
timers18: timers@40009c00 {
compatible = "st,stm32-timers";
reg = <0x40009c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000200>;
interrupts = <27 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_18";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_18";
#pwm-cells = <3>;
};
};
timers19: timers@40015c00 {
compatible = "st,stm32-timers";
reg = <0x40015c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00080000>;
interrupts = <78 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_19";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_19";
#pwm-cells = <3>;
};
};
adc1: adc@40012400 {
compatible = "st,stm32-adc";
reg = <0x40012400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000200>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
};
};
dts/arm/st/f3/stm32f373Xc.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f3/stm32f373.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
flash-controller@40022000 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(256)>;
};
};
dma2: dma@40020400 {
compatible = "st,stm32-dma-v2bis";
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x2>;
interrupts = <56 0 57 0 58 0 59 0 60 0>;
status = "disabled";
label = "DMA_2";
};
dac2: dac@40009800 {
compatible = "st,stm32-dac";
reg = <0x40009800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
status = "disabled";
label = "DAC_2";
#io-channel-cells = <1>;
};
};
};
dts/arm/st/f4/stm32f4.dtsi
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/*
* Copyright (c) 2017 Linaro Limited
* Copyright (c) 2019 Centaur Analytics, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <freq.h>
/ {
chosen {
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m4f";
reg = <0>;
};
};
sram0: memory@20000000 {
compatible = "mmio-sram";
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "st,stm32-hse-clock";
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(16)>;
status = "disabled";
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(32)>;
status = "disabled";
};
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32f4-pll-clock";
status = "disabled";
};
};
soc {
flash: flash-controller@40023c00 {
compatible = "st,stm32-flash-controller", "st,stm32f4-flash-controller";
label = "FLASH_CTRL";
reg = <0x40023c00 0x400>;
interrupts = <4 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
label = "FLASH_STM32";
write-block-size = <1>;
/* maximum erase time (ms) for a 128K sector */
max-erase-time = <4000>;
};
};
rcc: rcc@40023800 {
compatible = "st,stm32-rcc";
#clock-cells = <2>;
reg = <0x40023800 0x400>;
};
exti: interrupt-controller@40013c00 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x40013c00 0x400>;
};
pinctrl: pin-controller@40020000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40020000 0x2000>;
gpioa: gpio@40020000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
label = "GPIOA";
};
gpiob: gpio@40020400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
label = "GPIOB";
};
gpioc: gpio@40020800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
label = "GPIOC";
};
gpiod: gpio@40020c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
label = "GPIOD";
};
gpioe: gpio@40021000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
label = "GPIOE";
};
gpiof: gpio@40021400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
label = "GPIOF";
};
gpiog: gpio@40021800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
label = "GPIOG";
};
gpioh: gpio@40021c00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
label = "GPIOH";
};
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
label = "IWDG";
status = "disabled";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart6: serial@40011400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
interrupts = <71 0>;
status = "disabled";
label = "UART_6";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_2";
};
i2c3: i2c@40005c00 {
compatible = "st,stm32-i2c-v1";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
interrupts = <72 0>, <73 0>;
interrupt-names = "event", "error";
status = "disabled";
label= "I2C_3";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
status = "disabled";
label = "SPI_1";
};
usbotg_fs: usb@50000000 {
compatible = "st,stm32-otgfs";
reg = <0x50000000 0x40000>;
interrupts = <67 0>;
interrupt-names = "otgfs";
num-bidir-endpoints = <4>;
ram-size = <1280>;
maximum-speed = "full-speed";
phys = <&otgfs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
status = "disabled";
label= "OTGFS";
};
timers1: timers@40010000 {
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_1";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_1";
#pwm-cells = <3>;
};
};
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
interrupts = <28 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_2";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_2";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_2";
};
};
timers3: timers@40000400 {
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_3";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_3";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_3";
};
};
timers4: timers@40000800 {
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_4";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_4";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_4";
};
};
timers5: timers@40000c00 {
compatible = "st,stm32-timers";
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_5";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_5";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_5";
};
};
timers9: timers@40014000 {
compatible = "st,stm32-timers";
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
interrupts = <24 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_9";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_9";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_9";
};
};
timers10: timers@40014400 {
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
interrupts = <25 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_10";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_10";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_10";
};
};
timers11: timers@40014800 {
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
interrupts = <26 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_11";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_11";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_11";
};
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x400>;
interrupts = <41 0>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
prescaler = <32768>;
status = "disabled";
label = "RTC_0";
};
adc1: adc@40012000 {
compatible = "st,stm32-adc";
reg = <0x40012000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
dma1: dma@40026000 {
compatible = "st,stm32-dma-v1";
#dma-cells = <4>;
reg = <0x40026000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
status = "disabled";
label = "DMA_1";
};
dma2: dma@40026400 {
compatible = "st,stm32-dma-v1";
#dma-cells = <4>;
reg = <0x40026400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
};
otgfs_phy: otgfs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "OTGFS_PHY";
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
dts/arm/st/f4/stm32f401.dtsi
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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f4.dtsi>
/ {
soc {
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
spi4: spi@40013400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <84 5>;
status = "disabled";
label = "SPI_4";
};
i2s2: i2s@40003800 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
dmas = <&dma1 4 0 0x400 0x3
&dma1 3 0 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_2";
};
i2s3: i2s@40003c00 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
dmas = <&dma1 5 0 0x400 0x3
&dma1 0 0 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_3";
};
};
};
dts/arm/st/f4/stm32f401Xc.dtsi
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/*
* Copyright (c) 2019 Linumiz
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f401.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(64)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(256)>;
};
};
};
};
dts/arm/st/f4/stm32f401Xe.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f401.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(96)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};
dts/arm/st/f4/stm32f405.dtsi
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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f401.dtsi>
/ {
chosen {
zephyr,entropy = &rng;
};
soc {
pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x2400>;
gpiof: gpio@40021400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
label = "GPIOF";
};
gpiog: gpio@40021800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
label = "GPIOG";
};
gpioi: gpio@40022000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
label = "GPIOI";
};
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
uart4: serial@40004c00 {
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_6";
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_6";
};
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_7";
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_7";
};
};
timers8: timers@40010400 {
compatible = "st,stm32-timers";
reg = <0x40010400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_8";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_8";
#pwm-cells = <3>;
};
};
timers12: timers@40001800 {
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
interrupts = <43 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_12";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_12";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_12";
};
};
timers13: timers@40001c00 {
compatible = "st,stm32-timers";
reg = <0x40001c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
interrupts = <44 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_13";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_13";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_13";
};
};
timers14: timers@40002000 {
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
interrupts = <45 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_14";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_14";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_14";
};
};
usbotg_hs: usb@40040000 {
compatible = "st,stm32-otghs";
reg = <0x40040000 0x40000>;
interrupts = <77 0>, <74 0>, <75 0>;
interrupt-names = "otghs", "ep1_out", "ep1_in";
num-bidir-endpoints = <6>;
ram-size = <4096>;
maximum-speed = "full-speed";
phys = <&otghs_fs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
status = "disabled";
label= "OTGHS";
};
can1: can@40006400 {
compatible = "st,stm32-can";
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
bus-speed = <125000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
can2: can@40006800 {
compatible = "st,stm32-can";
reg = <0x40006800 0x400>;
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
master-can-reg = <0x40006400>;
status = "disabled";
label = "CAN_2";
bus-speed = <125000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
interrupts = <80 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
status = "disabled";
label = "RNG";
};
backup_sram: memory@40024000 {
compatible = "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "BACKUP_SRAM";
zephyr,memory-region = "BACKUP_SRAM";
status = "disabled";
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
};
otghs_fs_phy: otghs_fs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "OTGHS_FS_PHY";
};
};
dts/arm/st/f4/stm32f405Xg.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f405.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(1024)>;
};
};
};
};
dts/arm/st/f4/stm32f407.dtsi
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/*
* Copyright (c) 2017 Erwin Rol <erwin@erwinrol.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f405.dtsi>
/ {
soc {
mac: ethernet@40028000 {
compatible = "st,stm32-ethernet";
reg = <0x40028000 0x8000>;
label = "ETH_0";
interrupts = <61 0>;
clock-names = "stmmaceth", "mac-clk-tx",
"mac-clk-rx", "mac-clk-ptp";
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x02000000>,
<&rcc STM32_CLOCK_BUS_AHB1 0x04000000>,
<&rcc STM32_CLOCK_BUS_AHB1 0x08000000>,
<&rcc STM32_CLOCK_BUS_AHB1 0x10000000>;
status = "disabled";
};
};
};
dts/arm/st/f4/stm32f407Xe.dtsi
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/*
* Copyright (c) 2020 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f407.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};
dts/arm/st/f4/stm32f407Xg.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f407.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(1024)>;
};
};
};
};
dts/arm/st/f4/stm32f410.dtsi
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/*
* Copyright (c) 2020 Hans Unzner
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f4.dtsi>
/ {
soc {
spi2: spi@40003800 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
spi5: spi@40015000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
interrupts = <85 5>;
status = "disabled";
label = "SPI_5";
};
i2s1: i2s@40013000 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
dmas = <&dma2 3 3 0x400 0x3
&dma2 2 3 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_1";
};
i2s2: i2s@40003800 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
dmas = <&dma1 4 0 0x400 0x3
&dma1 3 0 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_2";
};
i2s5: i2s@40015000 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
interrupts = <85 5>;
dmas = <&dma2 6 7 0x400 0x3
&dma2 5 7 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_5";
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_6";
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_6";
};
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
};
};
dts/arm/st/f4/stm32f410Xb.dtsi
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/*
* Copyright (c) 2020 Hans Unzner
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f410.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(32)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(128)>;
};
};
};
};
dts/arm/st/f4/stm32f411.dtsi
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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f401.dtsi>
/ {
soc {
spi5: spi@40015000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
interrupts = <85 5>;
status = "disabled";
label = "SPI_5";
};
i2s1: i2s@40013000 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
dmas = <&dma2 3 3 0x400 0x3
&dma2 2 3 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_1";
};
i2s4: i2s@40013400 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <84 5>;
dmas = <&dma2 1 4 0x400 0x3
&dma2 0 4 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_4";
};
i2s5: i2s@40015000 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
interrupts = <85 5>;
dmas = <&dma2 6 7 0x400 0x3
&dma2 5 7 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_5";
};
};
};
dts/arm/st/f4/stm32f411Xe.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f411.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};
dts/arm/st/f4/stm32f412.dtsi
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/*
* Copyright (c) 2017 Florian Vaussard, HEIG-VD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f411.dtsi>
/ {
chosen {
zephyr,entropy = &rng;
};
soc {
pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x1c00>;
gpiof: gpio@40021400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
label = "GPIOF";
};
gpiog: gpio@40021800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
label = "GPIOG";
};
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_6";
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_6";
};
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_7";
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_7";
};
};
timers8: timers@40010400 {
compatible = "st,stm32-timers";
reg = <0x40010400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_8";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_8";
#pwm-cells = <3>;
};
};
timers12: timers@40001800 {
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
interrupts = <43 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_12";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_12";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_12";
};
};
timers13: timers@40001c00 {
compatible = "st,stm32-timers";
reg = <0x40001c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
interrupts = <44 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_13";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_13";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_13";
};
};
timers14: timers@40002000 {
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
interrupts = <45 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_14";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_14";
#pwm-cells = <3>;
};
counter {
compatible = "st,stm32-counter";
status = "disabled";
label = "COUNTER_14";
};
};
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
interrupts = <80 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
status = "disabled";
label = "RNG";
};
usbotg_fs: usb@50000000 {
num-bidir-endpoints = <6>;
};
quadspi: quadspi@a0001000 {
compatible = "st,stm32-qspi";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xa0001000 0x400>;
interrupts = <92 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000002>;
status = "disabled";
label = "QUADSPI";
};
};
};
dts/arm/st/f4/stm32f412Xe.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f412.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(256)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};
dts/arm/st/f4/stm32f412Xg.dtsi
+22
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f412.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(256)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(1024)>;
};
};
};
};
dts/arm/st/f4/stm32f413.dtsi
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/*
* Copyright (c) 2017 Florian Vaussard, HEIG-VD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f412.dtsi>
/ {
soc {
uart4: serial@40004c00 {
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
uart7: serial@40007800 {
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
interrupts = <82 0>;
status = "disabled";
label = "UART_7";
};
uart8: serial@40007c00 {
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
interrupts = <83 0>;
status = "disabled";
label = "UART_8";
};
uart9: serial@40011800 {
compatible = "st,stm32-uart";
reg = <0x40011800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000040>;
interrupts = <88 0>;
status = "disabled";
label = "UART_9";
};
uart10: serial@40011c00 {
compatible = "st,stm32-uart";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
interrupts = <89 0>;
status = "disabled";
label = "UART_10";
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
};
};
dts/arm/st/f4/stm32f413Xg.dtsi
+22
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f413.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(320)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(1024)>;
};
};
};
};
dts/arm/st/f4/stm32f413Xh.dtsi
+22
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@@ -0,0 +1,22 @@
/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f413.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(320)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(1536)>;
};
};
};
};
dts/arm/st/f4/stm32f415.dtsi
+20
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/*
* Copyright (c) 2019, Kwon Tae-young <tykwon@m2i.co.kr>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f405.dtsi>
/ {
soc {
cryp: cryp@50060000 {
compatible = "st,stm32-cryp";
reg = <0x50060000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
interrupts = <79 0>;
status = "disabled";
label = "CRYP";
};
};
};
dts/arm/st/f4/stm32f415Rg.dtsi
+28
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/*
* Copyright (c) 2019, Kwon Tae-young <tykwon@m2i.co.kr>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f415.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(1024)>;
};
};
};
};
dts/arm/st/f4/stm32f417.dtsi
+20
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@@ -0,0 +1,20 @@
/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f407.dtsi>
/ {
soc {
cryp: cryp@50060000 {
compatible = "st,stm32-cryp";
reg = <0x50060000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
interrupts = <79 0>;
status = "disabled";
label = "CRYP";
};
};
};
dts/arm/st/f4/stm32f417Xe.dtsi
+28
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@@ -0,0 +1,28 @@
/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f417.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};
dts/arm/st/f4/stm32f417Xg.dtsi
+28
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@@ -0,0 +1,28 @@
/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f417.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(1024)>;
};
};
};
};
dts/arm/st/f4/stm32f427.dtsi
+107
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/*
* Copyright (c) 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f407.dtsi>
#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
/ {
soc {
pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x2C00>;
gpioj: gpio@40022400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
label = "GPIOJ";
};
gpiok: gpio@40022800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
label = "GPIOK";
};
};
uart7: serial@40007800 {
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
interrupts = <82 0>;
status = "disabled";
label = "UART_7";
};
uart8: serial@40007c00 {
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
interrupts = <83 0>;
status = "disabled";
label = "UART_8";
};
spi4: spi@40013400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <84 5>;
status = "disabled";
label = "SPI_4";
};
/* spi5 is present on all STM32F429XX SoCs except
* STM32F429vX SoCs. Delete node in stm32f429vX.dtsi.
*/
spi5: spi@40015000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
interrupts = <85 5>;
status = "disabled";
label = "SPI_5";
};
/* spi6 is present on all STM32F429XX SoCs except
* STM32F429vX SoCs. Delete node in stm32f429vX.dtsi.
*/
spi6: spi@40015400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00200000>;
interrupts = <86 5>;
status = "disabled";
label = "SPI_6";
};
fmc: memory-controller@a0000000 {
compatible = "st,stm32-fmc";
reg = <0xa0000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
label = "STM32_FMC";
status = "disabled";
sdram: sdram {
compatible = "st,stm32-fmc-sdram";
#address-cells = <1>;
#size-cells = <0>;
label = "STM32_FMC_SDRAM";
status = "disabled";
};
};
};
};
dts/arm/st/f4/stm32f427Xi.dtsi
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/*
* Copyright (c) 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f427.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(192)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(2048)>;
};
};
};
};
dts/arm/st/f4/stm32f427vX.dtsi
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/*
* Copyright (c) 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f427.dtsi>
/delete-node/ &spi5;
/delete-node/ &spi6;
dts/arm/st/f4/stm32f427vi.dtsi
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/*
* Copyright (c) 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f427vX.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(192)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(2048)>;
};
};
};
};
dts/arm/st/f4/stm32f429.dtsi
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/*
* Copyright (c) 2017, 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f427.dtsi>
/ {
soc {
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
};
};
dts/arm/st/f4/stm32f429Xi.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f429.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(192)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(2048)>;
};
};
};
};
dts/arm/st/f4/stm32f429vX.dtsi
+21
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/*
* Copyright (c) 2018 Daniel Wagenknecht
*
* Document the usage of /delete-node/ for device tree nodes
* that are missing on on only a small subset of SoCs of a given group
* of SoCs.
* Don't remove this file even if none of the SoCs currently
* implemented in zephyr use it.
*
* spi5 and spi6 are present on all STM32F429XX SoCs except
* STM32F429vX SoCs, so they are defined in stm32f429.dtsi and deleted
* here.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f429.dtsi>
/delete-node/ &spi5;
/delete-node/ &spi6;
dts/arm/st/f4/stm32f429vi.dtsi
+29
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/*
* Copyright (c) 2020 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f429vX.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(192)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(2048)>;
};
};
};
};
dts/arm/st/f4/stm32f437.dtsi
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/*
* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f407.dtsi>
#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
/ {
soc {
pinctrl: pin-controller@40020000 {
reg = <0x40020000 0x2C00>;
gpioj: gpio@40022400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000200>;
label = "GPIOJ";
};
gpiok: gpio@40022800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000400>;
label = "GPIOK";
};
};
uart7: serial@40007800 {
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
interrupts = <82 0>;
status = "disabled";
label = "UART_7";
};
uart8: serial@40007c00 {
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
interrupts = <83 0>;
status = "disabled";
label = "UART_8";
};
spi4: spi@40013400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
interrupts = <84 5>;
status = "disabled";
label = "SPI_4";
};
/* spi5 is present on all STM32F437XX SoCs except
* STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
*/
spi5: spi@40015000 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
interrupts = <85 5>;
status = "disabled";
label = "SPI_5";
};
/* spi6 is present on all STM32F437XX SoCs except
* STM32F437vX SoCs. Delete node in stm32f437vX.dtsi.
*/
spi6: spi@40015400 {
compatible = "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015400 0x400>;
interrupts = <86 5>;
status = "disabled";
label = "SPI_6";
};
fmc: memory-controller@a0000000 {
compatible = "st,stm32-fmc";
reg = <0xa0000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
label = "STM32_FMC";
status = "disabled";
sdram: sdram {
compatible = "st,stm32-fmc-sdram";
#address-cells = <1>;
#size-cells = <0>;
label = "STM32_FMC_SDRAM";
status = "disabled";
};
};
cryp: cryp@50060000 {
compatible = "st,stm32-cryp";
reg = <0x50060000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000010>;
interrupts = <79 0>;
status = "disabled";
label = "CRYP";
};
};
};
dts/arm/st/f4/stm32f437Xi.dtsi
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/*
* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f437.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(192)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(2048)>;
};
};
};
};
dts/arm/st/f4/stm32f437vX.dtsi
+11
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/*
* Copyright (c) 2019, Markus Fuchs <markus.fuchs@de.sauter-bc.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f437.dtsi>
/delete-node/ &spi5;
/delete-node/ &spi6;
dts/arm/st/f4/stm32f446.dtsi
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/*
* Copyright (c) 2018 Philémon Jaermann
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f401.dtsi>
#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
/ {
soc {
i2s1: i2s@40013000 {
compatible = "st,stm32-i2s";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
dmas = <&dma2 3 3 0x400 0x3
&dma2 2 3 0x400 0x3>;
dma-names = "tx", "rx";
status = "disabled";
label = "I2S_1";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
uart4: serial@40004c00 {
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
can1: can@40006400 {
compatible = "st,stm32-can";
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
bus-speed = <125000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
can2: can@40006800 {
compatible = "st,stm32-can";
reg = <0x40006800 0x400>;
interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x04000000>;
master-can-reg = <0x40006400>;
status = "disabled";
label = "CAN_2";
bus-speed = <125000>;
sjw = <1>;
prop-seg = <0>;
phase-seg1 = <5>;
phase-seg2 = <6>;
};
usbotg_fs: usb@50000000 {
num-bidir-endpoints = <6>;
};
usbotg_hs: usb@40040000 {
compatible = "st,stm32-otghs";
reg = <0x40040000 0x40000>;
interrupts = <77 0>, <74 0>, <75 0>;
interrupt-names = "otghs", "ep1_out", "ep1_in";
num-bidir-endpoints = <9>;
ram-size = <4096>;
maximum-speed = "full-speed";
phys = <&otghs_fs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
status = "disabled";
label= "OTGHS";
};
backup_sram: memory@40024000 {
compatible = "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "BACKUP_SRAM";
zephyr,memory-region = "BACKUP_SRAM";
status = "disabled";
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
fmc: memory-controller@a0000000 {
compatible = "st,stm32-fmc";
reg = <0xa0000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
label = "STM32_FMC";
status = "disabled";
sdram: sdram {
compatible = "st,stm32-fmc-sdram";
#address-cells = <1>;
#size-cells = <0>;
label = "STM32_FMC_SDRAM";
status = "disabled";
};
};
};
otghs_fs_phy: otghs_fs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "OTGHS_FS_PHY";
};
};
dts/arm/st/f4/stm32f446Xe.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f446.dtsi>
/ {
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(128)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};
dts/arm/st/f4/stm32f469.dtsi
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/*
* Copyright (c) 2017 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f4/stm32f429.dtsi>
/ {
soc {
usbotg_fs: usb@50000000 {
num-bidir-endpoints = <6>;
};
usbotg_hs: usb@40040000 {
num-bidir-endpoints = <9>;
};
};
};
dts/arm/st/f4/stm32f469Xi.dtsi
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/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f4/stm32f469.dtsi>
/ {
ccm0: memory@10000000 {
compatible = "st,stm32-ccm";
reg = <0x10000000 DT_SIZE_K(64)>;
zephyr,memory-region = "CCM";
};
sram0: memory@20000000 {
reg = <0x20000000 DT_SIZE_K(320)>;
};
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(2048)>;
};
};
};
};
dts/arm/st/f7/stm32f7.dtsi
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/*
* Copyright (c) 2018 Yurii Hamann
* Copyright (c) 2019 Centaur Analytics, Inc
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <dt-bindings/clock/stm32_clock.h>
#include <dt-bindings/i2c/i2c.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pwm/pwm.h>
#include <dt-bindings/memory-controller/stm32-fmc-sdram.h>
#include <freq.h>
/ {
chosen {
zephyr,entropy = &rng;
zephyr,flash-controller = &flash;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m7";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv7m-mpu";
reg = <0xe000ed90 0x40>;
arm,num-mpu-regions = <8>;
};
};
};
clocks {
clk_hse: clk-hse {
#clock-cells = <0>;
compatible = "st,stm32-hse-clock";
status = "disabled";
};
clk_hsi: clk-hsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_M(16)>;
status = "disabled";
};
clk_lse: clk-lse {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <32768>;
status = "disabled";
};
clk_lsi: clk-lsi {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <DT_FREQ_K(32)>;
status = "disabled";
};
pll: pll {
#clock-cells = <0>;
compatible = "st,stm32f7-pll-clock";
status = "disabled";
};
};
soc {
fmc: memory-controller@a0000000 {
compatible = "st,stm32-fmc";
reg = <0xa0000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00000001>;
label = "STM32_FMC";
status = "disabled";
sdram: sdram {
compatible = "st,stm32-fmc-sdram";
#address-cells = <1>;
#size-cells = <0>;
label = "STM32_FMC_SDRAM";
status = "disabled";
};
};
flash: flash-controller@40023c00 {
compatible = "st,stm32-flash-controller", "st,stm32f7-flash-controller";
label = "FLASH_CTRL";
reg = <0x40023c00 0x400>;
interrupts = <4 0>;
#address-cells = <1>;
#size-cells = <1>;
flash0: flash@8000000 {
compatible = "st,stm32-nv-flash", "soc-nv-flash";
label = "FLASH_STM32";
write-block-size = <1>;
/* maximum erase time (ms) for a 256K sector */
max-erase-time = <4000>;
};
};
rcc: rcc@40023800 {
compatible = "st,stm32-rcc";
#clock-cells = <2>;
reg = <0x40023800 0x400>;
};
exti: interrupt-controller@40013c00 {
compatible = "st,stm32-exti";
interrupt-controller;
#interrupt-cells = <1>;
reg = <0x40013c00 0x400>;
};
pinctrl: pin-controller@40020000 {
compatible = "st,stm32-pinctrl";
#address-cells = <1>;
#size-cells = <1>;
reg = <0x40020000 0x2400>;
gpioa: gpio@40020000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000001>;
label = "GPIOA";
};
gpiob: gpio@40020400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000002>;
label = "GPIOB";
};
gpioc: gpio@40020800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000004>;
label = "GPIOC";
};
gpiod: gpio@40020C00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40020C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000008>;
label = "GPIOD";
};
gpioe: gpio@40021000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000010>;
label = "GPIOE";
};
gpiof: gpio@40021400 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000020>;
label = "GPIOF";
};
gpiog: gpio@40021800 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000040>;
label = "GPIOG";
};
gpioh: gpio@40021C00 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40021C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000080>;
label = "GPIOH";
};
gpioi: gpio@40022000 {
compatible = "st,stm32-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0x40022000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00000100>;
label = "GPIOI";
};
};
iwdg: watchdog@40003000 {
compatible = "st,stm32-watchdog";
reg = <0x40003000 0x400>;
label = "IWDG";
status = "disabled";
};
wwdg: watchdog@40002c00 {
compatible = "st,stm32-window-watchdog";
reg = <0x40002C00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000800>;
label = "WWDG";
interrupts = <0 7>;
status = "disabled";
};
usart1: serial@40011000 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000010>;
interrupts = <37 0>;
status = "disabled";
label = "UART_1";
};
usart2: serial@40004400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>;
interrupts = <38 0>;
status = "disabled";
label = "UART_2";
};
usart3: serial@40004800 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40004800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00040000>;
interrupts = <39 0>;
status = "disabled";
label = "UART_3";
};
uart4: serial@40004c00 {
compatible ="st,stm32-uart";
reg = <0x40004c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00080000>;
interrupts = <52 0>;
status = "disabled";
label = "UART_4";
};
uart5: serial@40005000 {
compatible = "st,stm32-uart";
reg = <0x40005000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00100000>;
interrupts = <53 0>;
status = "disabled";
label = "UART_5";
};
usart6: serial@40011400 {
compatible = "st,stm32-usart", "st,stm32-uart";
reg = <0x40011400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000020>;
interrupts = <71 0>;
status = "disabled";
label = "UART_6";
};
uart7: serial@40007800 {
compatible = "st,stm32-uart";
reg = <0x40007800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x40000000>;
interrupts = <82 0>;
status = "disabled";
label = "UART_7";
};
uart8: serial@40007c00 {
compatible = "st,stm32-uart";
reg = <0x40007c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>;
interrupts = <83 0>;
status = "disabled";
label = "UART_8";
};
i2c1: i2c@40005400 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>;
interrupts = <31 0>, <32 0>;
interrupt-names = "event", "error";
status = "disabled";
label = "I2C_1";
};
i2c2: i2c@40005800 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00400000>;
interrupts = <33 0>, <34 0>;
interrupt-names = "event", "error";
status = "disabled";
label = "I2C_2";
};
i2c3: i2c@40005c00 {
compatible = "st,stm32-i2c-v2";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40005c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>;
interrupts = <72 0>, <73 0>;
interrupt-names = "event", "error";
status = "disabled";
label = "I2C_3";
};
spi1: spi@40013000 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00001000>;
interrupts = <35 5>;
status = "disabled";
label = "SPI_1";
};
spi2: spi@40003800 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00004000>;
interrupts = <36 5>;
status = "disabled";
label = "SPI_2";
};
spi3: spi@40003c00 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40003c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00008000>;
interrupts = <51 5>;
status = "disabled";
label = "SPI_3";
};
spi4: spi@40013400 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40013400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00002000>;
interrupts = <84 5>;
status = "disabled";
label = "SPI_4";
};
spi5: spi@40015000 {
compatible = "st,stm32-spi-fifo", "st,stm32-spi";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x40015000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00100000>;
interrupts = <85 5>;
status = "disabled";
label = "SPI_5";
};
can1: can@40006400 {
compatible = "st,stm32-can";
reg = <0x40006400 0x400>;
interrupts = <19 0>, <20 0>, <21 0>, <22 0>;
interrupt-names = "TX", "RX0", "RX1", "SCE";
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>;
status = "disabled";
label = "CAN_1";
};
timers1: timers@40010000 {
compatible = "st,stm32-timers";
reg = <0x40010000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000001>;
interrupts = <24 0>, <25 0>, <26 0>, <27 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_1";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_1";
#pwm-cells = <3>;
};
};
timers2: timers@40000000 {
compatible = "st,stm32-timers";
reg = <0x40000000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000001>;
interrupts = <28 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_2";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_2";
#pwm-cells = <3>;
};
};
timers3: timers@40000400 {
compatible = "st,stm32-timers";
reg = <0x40000400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000002>;
interrupts = <29 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_3";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_3";
#pwm-cells = <3>;
};
};
timers4: timers@40000800 {
compatible = "st,stm32-timers";
reg = <0x40000800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000004>;
interrupts = <30 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_4";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_4";
#pwm-cells = <3>;
};
};
timers5: timers@40000c00 {
compatible = "st,stm32-timers";
reg = <0x40000c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000008>;
interrupts = <50 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_5";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_5";
#pwm-cells = <3>;
};
};
timers6: timers@40001000 {
compatible = "st,stm32-timers";
reg = <0x40001000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000010>;
interrupts = <54 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_6";
};
timers7: timers@40001400 {
compatible = "st,stm32-timers";
reg = <0x40001400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000020>;
interrupts = <55 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_7";
};
timers8: timers@40010400 {
compatible = "st,stm32-timers";
reg = <0x40010400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000002>;
interrupts = <43 0>, <44 0>, <45 0>, <46 0>;
interrupt-names = "brk", "up", "trgcom", "cc";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_8";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_8";
#pwm-cells = <3>;
};
};
timers9: timers@40014000 {
compatible = "st,stm32-timers";
reg = <0x40014000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00010000>;
interrupts = <24 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_9";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_9";
#pwm-cells = <3>;
};
};
timers10: timers@40014400 {
compatible = "st,stm32-timers";
reg = <0x40014400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00020000>;
interrupts = <25 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_10";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_10";
#pwm-cells = <3>;
};
};
timers11: timers@40014800 {
compatible = "st,stm32-timers";
reg = <0x40014800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00040000>;
interrupts = <26 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_11";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_11";
#pwm-cells = <3>;
};
};
timers12: timers@40001800 {
compatible = "st,stm32-timers";
reg = <0x40001800 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000040>;
interrupts = <43 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_12";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_12";
#pwm-cells = <3>;
};
};
timers13: timers@40001c00 {
compatible = "st,stm32-timers";
reg = <0x40001c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000080>;
interrupts = <44 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_13";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_13";
#pwm-cells = <3>;
};
};
timers14: timers@40002000 {
compatible = "st,stm32-timers";
reg = <0x40002000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000100>;
interrupts = <45 0>;
interrupt-names = "global";
st,prescaler = <0>;
status = "disabled";
label = "TIMERS_14";
pwm {
compatible = "st,stm32-pwm";
status = "disabled";
label = "PWM_14";
#pwm-cells = <3>;
};
};
usbotg_fs: usb@50000000 {
compatible = "st,stm32-otgfs";
reg = <0x50000000 0x40000>;
interrupts = <67 0>;
interrupt-names = "otgfs";
num-bidir-endpoints = <6>;
ram-size = <1280>;
maximum-speed = "full-speed";
phys = <&otgfs_phy>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>;
status = "disabled";
label = "OTGFS";
};
usbotg_hs: usb@40040000 {
compatible = "st,stm32-otghs";
reg = <0x40040000 0x40000>;
interrupts = <77 0>, <74 0>, <75 0>;
interrupt-names = "otghs", "ep1_out", "ep1_in";
num-bidir-endpoints = <9>;
ram-size = <4096>;
maximum-speed = "full-speed";
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x20000000>;
phys = <&otghs_fs_phy>;
status = "disabled";
label= "OTGHS";
};
rtc: rtc@40002800 {
compatible = "st,stm32-rtc";
reg = <0x40002800 0x300>;
interrupts = <41 0>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>;
prescaler = <32768>;
status = "disabled";
label = "RTC_0";
};
adc1: adc@40012000 {
compatible = "st,stm32-adc";
reg = <0x40012000 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000100>;
interrupts = <18 0>;
status = "disabled";
label = "ADC_1";
#io-channel-cells = <1>;
};
dac1: dac@40007400 {
compatible = "st,stm32-dac";
reg = <0x40007400 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB1 0x20000000>;
status = "disabled";
label = "DAC_1";
#io-channel-cells = <1>;
};
dma1: dma@40026000 {
compatible = "st,stm32-dma-v1";
#dma-cells = <4>;
reg = <0x40026000 0x400>;
interrupts = <11 0 12 0 13 0 14 0 15 0 16 0 17 0 47 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x200000>;
status = "disabled";
label = "DMA_1";
};
dma2: dma@40026400 {
compatible = "st,stm32-dma-v1";
#dma-cells = <4>;
reg = <0x40026400 0x400>;
interrupts = <56 0 57 0 58 0 59 0 60 0 68 0 69 0 70 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x400000>;
st,mem2mem;
status = "disabled";
label = "DMA_2";
};
rng: rng@50060800 {
compatible = "st,stm32-rng";
reg = <0x50060800 0x400>;
interrupts = <80 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000040>;
status = "disabled";
label = "RNG";
};
sdmmc1: sdmmc@40012c00 {
compatible = "st,stm32-sdmmc";
reg = <0x40012c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
interrupts = <49 0>;
status = "disabled";
label = "SDMMC_1";
};
backup_sram: memory@40024000 {
compatible = "st,stm32-backup-sram";
reg = <0x40024000 DT_SIZE_K(4)>;
clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x00040000>;
label = "BACKUP_SRAM";
zephyr,memory-region = "BACKUP_SRAM";
status = "disabled";
};
quadspi: quadspi@a0001000 {
compatible = "st,stm32-qspi";
#address-cells = <0x1>;
#size-cells = <0x0>;
reg = <0xa0001000 0x34>;
interrupts = <92 0>;
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x2>;
status = "disabled";
label = "QUADSPI";
};
};
otghs_fs_phy: otghs_fs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "OTGHS_FS_PHY";
};
otgfs_phy: otgfs_phy {
compatible = "usb-nop-xceiv";
#phy-cells = <0>;
label = "OTGFS_PHY";
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
dts/arm/st/f7/stm32f723.dtsi
+48
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@@ -0,0 +1,48 @@
/*
* Copyright (c) 2018 Aurelien Jarno
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <st/f7/stm32f7.dtsi>
/ {
/* 64KB DTCM @ 0x20000000, 176KB SRAM1 @ 0x20010000, 16KB SRAM2 @ 0x2003C00 */
sram0: memory@20010000 {
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(192)>;
};
dtcm: memory@20000000 {
compatible = "arm,dtcm";
reg = <0x20000000 DT_SIZE_K(64)>;
zephyr,memory-region = "DTCM";
};
soc {
usbphyc: usbphyc@40017c00 {
compatible = "st,stm32-usbphyc";
reg = <0x40017c00 0x400>;
#phy-cells = <0>;
label = "USBPHYC";
};
usbotg_hs: usb@40040000 {
phys = <&usbphyc>;
maximum-speed = "high-speed";
};
sdmmc2: sdmmc@40011c00 {
compatible = "st,stm32-sdmmc";
reg = <0x40011c00 0x400>;
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
interrupts = <103 0>;
status = "disabled";
label = "SDMMC_2";
};
};
};
/delete-node/ &otghs_fs_phy;
dts/arm/st/f7/stm32f723Xe.dtsi
+18
View File
@@ -0,0 +1,18 @@
/*
* Copyright (c) 2018 Linaro Limited
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <st/f7/stm32f723.dtsi>
/ {
soc {
flash-controller@40023c00 {
flash0: flash@8000000 {
reg = <0x08000000 DT_SIZE_K(512)>;
};
};
};
};

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