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153 lines
7.6 KiB
HTML
<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
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<meta http-equiv="Content-Type" content="text/xhtml;charset=UTF-8"/>
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<title>CPU Section (New)</title>
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<td style="padding-left: 0.5em;">
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<div id="projectname">CMSIS-SVD
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 <span id="projectnumber">Version 1.10</span>
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</div>
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<div id="projectbrief">CMSIS System View Description</div>
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<li><a href="../../General/html/index.html"><span>CMSIS</span></a></li>
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<li><a href="../../Core/html/index.html"><span>CORE</span></a></li>
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<li><a href="../../DSP/html/index.html"><span>DSP</span></a></li>
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<li><a href="../../RTOS/html/index.html"><span>RTOS API</span></a></li>
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<div class="title">CPU Section (New)</div> </div>
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<div class="ingroups"><a class="el" href="group__svd___format__1__1__gr.html">SVD Extension in Version 1.1</a></div></div>
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<div class="contents">
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<p>The CPU section describes the processor included in the microcontroller device. This section is mandatory if the SVD file shall be used for the device header file generation.</p>
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<pre>
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<span class="opt"><cpu></span>
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<span class="mand"><name><em>cpuNameType</em><name>
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<revision><em>revisionType</em><revision>
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<endian><em>endianType</em><endian>
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<mpuPresent><em>xs:boolean</em><mpuPresent>
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<fpuPresent><em>xs:boolean</em><fpuPresent>
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<nvicPrioBits><em>scaledNonNegativeInteger</em><nvicPrioBits>
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<vendorSystickConfig><em>xs:boolean</em><vendorSystickConfig></span>
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<span class="opt"></cpu></span>
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</pre><table class="cmtable" summary="CPU Section Elements">
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<tr>
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<th nowrap="nowrap">Element Name </th><th>Description </th><th>Type </th><th>Occurrence </th></tr>
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<tr>
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<td>name </td><td>The predefined tokens are:<ul>
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<li><span class="XML-Token">CM0</span>: ARM Cortex-M0</li>
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<li><span class="XML-Token">CM0PLUS</span>: ARM Cortex-M0+</li>
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<li><span class="XML-Token">CM3</span>: ARM Cortex-M3</li>
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<li><span class="XML-Token">CM4</span>: ARM Cortex-M4</li>
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<li><span class="XML-Token">SC000</span>: ARM Secure Core SC000</li>
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<li><span class="XML-Token">SC300</span>: ARM Secure Core SC300</li>
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<li><span class="XML-Token">other</span>: other processor architectures </li>
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</ul>
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</td><td>cpuNameType </td><td>1..1 </td></tr>
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<tr>
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<td>revisionType </td><td>Defines the HW revision of the processor. The defined version format is <span class="XML-Token">r<em>N</em>p<em>M</em></span> (N,M = [0 - 9]). </td><td>revisionType </td><td>1..1 </td></tr>
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<tr>
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<td>endian </td><td>Defines the endianess of the processor being one of:<ul>
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<li><span class="XML-Token">little</span>: little endian memory (least significant byte gets allocated at the lowest address).</li>
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<li><span class="XML-Token">big</span>: byte invariant big endian data organization (most significant byte gets allocated at the lowest address).</li>
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<li><span class="XML-Token">selectable</span>: little and big endian are configurable for the device and become active after the next reset.</li>
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<li><span class="XML-Token">other</span>: the endianess is neither little nor big endian. </li>
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</ul>
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</td><td>endianType </td><td>1..1 </td></tr>
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<tr>
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<td>mpuPresent </td><td>Indicates that the processor is equipped with a memory protection unit (MPU). This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr>
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<tr>
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<td>fpuPresent </td><td>Indicates that the processor is equipped with a hardware floating point unit (FPU). Cortex-M4 is the only available Cortex-M processor with an optional FPU. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr>
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<tr>
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<td>nvicPrioBits </td><td>Defines the number of bits that are available in the Nested Vectored Interrupt Controller (NVIC) for configuring the priority. </td><td>scaledNonNegativeInteger </td><td>1..1 </td></tr>
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<tr>
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<td>vendorSystickConfig </td><td>Indicates whether the processor implements a vendor-specific System Tick Timer. If <span class="XML-Token">false</span>, then the ARM defined System Tick Timer is available. If <span class="XML-Token">true</span>, then a vendor-specific System Tick Timer must be implemented. This tag is either set to <span class="XML-Token">true</span> or <span class="XML-Token">false</span>, <span class="XML-Token">1</span> or <span class="XML-Token">0</span>. </td><td>boolean </td><td>1..1 </td></tr>
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</table>
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<h2><a class="anchor" id="cpuSection_ex"></a>
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Example:</h2>
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<div class="fragment"><pre class="fragment">...
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<cpu>
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<name>CM4</name>
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<revision>r0p0</revision>
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<endian>little</endian>
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<mpuPresent><span class="keyword">true</span></mpuPresent>
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<fpuPresent><span class="keyword">true</span></fpuPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig><span class="keyword">false</span></vendorSystickConfig>
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</cpu>
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...
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</pre></div><p>This example describes a Cortex-M4 core of HW revision r0p0, with fixed little endian memory scheme, including Memory Protection Unit and hardware Floating Point Unit. The Nested Vectored Interrupt Controller uses 4 bits for configuring the priority of an interrupt. It is equipped with the standard System Tick Timer as defined by ARM. </p>
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</div>
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</div>
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<li class="footer">Generated on Wed Mar 28 2012 15:38:11 for CMSIS-SVD by ARM Ltd. All rights reserved.
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