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https://gitee.com/mirrors_PX4/PX4-Autopilot.git
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jgoppert
261 lines
9.4 KiB
ArmAsm
261 lines
9.4 KiB
ArmAsm
;/**************************************************************************//**
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; * @file startup_ARMCM3.s
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; * @brief CMSIS Core Device Startup File for
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; * ARMCM3 Device Series
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; * @version V1.08
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; * @date 03. February 2012
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; *
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; * @note
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; * Copyright (C) 2012 ARM Limited. All rights reserved.
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; *
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; * @par
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; * ARM Limited (ARM) is supplying this software for use with Cortex-M
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; * processor based microcontrollers. This file can be freely distributed
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; * within development tools that are supporting such ARM based processors.
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; *
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; * @par
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; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
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; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
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; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
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; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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; *
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; ******************************************************************************/
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;/*
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;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
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;*/
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE Stack_Size
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__initial_sp
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000C00
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WDT_IRQHandler ; 0: Watchdog Timer
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DCD RTC_IRQHandler ; 1: Real Time Clock
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DCD TIM0_IRQHandler ; 2: Timer0 / Timer1
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DCD TIM2_IRQHandler ; 3: Timer2 / Timer3
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DCD MCIA_IRQHandler ; 4: MCIa
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DCD MCIB_IRQHandler ; 5: MCIb
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DCD UART0_IRQHandler ; 6: UART0 - DUT FPGA
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DCD UART1_IRQHandler ; 7: UART1 - DUT FPGA
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DCD UART2_IRQHandler ; 8: UART2 - DUT FPGA
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DCD UART4_IRQHandler ; 9: UART4 - not connected
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DCD AACI_IRQHandler ; 10: AACI / AC97
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DCD CLCD_IRQHandler ; 11: CLCD Combined Interrupt
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DCD ENET_IRQHandler ; 12: Ethernet
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DCD USBDC_IRQHandler ; 13: USB Device
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DCD USBHC_IRQHandler ; 14: USB Host Controller
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DCD CHLCD_IRQHandler ; 15: Character LCD
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DCD FLEXRAY_IRQHandler ; 16: Flexray
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DCD CAN_IRQHandler ; 17: CAN
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DCD LIN_IRQHandler ; 18: LIN
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DCD I2C_IRQHandler ; 19: I2C ADC/DAC
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DCD 0 ; 20: Reserved
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DCD 0 ; 21: Reserved
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DCD 0 ; 22: Reserved
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DCD 0 ; 23: Reserved
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DCD 0 ; 24: Reserved
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DCD 0 ; 25: Reserved
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DCD 0 ; 26: Reserved
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DCD 0 ; 27: Reserved
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DCD CPU_CLCD_IRQHandler ; 28: Reserved - CPU FPGA CLCD
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DCD 0 ; 29: Reserved - CPU FPGA
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DCD UART3_IRQHandler ; 30: UART3 - CPU FPGA
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DCD SPI_IRQHandler ; 31: SPI Touchscreen - CPU FPGA
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT RTC_IRQHandler [WEAK]
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EXPORT TIM0_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT MCIA_IRQHandler [WEAK]
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EXPORT MCIB_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT UART1_IRQHandler [WEAK]
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EXPORT UART2_IRQHandler [WEAK]
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EXPORT UART3_IRQHandler [WEAK]
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EXPORT UART4_IRQHandler [WEAK]
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EXPORT AACI_IRQHandler [WEAK]
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EXPORT CLCD_IRQHandler [WEAK]
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EXPORT ENET_IRQHandler [WEAK]
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EXPORT USBDC_IRQHandler [WEAK]
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EXPORT USBHC_IRQHandler [WEAK]
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EXPORT CHLCD_IRQHandler [WEAK]
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EXPORT FLEXRAY_IRQHandler [WEAK]
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EXPORT CAN_IRQHandler [WEAK]
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EXPORT LIN_IRQHandler [WEAK]
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EXPORT I2C_IRQHandler [WEAK]
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EXPORT CPU_CLCD_IRQHandler [WEAK]
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EXPORT SPI_IRQHandler [WEAK]
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WDT_IRQHandler
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RTC_IRQHandler
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TIM0_IRQHandler
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TIM2_IRQHandler
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MCIA_IRQHandler
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MCIB_IRQHandler
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UART0_IRQHandler
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UART1_IRQHandler
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UART2_IRQHandler
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UART3_IRQHandler
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UART4_IRQHandler
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AACI_IRQHandler
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CLCD_IRQHandler
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ENET_IRQHandler
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USBDC_IRQHandler
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USBHC_IRQHandler
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CHLCD_IRQHandler
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FLEXRAY_IRQHandler
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CAN_IRQHandler
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LIN_IRQHandler
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I2C_IRQHandler
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CPU_CLCD_IRQHandler
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SPI_IRQHandler
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B .
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ENDP
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ALIGN
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; User Initial Stack & Heap
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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EXPORT __heap_base
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EXPORT __heap_limit
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ELSE
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IMPORT __use_two_region_memory
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EXPORT __user_initial_stackheap
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__user_initial_stackheap PROC
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LDR R0, = Heap_Mem
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LDR R1, =(Stack_Mem + Stack_Size)
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LDR R2, = (Heap_Mem + Heap_Size)
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LDR R3, = Stack_Mem
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BX LR
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ENDP
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ALIGN
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ENDIF
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END
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