mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-05-23 18:47:34 +08:00
Compare commits
4 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 Matthias Grob
|
25ed6b67fb | ||
|
Matthias Grob
|
437148f8f3 | ||
|
Matthias Grob
|
94f8a79c2c | ||
|
Matthias Grob
|
d146405753 |
@@ -0,0 +1,13 @@
|
||||
# Google C++ style as base
|
||||
Language: Cpp
|
||||
BasedOnStyle: Google
|
||||
|
||||
# Indentation using tabs
|
||||
UseTab: ForContinuationAndIndentation
|
||||
TabWidth: 8
|
||||
IndentWidth: 8
|
||||
ContinuationIndentWidth: 8
|
||||
ConstructorInitializerIndentWidth: 8
|
||||
AccessModifierOffset: -8
|
||||
|
||||
ColumnLimit: 120 # Allow more collumns
|
||||
@@ -375,6 +375,10 @@ format:
|
||||
$(call colorecho,'Formatting with astyle')
|
||||
@"$(SRC_DIR)"/Tools/astyle/check_code_style_all.sh --fix
|
||||
|
||||
format_clang:
|
||||
$(call colorecho,'Formatting with clang-format')
|
||||
@"$(SRC_DIR)"/Tools/astyle/files_to_check_code_style.sh | xargs clang-format -i -style=file
|
||||
|
||||
# Testing
|
||||
# --------------------------------------------------------------------
|
||||
.PHONY: tests tests_coverage tests_mission tests_mission_coverage tests_offboard tests_avoidance
|
||||
|
||||
@@ -8,23 +8,24 @@ if [ $# -gt 0 ]; then
|
||||
fi
|
||||
|
||||
exec find boards msg src platforms test \
|
||||
-path msg/templates/urtps -prune -o \
|
||||
-path platforms/nuttx/NuttX -prune -o \
|
||||
-path platforms/qurt/dspal -prune -o \
|
||||
-path src/drivers/uavcan/libuavcan -prune -o \
|
||||
-path src/drivers/uavcan/uavcan_drivers/kinetis/driver/include/uavcan_kinetis -prune -o \
|
||||
-path src/drivers/cyphal/libcanard -prune -o \
|
||||
-path src/lib/crypto/monocypher -prune -o \
|
||||
-path src/lib/events/libevents -prune -o \
|
||||
-path src/lib/parameters/uthash -prune -o \
|
||||
-path src/modules/ekf2/EKF -prune -o \
|
||||
-path src/modules/gyro_fft/CMSIS_5 -prune -o \
|
||||
-path src/modules/mavlink/mavlink -prune -o \
|
||||
-path src/modules/micrortps_bridge/micro-CDR -prune -o \
|
||||
-path src/modules/micrortps_bridge/microRTPS_client -prune -o \
|
||||
-path test/mavsdk_tests/catch2 -prune -o \
|
||||
-path src/lib/crypto/monocypher -prune -o \
|
||||
-path src/lib/crypto/libtomcrypt -prune -o \
|
||||
-path src/lib/crypto/libtommath -prune -o \
|
||||
-path src/modules/microdds_client/Micro-XRCE-DDS-Client -prune -o \
|
||||
-not -path "msg/templates/urtps/*" \
|
||||
-not -path "platforms/nuttx/NuttX/*" \
|
||||
-not -path "platforms/qurt/dspal/*" \
|
||||
-not -path "src/drivers/gps/devices/*" \
|
||||
-not -path "src/drivers/uavcan/libuavcan/*" \
|
||||
-not -path "src/drivers/uavcan/uavcan_drivers/kinetis/driver/include/uavcan_kinetis/*" \
|
||||
-not -path "src/drivers/cyphal/libcanard/*" \
|
||||
-not -path "src/lib/crypto/monocypher/*" \
|
||||
-not -path "src/lib/events/libevents/*" \
|
||||
-not -path "src/lib/parameters/uthash/*" \
|
||||
-not -path "src/modules/ekf2/EKF/*" \
|
||||
-not -path "src/modules/gyro_fft/CMSIS_5/*" \
|
||||
-not -path "src/modules/mavlink/mavlink/*" \
|
||||
-not -path "src/modules/micrortps_bridge/micro-CDR/*" \
|
||||
-not -path "src/modules/micrortps_bridge/microRTPS_client/*" \
|
||||
-not -path "test/mavsdk_tests/catch2/*" \
|
||||
-not -path "src/lib/crypto/monocypher/*" \
|
||||
-not -path "src/lib/crypto/libtomcrypt/*" \
|
||||
-not -path "src/lib/crypto/libtommath/*" \
|
||||
-not -path "src/modules/microdds_client/Micro-XRCE-DDS-Client/*" \
|
||||
-type f \( -name "*.c" -o -name "*.h" -o -name "*.cpp" -o -name "*.hpp" \) | grep $PATTERN
|
||||
|
||||
@@ -40,11 +40,11 @@
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
#include "board_dma_map.h"
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "board_dma_map.h"
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include <stm32.h>
|
||||
@@ -83,11 +83,11 @@
|
||||
* LSE - not installed
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
//#define STM32_LSE_FREQUENCY 32768
|
||||
|
||||
/* Main PLL Configuration.
|
||||
@@ -103,68 +103,68 @@
|
||||
* = 48,000,000
|
||||
*/
|
||||
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
|
||||
|
||||
#define STM32_SYSCLK_FREQUENCY 168000000ul
|
||||
#define STM32_SYSCLK_FREQUENCY 168000000ul
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (168MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 4)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 */
|
||||
|
||||
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
||||
/* Timers driven from APB2 will be twice PCLK2 */
|
||||
|
||||
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
||||
* otherwise frequency is 2xAPBx.
|
||||
* Note: TIM1,8-11 are on APB2, others on APB1
|
||||
*/
|
||||
|
||||
#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN
|
||||
#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN
|
||||
#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN
|
||||
#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN
|
||||
#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN
|
||||
#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN
|
||||
#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN
|
||||
#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN
|
||||
#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN
|
||||
#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN
|
||||
#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN
|
||||
#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN
|
||||
#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN
|
||||
#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN
|
||||
#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN
|
||||
#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN
|
||||
|
||||
/* SDIO dividers. Note that slower clocking is required when DMA is disabled
|
||||
* in order to avoid RX overrun/TX underrun errors due to delayed responses
|
||||
@@ -174,16 +174,16 @@
|
||||
* SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
|
||||
*/
|
||||
|
||||
#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
|
||||
/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
|
||||
* DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32_SDIO_DMA
|
||||
# define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#else
|
||||
# define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
/* DMA ON: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
|
||||
@@ -191,9 +191,9 @@
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32_SDIO_DMA
|
||||
# define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#else
|
||||
# define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
/* Alternate function pin selections ************************************************/
|
||||
@@ -201,27 +201,27 @@
|
||||
/*
|
||||
* UARTs.
|
||||
*/
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 /* RC_INPUT */
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 /* RC_INPUT */
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_2
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_2
|
||||
#define GPIO_USART2_RTS GPIO_USART2_RTS_2
|
||||
#define GPIO_USART2_CTS GPIO_USART2_CTS_2
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_2
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_2
|
||||
#define GPIO_USART2_RTS GPIO_USART2_RTS_2
|
||||
#define GPIO_USART2_CTS GPIO_USART2_CTS_2
|
||||
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_3
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_3
|
||||
#define GPIO_USART3_CTS 0 // unused
|
||||
#define GPIO_USART3_RTS 0 // unused
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_3
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_3
|
||||
#define GPIO_USART3_CTS 0 // unused
|
||||
#define GPIO_USART3_RTS 0 // unused
|
||||
|
||||
#define GPIO_UART4_RX GPIO_UART4_RX_1
|
||||
#define GPIO_UART4_TX GPIO_UART4_TX_1
|
||||
#define GPIO_UART4_RX GPIO_UART4_RX_1
|
||||
#define GPIO_UART4_TX GPIO_UART4_TX_1
|
||||
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_2
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_2
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_2
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_2
|
||||
|
||||
#define GPIO_UART7_RX GPIO_UART7_RX_1
|
||||
#define GPIO_UART7_TX GPIO_UART7_TX_1
|
||||
#define GPIO_UART7_RX GPIO_UART7_RX_1
|
||||
#define GPIO_UART7_TX GPIO_UART7_TX_1
|
||||
|
||||
/* UART8 has no alternate pin config */
|
||||
|
||||
@@ -230,8 +230,8 @@
|
||||
*
|
||||
* CAN1 is routed to the onboard transceiver.
|
||||
*/
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_3
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_3
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_3
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_3
|
||||
|
||||
/*
|
||||
* I2C
|
||||
@@ -240,32 +240,31 @@
|
||||
* reset the bus to clear stuck slaves. They match the pin configuration,
|
||||
* but are normally-high GPIOs.
|
||||
*/
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN8)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
|
||||
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
|
||||
#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11)
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
|
||||
#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN11)
|
||||
|
||||
/*
|
||||
* SPI
|
||||
*
|
||||
* There are sensors on SPI1, and SPI2 is connected to the FRAM.
|
||||
*/
|
||||
#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1 | GPIO_SPEED_50MHz)
|
||||
|
||||
#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2 | GPIO_SPEED_50MHz)
|
||||
|
||||
#define GPIO_SPI4_MISO (GPIO_SPI4_MISO_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI4_MOSI (GPIO_SPI4_MOSI_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI4_SCK (GPIO_SPI4_SCK_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI4_MISO (GPIO_SPI4_MISO_1 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI4_MOSI (GPIO_SPI4_MOSI_1 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI4_SCK (GPIO_SPI4_SCK_1 | GPIO_SPEED_50MHz)
|
||||
|
||||
|
||||
#endif /* __ARCH_BOARD_BOARD_H */
|
||||
#endif /* __ARCH_BOARD_BOARD_H */
|
||||
|
||||
@@ -33,55 +33,61 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
|
||||
/*
|
||||
| DMA1 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
|
||||
| DMA1 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5
|
||||
| Stream 6 | Stream 7 |
|
||||
|------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
|
||||
| Channel 0 | SPI3_RX_1 | - | SPI3_RX_2 | SPI2_RX | SPI2_TX | SPI3_TX_1 | - | SPI3_TX_2 |
|
||||
| Channel 1 | I2C1_RX | - | TIM7_UP_1 | - | TIM7_UP_2 | I2C1_RX_1 | I2C1_TX | I2C1_TX_1 |
|
||||
| Channel 2 | TIM4_CH1 | - | I2C4_RX | TIM4_CH2 | - | I2C4_RX | TIM4_UP | TIM4_CH3 |
|
||||
| Channel 3 | - | TIM2_UP_1 | I2C3_RX_1 | I2C2_EXT_RX | I2C3_TX | TIM2_CH1 | TIM2_CH2 | TIM2_UP_2 |
|
||||
| | | TIM2_CH3 | | | | | TIM2_CH4_1 | TIM2_CH4_2 |
|
||||
| Channel 4 | UART5_RX | USART3_RX | UART4_RX | USART3_TX_1 | UART4_TX | USART2_RX | USART2_TX | UART5_TX |
|
||||
| Channel 5 | UART8_TX | UART7_TX | TIM3_CH4 | UART7_RX | TIM3_CH1 | TIM3_CH2 | UART8_RX | TIM3_CH3 |
|
||||
| | | | TIM3_UP | | TIM3_TRIG | | | |
|
||||
| Channel 6 | TIM5_CH3 | TIM5_CH4_1 | TIM5_CH1 | TIM5_CH4_2 | TIM5_CH2 | - | TIM5_UP_2 | - |
|
||||
| | TIM5_UP_1 | TIM5_TRIG_1 | | TIM5_TRIG_2 | | | | |
|
||||
| Channel 7 | - | TIM6_UP | I2C2_RX | I2C2_RX_1 | USART3_TX_2 | DAC1 | DAC2 | I2C2_TX |
|
||||
| | | | | | | | | |
|
||||
| Usage | | | | | | | | |
|
||||
| Channel 0 | SPI3_RX_1 | - | SPI3_RX_2 | SPI2_RX | SPI2_TX | SPI3_TX_1
|
||||
| - | SPI3_TX_2 | | Channel 1 | I2C1_RX | - | TIM7_UP_1 | - |
|
||||
TIM7_UP_2 | I2C1_RX_1 | I2C1_TX | I2C1_TX_1 | | Channel 2 | TIM4_CH1 | - |
|
||||
I2C4_RX | TIM4_CH2 | - | I2C4_RX | TIM4_UP | TIM4_CH3 | |
|
||||
Channel 3 | - | TIM2_UP_1 | I2C3_RX_1 | I2C2_EXT_RX | I2C3_TX | TIM2_CH1 |
|
||||
TIM2_CH2 | TIM2_UP_2 | | | | TIM2_CH3 | | | | |
|
||||
TIM2_CH4_1 | TIM2_CH4_2 | | Channel 4 | UART5_RX | USART3_RX | UART4_RX | USART3_TX_1
|
||||
| UART4_TX | USART2_RX | USART2_TX | UART5_TX | | Channel 5 | UART8_TX | UART7_TX
|
||||
| TIM3_CH4 | UART7_RX | TIM3_CH1 | TIM3_CH2 | UART8_RX | TIM3_CH3 | | |
|
||||
| | TIM3_UP | | TIM3_TRIG | | | | |
|
||||
Channel 6 | TIM5_CH3 | TIM5_CH4_1 | TIM5_CH1 | TIM5_CH4_2 | TIM5_CH2 | - |
|
||||
TIM5_UP_2 | - | | | TIM5_UP_1 | TIM5_TRIG_1 | |
|
||||
TIM5_TRIG_2 | | | | | | Channel 7 | - | TIM6_UP
|
||||
| I2C2_RX | I2C2_RX_1 | USART3_TX_2 | DAC1 | DAC2 | I2C2_TX | | |
|
||||
| | | | | | | | |
|
||||
Usage | | | | | | | | |
|
||||
|
||||
|
||||
| DMA2 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
|
||||
| DMA2 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5
|
||||
| Stream 6 | Stream 7 |
|
||||
|------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
|
||||
| Channel 0 | ADC1_1 | SAI1_A | TIM8_CH1_1 | SAI1_A_1 | ADC1_2 | SAI1_B_1 | TIM1_CH1_1 | - |
|
||||
| | | | TIM8_CH2_1 | | | | TIM1_CH2_1 | |
|
||||
| | | | TIM8_CH3_1 | | | | TIM1_CH3_1 | |
|
||||
| Channel 1 | - | DCMI_1 | ADC2_1 | ADC2_2 | SAI1_B | SPI6_TX | SPI6_RX | DCMI_2 |
|
||||
| Channel 2 | ADC3_1 | ADC3_2 | - | SPI5_RX_1 | SPI5_TX_1 | CRYP_OUT | CRYP_IN | HASH_IN |
|
||||
| Channel 3 | SPI1_RX_1 | - | SPI1_RX_2 | SPI1_TX_1 | - | SPI1_TX_2 | - | QUADSPI |
|
||||
| Channel 4 | SPI4_RX_1 | SPI4_TX_1 | USART1_RX_1 | SDIO | - | USART1_RX_2 | SDIO | USART1_TX |
|
||||
| Channel 5 | - | USART6_RX_1 | USART6_RX_2 | SPI4_RX_2 | SPI4_TX_2 | - | USART6_TX_1 | USART6_TX_2 |
|
||||
| Channel 6 | TIM1_TRIG_1 | TIM1_CH1_2 | TIM1_CH2_2 | TIM1_CH1 | TIM1_CH4 | TIM1_UP | TIM1_CH3_2 | - |
|
||||
| | | | | | TIM1_TRIG_2 | | | |
|
||||
| | | | | | TIM1_COM | | | |
|
||||
| Channel 7 | - | TIM8_UP | TIM8_CH1_2 | TIM8_CH2_2 | TIM8_CH3_2 | SPI5_RX_2 | SPI5_TX_2 | TIM8_CH4 |
|
||||
| | | | | | | | | TIM8_TRIG |
|
||||
| | | | | | | | | TIM8_COM |
|
||||
| | | | | | | | | |
|
||||
| Usage | SPI4_RX_1 | USART6_RX_1 | USART1_RX_1 | | SPI4_TX_2 | | SDIO | |
|
||||
| Channel 0 | ADC1_1 | SAI1_A | TIM8_CH1_1 | SAI1_A_1 | ADC1_2 | SAI1_B_1
|
||||
| TIM1_CH1_1 | - | | | | | TIM8_CH2_1 | | | |
|
||||
TIM1_CH2_1 | | | | | | TIM8_CH3_1 | | | |
|
||||
TIM1_CH3_1 | | | Channel 1 | - | DCMI_1 | ADC2_1 | ADC2_2 |
|
||||
SAI1_B | SPI6_TX | SPI6_RX | DCMI_2 | | Channel 2 | ADC3_1 | ADC3_2 | -
|
||||
| SPI5_RX_1 | SPI5_TX_1 | CRYP_OUT | CRYP_IN | HASH_IN | | Channel 3 |
|
||||
SPI1_RX_1 | - | SPI1_RX_2 | SPI1_TX_1 | - | SPI1_TX_2 | - |
|
||||
QUADSPI | | Channel 4 | SPI4_RX_1 | SPI4_TX_1 | USART1_RX_1 | SDIO | - |
|
||||
USART1_RX_2 | SDIO | USART1_TX | | Channel 5 | - | USART6_RX_1 |
|
||||
USART6_RX_2 | SPI4_RX_2 | SPI4_TX_2 | - | USART6_TX_1 | USART6_TX_2 | |
|
||||
Channel 6 | TIM1_TRIG_1 | TIM1_CH1_2 | TIM1_CH2_2 | TIM1_CH1 | TIM1_CH4 | TIM1_UP |
|
||||
TIM1_CH3_2 | - | | | | | | |
|
||||
TIM1_TRIG_2 | | | | | | | | | |
|
||||
TIM1_COM | | | | | Channel 7 | - | TIM8_UP |
|
||||
TIM8_CH1_2 | TIM8_CH2_2 | TIM8_CH3_2 | SPI5_RX_2 | SPI5_TX_2 | TIM8_CH4 | | | |
|
||||
| | | | | | TIM8_TRIG | | |
|
||||
| | | | | | |
|
||||
TIM8_COM | | | | | | | | | | | |
|
||||
Usage | SPI4_RX_1 | USART6_RX_1 | USART1_RX_1 | | SPI4_TX_2 | | SDIO | |
|
||||
*/
|
||||
|
||||
// DMA1 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
|
||||
|
||||
// DMA2 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
#define DMACHAN_SPI4_RX DMAMAP_SPI4_RX_1 // DMA2, Stream 0, Channel 4 (SPI sensors RX)
|
||||
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 // DMA2, Stream 1, Channel 4
|
||||
#define DMAMAP_USART1_RX DMAMAP_USART1_RX_1 // DMA2, Stream 2, Channel 4
|
||||
#define DMACHAN_SPI4_RX DMAMAP_SPI4_RX_1 // DMA2, Stream 0, Channel 4 (SPI sensors RX)
|
||||
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1 // DMA2, Stream 1, Channel 4
|
||||
#define DMAMAP_USART1_RX DMAMAP_USART1_RX_1 // DMA2, Stream 2, Channel 4
|
||||
// AVAILABLE // DMA2, Stream 3
|
||||
#define DMACHAN_SPI4_TX DMAMAP_SPI4_TX_2 // DMA2, Stream 4, Channel 5 (SPI sensors TX)
|
||||
#define DMACHAN_SPI4_TX DMAMAP_SPI4_TX_2 // DMA2, Stream 4, Channel 5 (SPI sensors TX)
|
||||
// AVAILABLE // DMA2, Stream 5, Channel 6
|
||||
#define DMAMAP_SDIO DMAMAP_SDIO_2 // DMA2, Stream 6, Channel 4
|
||||
#define DMAMAP_SDIO DMAMAP_SDIO_2 // DMA2, Stream 6, Channel 4
|
||||
|
||||
@@ -43,8 +43,8 @@
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************************************
|
||||
@@ -52,75 +52,77 @@
|
||||
****************************************************************************************************/
|
||||
/* Configuration ************************************************************************************/
|
||||
|
||||
|
||||
/* PX4FMU GPIOs ***********************************************************************************/
|
||||
/* LEDs */
|
||||
#define GPIO_LED1 (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN8)
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define GPIO_LED1 (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN8)
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
|
||||
/*
|
||||
* ADC channels
|
||||
*
|
||||
* These are the channel numbers of the ADCs of the microcontroller that can be used by the Px4 Firmware in the adc driver
|
||||
* These are the channel numbers of the ADCs of the microcontroller that can be used by the Px4 Firmware in the adc
|
||||
* driver
|
||||
*/
|
||||
#define ADC_CHANNELS (1 << 4) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 15)
|
||||
|
||||
// ADC defines to be used in sensors.cpp to read from a particular channel
|
||||
#define ADC_5V_RAIL_SENSE 4
|
||||
#define ADC_BATTERY_CURRENT_CHANNEL 10
|
||||
#define ADC_BATTERY_VOLTAGE_CHANNEL 12
|
||||
#define ADC_RC_RSSI_CHANNEL 11
|
||||
#define ADC_AIRSPEED_VOLTAGE_CHANNEL 15
|
||||
#define ADC_5V_RAIL_SENSE 4
|
||||
#define ADC_BATTERY_CURRENT_CHANNEL 10
|
||||
#define ADC_BATTERY_VOLTAGE_CHANNEL 12
|
||||
#define ADC_RC_RSSI_CHANNEL 11
|
||||
#define ADC_AIRSPEED_VOLTAGE_CHANNEL 15
|
||||
|
||||
/* Power supply control and monitoring GPIOs */
|
||||
// #define GPIO_VDD_5V_PERIPH_EN (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN8)
|
||||
// #define GPIO_VDD_BRICK_VALID (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN5)
|
||||
// #define GPIO_VDD_SERVO_VALID (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN7)
|
||||
// #define GPIO_VDD_3V3_SENSORS_EN (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
|
||||
// #define GPIO_VDD_5V_HIPOWER_OC (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN10)
|
||||
// #define GPIO_VDD_5V_PERIPH_OC (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN15)
|
||||
// #define GPIO_VDD_5V_PERIPH_EN
|
||||
// (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN8) #define GPIO_VDD_BRICK_VALID
|
||||
// (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN5) #define GPIO_VDD_SERVO_VALID
|
||||
// (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN7) #define GPIO_VDD_3V3_SENSORS_EN
|
||||
// (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3) #define GPIO_VDD_5V_HIPOWER_OC
|
||||
// (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN10) #define GPIO_VDD_5V_PERIPH_OC
|
||||
// (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN15)
|
||||
|
||||
/* Tone alarm output */
|
||||
#define TONE_ALARM_TIMER 14 /* timer 14 */
|
||||
#define TONE_ALARM_CHANNEL 1 /* channel 1 */
|
||||
#define GPIO_TONE_ALARM_IDLE (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_TONE_ALARM (GPIO_ALT|GPIO_AF9|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
|
||||
#define TONE_ALARM_TIMER 14 /* timer 14 */
|
||||
#define TONE_ALARM_CHANNEL 1 /* channel 1 */
|
||||
#define GPIO_TONE_ALARM_IDLE \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN7)
|
||||
#define GPIO_TONE_ALARM (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_2MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7)
|
||||
|
||||
/* AUX PWMs
|
||||
*/
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 8
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 8
|
||||
|
||||
/* USB OTG FS
|
||||
*
|
||||
* PA9 OTG_FS_VBUS VBUS sensing
|
||||
*/
|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
|
||||
|
||||
|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT | GPIO_FLOAT | GPIO_SPEED_100MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN9)
|
||||
|
||||
/* High-resolution timer */
|
||||
#define HRT_TIMER 8 /* use timer8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 2 /* use capture/compare channel */
|
||||
#define HRT_TIMER 8 /* use timer8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 2 /* use capture/compare channel */
|
||||
|
||||
#define HRT_PPM_CHANNEL 1
|
||||
#define GPIO_PPM_IN GPIO_TIM8_CH1IN_1
|
||||
#define HRT_PPM_CHANNEL 1
|
||||
#define GPIO_PPM_IN GPIO_TIM8_CH1IN_1
|
||||
|
||||
/* PWM input driver. Use FMU AUX5 pins attached to timer4 channel 1 */
|
||||
#define PWMIN_TIMER 4
|
||||
#define PWMIN_TIMER_CHANNEL 1
|
||||
#define GPIO_PWM_IN GPIO_TIM1_CH1IN_2
|
||||
#define PWMIN_TIMER 4
|
||||
#define PWMIN_TIMER_CHANNEL 1
|
||||
#define GPIO_PWM_IN GPIO_TIM1_CH1IN_2
|
||||
|
||||
#define RC_SERIAL_PORT "/dev/ttyS0"
|
||||
#define RC_SERIAL_PORT "/dev/ttyS0"
|
||||
|
||||
// #define GPIO_RSSI_IN (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_SBUS_INV (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN10)
|
||||
#define RC_INVERT_INPUT(_invert_true) px4_arch_gpiowrite(GPIO_SBUS_INV, _invert_true);
|
||||
#define GPIO_SBUS_INV (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN10)
|
||||
#define RC_INVERT_INPUT(_invert_true) px4_arch_gpiowrite(GPIO_SBUS_INV, _invert_true);
|
||||
|
||||
#define GPIO_FRSKY_INV (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN12)
|
||||
#define INVERT_FRSKY(_invert_true) px4_arch_gpiowrite(GPIO_FRSKY_INV, _invert_true);
|
||||
#define GPIO_FRSKY_INV (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12)
|
||||
#define INVERT_FRSKY(_invert_true) px4_arch_gpiowrite(GPIO_FRSKY_INV, _invert_true);
|
||||
|
||||
/* Power switch controls */
|
||||
#define SPEKTRUM_POWER(_on_true) do { } while (0)
|
||||
#define SPEKTRUM_POWER(_on_true) \
|
||||
do { \
|
||||
} while (0)
|
||||
|
||||
/*
|
||||
* MindPXv2 has one RC_IN
|
||||
@@ -131,22 +133,21 @@
|
||||
* The FMU can drive GPIO PPM_IN as an output
|
||||
*/
|
||||
|
||||
#define GPIO_PPM_IN_AS_OUT (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN6)
|
||||
#define SPEKTRUM_RX_AS_GPIO_OUTPUT() px4_arch_configgpio(GPIO_PPM_IN_AS_OUT)
|
||||
#define SPEKTRUM_RX_AS_UART() px4_arch_configgpio(GPIO_USART1_RX)
|
||||
#define SPEKTRUM_OUT(_one_true) px4_arch_gpiowrite(GPIO_PPM_IN_AS_OUT, (_one_true))
|
||||
#define GPIO_PPM_IN_AS_OUT (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN6)
|
||||
#define SPEKTRUM_RX_AS_GPIO_OUTPUT() px4_arch_configgpio(GPIO_PPM_IN_AS_OUT)
|
||||
#define SPEKTRUM_RX_AS_UART() px4_arch_configgpio(GPIO_USART1_RX)
|
||||
#define SPEKTRUM_OUT(_one_true) px4_arch_gpiowrite(GPIO_PPM_IN_AS_OUT, (_one_true))
|
||||
|
||||
/* By Providing BOARD_ADC_USB_CONNECTED (using the px4_arch abstraction)
|
||||
* this board support the ADC system_power interface, and therefore
|
||||
* provides the true logic GPIO BOARD_ADC_xxxx macros.
|
||||
*/
|
||||
#define BOARD_ADC_USB_CONNECTED (px4_arch_gpioread(GPIO_OTGFS_VBUS))
|
||||
#define BOARD_ADC_BRICK_VALID (1)
|
||||
#define BOARD_ADC_SERVO_VALID (1)
|
||||
#define BOARD_ADC_PERIPH_5V_OC (0)
|
||||
#define BOARD_ADC_BRICK_VALID (1)
|
||||
#define BOARD_ADC_SERVO_VALID (1)
|
||||
#define BOARD_ADC_PERIPH_5V_OC (0)
|
||||
#define BOARD_ADC_HIPOWER_5V_OC (0)
|
||||
|
||||
|
||||
/* This board provides a DMA pool and APIs */
|
||||
#define BOARD_DMA_ALLOC_POOL_SIZE 5120
|
||||
|
||||
@@ -182,10 +183,8 @@ extern void stm32_spiinitialize(void);
|
||||
|
||||
extern void stm32_usbinitialize(void);
|
||||
|
||||
|
||||
#define board_peripheral_reset(ms)
|
||||
|
||||
|
||||
#include <px4_platform_common/board_common.h>
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
@@ -41,20 +41,17 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/can/can.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/can/can.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32.h"
|
||||
#include "stm32_can.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#ifdef CONFIG_CAN
|
||||
|
||||
@@ -64,14 +61,14 @@
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
|
||||
# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
# undef CONFIG_STM32_CAN2
|
||||
#warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
#undef CONFIG_STM32_CAN2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CAN1
|
||||
# define CAN_PORT 1
|
||||
#define CAN_PORT 1
|
||||
#else
|
||||
# define CAN_PORT 2
|
||||
#define CAN_PORT 2
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -91,8 +88,7 @@ int can_devinit(void);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int can_devinit(void)
|
||||
{
|
||||
int can_devinit(void) {
|
||||
static bool initialized = false;
|
||||
struct can_dev_s *can;
|
||||
int ret;
|
||||
|
||||
@@ -37,4 +37,3 @@ constexpr px4_i2c_bus_t px4_i2c_buses[I2C_BUS_MAX_BUS_ITEMS] = {
|
||||
initI2CBusInternal(1),
|
||||
initI2CBusExternal(2),
|
||||
};
|
||||
|
||||
|
||||
@@ -45,37 +45,32 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_pwm_output.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
#include <nuttx/mm/gran.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/io_timer.h>
|
||||
#include <px4_platform/board_dma_alloc.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/tasks.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <stm32.h>
|
||||
#include <stm32_uart.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/mm/gran.h>
|
||||
|
||||
#include <stm32.h>
|
||||
#include "board_config.h"
|
||||
#include <stm32_uart.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform/board_dma_alloc.h>
|
||||
#include <drivers/drv_pwm_output.h>
|
||||
#include <px4_arch/io_timer.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
@@ -105,8 +100,7 @@ __END_DECLS
|
||||
* 0 if just resetting
|
||||
*
|
||||
************************************************************************************/
|
||||
__EXPORT void board_on_reset(int status)
|
||||
{
|
||||
__EXPORT void board_on_reset(int status) {
|
||||
/* configure the GPIO pins to outputs and keep them low */
|
||||
for (int i = 0; i < DIRECT_PWM_OUTPUT_CHANNELS; ++i) {
|
||||
px4_arch_configgpio(io_timer_channel_get_gpio_output(i));
|
||||
@@ -135,9 +129,7 @@ __EXPORT void board_on_reset(int status)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void
|
||||
stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
// Reset all PWM to Low outputs.
|
||||
|
||||
board_on_reset(-1);
|
||||
@@ -148,13 +140,13 @@ stm32_boardinitialize(void)
|
||||
|
||||
/* configure ADC pins */
|
||||
|
||||
stm32_configgpio(GPIO_ADC1_IN4); /* VDD_5V_SENS */
|
||||
stm32_configgpio(GPIO_ADC1_IN10); /* BATT_CURRENT_SENS */
|
||||
stm32_configgpio(GPIO_ADC1_IN12); /* BATT_VOLTAGE_SENS */
|
||||
stm32_configgpio(GPIO_ADC1_IN11); /* RSSI analog in */
|
||||
stm32_configgpio(GPIO_ADC1_IN13); /* FMU_AUX_ADC_1 */
|
||||
stm32_configgpio(GPIO_ADC1_IN14); /* FMU_AUX_ADC_2 */
|
||||
stm32_configgpio(GPIO_ADC1_IN15); /* PRESSURE_SENS */
|
||||
stm32_configgpio(GPIO_ADC1_IN4); /* VDD_5V_SENS */
|
||||
stm32_configgpio(GPIO_ADC1_IN10); /* BATT_CURRENT_SENS */
|
||||
stm32_configgpio(GPIO_ADC1_IN12); /* BATT_VOLTAGE_SENS */
|
||||
stm32_configgpio(GPIO_ADC1_IN11); /* RSSI analog in */
|
||||
stm32_configgpio(GPIO_ADC1_IN13); /* FMU_AUX_ADC_1 */
|
||||
stm32_configgpio(GPIO_ADC1_IN14); /* FMU_AUX_ADC_2 */
|
||||
stm32_configgpio(GPIO_ADC1_IN15); /* PRESSURE_SENS */
|
||||
|
||||
/* configure power supply control/sense pins */
|
||||
|
||||
@@ -175,7 +167,6 @@ stm32_boardinitialize(void)
|
||||
|
||||
stm32_configgpio(GPIO_I2C1_SCL);
|
||||
stm32_configgpio(GPIO_I2C1_SDA);
|
||||
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -208,8 +199,7 @@ static struct spi_dev_s *spi2;
|
||||
static struct spi_dev_s *spi4;
|
||||
static struct sdio_dev_s *sdio;
|
||||
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
__EXPORT int board_app_initialize(uintptr_t arg) {
|
||||
px4_platform_init();
|
||||
|
||||
/* configure the DMA allocator */
|
||||
@@ -263,14 +253,12 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
SPI_SETFREQUENCY(spi1, 24 * 1000 * 1000);
|
||||
SPI_SETBITS(spi1, 8);
|
||||
|
||||
|
||||
spi2 = px4_spibus_initialize(2);
|
||||
|
||||
/* Default SPI2 to 10MHz and de-assert the known chip selects. */
|
||||
SPI_SETFREQUENCY(spi2, 10000000);
|
||||
SPI_SETBITS(spi2, 8);
|
||||
|
||||
|
||||
#ifdef CONFIG_MMCSD
|
||||
/* First, get an instance of the SDIO interface */
|
||||
|
||||
|
||||
@@ -37,14 +37,12 @@
|
||||
* PX4FMU LED backend.
|
||||
*/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "stm32.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include "stm32.h"
|
||||
|
||||
/*
|
||||
* Ideally we'd be able to get these from arm_internal.h,
|
||||
@@ -60,31 +58,27 @@ extern void led_off(int led);
|
||||
extern void led_toggle(int led);
|
||||
__END_DECLS
|
||||
|
||||
__EXPORT void led_init()
|
||||
{
|
||||
__EXPORT void led_init() {
|
||||
/* Configure LED1 GPIO for output */
|
||||
|
||||
stm32_configgpio(GPIO_LED1);
|
||||
}
|
||||
|
||||
__EXPORT void led_on(int led)
|
||||
{
|
||||
__EXPORT void led_on(int led) {
|
||||
if (led == 1) {
|
||||
/* Pull down to switch on */
|
||||
stm32_gpiowrite(GPIO_LED1, false);
|
||||
}
|
||||
}
|
||||
|
||||
__EXPORT void led_off(int led)
|
||||
{
|
||||
__EXPORT void led_off(int led) {
|
||||
if (led == 1) {
|
||||
/* Pull up to switch off */
|
||||
stm32_gpiowrite(GPIO_LED1, true);
|
||||
}
|
||||
}
|
||||
|
||||
__EXPORT void led_toggle(int led)
|
||||
{
|
||||
__EXPORT void led_toggle(int led) {
|
||||
if (led == 1) {
|
||||
if (stm32_gpioread(GPIO_LED1)) {
|
||||
stm32_gpiowrite(GPIO_LED1, false);
|
||||
|
||||
@@ -31,24 +31,30 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::SPI1, {
|
||||
initSPIDevice(SPIDEV_FLASH(0), SPI::CS{GPIO::PortE, GPIO::Pin12}),
|
||||
}),
|
||||
initSPIBusExternal(SPI::Bus::SPI2, {
|
||||
initSPIConfigExternal(SPI::CS{GPIO::PortD, GPIO::Pin7}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI4, {
|
||||
initSPIDevice(DRV_GYR_DEVTYPE_L3GD20, SPI::CS{GPIO::PortB, GPIO::Pin2}, SPI::DRDY{GPIO::PortE, GPIO::Pin4}),
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_LSM303D, SPI::CS{GPIO::PortD, GPIO::Pin11}),
|
||||
initSPIDevice(DRV_BARO_DEVTYPE_MS5611, SPI::CS{GPIO::PortC, GPIO::Pin15}),
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_MPU6000, SPI::CS{GPIO::PortE, GPIO::Pin3}, SPI::DRDY{GPIO::PortE, GPIO::Pin10}),
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_MPU6500, SPI::CS{GPIO::PortE, GPIO::Pin3}, SPI::DRDY{GPIO::PortE, GPIO::Pin10}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI1,
|
||||
{
|
||||
initSPIDevice(SPIDEV_FLASH(0), SPI::CS{GPIO::PortE, GPIO::Pin12}),
|
||||
}),
|
||||
initSPIBusExternal(SPI::Bus::SPI2,
|
||||
{
|
||||
initSPIConfigExternal(SPI::CS{GPIO::PortD, GPIO::Pin7}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI4,
|
||||
{
|
||||
initSPIDevice(DRV_GYR_DEVTYPE_L3GD20, SPI::CS{GPIO::PortB, GPIO::Pin2},
|
||||
SPI::DRDY{GPIO::PortE, GPIO::Pin4}),
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_LSM303D, SPI::CS{GPIO::PortD, GPIO::Pin11}),
|
||||
initSPIDevice(DRV_BARO_DEVTYPE_MS5611, SPI::CS{GPIO::PortC, GPIO::Pin15}),
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_MPU6000, SPI::CS{GPIO::PortE, GPIO::Pin3},
|
||||
SPI::DRDY{GPIO::PortE, GPIO::Pin10}),
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_MPU6500, SPI::CS{GPIO::PortE, GPIO::Pin3},
|
||||
SPI::DRDY{GPIO::PortE, GPIO::Pin10}),
|
||||
}),
|
||||
};
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
|
||||
@@ -41,18 +41,16 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <arm_arch.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/usb/usbdev.h>
|
||||
#include <nuttx/usb/usbdev_trace.h>
|
||||
|
||||
#include <arm_arch.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "board_config.h"
|
||||
|
||||
/************************************************************************************
|
||||
@@ -75,8 +73,7 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_usbinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_usbinitialize(void) {
|
||||
/* The OTG FS has an internal soft pull-up */
|
||||
|
||||
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
|
||||
@@ -101,8 +98,4 @@ __EXPORT void stm32_usbinitialize(void)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
|
||||
{
|
||||
uinfo("resume: %d\n", resume);
|
||||
}
|
||||
|
||||
__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); }
|
||||
|
||||
@@ -40,7 +40,7 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include <stm32.h>
|
||||
@@ -50,19 +50,19 @@
|
||||
* HSE - 8 MHz Crystal
|
||||
* LSE - not installed
|
||||
*/
|
||||
#define STM32_BOARD_USEHSE 1
|
||||
#define STM32_BOARD_XTAL 8000000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_BOARD_USEHSE 1
|
||||
#define STM32_BOARD_XTAL 8000000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
|
||||
/* Main PLL Configuration */
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
||||
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
@@ -74,63 +74,63 @@
|
||||
#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
|
||||
|
||||
#define STM32_SYSCLK_FREQUENCY 96000000ul
|
||||
#define STM32_SYSCLK_FREQUENCY 96000000ul
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (96MHz) */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
|
||||
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (96MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
|
||||
|
||||
/* Timers driven from APB2 will be PCLK2 since no prescale division */
|
||||
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
|
||||
#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Alternate function pin selections ************************************************/
|
||||
|
||||
/* UARTs */
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
|
||||
/* CAN */
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_2
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_2
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_2
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_2
|
||||
|
||||
/* SPI */
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
|
||||
#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
|
||||
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
|
||||
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_1 /* PB10 */
|
||||
#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
|
||||
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
|
||||
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_1 /* PB10 */
|
||||
|
||||
#endif /* __ARCH_BOARD_BOARD_H */
|
||||
|
||||
@@ -35,10 +35,10 @@
|
||||
|
||||
// DMA1 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX // DMA1, Stream 3, Channel 0
|
||||
#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX // DMA1, Stream 4, Channel 0
|
||||
#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX // DMA1, Stream 3, Channel 0
|
||||
#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX // DMA1, Stream 4, Channel 0
|
||||
|
||||
// DMA2 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_2 // DMA2, Stream 5, Channel 3
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_2 // DMA2, Stream 5, Channel 3
|
||||
|
||||
@@ -39,40 +39,45 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* CAN Silent mode control */
|
||||
#define GPIO_CAN1_SILENT_S0 /* PA9 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_CAN1_SILENT_S0 /* PA9 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN9)
|
||||
|
||||
/* CAN termination software control */
|
||||
#define GPIO_CAN1_TERMINATION /* PB13 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
|
||||
#define GPIO_CAN1_TERMINATION /* PB13 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN13)
|
||||
#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
|
||||
|
||||
/* Boot config */
|
||||
#define GPIO_BOOT_CONFIG /* PC15 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN15|GPIO_EXTI)
|
||||
#define GPIO_BOOT_CONFIG /* PC15 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTC | GPIO_PIN15 | GPIO_EXTI)
|
||||
|
||||
/* LEDs are driven with push open drain to support Anode to 5V or 3.3V */
|
||||
#define GPIO_nLED_RED /* PB3 */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_nLED_BLUE /* PA8 */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_nLED_RED /* PB3 */ \
|
||||
(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_nLED_BLUE /* PA8 */ \
|
||||
(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN8)
|
||||
|
||||
#define BROADCOM_AFBR_S50_S2PI_SPI_BUS 2
|
||||
#define BROADCOM_AFBR_S50_S2PI_CS /* PB12 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN12)
|
||||
#define BROADCOM_AFBR_S50_S2PI_IRQ /* PB4 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN4|GPIO_EXTI)
|
||||
#define BROADCOM_AFBR_S50_S2PI_CLK /* PB10 */ GPIO_SPI2_SCK_1
|
||||
#define BROADCOM_AFBR_S50_S2PI_MOSI /* PB15 */ GPIO_SPI2_MOSI_1
|
||||
#define BROADCOM_AFBR_S50_S2PI_MISO /* PB14 */ GPIO_SPI2_MISO_1
|
||||
#define BROADCOM_AFBR_S50_S2PI_CS /* PB12 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12)
|
||||
#define BROADCOM_AFBR_S50_S2PI_IRQ /* PB4 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTB | GPIO_PIN4 | GPIO_EXTI)
|
||||
#define BROADCOM_AFBR_S50_S2PI_CLK /* PB10 */ GPIO_SPI2_SCK_1
|
||||
#define BROADCOM_AFBR_S50_S2PI_MOSI /* PB15 */ GPIO_SPI2_MOSI_1
|
||||
#define BROADCOM_AFBR_S50_S2PI_MISO /* PB14 */ GPIO_SPI2_MISO_1
|
||||
|
||||
#define BOARD_HAS_CONTROL_STATUS_LEDS 1
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_STATE_LED LED_BLUE
|
||||
#define BOARD_HAS_CONTROL_STATUS_LEDS 1
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_STATE_LED LED_BLUE
|
||||
|
||||
#define FLASH_BASED_PARAMS
|
||||
|
||||
/* High-resolution timer */
|
||||
#define HRT_TIMER 3 /* use timer 3 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 4 /* use capture/compare channel 4 */
|
||||
#define HRT_TIMER 3 /* use timer 3 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 4 /* use capture/compare channel 4 */
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
|
||||
@@ -38,16 +38,15 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_config.h>
|
||||
#include <stdint.h>
|
||||
#include "boot_config.h"
|
||||
#include "board.h"
|
||||
|
||||
#include <debug.h>
|
||||
#include <string.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include "board.h"
|
||||
#include "boot_config.h"
|
||||
|
||||
__BEGIN_DECLS
|
||||
extern void led_init(void);
|
||||
@@ -65,8 +64,7 @@ __END_DECLS
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
putreg32(getreg32(STM32_RCC_APB1ENR) | RCC_APB1ENR_CAN1EN, STM32_RCC_APB1ENR);
|
||||
stm32_configgpio(GPIO_CAN1_RX);
|
||||
stm32_configgpio(GPIO_CAN1_TX);
|
||||
@@ -80,7 +78,6 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
#if defined(OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO)
|
||||
stm32_configgpio(GPIO_GETNODEINFO_JUMPER);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
@@ -92,10 +89,7 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void board_deinitialize(void)
|
||||
{
|
||||
putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR);
|
||||
}
|
||||
void board_deinitialize(void) { putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR); }
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_get_product_name
|
||||
@@ -114,8 +108,7 @@ void board_deinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
|
||||
{
|
||||
uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen) {
|
||||
DEBUGASSERT(maxlen > UAVCAN_STRLEN(HW_UAVCAN_NAME));
|
||||
memcpy(product_name, HW_UAVCAN_NAME, UAVCAN_STRLEN(HW_UAVCAN_NAME));
|
||||
return UAVCAN_STRLEN(HW_UAVCAN_NAME);
|
||||
@@ -136,14 +129,13 @@ uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
|
||||
{
|
||||
size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version) {
|
||||
memset(hw_version, 0, sizeof(uavcan_HardwareVersion_t));
|
||||
|
||||
hw_version->major = HW_VERSION_MAJOR;
|
||||
hw_version->minor = HW_VERSION_MINOR;
|
||||
|
||||
return board_get_mfguid(*(mfguid_t *) hw_version->unique_id);
|
||||
return board_get_mfguid(*(mfguid_t *)hw_version->unique_id);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -160,8 +152,7 @@ size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
void board_indicate(uiindication_t indication)
|
||||
{
|
||||
void board_indicate(uiindication_t indication) {
|
||||
if (indication == off) {
|
||||
bootloader_led_off(GPIO_nLED_RED);
|
||||
bootloader_led_off(GPIO_nLED_BLUE);
|
||||
@@ -170,8 +161,8 @@ void board_indicate(uiindication_t indication)
|
||||
bootloader_led_on(GPIO_nLED_RED);
|
||||
bootloader_led_on(GPIO_nLED_BLUE);
|
||||
|
||||
} else if ((indication == fw_update_erase_fail) || (indication == fw_update_invalid_response)
|
||||
|| (indication == fw_update_timeout) || (indication == fw_update_invalid_crc)) {
|
||||
} else if ((indication == fw_update_erase_fail) || (indication == fw_update_invalid_response) ||
|
||||
(indication == fw_update_timeout) || (indication == fw_update_invalid_crc)) {
|
||||
bootloader_led_on(GPIO_nLED_RED);
|
||||
bootloader_led_off(GPIO_nLED_BLUE);
|
||||
|
||||
|
||||
@@ -50,13 +50,12 @@
|
||||
* todo:make this be pulled in from a targed's build
|
||||
* files in nuttx*/
|
||||
|
||||
#include <nuttx/compiler.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32_flash.h>
|
||||
|
||||
#include "board_config.h"
|
||||
#include "uavcan.h"
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <stm32_flash.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -64,11 +63,11 @@
|
||||
|
||||
#define OPT_PREFERRED_NODE_ID ANY_NODE_ID
|
||||
|
||||
//todo:wrap OPT_x in in ifdefs for command line definitions
|
||||
#define OPT_TBOOT_MS 5000
|
||||
#define OPT_NODE_STATUS_RATE_MS 800
|
||||
#define OPT_NODE_INFO_RATE_MS 50
|
||||
#define OPT_BL_NUMBER_TIMERS 7
|
||||
// todo:wrap OPT_x in in ifdefs for command line definitions
|
||||
#define OPT_TBOOT_MS 5000
|
||||
#define OPT_NODE_STATUS_RATE_MS 800
|
||||
#define OPT_NODE_INFO_RATE_MS 50
|
||||
#define OPT_BL_NUMBER_TIMERS 7
|
||||
|
||||
/*
|
||||
* This Option set is set to 1 ensure a provider of firmware has an
|
||||
@@ -91,34 +90,33 @@
|
||||
* no 0 1 Not Active
|
||||
*
|
||||
*/
|
||||
#define OPT_WAIT_FOR_GETNODEINFO 0
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
|
||||
#define OPT_WAIT_FOR_GETNODEINFO 0
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO_INVERT 0
|
||||
|
||||
#define OPT_ENABLE_WD 1
|
||||
#define OPT_ENABLE_WD 1
|
||||
|
||||
#define OPT_RESTART_TIMEOUT_MS 20000
|
||||
#define OPT_RESTART_TIMEOUT_MS 20000
|
||||
|
||||
/* Reserved for the Booloader */
|
||||
#define OPT_BOOTLOADER_SIZE_IN_K (1024*64)
|
||||
#define OPT_BOOTLOADER_SIZE_IN_K (1024 * 64)
|
||||
|
||||
/* Reserved for the application out of the total
|
||||
* system flash minus the BOOTLOADER_SIZE_IN_K
|
||||
*/
|
||||
#define OPT_APPLICATION_RESERVER_IN_K 0
|
||||
#define OPT_APPLICATION_RESERVER_IN_K 0
|
||||
|
||||
#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
|
||||
#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE-(OPT_BOOTLOADER_SIZE_IN_K+OPT_APPLICATION_RESERVER_IN_K))
|
||||
#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
|
||||
#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE - (OPT_BOOTLOADER_SIZE_IN_K + OPT_APPLICATION_RESERVER_IN_K))
|
||||
|
||||
|
||||
#define FLASH_BASE STM32_FLASH_BASE
|
||||
#define FLASH_SIZE STM32_FLASH_SIZE
|
||||
#define FLASH_BASE STM32_FLASH_BASE
|
||||
#define FLASH_SIZE STM32_FLASH_SIZE
|
||||
|
||||
#define APPLICATION_LOAD_ADDRESS (FLASH_BASE + OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_SIZE (FLASH_SIZE-OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint8_t)))
|
||||
#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint32_t)))
|
||||
#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint64_t)))
|
||||
#define APPLICATION_SIZE (FLASH_SIZE - OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint8_t)))
|
||||
#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint32_t)))
|
||||
#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint64_t)))
|
||||
|
||||
/* If this board uses big flash that have large sectors */
|
||||
|
||||
|
||||
@@ -41,20 +41,17 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/can/can.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/can/can.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32.h"
|
||||
#include "stm32_can.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#ifdef CONFIG_CAN
|
||||
|
||||
@@ -64,14 +61,14 @@
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
|
||||
# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
# undef CONFIG_STM32_CAN2
|
||||
#warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
#undef CONFIG_STM32_CAN2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CAN1
|
||||
# define CAN_PORT 1
|
||||
#define CAN_PORT 1
|
||||
#else
|
||||
# define CAN_PORT 2
|
||||
#define CAN_PORT 2
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -92,8 +89,7 @@ int can_devinit(void);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int can_devinit(void)
|
||||
{
|
||||
int can_devinit(void) {
|
||||
static bool initialized = false;
|
||||
struct can_dev_s *can;
|
||||
int ret;
|
||||
|
||||
@@ -41,34 +41,28 @@
|
||||
* subsystems and perform board-specific initialization.
|
||||
*/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_watchdog.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/tasks.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include <stm32.h>
|
||||
#include "board_config.h"
|
||||
#include <stm32_uart.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_watchdog.h>
|
||||
|
||||
#include <string.h>
|
||||
#include <syslog.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
|
||||
#include <px4_platform_common/init.h>
|
||||
#include "board_config.h"
|
||||
|
||||
# if defined(FLASH_BASED_PARAMS)
|
||||
# include <parameters/flashparams/flashfs.h>
|
||||
#if defined(FLASH_BASED_PARAMS)
|
||||
#include <parameters/flashparams/flashfs.h>
|
||||
#endif
|
||||
|
||||
__BEGIN_DECLS
|
||||
@@ -87,8 +81,7 @@ __END_DECLS
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
watchdog_init();
|
||||
|
||||
// Configure CAN interface
|
||||
@@ -127,8 +120,7 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
__EXPORT int board_app_initialize(uintptr_t arg) {
|
||||
px4_platform_init();
|
||||
|
||||
// Configure LEDs.
|
||||
@@ -148,7 +140,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
syslog(LOG_ERR, "[boot] FAILED to init params in FLASH %d\n", result);
|
||||
}
|
||||
|
||||
#endif // FLASH_BASED_PARAMS
|
||||
#endif // FLASH_BASED_PARAMS
|
||||
|
||||
/* initial LED state */
|
||||
drv_led_start();
|
||||
|
||||
@@ -37,14 +37,12 @@
|
||||
* board LED backend.
|
||||
*/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "stm32.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include "stm32.h"
|
||||
|
||||
/*
|
||||
* Ideally we'd be able to get these from up_internal.h,
|
||||
@@ -62,54 +60,38 @@ extern void led_off(int led);
|
||||
extern void led_toggle(int led);
|
||||
__END_DECLS
|
||||
|
||||
# define xlat(p) (p)
|
||||
#define xlat(p) (p)
|
||||
static uint32_t g_ledmap[] = {
|
||||
GPIO_nLED_BLUE,
|
||||
GPIO_nLED_RED,
|
||||
};
|
||||
|
||||
__EXPORT void led_init(void)
|
||||
{
|
||||
__EXPORT void led_init(void) {
|
||||
/* Configure LED GPIOs for output */
|
||||
for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
|
||||
stm32_configgpio(g_ledmap[l]);
|
||||
}
|
||||
}
|
||||
|
||||
__EXPORT void bootloader_led_on(int led)
|
||||
{
|
||||
__EXPORT void bootloader_led_on(int led) {
|
||||
/* Pull Down to switch on */
|
||||
stm32_gpiowrite(led, false);
|
||||
}
|
||||
|
||||
__EXPORT void bootloader_led_off(int led)
|
||||
{
|
||||
__EXPORT void bootloader_led_off(int led) {
|
||||
/* Pull Up to switch on */
|
||||
stm32_gpiowrite(led, true);
|
||||
}
|
||||
|
||||
static void phy_set_led(int led, bool state)
|
||||
{
|
||||
static void phy_set_led(int led, bool state) {
|
||||
/* Pull Down to switch on */
|
||||
stm32_gpiowrite(g_ledmap[led], !state);
|
||||
}
|
||||
|
||||
static bool phy_get_led(int led)
|
||||
{
|
||||
return !stm32_gpioread(g_ledmap[led]);
|
||||
}
|
||||
static bool phy_get_led(int led) { return !stm32_gpioread(g_ledmap[led]); }
|
||||
|
||||
__EXPORT void led_on(int led)
|
||||
{
|
||||
phy_set_led(xlat(led), true);
|
||||
}
|
||||
__EXPORT void led_on(int led) { phy_set_led(xlat(led), true); }
|
||||
|
||||
__EXPORT void led_off(int led)
|
||||
{
|
||||
phy_set_led(xlat(led), false);
|
||||
}
|
||||
__EXPORT void led_off(int led) { phy_set_led(xlat(led), false); }
|
||||
|
||||
__EXPORT void led_toggle(int led)
|
||||
{
|
||||
phy_set_led(xlat(led), !phy_get_led(xlat(led)));
|
||||
}
|
||||
__EXPORT void led_toggle(int led) { phy_set_led(xlat(led), !phy_get_led(xlat(led))); }
|
||||
|
||||
@@ -31,20 +31,27 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::SPI1, {
|
||||
initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::PortA, GPIO::Pin15}, SPI::DRDY{GPIO::PortA, GPIO::Pin10}),
|
||||
initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::PortA, GPIO::Pin4}, SPI::DRDY{GPIO::PortB, GPIO::Pin0}),
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortA, GPIO::Pin4}, SPI::DRDY{GPIO::PortB, GPIO::Pin0}),
|
||||
initSPIDevice(DRV_FLOW_DEVTYPE_PAW3902, SPI::CS{GPIO::PortB, GPIO::Pin5}, SPI::DRDY{GPIO::PortB, GPIO::Pin2}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI2, {
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortB, GPIO::Pin12}, SPI::DRDY{GPIO::PortB, GPIO::Pin4}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI1,
|
||||
{
|
||||
initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::PortA, GPIO::Pin15},
|
||||
SPI::DRDY{GPIO::PortA, GPIO::Pin10}),
|
||||
initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::PortA, GPIO::Pin4},
|
||||
SPI::DRDY{GPIO::PortB, GPIO::Pin0}),
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortA, GPIO::Pin4},
|
||||
SPI::DRDY{GPIO::PortB, GPIO::Pin0}),
|
||||
initSPIDevice(DRV_FLOW_DEVTYPE_PAW3902, SPI::CS{GPIO::PortB, GPIO::Pin5},
|
||||
SPI::DRDY{GPIO::PortB, GPIO::Pin2}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI2,
|
||||
{
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortB, GPIO::Pin12},
|
||||
SPI::DRDY{GPIO::PortB, GPIO::Pin4}),
|
||||
}),
|
||||
};
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
|
||||
@@ -40,7 +40,7 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include <stm32.h>
|
||||
@@ -50,19 +50,19 @@
|
||||
* HSE - 8 MHz Crystal
|
||||
* LSE - not installed
|
||||
*/
|
||||
#define STM32_BOARD_USEHSE 1
|
||||
#define STM32_BOARD_XTAL 8000000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_BOARD_USEHSE 1
|
||||
#define STM32_BOARD_XTAL 8000000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
|
||||
/* Main PLL Configuration */
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
||||
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
@@ -74,79 +74,79 @@
|
||||
#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
|
||||
|
||||
#define STM32_SYSCLK_FREQUENCY 96000000ul
|
||||
#define STM32_SYSCLK_FREQUENCY 96000000ul
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (96MHz) */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
|
||||
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (96MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
|
||||
|
||||
/* Timers driven from APB2 will be PCLK2 since no prescale division */
|
||||
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
|
||||
#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Alternate function pin selections ************************************************/
|
||||
|
||||
/* UARTs */
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_3
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_3
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
|
||||
/* CAN */
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_1
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_1
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_MCU_I2C1_SCL
|
||||
#define GPIO_MCU_I2C1_SDA
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_4
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_4
|
||||
|
||||
#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
|
||||
|
||||
/* SPI */
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
|
||||
#endif /* __ARCH_BOARD_BOARD_H */
|
||||
|
||||
@@ -36,8 +36,7 @@
|
||||
// DMA1 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
|
||||
|
||||
// DMA2 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 5, Channel 3
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 5, Channel 3
|
||||
|
||||
@@ -39,77 +39,78 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* BUTTON */
|
||||
#define GPIO_BTN_SAFETY /* PB15 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_BTN_SAFETY /* PB15 */ (GPIO_INPUT | GPIO_PULLDOWN | GPIO_PORTB | GPIO_PIN15)
|
||||
|
||||
/* Safety LED */
|
||||
#define GPIO_LED_SAFETY /* PA1 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_LED_SAFETY /* PA1 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN1)
|
||||
|
||||
/* Tone alarm output. */
|
||||
#define TONE_ALARM_TIMER 2 /* timer 2 */
|
||||
#define TONE_ALARM_CHANNEL 1 /* channel 1 */
|
||||
#define GPIO_TONE_ALARM_IDLE /* PA0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TONE_ALARM /* PA0 */ (GPIO_ALT|GPIO_AF1|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define TONE_ALARM_TIMER 2 /* timer 2 */
|
||||
#define TONE_ALARM_CHANNEL 1 /* channel 1 */
|
||||
#define GPIO_TONE_ALARM_IDLE /* PA0 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN0)
|
||||
#define GPIO_TONE_ALARM /* PA0 */ (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_2MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN0)
|
||||
|
||||
/* CAN Silent mode control */
|
||||
#define GPIO_CAN1_SILENT_S0 /* PB12 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_CAN1_SILENT_S0 /* PB12 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN12)
|
||||
|
||||
/* CAN termination software control */
|
||||
#define GPIO_CAN1_TERMINATION /* PB13 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
|
||||
#define GPIO_CAN1_TERMINATION /* PB13 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN13)
|
||||
#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
|
||||
|
||||
/* ICM42688p FSYNC */
|
||||
#define GPIO_42688P_FSYNC /* PB8 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_42688P_FSYNC /* PB8 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN8)
|
||||
|
||||
/* Boot config */
|
||||
#define GPIO_BOOT_CONFIG /* PC15 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN15|GPIO_EXTI)
|
||||
#define GPIO_BOOT_CONFIG /* PC15 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTC | GPIO_PIN15 | GPIO_EXTI)
|
||||
|
||||
/* LEDs are driven with open drain to support Anode to 5V or 3.3V */
|
||||
#define GPIO_TIM1_CH1 /* PA8 */ (GPIO_TIM1_CH1_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH2 /* PA9 */ (GPIO_TIM1_CH2_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH3 /* PA10 */ (GPIO_TIM1_CH3_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH1 /* PA8 */ (GPIO_TIM1_CH1_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH2 /* PA9 */ (GPIO_TIM1_CH2_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH3 /* PA10 */ (GPIO_TIM1_CH3_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
|
||||
|
||||
#define GPIO_I2C1_SCL_RESET /* PB6 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_RESET /* PB7 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C1_SCL_RESET /* PB6 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_RESET /* PB7 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#define GPIO_I2C2_SCL_RESET /* PB10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA_RESET /* PB9 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C2_SCL_RESET /* PB10 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA_RESET /* PB9 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN9)
|
||||
|
||||
#define GPIO_USART1_RX_GPIO (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_USART1_TX_GPIO (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_USART1_RX_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_USART1_TX_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN15)
|
||||
|
||||
#define GPIO_USART2_RX_GPIO (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_USART2_TX_GPIO (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_USART2_RX_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN3)
|
||||
#define GPIO_USART2_TX_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN2)
|
||||
|
||||
#define FLASH_BASED_PARAMS
|
||||
|
||||
/* High-resolution timer */
|
||||
#define HRT_TIMER 3 /* use timer 3 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 4 /* use capture/compare channel 4 */
|
||||
#define HRT_TIMER 3 /* use timer 3 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 4 /* use capture/compare channel 4 */
|
||||
|
||||
#define PX4_GPIO_INIT_LIST { \
|
||||
GPIO_BTN_SAFETY, \
|
||||
GPIO_LED_SAFETY, \
|
||||
GPIO_I2C1_SCL_RESET, \
|
||||
GPIO_I2C1_SDA_RESET, \
|
||||
GPIO_I2C2_SCL_RESET, \
|
||||
GPIO_I2C2_SDA_RESET, \
|
||||
GPIO_42688P_FSYNC, \
|
||||
GPIO_BOOT_CONFIG, \
|
||||
GPIO_CAN1_TX, \
|
||||
GPIO_CAN1_RX, \
|
||||
GPIO_CAN1_SILENT_S0, \
|
||||
GPIO_CAN1_TERMINATION, \
|
||||
#define PX4_GPIO_INIT_LIST \
|
||||
{ \
|
||||
GPIO_BTN_SAFETY, GPIO_LED_SAFETY, GPIO_I2C1_SCL_RESET, GPIO_I2C1_SDA_RESET, GPIO_I2C2_SCL_RESET, \
|
||||
GPIO_I2C2_SDA_RESET, GPIO_42688P_FSYNC, GPIO_BOOT_CONFIG, GPIO_CAN1_TX, GPIO_CAN1_RX, \
|
||||
GPIO_CAN1_SILENT_S0, GPIO_CAN1_TERMINATION, \
|
||||
}
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
#define BOARD_HAS_N_S_RGB_LED 1
|
||||
#define BOARD_MAX_LEDS BOARD_HAS_N_S_RGB_LED
|
||||
#define BOARD_HAS_N_S_RGB_LED 1
|
||||
#define BOARD_MAX_LEDS BOARD_HAS_N_S_RGB_LED
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
||||
@@ -38,16 +38,15 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_config.h>
|
||||
#include <stdint.h>
|
||||
#include "boot_config.h"
|
||||
#include "board.h"
|
||||
|
||||
#include <debug.h>
|
||||
#include <string.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include "board.h"
|
||||
#include "boot_config.h"
|
||||
#include "led.h"
|
||||
|
||||
/************************************************************************************
|
||||
@@ -60,8 +59,7 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
putreg32(getreg32(STM32_RCC_APB1ENR) | RCC_APB1ENR_CAN1EN, STM32_RCC_APB1ENR);
|
||||
stm32_configgpio(GPIO_CAN1_RX);
|
||||
stm32_configgpio(GPIO_CAN1_TX);
|
||||
@@ -73,7 +71,6 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
#if defined(OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO)
|
||||
stm32_configgpio(GPIO_GETNODEINFO_JUMPER);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
@@ -85,10 +82,7 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void board_deinitialize(void)
|
||||
{
|
||||
putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR);
|
||||
}
|
||||
void board_deinitialize(void) { putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR); }
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_get_product_name
|
||||
@@ -107,8 +101,7 @@ void board_deinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
|
||||
{
|
||||
uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen) {
|
||||
DEBUGASSERT(maxlen > UAVCAN_STRLEN(HW_UAVCAN_NAME));
|
||||
memcpy(product_name, HW_UAVCAN_NAME, UAVCAN_STRLEN(HW_UAVCAN_NAME));
|
||||
return UAVCAN_STRLEN(HW_UAVCAN_NAME);
|
||||
@@ -129,14 +122,13 @@ uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
|
||||
{
|
||||
size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version) {
|
||||
memset(hw_version, 0, sizeof(uavcan_HardwareVersion_t));
|
||||
|
||||
hw_version->major = HW_VERSION_MAJOR;
|
||||
hw_version->minor = HW_VERSION_MINOR;
|
||||
|
||||
return board_get_mfguid(*(mfguid_t *) hw_version->unique_id);
|
||||
return board_get_mfguid(*(mfguid_t *)hw_version->unique_id);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -153,7 +145,8 @@ size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
#define led(n, code, r , g , b, h) {.red = (r),.green = (g), .blue = (b),.hz = (h)}
|
||||
#define led(n, code, r, g, b, h) \
|
||||
{ .red = (r), .green = (g), .blue = (b), .hz = (h) }
|
||||
|
||||
typedef begin_packed_struct struct led_t {
|
||||
uint8_t red;
|
||||
@@ -162,27 +155,23 @@ typedef begin_packed_struct struct led_t {
|
||||
uint8_t hz;
|
||||
} end_packed_struct led_t;
|
||||
|
||||
static const led_t i2l[] = {
|
||||
static const led_t i2l[] = {
|
||||
|
||||
led(0, off, 0, 0, 0, 0),
|
||||
led(1, reset, 128, 128, 128, 30),
|
||||
led(2, autobaud_start, 0, 128, 0, 1),
|
||||
led(3, autobaud_end, 0, 128, 0, 2),
|
||||
led(4, allocation_start, 0, 0, 64, 2),
|
||||
led(5, allocation_end, 0, 128, 64, 3),
|
||||
led(6, fw_update_start, 32, 128, 64, 3),
|
||||
led(7, fw_update_erase_fail, 32, 128, 32, 3),
|
||||
led(8, fw_update_invalid_response, 64, 0, 0, 1),
|
||||
led(9, fw_update_timeout, 64, 0, 0, 2),
|
||||
led(a, fw_update_invalid_crc, 64, 0, 0, 4),
|
||||
led(b, jump_to_app, 0, 128, 0, 10),
|
||||
led(0, off, 0, 0, 0, 0),
|
||||
led(1, reset, 128, 128, 128, 30),
|
||||
led(2, autobaud_start, 0, 128, 0, 1),
|
||||
led(3, autobaud_end, 0, 128, 0, 2),
|
||||
led(4, allocation_start, 0, 0, 64, 2),
|
||||
led(5, allocation_end, 0, 128, 64, 3),
|
||||
led(6, fw_update_start, 32, 128, 64, 3),
|
||||
led(7, fw_update_erase_fail, 32, 128, 32, 3),
|
||||
led(8, fw_update_invalid_response, 64, 0, 0, 1),
|
||||
led(9, fw_update_timeout, 64, 0, 0, 2),
|
||||
led(a, fw_update_invalid_crc, 64, 0, 0, 4),
|
||||
led(b, jump_to_app, 0, 128, 0, 10),
|
||||
|
||||
};
|
||||
|
||||
void board_indicate(uiindication_t indication)
|
||||
{
|
||||
rgb_led(i2l[indication].red,
|
||||
i2l[indication].green,
|
||||
i2l[indication].blue,
|
||||
i2l[indication].hz);
|
||||
void board_indicate(uiindication_t indication) {
|
||||
rgb_led(i2l[indication].red, i2l[indication].green, i2l[indication].blue, i2l[indication].hz);
|
||||
}
|
||||
|
||||
@@ -50,13 +50,12 @@
|
||||
* todo:make this be pulled in from a targed's build
|
||||
* files in nuttx*/
|
||||
|
||||
#include <nuttx/compiler.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32_flash.h>
|
||||
|
||||
#include "board_config.h"
|
||||
#include "uavcan.h"
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <stm32_flash.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -64,11 +63,11 @@
|
||||
|
||||
#define OPT_PREFERRED_NODE_ID ANY_NODE_ID
|
||||
|
||||
//todo:wrap OPT_x in in ifdefs for command line definitions
|
||||
#define OPT_TBOOT_MS 5000
|
||||
#define OPT_NODE_STATUS_RATE_MS 800
|
||||
#define OPT_NODE_INFO_RATE_MS 50
|
||||
#define OPT_BL_NUMBER_TIMERS 7
|
||||
// todo:wrap OPT_x in in ifdefs for command line definitions
|
||||
#define OPT_TBOOT_MS 5000
|
||||
#define OPT_NODE_STATUS_RATE_MS 800
|
||||
#define OPT_NODE_INFO_RATE_MS 50
|
||||
#define OPT_BL_NUMBER_TIMERS 7
|
||||
|
||||
/*
|
||||
* This Option set is set to 1 ensure a provider of firmware has an
|
||||
@@ -91,34 +90,33 @@
|
||||
* no 0 1 Not Active
|
||||
*
|
||||
*/
|
||||
#define OPT_WAIT_FOR_GETNODEINFO 0
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
|
||||
#define OPT_WAIT_FOR_GETNODEINFO 0
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO_INVERT 0
|
||||
|
||||
#define OPT_ENABLE_WD 1
|
||||
#define OPT_ENABLE_WD 1
|
||||
|
||||
#define OPT_RESTART_TIMEOUT_MS 20000
|
||||
#define OPT_RESTART_TIMEOUT_MS 20000
|
||||
|
||||
/* Reserved for the Booloader */
|
||||
#define OPT_BOOTLOADER_SIZE_IN_K (1024*64)
|
||||
#define OPT_BOOTLOADER_SIZE_IN_K (1024 * 64)
|
||||
|
||||
/* Reserved for the application out of the total
|
||||
* system flash minus the BOOTLOADER_SIZE_IN_K
|
||||
*/
|
||||
#define OPT_APPLICATION_RESERVER_IN_K 0
|
||||
#define OPT_APPLICATION_RESERVER_IN_K 0
|
||||
|
||||
#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
|
||||
#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE-(OPT_BOOTLOADER_SIZE_IN_K+OPT_APPLICATION_RESERVER_IN_K))
|
||||
#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
|
||||
#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE - (OPT_BOOTLOADER_SIZE_IN_K + OPT_APPLICATION_RESERVER_IN_K))
|
||||
|
||||
|
||||
#define FLASH_BASE STM32_FLASH_BASE
|
||||
#define FLASH_SIZE STM32_FLASH_SIZE
|
||||
#define FLASH_BASE STM32_FLASH_BASE
|
||||
#define FLASH_SIZE STM32_FLASH_SIZE
|
||||
|
||||
#define APPLICATION_LOAD_ADDRESS (FLASH_BASE + OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_SIZE (FLASH_SIZE-OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint8_t)))
|
||||
#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint32_t)))
|
||||
#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint64_t)))
|
||||
#define APPLICATION_SIZE (FLASH_SIZE - OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint8_t)))
|
||||
#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint32_t)))
|
||||
#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint64_t)))
|
||||
|
||||
/* If this board uses big flash that have large sectors */
|
||||
|
||||
|
||||
@@ -41,20 +41,17 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/can/can.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/can/can.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32.h"
|
||||
#include "stm32_can.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#ifdef CONFIG_CAN
|
||||
|
||||
@@ -64,14 +61,14 @@
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
|
||||
# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
# undef CONFIG_STM32_CAN2
|
||||
#warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
#undef CONFIG_STM32_CAN2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CAN1
|
||||
# define CAN_PORT 1
|
||||
#define CAN_PORT 1
|
||||
#else
|
||||
# define CAN_PORT 2
|
||||
#define CAN_PORT 2
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -92,8 +89,7 @@ int can_devinit(void);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int can_devinit(void)
|
||||
{
|
||||
int can_devinit(void) {
|
||||
static bool initialized = false;
|
||||
struct can_dev_s *can;
|
||||
int ret;
|
||||
|
||||
@@ -41,36 +41,30 @@
|
||||
* subsystems and perform board-specific initialization.
|
||||
*/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_watchdog.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/tasks.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include <stm32.h>
|
||||
#include "board_config.h"
|
||||
#include "led.h"
|
||||
#include <stm32_uart.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_watchdog.h>
|
||||
|
||||
#include <string.h>
|
||||
#include <syslog.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include "board_config.h"
|
||||
#include "led.h"
|
||||
|
||||
# if defined(FLASH_BASED_PARAMS)
|
||||
# include <parameters/flashparams/flashfs.h>
|
||||
#if defined(FLASH_BASED_PARAMS)
|
||||
#include <parameters/flashparams/flashfs.h>
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -83,8 +77,7 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
watchdog_init();
|
||||
|
||||
/* configure pins */
|
||||
@@ -135,8 +128,7 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
__EXPORT int board_app_initialize(uintptr_t arg) {
|
||||
px4_platform_init();
|
||||
|
||||
#if defined(FLASH_BASED_PARAMS)
|
||||
@@ -153,7 +145,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
syslog(LOG_ERR, "[boot] FAILED to init params in FLASH %d\n", result);
|
||||
}
|
||||
|
||||
#endif // FLASH_BASED_PARAMS
|
||||
#endif // FLASH_BASED_PARAMS
|
||||
|
||||
/* Configure the HW based on the manifest */
|
||||
|
||||
|
||||
@@ -37,30 +37,26 @@
|
||||
* LED backend.
|
||||
*/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "led.h"
|
||||
|
||||
#define TMR_BASE STM32_TIM1_BASE
|
||||
#define TMR_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define TMR_REG(o) (TMR_BASE+(o))
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
void rgb_led(int r, int g, int b, int freqs)
|
||||
{
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
#define TMR_BASE STM32_TIM1_BASE
|
||||
#define TMR_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define TMR_REG(o) (TMR_BASE + (o))
|
||||
|
||||
void rgb_led(int r, int g, int b, int freqs) {
|
||||
long fosc = TMR_FREQUENCY;
|
||||
long prescale = 2048;
|
||||
long p1s = fosc / prescale;
|
||||
long p0p5s = p1s / 2;
|
||||
long p0p5s = p1s / 2;
|
||||
uint16_t val;
|
||||
static bool once = 0;
|
||||
|
||||
@@ -84,14 +80,14 @@ void rgb_led(int r, int g, int b, int freqs)
|
||||
|
||||
putreg16(ATIM_CR1_CEN | ATIM_CR1_ARPE, TMR_REG(STM32_BTIM_CR1_OFFSET));
|
||||
|
||||
|
||||
putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | ATIM_CCMR1_OC1PE |
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE, TMR_REG(STM32_GTIM_CCMR1_OFFSET));
|
||||
putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE, TMR_REG(STM32_GTIM_CCMR2_OFFSET));
|
||||
putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P |
|
||||
ATIM_CCER_CC2E | ATIM_CCER_CC2P |
|
||||
ATIM_CCER_CC1E | ATIM_CCER_CC1P, TMR_REG(STM32_GTIM_CCER_OFFSET));
|
||||
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE,
|
||||
TMR_REG(STM32_GTIM_CCMR1_OFFSET));
|
||||
putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE,
|
||||
TMR_REG(STM32_GTIM_CCMR2_OFFSET));
|
||||
putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P | ATIM_CCER_CC2E | ATIM_CCER_CC2P | ATIM_CCER_CC1E |
|
||||
ATIM_CCER_CC1P,
|
||||
TMR_REG(STM32_GTIM_CCER_OFFSET));
|
||||
|
||||
stm32_configgpio(GPIO_TIM1_CH1);
|
||||
stm32_configgpio(GPIO_TIM1_CH2);
|
||||
@@ -101,10 +97,10 @@ void rgb_led(int r, int g, int b, int freqs)
|
||||
putreg16(ATIM_BDTR_MOE, (TMR_REG(STM32_ATIM_BDTR_OFFSET)));
|
||||
}
|
||||
|
||||
long p = freqs == 0 ? p1s : p1s / freqs;
|
||||
long p = freqs == 0 ? p1s : p1s / freqs;
|
||||
putreg32(p, TMR_REG(STM32_BTIM_ARR_OFFSET));
|
||||
|
||||
p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
|
||||
p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
|
||||
|
||||
putreg32((r * p) / 255, TMR_REG(STM32_GTIM_CCR1_OFFSET));
|
||||
putreg32((g * p) / 255, TMR_REG(STM32_GTIM_CCR2_OFFSET));
|
||||
@@ -120,5 +116,4 @@ void rgb_led(int r, int g, int b, int freqs)
|
||||
}
|
||||
|
||||
putreg16(val, TMR_REG(STM32_BTIM_CR1_OFFSET));
|
||||
|
||||
}
|
||||
|
||||
@@ -31,14 +31,16 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::SPI1, {
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortB, GPIO::Pin0}, SPI::DRDY{GPIO::PortB, GPIO::Pin1}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI1,
|
||||
{
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortB, GPIO::Pin0},
|
||||
SPI::DRDY{GPIO::PortB, GPIO::Pin1}),
|
||||
}),
|
||||
};
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
|
||||
@@ -40,7 +40,7 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include <stm32.h>
|
||||
@@ -50,19 +50,19 @@
|
||||
* HSE - 8 MHz Crystal
|
||||
* LSE - not installed
|
||||
*/
|
||||
#define STM32_BOARD_USEHSE 1
|
||||
#define STM32_BOARD_XTAL 8000000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_BOARD_USEHSE 1
|
||||
#define STM32_BOARD_XTAL 8000000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
|
||||
/* Main PLL Configuration */
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
||||
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
@@ -74,79 +74,79 @@
|
||||
#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
|
||||
|
||||
#define STM32_SYSCLK_FREQUENCY 96000000ul
|
||||
#define STM32_SYSCLK_FREQUENCY 96000000ul
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (96MHz) */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
|
||||
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (96MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
|
||||
|
||||
/* Timers driven from APB2 will be PCLK2 since no prescale division */
|
||||
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
|
||||
#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Alternate function pin selections ************************************************/
|
||||
|
||||
/* UARTs */
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_3
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_3
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
|
||||
/* CAN */
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_1
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_1
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define GPIO_MCU_I2C1_SCL
|
||||
#define GPIO_MCU_I2C1_SDA
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_4
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_4
|
||||
|
||||
#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
|
||||
#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
|
||||
|
||||
/* SPI */
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
|
||||
#endif /* __ARCH_BOARD_BOARD_H */
|
||||
|
||||
@@ -36,11 +36,10 @@
|
||||
// DMA1 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
|
||||
|
||||
// DMA2 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 // DMA2, Stream 0, Channel 3
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3
|
||||
#define DMACHAN_USART1_RX DMAMAP_USART1_RX_1 // DMA2, Stream 2, Channel 4
|
||||
#define DMAMAP_USART1_RX DMAMAP_USART1_RX_1
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1 // DMA2, Stream 0, Channel 3
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3
|
||||
#define DMACHAN_USART1_RX DMAMAP_USART1_RX_1 // DMA2, Stream 2, Channel 4
|
||||
#define DMAMAP_USART1_RX DMAMAP_USART1_RX_1
|
||||
//#define DMACHAN_USART1_TX DMAMAP_USART1_TX // DMA2, Stream 7, Channel 4
|
||||
|
||||
@@ -39,80 +39,83 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* BUTTON */
|
||||
#define GPIO_BTN_SAFETY /* PB15 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTB|GPIO_PIN15)
|
||||
#define GPIO_BTN_SAFETY /* PB15 */ (GPIO_INPUT | GPIO_PULLDOWN | GPIO_PORTB | GPIO_PIN15)
|
||||
|
||||
/* Safety LED */
|
||||
#define GPIO_LED_SAFETY /* PA1 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_LED_SAFETY /* PA1 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN1)
|
||||
|
||||
/* Tone alarm output. */
|
||||
#define TONE_ALARM_TIMER 2 /* timer 2 */
|
||||
#define TONE_ALARM_CHANNEL 1 /* channel 1 */
|
||||
#define GPIO_TONE_ALARM_IDLE /* PA0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TONE_ALARM /* PA0 */ (GPIO_ALT|GPIO_AF1|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
|
||||
#define TONE_ALARM_TIMER 2 /* timer 2 */
|
||||
#define TONE_ALARM_CHANNEL 1 /* channel 1 */
|
||||
#define GPIO_TONE_ALARM_IDLE /* PA0 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN0)
|
||||
#define GPIO_TONE_ALARM /* PA0 */ (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_2MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN0)
|
||||
|
||||
/* CAN Silent mode control */
|
||||
#define GPIO_CAN1_SILENT_S0 /* PB12 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12)
|
||||
#define GPIO_CAN1_SILENT_S0 /* PB12 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN12)
|
||||
|
||||
/* CAN termination software control */
|
||||
#define GPIO_CAN1_TERMINATION /* PB13 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13)
|
||||
#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
|
||||
#define GPIO_CAN1_TERMINATION /* PB13 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN13)
|
||||
#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
|
||||
|
||||
/* ICM42688p FSYNC */
|
||||
#define GPIO_42688P_FSYNC /* PB8 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_42688P_FSYNC /* PB8 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN8)
|
||||
|
||||
/* Boot config */
|
||||
#define GPIO_BOOT_CONFIG /* PC15 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN15|GPIO_EXTI)
|
||||
#define GPIO_BOOT_CONFIG /* PC15 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTC | GPIO_PIN15 | GPIO_EXTI)
|
||||
|
||||
/* LEDs are driven with open drain to support Anode to 5V or 3.3V */
|
||||
#define GPIO_TIM1_CH1 /* PA8 */ (GPIO_TIM1_CH1_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH2 /* PA9 */ (GPIO_TIM1_CH2_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH3 /* PA10 */ (GPIO_TIM1_CH3_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH1 /* PA8 */ (GPIO_TIM1_CH1_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH2 /* PA9 */ (GPIO_TIM1_CH2_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH3 /* PA10 */ (GPIO_TIM1_CH3_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
|
||||
|
||||
#define GPIO_I2C1_SCL_RESET /* PB6 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_RESET /* PB7 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C1_SCL_RESET /* PB6 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_RESET /* PB7 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#define GPIO_I2C2_SCL_RESET /* PB10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA_RESET /* PB9 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C2_SCL_RESET /* PB10 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA_RESET /* PB9 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN9)
|
||||
|
||||
#define GPIO_I2C2_SCL_RESET /* PB10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA_RESET /* PB9 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C2_SCL_RESET /* PB10 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_I2C2_SDA_RESET /* PB9 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN9)
|
||||
|
||||
#define GPIO_USART1_RX_GPIO (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_USART1_TX_GPIO (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_USART1_RX_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_USART1_TX_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN15)
|
||||
|
||||
#define GPIO_USART2_RX_GPIO (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_USART2_TX_GPIO (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_USART2_RX_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN3)
|
||||
#define GPIO_USART2_TX_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN2)
|
||||
|
||||
#define FLASH_BASED_PARAMS
|
||||
|
||||
/* High-resolution timer */
|
||||
#define HRT_TIMER 3 /* use timer 3 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 4 /* use capture/compare channel 4 */
|
||||
#define HRT_TIMER 3 /* use timer 3 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 4 /* use capture/compare channel 4 */
|
||||
|
||||
#define PX4_GPIO_INIT_LIST { \
|
||||
GPIO_BTN_SAFETY, \
|
||||
GPIO_LED_SAFETY, \
|
||||
GPIO_I2C1_SCL_RESET, \
|
||||
GPIO_I2C1_SDA_RESET, \
|
||||
GPIO_I2C2_SCL_RESET, \
|
||||
GPIO_I2C2_SDA_RESET, \
|
||||
GPIO_42688P_FSYNC, \
|
||||
GPIO_BOOT_CONFIG, \
|
||||
GPIO_CAN1_TX, \
|
||||
GPIO_CAN1_RX, \
|
||||
GPIO_CAN1_SILENT_S0, \
|
||||
GPIO_CAN1_TERMINATION, \
|
||||
#define PX4_GPIO_INIT_LIST \
|
||||
{ \
|
||||
GPIO_BTN_SAFETY, GPIO_LED_SAFETY, GPIO_I2C1_SCL_RESET, GPIO_I2C1_SDA_RESET, GPIO_I2C2_SCL_RESET, \
|
||||
GPIO_I2C2_SDA_RESET, GPIO_42688P_FSYNC, GPIO_BOOT_CONFIG, GPIO_CAN1_TX, GPIO_CAN1_RX, \
|
||||
GPIO_CAN1_SILENT_S0, GPIO_CAN1_TERMINATION, \
|
||||
}
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
#define BOARD_HAS_N_S_RGB_LED 1
|
||||
#define BOARD_MAX_LEDS BOARD_HAS_N_S_RGB_LED
|
||||
#define BOARD_HAS_N_S_RGB_LED 1
|
||||
#define BOARD_MAX_LEDS BOARD_HAS_N_S_RGB_LED
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
||||
@@ -38,16 +38,15 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_config.h>
|
||||
#include <stdint.h>
|
||||
#include "boot_config.h"
|
||||
#include "board.h"
|
||||
|
||||
#include <debug.h>
|
||||
#include <string.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include "board.h"
|
||||
#include "boot_config.h"
|
||||
#include "led.h"
|
||||
|
||||
/************************************************************************************
|
||||
@@ -60,8 +59,7 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
putreg32(getreg32(STM32_RCC_APB1ENR) | RCC_APB1ENR_CAN1EN, STM32_RCC_APB1ENR);
|
||||
stm32_configgpio(GPIO_CAN1_RX);
|
||||
stm32_configgpio(GPIO_CAN1_TX);
|
||||
@@ -73,7 +71,6 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
#if defined(OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO)
|
||||
stm32_configgpio(GPIO_GETNODEINFO_JUMPER);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
@@ -85,10 +82,7 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void board_deinitialize(void)
|
||||
{
|
||||
putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR);
|
||||
}
|
||||
void board_deinitialize(void) { putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR); }
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_get_product_name
|
||||
@@ -107,8 +101,7 @@ void board_deinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
|
||||
{
|
||||
uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen) {
|
||||
DEBUGASSERT(maxlen > UAVCAN_STRLEN(HW_UAVCAN_NAME));
|
||||
memcpy(product_name, HW_UAVCAN_NAME, UAVCAN_STRLEN(HW_UAVCAN_NAME));
|
||||
return UAVCAN_STRLEN(HW_UAVCAN_NAME);
|
||||
@@ -129,14 +122,13 @@ uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
|
||||
{
|
||||
size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version) {
|
||||
memset(hw_version, 0, sizeof(uavcan_HardwareVersion_t));
|
||||
|
||||
hw_version->major = HW_VERSION_MAJOR;
|
||||
hw_version->minor = HW_VERSION_MINOR;
|
||||
|
||||
return board_get_mfguid(*(mfguid_t *) hw_version->unique_id);
|
||||
return board_get_mfguid(*(mfguid_t *)hw_version->unique_id);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -153,7 +145,8 @@ size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
#define led(n, code, r , g , b, h) {.red = (r),.green = (g), .blue = (b),.hz = (h)}
|
||||
#define led(n, code, r, g, b, h) \
|
||||
{ .red = (r), .green = (g), .blue = (b), .hz = (h) }
|
||||
|
||||
typedef begin_packed_struct struct led_t {
|
||||
uint8_t red;
|
||||
@@ -162,27 +155,23 @@ typedef begin_packed_struct struct led_t {
|
||||
uint8_t hz;
|
||||
} end_packed_struct led_t;
|
||||
|
||||
static const led_t i2l[] = {
|
||||
static const led_t i2l[] = {
|
||||
|
||||
led(0, off, 0, 0, 0, 0),
|
||||
led(1, reset, 128, 128, 128, 30),
|
||||
led(2, autobaud_start, 0, 128, 0, 1),
|
||||
led(3, autobaud_end, 0, 128, 0, 2),
|
||||
led(4, allocation_start, 0, 0, 64, 2),
|
||||
led(5, allocation_end, 0, 128, 64, 3),
|
||||
led(6, fw_update_start, 32, 128, 64, 3),
|
||||
led(7, fw_update_erase_fail, 32, 128, 32, 3),
|
||||
led(8, fw_update_invalid_response, 64, 0, 0, 1),
|
||||
led(9, fw_update_timeout, 64, 0, 0, 2),
|
||||
led(a, fw_update_invalid_crc, 64, 0, 0, 4),
|
||||
led(b, jump_to_app, 0, 128, 0, 10),
|
||||
led(0, off, 0, 0, 0, 0),
|
||||
led(1, reset, 128, 128, 128, 30),
|
||||
led(2, autobaud_start, 0, 128, 0, 1),
|
||||
led(3, autobaud_end, 0, 128, 0, 2),
|
||||
led(4, allocation_start, 0, 0, 64, 2),
|
||||
led(5, allocation_end, 0, 128, 64, 3),
|
||||
led(6, fw_update_start, 32, 128, 64, 3),
|
||||
led(7, fw_update_erase_fail, 32, 128, 32, 3),
|
||||
led(8, fw_update_invalid_response, 64, 0, 0, 1),
|
||||
led(9, fw_update_timeout, 64, 0, 0, 2),
|
||||
led(a, fw_update_invalid_crc, 64, 0, 0, 4),
|
||||
led(b, jump_to_app, 0, 128, 0, 10),
|
||||
|
||||
};
|
||||
|
||||
void board_indicate(uiindication_t indication)
|
||||
{
|
||||
rgb_led(i2l[indication].red,
|
||||
i2l[indication].green,
|
||||
i2l[indication].blue,
|
||||
i2l[indication].hz);
|
||||
void board_indicate(uiindication_t indication) {
|
||||
rgb_led(i2l[indication].red, i2l[indication].green, i2l[indication].blue, i2l[indication].hz);
|
||||
}
|
||||
|
||||
@@ -50,13 +50,12 @@
|
||||
* todo:make this be pulled in from a targed's build
|
||||
* files in nuttx*/
|
||||
|
||||
#include <nuttx/compiler.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32_flash.h>
|
||||
|
||||
#include "board_config.h"
|
||||
#include "uavcan.h"
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <stm32_flash.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -64,11 +63,11 @@
|
||||
|
||||
#define OPT_PREFERRED_NODE_ID ANY_NODE_ID
|
||||
|
||||
//todo:wrap OPT_x in in ifdefs for command line definitions
|
||||
#define OPT_TBOOT_MS 5000
|
||||
#define OPT_NODE_STATUS_RATE_MS 800
|
||||
#define OPT_NODE_INFO_RATE_MS 50
|
||||
#define OPT_BL_NUMBER_TIMERS 7
|
||||
// todo:wrap OPT_x in in ifdefs for command line definitions
|
||||
#define OPT_TBOOT_MS 5000
|
||||
#define OPT_NODE_STATUS_RATE_MS 800
|
||||
#define OPT_NODE_INFO_RATE_MS 50
|
||||
#define OPT_BL_NUMBER_TIMERS 7
|
||||
|
||||
/*
|
||||
* This Option set is set to 1 ensure a provider of firmware has an
|
||||
@@ -91,34 +90,33 @@
|
||||
* no 0 1 Not Active
|
||||
*
|
||||
*/
|
||||
#define OPT_WAIT_FOR_GETNODEINFO 0
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
|
||||
#define OPT_WAIT_FOR_GETNODEINFO 0
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO_INVERT 0
|
||||
|
||||
#define OPT_ENABLE_WD 1
|
||||
#define OPT_ENABLE_WD 1
|
||||
|
||||
#define OPT_RESTART_TIMEOUT_MS 20000
|
||||
#define OPT_RESTART_TIMEOUT_MS 20000
|
||||
|
||||
/* Reserved for the Booloader */
|
||||
#define OPT_BOOTLOADER_SIZE_IN_K (1024*64)
|
||||
#define OPT_BOOTLOADER_SIZE_IN_K (1024 * 64)
|
||||
|
||||
/* Reserved for the application out of the total
|
||||
* system flash minus the BOOTLOADER_SIZE_IN_K
|
||||
*/
|
||||
#define OPT_APPLICATION_RESERVER_IN_K 0
|
||||
#define OPT_APPLICATION_RESERVER_IN_K 0
|
||||
|
||||
#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
|
||||
#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE-(OPT_BOOTLOADER_SIZE_IN_K+OPT_APPLICATION_RESERVER_IN_K))
|
||||
#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
|
||||
#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE - (OPT_BOOTLOADER_SIZE_IN_K + OPT_APPLICATION_RESERVER_IN_K))
|
||||
|
||||
|
||||
#define FLASH_BASE STM32_FLASH_BASE
|
||||
#define FLASH_SIZE STM32_FLASH_SIZE
|
||||
#define FLASH_BASE STM32_FLASH_BASE
|
||||
#define FLASH_SIZE STM32_FLASH_SIZE
|
||||
|
||||
#define APPLICATION_LOAD_ADDRESS (FLASH_BASE + OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_SIZE (FLASH_SIZE-OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint8_t)))
|
||||
#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint32_t)))
|
||||
#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint64_t)))
|
||||
#define APPLICATION_SIZE (FLASH_SIZE - OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint8_t)))
|
||||
#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint32_t)))
|
||||
#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint64_t)))
|
||||
|
||||
/* If this board uses big flash that have large sectors */
|
||||
|
||||
|
||||
@@ -41,20 +41,17 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/can/can.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/can/can.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32.h"
|
||||
#include "stm32_can.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#ifdef CONFIG_CAN
|
||||
|
||||
@@ -64,14 +61,14 @@
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
|
||||
# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
# undef CONFIG_STM32_CAN2
|
||||
#warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
#undef CONFIG_STM32_CAN2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CAN1
|
||||
# define CAN_PORT 1
|
||||
#define CAN_PORT 1
|
||||
#else
|
||||
# define CAN_PORT 2
|
||||
#define CAN_PORT 2
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -92,8 +89,7 @@ int can_devinit(void);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int can_devinit(void)
|
||||
{
|
||||
int can_devinit(void) {
|
||||
static bool initialized = false;
|
||||
struct can_dev_s *can;
|
||||
int ret;
|
||||
|
||||
@@ -41,36 +41,30 @@
|
||||
* subsystems and perform board-specific initialization.
|
||||
*/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_watchdog.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/tasks.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include <stm32.h>
|
||||
#include "board_config.h"
|
||||
#include "led.h"
|
||||
#include <stm32_uart.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_watchdog.h>
|
||||
|
||||
#include <string.h>
|
||||
#include <syslog.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include "board_config.h"
|
||||
#include "led.h"
|
||||
|
||||
# if defined(FLASH_BASED_PARAMS)
|
||||
# include <parameters/flashparams/flashfs.h>
|
||||
#if defined(FLASH_BASED_PARAMS)
|
||||
#include <parameters/flashparams/flashfs.h>
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -83,8 +77,7 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
watchdog_init();
|
||||
|
||||
/* configure pins */
|
||||
@@ -135,8 +128,7 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
__EXPORT int board_app_initialize(uintptr_t arg) {
|
||||
px4_platform_init();
|
||||
|
||||
#if defined(SERIAL_HAVE_RXDMA)
|
||||
@@ -159,7 +151,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
syslog(LOG_ERR, "[boot] FAILED to init params in FLASH %d\n", result);
|
||||
}
|
||||
|
||||
#endif // FLASH_BASED_PARAMS
|
||||
#endif // FLASH_BASED_PARAMS
|
||||
|
||||
/* Configure the HW based on the manifest */
|
||||
|
||||
|
||||
@@ -37,30 +37,26 @@
|
||||
* LED backend.
|
||||
*/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "led.h"
|
||||
|
||||
#define TMR_BASE STM32_TIM1_BASE
|
||||
#define TMR_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define TMR_REG(o) (TMR_BASE+(o))
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
void rgb_led(int r, int g, int b, int freqs)
|
||||
{
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
#define TMR_BASE STM32_TIM1_BASE
|
||||
#define TMR_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define TMR_REG(o) (TMR_BASE + (o))
|
||||
|
||||
void rgb_led(int r, int g, int b, int freqs) {
|
||||
long fosc = TMR_FREQUENCY;
|
||||
long prescale = 2048;
|
||||
long p1s = fosc / prescale;
|
||||
long p0p5s = p1s / 2;
|
||||
long p0p5s = p1s / 2;
|
||||
uint16_t val;
|
||||
static bool once = 0;
|
||||
|
||||
@@ -84,14 +80,14 @@ void rgb_led(int r, int g, int b, int freqs)
|
||||
|
||||
putreg16(ATIM_CR1_CEN | ATIM_CR1_ARPE, TMR_REG(STM32_BTIM_CR1_OFFSET));
|
||||
|
||||
|
||||
putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | ATIM_CCMR1_OC1PE |
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE, TMR_REG(STM32_GTIM_CCMR1_OFFSET));
|
||||
putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE, TMR_REG(STM32_GTIM_CCMR2_OFFSET));
|
||||
putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P |
|
||||
ATIM_CCER_CC2E | ATIM_CCER_CC2P |
|
||||
ATIM_CCER_CC1E | ATIM_CCER_CC1P, TMR_REG(STM32_GTIM_CCER_OFFSET));
|
||||
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE,
|
||||
TMR_REG(STM32_GTIM_CCMR1_OFFSET));
|
||||
putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE,
|
||||
TMR_REG(STM32_GTIM_CCMR2_OFFSET));
|
||||
putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P | ATIM_CCER_CC2E | ATIM_CCER_CC2P | ATIM_CCER_CC1E |
|
||||
ATIM_CCER_CC1P,
|
||||
TMR_REG(STM32_GTIM_CCER_OFFSET));
|
||||
|
||||
stm32_configgpio(GPIO_TIM1_CH1);
|
||||
stm32_configgpio(GPIO_TIM1_CH2);
|
||||
@@ -101,10 +97,10 @@ void rgb_led(int r, int g, int b, int freqs)
|
||||
putreg16(ATIM_BDTR_MOE, (TMR_REG(STM32_ATIM_BDTR_OFFSET)));
|
||||
}
|
||||
|
||||
long p = freqs == 0 ? p1s : p1s / freqs;
|
||||
long p = freqs == 0 ? p1s : p1s / freqs;
|
||||
putreg32(p, TMR_REG(STM32_BTIM_ARR_OFFSET));
|
||||
|
||||
p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
|
||||
p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
|
||||
|
||||
putreg32((r * p) / 255, TMR_REG(STM32_GTIM_CCR1_OFFSET));
|
||||
putreg32((g * p) / 255, TMR_REG(STM32_GTIM_CCR2_OFFSET));
|
||||
@@ -120,5 +116,4 @@ void rgb_led(int r, int g, int b, int freqs)
|
||||
}
|
||||
|
||||
putreg16(val, TMR_REG(STM32_BTIM_CR1_OFFSET));
|
||||
|
||||
}
|
||||
|
||||
@@ -31,14 +31,16 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::SPI1, {
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortB, GPIO::Pin0}, SPI::DRDY{GPIO::PortB, GPIO::Pin1}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI1,
|
||||
{
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortB, GPIO::Pin0},
|
||||
SPI::DRDY{GPIO::PortB, GPIO::Pin1}),
|
||||
}),
|
||||
};
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
|
||||
@@ -40,7 +40,7 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include <stm32.h>
|
||||
@@ -50,19 +50,19 @@
|
||||
* HSE - 8 MHz Crystal
|
||||
* LSE - not installed
|
||||
*/
|
||||
#define STM32_BOARD_USEHSE 1
|
||||
#define STM32_BOARD_XTAL 8000000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_BOARD_USEHSE 1
|
||||
#define STM32_BOARD_XTAL 8000000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
|
||||
/* Main PLL Configuration */
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
|
||||
#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
|
||||
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
@@ -74,76 +74,76 @@
|
||||
#define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
|
||||
|
||||
#define STM32_SYSCLK_FREQUENCY 96000000ul
|
||||
#define STM32_SYSCLK_FREQUENCY 96000000ul
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (96MHz) */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
|
||||
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK (96MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
|
||||
|
||||
/* Timers driven from APB2 will be PCLK2 since no prescale division */
|
||||
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
|
||||
#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Alternate function pin selections ************************************************/
|
||||
|
||||
/* UARTs */
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_3
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_3
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
|
||||
/* CAN */
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_1
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_1
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_1
|
||||
|
||||
/* SPI */
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
|
||||
|
||||
#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
|
||||
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
|
||||
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 /* PB13 */
|
||||
#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
|
||||
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
|
||||
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2 /* PB13 */
|
||||
|
||||
/* I2C */
|
||||
#define GPIO_MCU_I2C1_SCL
|
||||
#define GPIO_MCU_I2C1_SDA
|
||||
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
|
||||
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#endif /* __ARCH_BOARD_BOARD_H */
|
||||
|
||||
@@ -35,10 +35,10 @@
|
||||
|
||||
// DMA1 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX // DMA1, Stream 3, Channel 0
|
||||
#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX // DMA1, Stream 4, Channel 0
|
||||
#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX // DMA1, Stream 3, Channel 0
|
||||
#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX // DMA1, Stream 4, Channel 0
|
||||
|
||||
// DMA2 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_2 // DMA2, Stream 5, Channel 3
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2 // DMA2, Stream 2, Channel 3
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_2 // DMA2, Stream 5, Channel 3
|
||||
|
||||
@@ -39,69 +39,80 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/* CAN Silent mode control */
|
||||
#define GPIO_CAN1_SILENT_S0 /* PC14 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN14)
|
||||
#define GPIO_CAN1_SILENT_S0 /* PC14 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN14)
|
||||
|
||||
/* CAN termination software control */
|
||||
#define GPIO_CAN1_TERMINATION /* PC15 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN15)
|
||||
#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
|
||||
#define GPIO_CAN1_TERMINATION /* PC15 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN15)
|
||||
#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
|
||||
|
||||
/* Boot config */
|
||||
#define GPIO_BOOT_CONFIG /* PH1 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTH|GPIO_PIN1|GPIO_EXTI)
|
||||
#define GPIO_BOOT_CONFIG /* PH1 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTH | GPIO_PIN1 | GPIO_EXTI)
|
||||
|
||||
/* ICM42688p FSYNC */
|
||||
#define GPIO_42688P_FSYNC /* PB8 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8)
|
||||
#define GPIO_42688P_FSYNC /* PB8 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN8)
|
||||
|
||||
/* LEDs are driven with open drain to support Anode to 5V or 3.3V */
|
||||
#define GPIO_TIM1_CH1 /* PA8 */ (GPIO_TIM1_CH1_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH2 /* PA9 */ (GPIO_TIM1_CH2_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH3 /* PA10 */ (GPIO_TIM1_CH3_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH1 /* PA8 */ (GPIO_TIM1_CH1_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH2 /* PA9 */ (GPIO_TIM1_CH2_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
|
||||
#define GPIO_TIM1_CH3 /* PA10 */ (GPIO_TIM1_CH3_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
|
||||
|
||||
/* PWM Outputs */
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 6 // Actually 8
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 6 // Actually 8
|
||||
|
||||
#define GPIO_TIM2_CH1_RESET /* PA0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN0)
|
||||
#define GPIO_TIM2_CH2_RESET /* PA1 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH3_RESET /* PB10 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
|
||||
#define GPIO_TIM3_CH1_RESET /* PB4 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH2_RESET /* PB5 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH3_RESET /* PB0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_TIM3_CH4_RESET /* PB1 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_TIM4_CH4_RESET /* PB7 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_TIM2_CH1_RESET /* PA0 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN0)
|
||||
#define GPIO_TIM2_CH2_RESET /* PA1 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN1)
|
||||
#define GPIO_TIM2_CH3_RESET /* PB10 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN10)
|
||||
#define GPIO_TIM3_CH1_RESET /* PB4 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN4)
|
||||
#define GPIO_TIM3_CH2_RESET /* PB5 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN5)
|
||||
#define GPIO_TIM3_CH3_RESET /* PB0 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN0)
|
||||
#define GPIO_TIM3_CH4_RESET /* PB1 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN1)
|
||||
#define GPIO_TIM4_CH4_RESET /* PB7 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#define GPIO_I2C1_SCL_RESET /* PB6 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_RESET /* PB9 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
|
||||
#define GPIO_I2C1_SCL_RESET /* PB6 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_RESET /* PB9 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN9)
|
||||
|
||||
#define GPIO_USART1_RX_GPIO /* PB3 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
|
||||
#define GPIO_USART1_TX_GPIO /* PA15 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
|
||||
#define GPIO_USART1_RX_GPIO /* PB3 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN3)
|
||||
#define GPIO_USART1_TX_GPIO /* PA15 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN15)
|
||||
|
||||
#define GPIO_USART2_RX_GPIO /* PA3 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
|
||||
#define GPIO_USART2_TX_GPIO /* PA2 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_USART2_RX_GPIO /* PA3 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN3)
|
||||
#define GPIO_USART2_TX_GPIO /* PA2 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN2)
|
||||
|
||||
#define FLASH_BASED_PARAMS
|
||||
|
||||
/* High-resolution timer */
|
||||
#define HRT_TIMER 8 /* use timer 8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel 1 */
|
||||
#define HRT_TIMER 8 /* use timer 8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel 1 */
|
||||
|
||||
#define PX4_GPIO_INIT_LIST { \
|
||||
GPIO_CAN1_SILENT_S0, \
|
||||
GPIO_CAN1_TERMINATION, \
|
||||
GPIO_42688P_FSYNC, \
|
||||
GPIO_CAN1_TX, \
|
||||
GPIO_CAN1_RX, \
|
||||
GPIO_I2C1_SCL_RESET, \
|
||||
GPIO_I2C1_SDA_RESET, \
|
||||
#define PX4_GPIO_INIT_LIST \
|
||||
{ \
|
||||
GPIO_CAN1_SILENT_S0, GPIO_CAN1_TERMINATION, GPIO_42688P_FSYNC, GPIO_CAN1_TX, GPIO_CAN1_RX, \
|
||||
GPIO_I2C1_SCL_RESET, GPIO_I2C1_SDA_RESET, \
|
||||
}
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
#define BOARD_HAS_N_S_RGB_LED 1
|
||||
#define BOARD_MAX_LEDS BOARD_HAS_N_S_RGB_LED
|
||||
#define BOARD_HAS_N_S_RGB_LED 1
|
||||
#define BOARD_MAX_LEDS BOARD_HAS_N_S_RGB_LED
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
||||
@@ -38,16 +38,15 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_config.h>
|
||||
#include <stdint.h>
|
||||
#include "boot_config.h"
|
||||
#include "board.h"
|
||||
|
||||
#include <debug.h>
|
||||
#include <string.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include "board.h"
|
||||
#include "boot_config.h"
|
||||
#include "led.h"
|
||||
|
||||
/************************************************************************************
|
||||
@@ -60,8 +59,7 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
putreg32(getreg32(STM32_RCC_APB1ENR) | RCC_APB1ENR_CAN1EN, STM32_RCC_APB1ENR);
|
||||
stm32_configgpio(GPIO_CAN1_RX);
|
||||
stm32_configgpio(GPIO_CAN1_TX);
|
||||
@@ -73,7 +71,6 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
#if defined(OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO)
|
||||
stm32_configgpio(GPIO_GETNODEINFO_JUMPER);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
@@ -85,10 +82,7 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void board_deinitialize(void)
|
||||
{
|
||||
putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR);
|
||||
}
|
||||
void board_deinitialize(void) { putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR); }
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_get_product_name
|
||||
@@ -107,8 +101,7 @@ void board_deinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
|
||||
{
|
||||
uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen) {
|
||||
DEBUGASSERT(maxlen > UAVCAN_STRLEN(HW_UAVCAN_NAME));
|
||||
memcpy(product_name, HW_UAVCAN_NAME, UAVCAN_STRLEN(HW_UAVCAN_NAME));
|
||||
return UAVCAN_STRLEN(HW_UAVCAN_NAME);
|
||||
@@ -129,14 +122,13 @@ uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
|
||||
{
|
||||
size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version) {
|
||||
memset(hw_version, 0, sizeof(uavcan_HardwareVersion_t));
|
||||
|
||||
hw_version->major = HW_VERSION_MAJOR;
|
||||
hw_version->minor = HW_VERSION_MINOR;
|
||||
|
||||
return board_get_mfguid(*(mfguid_t *) hw_version->unique_id);
|
||||
return board_get_mfguid(*(mfguid_t *)hw_version->unique_id);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -153,7 +145,8 @@ size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
#define led(n, code, r , g , b, h) {.red = (r),.green = (g), .blue = (b),.hz = (h)}
|
||||
#define led(n, code, r, g, b, h) \
|
||||
{ .red = (r), .green = (g), .blue = (b), .hz = (h) }
|
||||
|
||||
typedef begin_packed_struct struct led_t {
|
||||
uint8_t red;
|
||||
@@ -162,27 +155,23 @@ typedef begin_packed_struct struct led_t {
|
||||
uint8_t hz;
|
||||
} end_packed_struct led_t;
|
||||
|
||||
static const led_t i2l[] = {
|
||||
static const led_t i2l[] = {
|
||||
|
||||
led(0, off, 0, 0, 0, 0),
|
||||
led(1, reset, 128, 128, 128, 30),
|
||||
led(2, autobaud_start, 0, 128, 0, 1),
|
||||
led(3, autobaud_end, 0, 128, 0, 2),
|
||||
led(4, allocation_start, 0, 0, 64, 2),
|
||||
led(5, allocation_end, 0, 128, 64, 3),
|
||||
led(6, fw_update_start, 32, 128, 64, 3),
|
||||
led(7, fw_update_erase_fail, 32, 128, 32, 3),
|
||||
led(8, fw_update_invalid_response, 64, 0, 0, 1),
|
||||
led(9, fw_update_timeout, 64, 0, 0, 2),
|
||||
led(a, fw_update_invalid_crc, 64, 0, 0, 4),
|
||||
led(b, jump_to_app, 0, 128, 0, 10),
|
||||
led(0, off, 0, 0, 0, 0),
|
||||
led(1, reset, 128, 128, 128, 30),
|
||||
led(2, autobaud_start, 0, 128, 0, 1),
|
||||
led(3, autobaud_end, 0, 128, 0, 2),
|
||||
led(4, allocation_start, 0, 0, 64, 2),
|
||||
led(5, allocation_end, 0, 128, 64, 3),
|
||||
led(6, fw_update_start, 32, 128, 64, 3),
|
||||
led(7, fw_update_erase_fail, 32, 128, 32, 3),
|
||||
led(8, fw_update_invalid_response, 64, 0, 0, 1),
|
||||
led(9, fw_update_timeout, 64, 0, 0, 2),
|
||||
led(a, fw_update_invalid_crc, 64, 0, 0, 4),
|
||||
led(b, jump_to_app, 0, 128, 0, 10),
|
||||
|
||||
};
|
||||
|
||||
void board_indicate(uiindication_t indication)
|
||||
{
|
||||
rgb_led(i2l[indication].red,
|
||||
i2l[indication].green,
|
||||
i2l[indication].blue,
|
||||
i2l[indication].hz);
|
||||
void board_indicate(uiindication_t indication) {
|
||||
rgb_led(i2l[indication].red, i2l[indication].green, i2l[indication].blue, i2l[indication].hz);
|
||||
}
|
||||
|
||||
@@ -50,13 +50,12 @@
|
||||
* todo:make this be pulled in from a targed's build
|
||||
* files in nuttx*/
|
||||
|
||||
#include <nuttx/compiler.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32_flash.h>
|
||||
|
||||
#include "board_config.h"
|
||||
#include "uavcan.h"
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <stm32_flash.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -64,11 +63,11 @@
|
||||
|
||||
#define OPT_PREFERRED_NODE_ID ANY_NODE_ID
|
||||
|
||||
//todo:wrap OPT_x in in ifdefs for command line definitions
|
||||
#define OPT_TBOOT_MS 5000
|
||||
#define OPT_NODE_STATUS_RATE_MS 800
|
||||
#define OPT_NODE_INFO_RATE_MS 50
|
||||
#define OPT_BL_NUMBER_TIMERS 7
|
||||
// todo:wrap OPT_x in in ifdefs for command line definitions
|
||||
#define OPT_TBOOT_MS 5000
|
||||
#define OPT_NODE_STATUS_RATE_MS 800
|
||||
#define OPT_NODE_INFO_RATE_MS 50
|
||||
#define OPT_BL_NUMBER_TIMERS 7
|
||||
|
||||
/*
|
||||
* This Option set is set to 1 ensure a provider of firmware has an
|
||||
@@ -91,34 +90,33 @@
|
||||
* no 0 1 Not Active
|
||||
*
|
||||
*/
|
||||
#define OPT_WAIT_FOR_GETNODEINFO 0
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
|
||||
#define OPT_WAIT_FOR_GETNODEINFO 0
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
|
||||
#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO_INVERT 0
|
||||
|
||||
#define OPT_ENABLE_WD 1
|
||||
#define OPT_ENABLE_WD 1
|
||||
|
||||
#define OPT_RESTART_TIMEOUT_MS 20000
|
||||
#define OPT_RESTART_TIMEOUT_MS 20000
|
||||
|
||||
/* Reserved for the Booloader */
|
||||
#define OPT_BOOTLOADER_SIZE_IN_K (1024*64)
|
||||
#define OPT_BOOTLOADER_SIZE_IN_K (1024 * 64)
|
||||
|
||||
/* Reserved for the application out of the total
|
||||
* system flash minus the BOOTLOADER_SIZE_IN_K
|
||||
*/
|
||||
#define OPT_APPLICATION_RESERVER_IN_K 0
|
||||
#define OPT_APPLICATION_RESERVER_IN_K 0
|
||||
|
||||
#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
|
||||
#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE-(OPT_BOOTLOADER_SIZE_IN_K+OPT_APPLICATION_RESERVER_IN_K))
|
||||
#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
|
||||
#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE - (OPT_BOOTLOADER_SIZE_IN_K + OPT_APPLICATION_RESERVER_IN_K))
|
||||
|
||||
|
||||
#define FLASH_BASE STM32_FLASH_BASE
|
||||
#define FLASH_SIZE STM32_FLASH_SIZE
|
||||
#define FLASH_BASE STM32_FLASH_BASE
|
||||
#define FLASH_SIZE STM32_FLASH_SIZE
|
||||
|
||||
#define APPLICATION_LOAD_ADDRESS (FLASH_BASE + OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_SIZE (FLASH_SIZE-OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint8_t)))
|
||||
#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint32_t)))
|
||||
#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint64_t)))
|
||||
#define APPLICATION_SIZE (FLASH_SIZE - OPT_APPLICATION_IMAGE_OFFSET)
|
||||
#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint8_t)))
|
||||
#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint32_t)))
|
||||
#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint64_t)))
|
||||
|
||||
/* If this board uses big flash that have large sectors */
|
||||
|
||||
|
||||
@@ -41,20 +41,17 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/can/can.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <errno.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/can/can.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "arm_arch.h"
|
||||
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32.h"
|
||||
#include "stm32_can.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#ifdef CONFIG_CAN
|
||||
|
||||
@@ -64,14 +61,14 @@
|
||||
/* Configuration ********************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
|
||||
# warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
# undef CONFIG_STM32_CAN2
|
||||
#warning "Both CAN1 and CAN2 are enabled. Assuming only CAN1."
|
||||
#undef CONFIG_STM32_CAN2
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_CAN1
|
||||
# define CAN_PORT 1
|
||||
#define CAN_PORT 1
|
||||
#else
|
||||
# define CAN_PORT 2
|
||||
#define CAN_PORT 2
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -92,8 +89,7 @@ int can_devinit(void);
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int can_devinit(void)
|
||||
{
|
||||
int can_devinit(void) {
|
||||
static bool initialized = false;
|
||||
struct can_dev_s *can;
|
||||
int ret;
|
||||
|
||||
@@ -41,39 +41,32 @@
|
||||
* subsystems and perform board-specific initialization.
|
||||
*/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_pwm_output.h>
|
||||
#include <drivers/drv_watchdog.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_arch/io_timer.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/tasks.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include <stm32.h>
|
||||
#include "board_config.h"
|
||||
#include "led.h"
|
||||
#include <stm32_uart.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_watchdog.h>
|
||||
|
||||
#include <string.h>
|
||||
#include <syslog.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include "board_config.h"
|
||||
#include "led.h"
|
||||
|
||||
#include <drivers/drv_pwm_output.h>
|
||||
#include <px4_arch/io_timer.h>
|
||||
|
||||
# if defined(FLASH_BASED_PARAMS)
|
||||
# include <parameters/flashparams/flashfs.h>
|
||||
#if defined(FLASH_BASED_PARAMS)
|
||||
#include <parameters/flashparams/flashfs.h>
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -87,8 +80,7 @@
|
||||
* 0 if just resetting
|
||||
*
|
||||
************************************************************************************/
|
||||
__EXPORT void board_on_reset(int status)
|
||||
{
|
||||
__EXPORT void board_on_reset(int status) {
|
||||
// Configure the GPIO pins to outputs and keep them low.
|
||||
for (int i = 0; i < DIRECT_PWM_OUTPUT_CHANNELS; ++i) {
|
||||
px4_arch_configgpio(io_timer_channel_get_gpio_output(i));
|
||||
@@ -114,8 +106,7 @@ __EXPORT void board_on_reset(int status)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
// Reset all PWM to Low outputs.
|
||||
board_on_reset(-1);
|
||||
|
||||
@@ -154,8 +145,7 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
__EXPORT int board_app_initialize(uintptr_t arg) {
|
||||
px4_platform_init();
|
||||
|
||||
#if defined(SERIAL_HAVE_RXDMA)
|
||||
@@ -178,7 +168,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
syslog(LOG_ERR, "[boot] FAILED to init params in FLASH %d\n", result);
|
||||
}
|
||||
|
||||
#endif // FLASH_BASED_PARAMS
|
||||
#endif // FLASH_BASED_PARAMS
|
||||
|
||||
/* Configure the HW based on the manifest */
|
||||
|
||||
|
||||
@@ -37,30 +37,26 @@
|
||||
* LED backend.
|
||||
*/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "led.h"
|
||||
|
||||
#define TMR_BASE STM32_TIM1_BASE
|
||||
#define TMR_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define TMR_REG(o) (TMR_BASE+(o))
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
void rgb_led(int r, int g, int b, int freqs)
|
||||
{
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
#define TMR_BASE STM32_TIM1_BASE
|
||||
#define TMR_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define TMR_REG(o) (TMR_BASE + (o))
|
||||
|
||||
void rgb_led(int r, int g, int b, int freqs) {
|
||||
long fosc = TMR_FREQUENCY;
|
||||
long prescale = 2048;
|
||||
long p1s = fosc / prescale;
|
||||
long p0p5s = p1s / 2;
|
||||
long p0p5s = p1s / 2;
|
||||
uint16_t val;
|
||||
static bool once = 0;
|
||||
|
||||
@@ -84,14 +80,14 @@ void rgb_led(int r, int g, int b, int freqs)
|
||||
|
||||
putreg16(ATIM_CR1_CEN | ATIM_CR1_ARPE, TMR_REG(STM32_BTIM_CR1_OFFSET));
|
||||
|
||||
|
||||
putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | ATIM_CCMR1_OC1PE |
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE, TMR_REG(STM32_GTIM_CCMR1_OFFSET));
|
||||
putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE, TMR_REG(STM32_GTIM_CCMR2_OFFSET));
|
||||
putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P |
|
||||
ATIM_CCER_CC2E | ATIM_CCER_CC2P |
|
||||
ATIM_CCER_CC1E | ATIM_CCER_CC1P, TMR_REG(STM32_GTIM_CCER_OFFSET));
|
||||
|
||||
(ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE,
|
||||
TMR_REG(STM32_GTIM_CCMR1_OFFSET));
|
||||
putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE,
|
||||
TMR_REG(STM32_GTIM_CCMR2_OFFSET));
|
||||
putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P | ATIM_CCER_CC2E | ATIM_CCER_CC2P | ATIM_CCER_CC1E |
|
||||
ATIM_CCER_CC1P,
|
||||
TMR_REG(STM32_GTIM_CCER_OFFSET));
|
||||
|
||||
stm32_configgpio(GPIO_TIM1_CH1);
|
||||
stm32_configgpio(GPIO_TIM1_CH2);
|
||||
@@ -101,10 +97,10 @@ void rgb_led(int r, int g, int b, int freqs)
|
||||
putreg16(ATIM_BDTR_MOE, (TMR_REG(STM32_ATIM_BDTR_OFFSET)));
|
||||
}
|
||||
|
||||
long p = freqs == 0 ? p1s : p1s / freqs;
|
||||
long p = freqs == 0 ? p1s : p1s / freqs;
|
||||
putreg32(p, TMR_REG(STM32_BTIM_ARR_OFFSET));
|
||||
|
||||
p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
|
||||
p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
|
||||
|
||||
putreg32((r * p) / 255, TMR_REG(STM32_GTIM_CCR1_OFFSET));
|
||||
putreg32((g * p) / 255, TMR_REG(STM32_GTIM_CCR2_OFFSET));
|
||||
@@ -120,5 +116,4 @@ void rgb_led(int r, int g, int b, int freqs)
|
||||
}
|
||||
|
||||
putreg16(val, TMR_REG(STM32_BTIM_CR1_OFFSET));
|
||||
|
||||
}
|
||||
|
||||
@@ -31,18 +31,21 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::SPI1, {
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortA, GPIO::Pin4}, SPI::DRDY{GPIO::PortB, GPIO::Pin2}),
|
||||
}),
|
||||
initSPIBusExternal(SPI::Bus::SPI2, {
|
||||
initSPIConfigExternal(SPI::CS{GPIO::PortB, GPIO::Pin12}),
|
||||
initSPIConfigExternal(SPI::CS{GPIO::PortC, GPIO::Pin13}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI1,
|
||||
{
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortA, GPIO::Pin4},
|
||||
SPI::DRDY{GPIO::PortB, GPIO::Pin2}),
|
||||
}),
|
||||
initSPIBusExternal(SPI::Bus::SPI2,
|
||||
{
|
||||
initSPIConfigExternal(SPI::CS{GPIO::PortB, GPIO::Pin12}),
|
||||
initSPIConfigExternal(SPI::CS{GPIO::PortC, GPIO::Pin13}),
|
||||
}),
|
||||
};
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
|
||||
@@ -34,9 +34,8 @@
|
||||
#include <px4_arch/io_timer_hw_description.h>
|
||||
|
||||
constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
|
||||
initIOTimer(Timer::Timer2),
|
||||
initIOTimer(Timer::Timer3),
|
||||
//initIOTimer(Timer::Timer4),
|
||||
initIOTimer(Timer::Timer2), initIOTimer(Timer::Timer3),
|
||||
// initIOTimer(Timer::Timer4),
|
||||
};
|
||||
|
||||
constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
|
||||
@@ -46,8 +45,8 @@ constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
|
||||
initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel1}, {GPIO::PortB, GPIO::Pin4}),
|
||||
initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel2}, {GPIO::PortB, GPIO::Pin5}),
|
||||
initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel3}, {GPIO::PortB, GPIO::Pin0}),
|
||||
//initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel4}, {GPIO::PortB, GPIO::Pin1}),
|
||||
//initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel2}, {GPIO::PortB, GPIO::Pin7}),
|
||||
// initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel4}, {GPIO::PortB, GPIO::Pin1}),
|
||||
// initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel2}, {GPIO::PortB, GPIO::Pin7}),
|
||||
};
|
||||
|
||||
constexpr io_timers_channel_mapping_t io_timers_channel_mapping =
|
||||
|
||||
@@ -38,12 +38,12 @@
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
#include "board_dma_map.h"
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "board_dma_map.h"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include "stm32_rcc.h"
|
||||
@@ -64,12 +64,12 @@
|
||||
* HSE: 16 MHz crystal for HSE
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 16000000ul
|
||||
#define STM32_BOARD_XTAL 16000000ul
|
||||
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_LSE_FREQUENCY 0
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_LSE_FREQUENCY 0
|
||||
|
||||
/* Main PLL Configuration.
|
||||
*
|
||||
@@ -103,59 +103,57 @@
|
||||
* SYSCLK = 432 MHz / 2 = 216 MHz
|
||||
* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
|
||||
*/
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
|
||||
|
||||
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 216)
|
||||
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
|
||||
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
|
||||
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 216)
|
||||
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
|
||||
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
|
||||
|
||||
/* Configure factors for PLLSAI clock */
|
||||
#define CONFIG_STM32F7_PLLSAI 1
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register */
|
||||
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
|
||||
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
|
||||
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
|
||||
|
||||
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
|
||||
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
|
||||
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
|
||||
|
||||
/* Configure factors for PLLI2S clock */
|
||||
#define CONFIG_STM32F7_PLLI2S 1
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register 2 */
|
||||
#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
|
||||
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
|
||||
|
||||
#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
|
||||
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
|
||||
|
||||
/* Several prescalers allow the configuration of the two AHB buses, the
|
||||
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
|
||||
@@ -165,35 +163,35 @@
|
||||
*/
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (216 MHz) */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 4)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 */
|
||||
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
||||
/* Timers driven from APB2 will be twice PCLK2 */
|
||||
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* SDMMC dividers. Note that slower clocking is required when DMA is disabled
|
||||
* in order to avoid RX overrun/TX underrun errors due to delayed responses
|
||||
@@ -209,27 +207,27 @@
|
||||
|
||||
#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
|
||||
|
||||
#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
|
||||
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
|
||||
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32F7_SDMMC_DMA
|
||||
# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#else
|
||||
# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
|
||||
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
|
||||
*/
|
||||
//TODO #warning "Check Freq for 24mHz"
|
||||
// TODO #warning "Check Freq for 24mHz"
|
||||
|
||||
#ifdef CONFIG_STM32F7_SDMMC_DMA
|
||||
# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#else
|
||||
# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
/* FLASH wait states
|
||||
@@ -248,14 +246,14 @@
|
||||
|
||||
/* LED index values for use with board_userled() */
|
||||
|
||||
#define BOARD_LED1 0
|
||||
#define BOARD_LED2 1
|
||||
#define BOARD_LED3 2
|
||||
#define BOARD_NLEDS 3
|
||||
#define BOARD_LED1 0
|
||||
#define BOARD_LED2 1
|
||||
#define BOARD_LED3 2
|
||||
#define BOARD_NLEDS 3
|
||||
|
||||
#define BOARD_LED_RED BOARD_LED1
|
||||
#define BOARD_LED_GREEN BOARD_LED2
|
||||
#define BOARD_LED_BLUE BOARD_LED3
|
||||
#define BOARD_LED_RED BOARD_LED1
|
||||
#define BOARD_LED_GREEN BOARD_LED2
|
||||
#define BOARD_LED_BLUE BOARD_LED3
|
||||
|
||||
/* Thus if the Green LED is statically on, NuttX has successfully booted and
|
||||
* is, apparently, running normally. If the Red LED is flashing at
|
||||
@@ -265,32 +263,32 @@
|
||||
|
||||
/* Alternate function pin selections ************************************************/
|
||||
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
|
||||
#define GPIO_USART2_RTS GPIO_USART2_RTS_2 /* PD4 */
|
||||
#define GPIO_USART2_CTS GPIO_USART2_CTS_2 /* PD3 */
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
|
||||
#define GPIO_USART2_RTS GPIO_USART2_RTS_2 /* PD4 */
|
||||
#define GPIO_USART2_CTS GPIO_USART2_CTS_2 /* PD3 */
|
||||
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
|
||||
#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */
|
||||
#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
|
||||
#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */
|
||||
#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */
|
||||
|
||||
#define GPIO_UART4_RX GPIO_UART4_RX_4 /* PD0 */
|
||||
#define GPIO_UART4_TX GPIO_UART4_TX_4 /* PD1 */
|
||||
#define GPIO_UART4_RX GPIO_UART4_RX_4 /* PD0 */
|
||||
#define GPIO_UART4_TX GPIO_UART4_TX_4 /* PD1 */
|
||||
|
||||
#define GPIO_UART5_RX GPIO_UART5_RX_3 /* PB12 */
|
||||
#define GPIO_UART5_TX GPIO_UART5_TX_3 /* PB13 */
|
||||
#define GPIO_UART5_RX GPIO_UART5_RX_3 /* PB12 */
|
||||
#define GPIO_UART5_TX GPIO_UART5_TX_3 /* PB13 */
|
||||
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */
|
||||
#define GPIO_USART6_RTS GPIO_USART6_RTS_2 /* PG8 */
|
||||
#define GPIO_USART6_CTS GPIO_USART6_CTS_2 /* PG15 */
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */
|
||||
#define GPIO_USART6_RTS GPIO_USART6_RTS_2 /* PG8 */
|
||||
#define GPIO_USART6_CTS GPIO_USART6_CTS_2 /* PG15 */
|
||||
|
||||
#define GPIO_UART7_RX GPIO_UART7_RX_2 /* PF6 */
|
||||
#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE8 */
|
||||
#define GPIO_UART7_RX GPIO_UART7_RX_2 /* PF6 */
|
||||
#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE8 */
|
||||
|
||||
/* USART8: has no remap
|
||||
*
|
||||
@@ -298,23 +296,21 @@
|
||||
* GPIO_UART8_TX PE1[CN11-61]
|
||||
*/
|
||||
|
||||
|
||||
/* SPI */
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_3 /* PD7 */
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_3 /* PG11 */
|
||||
|
||||
#define GPIO_SPI4_MISO GPIO_SPI4_MISO_2 /* PE13 */
|
||||
#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE6 */
|
||||
#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 /* PE2 */
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_3 /* PD7 */
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_3 /* PG11 */
|
||||
|
||||
#define GPIO_SPI4_MISO GPIO_SPI4_MISO_2 /* PE13 */
|
||||
#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE6 */
|
||||
#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 /* PE2 */
|
||||
|
||||
/* I2C */
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 /* PF1 */
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 /* PF0 */
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 /* PF1 */
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 /* PF0 */
|
||||
|
||||
#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2 /* PF14 */
|
||||
#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2 /* PF15 */
|
||||
#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2 /* PF14 */
|
||||
#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2 /* PF15 */
|
||||
|
||||
/* SDMMC1
|
||||
*
|
||||
@@ -329,4 +325,4 @@
|
||||
* GPIO_SDMMC1_NCD PG0
|
||||
*/
|
||||
|
||||
#endif /*__NUTTX_CONFIG_PX4_FMU_V5_INCLUDE_BOARD_H */
|
||||
#endif /*__NUTTX_CONFIG_PX4_FMU_V5_INCLUDE_BOARD_H */
|
||||
|
||||
@@ -34,47 +34,58 @@
|
||||
#pragma once
|
||||
|
||||
/*
|
||||
| DMA1 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
|
||||
| DMA1 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5
|
||||
| Stream 6 | Stream 7 |
|
||||
|------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
|
||||
| Channel 0 | SPI3_RX_1 | SPDIFRX_DT | SPI3_RX_2 | SPI2_RX | SPI2_TX | SPI3_TX_1 | SPDIFRX_CS | SPI3_TX_2 |
|
||||
| Channel 1 | I2C1_RX | I2C3_RX | TIM7_UP_1 | - | TIM7_UP_2 | I2C1_RX_1 | I2C1_TX | I2C1_TX_1 |
|
||||
| Channel 2 | TIM4_CH1 | - | I2C4_RX | TIM4_CH2 | - | I2C4_TX | TIM4_UP | TIM4_CH3 |
|
||||
| Channel 3 | - | TIM2_UP_1 | I2C3_RX_1 | - | I2C3_TX | TIM2_CH1 | TIM2_CH2 | TIM2_UP_2 |
|
||||
| | | TIM2_CH3 | | | | | TIM2_CH4_1 | TIM2_CH4_2 |
|
||||
| Channel 4 | UART5_RX | USART3_RX | UART4_RX | USART3_TX_1 | UART4_TX | USART2_RX | USART2_TX | UART5_TX |
|
||||
| Channel 5 | UART8_TX | UART7_TX | TIM3_CH4 | UART7_RX | TIM3_CH1 | TIM3_CH2 | UART8_RX | TIM3_CH3 |
|
||||
| | | | TIM3_UP | | TIM3_TRIG | | | |
|
||||
| Channel 6 | TIM5_CH3 | TIM5_CH4_1 | TIM5_CH1 | TIM5_CH4_2 | TIM5_CH2 | - | TIM5_UP_2 | - |
|
||||
| | TIM5_UP_1 | TIM5_TRIG_1 | | TIM5_TRIG_2 | | | | |
|
||||
| Channel 7 | - | TIM6_UP | I2C2_RX | I2C2_RX_1 | USART3_TX_2 | DAC1 | DAC2 | I2C2_TX |
|
||||
| Channel 8 | I2C3_TX_1 | I2C4_RX_1 | - | - | I2C2_TX_1 | - | I2C4_TX_1 | - |
|
||||
| Channel 9 | - | SPI2_RX | - | - | - | - | SPI2_TX | - |
|
||||
| | | | | | | | | |
|
||||
| Usage | UART8_TX | USART3_RX | UART4_RX | USART3_TX_1 | | USART2_RX | UART8_RX | |
|
||||
| Channel 0 | SPI3_RX_1 | SPDIFRX_DT | SPI3_RX_2 | SPI2_RX | SPI2_TX | SPI3_TX_1
|
||||
| SPDIFRX_CS | SPI3_TX_2 | | Channel 1 | I2C1_RX | I2C3_RX | TIM7_UP_1 | - |
|
||||
TIM7_UP_2 | I2C1_RX_1 | I2C1_TX | I2C1_TX_1 | | Channel 2 | TIM4_CH1 | - |
|
||||
I2C4_RX | TIM4_CH2 | - | I2C4_TX | TIM4_UP | TIM4_CH3 | |
|
||||
Channel 3 | - | TIM2_UP_1 | I2C3_RX_1 | - | I2C3_TX | TIM2_CH1 |
|
||||
TIM2_CH2 | TIM2_UP_2 | | | | TIM2_CH3 | | | | |
|
||||
TIM2_CH4_1 | TIM2_CH4_2 | | Channel 4 | UART5_RX | USART3_RX | UART4_RX | USART3_TX_1
|
||||
| UART4_TX | USART2_RX | USART2_TX | UART5_TX | | Channel 5 | UART8_TX | UART7_TX
|
||||
| TIM3_CH4 | UART7_RX | TIM3_CH1 | TIM3_CH2 | UART8_RX | TIM3_CH3 | | |
|
||||
| | TIM3_UP | | TIM3_TRIG | | | | |
|
||||
Channel 6 | TIM5_CH3 | TIM5_CH4_1 | TIM5_CH1 | TIM5_CH4_2 | TIM5_CH2 | - |
|
||||
TIM5_UP_2 | - | | | TIM5_UP_1 | TIM5_TRIG_1 | |
|
||||
TIM5_TRIG_2 | | | | | | Channel 7 | - | TIM6_UP
|
||||
| I2C2_RX | I2C2_RX_1 | USART3_TX_2 | DAC1 | DAC2 | I2C2_TX | |
|
||||
Channel 8 | I2C3_TX_1 | I2C4_RX_1 | - | - | I2C2_TX_1 | - |
|
||||
I2C4_TX_1 | - | | Channel 9 | - | SPI2_RX | - | - | - | -
|
||||
| SPI2_TX | - | | | | | | | | | |
|
||||
| | Usage | UART8_TX | USART3_RX | UART4_RX | USART3_TX_1 | |
|
||||
USART2_RX | UART8_RX | |
|
||||
|
||||
|
||||
| DMA2 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
|
||||
| DMA2 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5
|
||||
| Stream 6 | Stream 7 |
|
||||
|------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
|
||||
| Channel 0 | ADC1_1 | SAI1_A | TIM8_CH1_1 | SAI1_A_2 | ADC1_2 | SAI1_B_1 | TIM1_CH1_1 | SAI1_B_2 |
|
||||
| | | | TIM8_CH2_1 | | | | TIM1_CH2_1 | |
|
||||
| | | | TIM8_CH3_1 | | | | TIM1_CH3_1 | |
|
||||
| Channel 1 | - | DCMI_1 | ADC2_1 | ADC2_2 | SAI1_B | SPI6_TX | SPI6_RX | DCMI_2 |
|
||||
| Channel 2 | ADC3_1 | ADC3_2 | - | SPI5_RX_1 | SPI5_TX_1 | CRYP_OUT | CRYP_IN | HASH_IN |
|
||||
| Channel 3 | SPI1_RX_1 | - | SPI1_RX_2 | SPI1_TX_1 | SAI2_A | SPI1_TX_2 | SAI2_B | QUADSPI |
|
||||
| Channel 4 | SPI4_RX_1 | SPI4_TX_1 | USART1_RX_1 | SDMMC1_1 | - | USART1_RX_2 | SDMMC1_2 | USART1_TX |
|
||||
| Channel 5 | - | USART6_RX_1 | USART6_RX_2 | SPI4_RX_2 | SPI4_TX_2 | - | USART6_TX_1 | USART6_TX_2 |
|
||||
| Channel 6 | TIM1_TRIG_1 | TIM1_CH1_2 | TIM1_CH2_2 | TIM1_CH1 | TIM1_CH4 | TIM1_UP | TIM1_CH3_2 | - |
|
||||
| | | | | | TIM1_TRIG_2 | | | |
|
||||
| | | | | | TIM1_COM | | | |
|
||||
| Channel 7 | - | TIM8_UP | TIM8_CH1_2 | TIM8_CH2_2 | TIM8_CH3_2 | SPI5_RX_2 | SPI5_TX_2 | TIM8_CH4 |
|
||||
| | | | | | | | | TIM8_TRIG |
|
||||
| | | | | | | | | TIM8_COM |
|
||||
| Channel 8 | DFSDM1_FLT0_1 | DFSDM1_FLT1_1 | DFSDM1_FLT2_1 | DFSDM1_FLT3_1 | DFSDM1_FLT0_2 | DFSDM1_FLT1_2 | DFSDM1_FLT2_2 | DFSDM1_FLT3_2 |
|
||||
| Channel 9 | JPEG_IN_1 | JPEG_OUT | SPI4_TX_3 | JPEG_IN_2 | JPEG_OUT_2 | SPI5_RX_3 | - | - |
|
||||
| Channel 10 | SAI1_B_3 | SAI2_B_1 | SAI2_A_1 | - | - | - | SAI1_A_3 | - |
|
||||
| Channel 11 | SDMMC2_1 | - | QUADSPI_1 | - | - | SDMMC2_2 | - | - |
|
||||
| | | | | | | | | |
|
||||
| Usage | SPI1_RX_1 | | USART6_RX_2 | SPI1_TX_1 | | TIM1_UP | SDMMC1_2 | |
|
||||
| Channel 0 | ADC1_1 | SAI1_A | TIM8_CH1_1 | SAI1_A_2 | ADC1_2 | SAI1_B_1
|
||||
| TIM1_CH1_1 | SAI1_B_2 | | | | | TIM8_CH2_1 | | | |
|
||||
TIM1_CH2_1 | | | | | | TIM8_CH3_1 | | | |
|
||||
TIM1_CH3_1 | | | Channel 1 | - | DCMI_1 | ADC2_1 | ADC2_2 |
|
||||
SAI1_B | SPI6_TX | SPI6_RX | DCMI_2 | | Channel 2 | ADC3_1 | ADC3_2 | -
|
||||
| SPI5_RX_1 | SPI5_TX_1 | CRYP_OUT | CRYP_IN | HASH_IN | | Channel 3 |
|
||||
SPI1_RX_1 | - | SPI1_RX_2 | SPI1_TX_1 | SAI2_A | SPI1_TX_2 | SAI2_B
|
||||
| QUADSPI | | Channel 4 | SPI4_RX_1 | SPI4_TX_1 | USART1_RX_1 | SDMMC1_1 | - |
|
||||
USART1_RX_2 | SDMMC1_2 | USART1_TX | | Channel 5 | - | USART6_RX_1 |
|
||||
USART6_RX_2 | SPI4_RX_2 | SPI4_TX_2 | - | USART6_TX_1 | USART6_TX_2 | |
|
||||
Channel 6 | TIM1_TRIG_1 | TIM1_CH1_2 | TIM1_CH2_2 | TIM1_CH1 | TIM1_CH4 | TIM1_UP |
|
||||
TIM1_CH3_2 | - | | | | | | |
|
||||
TIM1_TRIG_2 | | | | | | | | | |
|
||||
TIM1_COM | | | | | Channel 7 | - | TIM8_UP |
|
||||
TIM8_CH1_2 | TIM8_CH2_2 | TIM8_CH3_2 | SPI5_RX_2 | SPI5_TX_2 | TIM8_CH4 | | | |
|
||||
| | | | | | TIM8_TRIG | | |
|
||||
| | | | | | |
|
||||
TIM8_COM | | Channel 8 | DFSDM1_FLT0_1 | DFSDM1_FLT1_1 | DFSDM1_FLT2_1 | DFSDM1_FLT3_1 |
|
||||
DFSDM1_FLT0_2 | DFSDM1_FLT1_2 | DFSDM1_FLT2_2 | DFSDM1_FLT3_2 | | Channel 9 | JPEG_IN_1 | JPEG_OUT
|
||||
| SPI4_TX_3 | JPEG_IN_2 | JPEG_OUT_2 | SPI5_RX_3 | - | - | |
|
||||
Channel 10 | SAI1_B_3 | SAI2_B_1 | SAI2_A_1 | - | - | - | SAI1_A_3
|
||||
| - | | Channel 11 | SDMMC2_1 | - | QUADSPI_1 | - | - |
|
||||
SDMMC2_2 | - | - | | | | | | | | | |
|
||||
| | Usage | SPI1_RX_1 | | USART6_RX_2 | SPI1_TX_1 | | TIM1_UP
|
||||
| SDMMC1_2 | |
|
||||
*/
|
||||
|
||||
// DMA1 Channel/Stream Selections
|
||||
@@ -82,18 +93,17 @@
|
||||
// DMAMAP_UART8_TX // DMA1, Stream 0, Channel 5 (PX4IO TX)
|
||||
// DMAMAP_USART3_RX // DMA1, Stream 1, Channel 4 (TELEM2 RX)
|
||||
// DMAMAP_UART4_RX // DMA1, Stream 2, Channel 4 (TELEM4 RX)
|
||||
#define DMAMAP_USART3_TX DMAMAP_USART3_TX_1 // DMA1, Stream 3, Channel 4 (TELEM2 TX)
|
||||
#define DMAMAP_USART3_TX DMAMAP_USART3_TX_1 // DMA1, Stream 3, Channel 4 (TELEM2 TX)
|
||||
// DMAMAP_USART2_RX // DMA1, Stream 5, Channel 4 (TELEM1 RX)
|
||||
// DMAMAP_UART8_RX // DMA1, Stream 6, Channel 5 (PX4IO RX)
|
||||
|
||||
|
||||
// DMA2 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1 // DMA2, Stream 0, Channel 3 (SPI sensors RX)
|
||||
#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1 // DMA2, Stream 0, Channel 3 (SPI sensors RX)
|
||||
// AVAILABLE // DMA2, Stream 1
|
||||
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 // DMA2, Stream 2, Channel 5
|
||||
#define DMAMAP_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI sensors TX)
|
||||
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 // DMA2, Stream 2, Channel 5
|
||||
#define DMAMAP_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI sensors TX)
|
||||
// AVAILABLE // DMA2, Stream 4
|
||||
// DMAMAP_TIM1_UP // DMA2, Stream 5, Channel 6 (DSHOT)
|
||||
#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_2 // DMA2, Stream 6, Channel 4
|
||||
#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_2 // DMA2, Stream 6, Channel 4
|
||||
// AVAILABLE // DMA2, Stream 7
|
||||
|
||||
@@ -43,20 +43,22 @@
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <stm32_gpio.h>
|
||||
|
||||
/* LEDs are driven with push open drain to support Anode to 5V or 3.3V */
|
||||
#define GPIO_nLED_RED /* PB1 */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN1)
|
||||
#define GPIO_nLED_GREEN /* PC6 */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN6)
|
||||
#define GPIO_nLED_BLUE /* PC7 */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN7)
|
||||
#define GPIO_nLED_RED /* PB1 */ \
|
||||
(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1)
|
||||
#define GPIO_nLED_GREEN /* PC6 */ \
|
||||
(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN6)
|
||||
#define GPIO_nLED_BLUE /* PC7 */ \
|
||||
(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN7)
|
||||
|
||||
#define BOARD_HAS_CONTROL_STATUS_LEDS 1
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_STATE_LED LED_BLUE
|
||||
#define BOARD_HAS_CONTROL_STATUS_LEDS 1
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_STATE_LED LED_BLUE
|
||||
|
||||
#define FLASH_BASED_PARAMS
|
||||
#define RAM_BASED_MISSIONS
|
||||
@@ -75,104 +77,102 @@
|
||||
*/
|
||||
|
||||
/* ADC defines to be used in sensors.cpp to read from a particular channel */
|
||||
#define ADC1_CH(n) (n)
|
||||
#define ADC1_GPIO(n) GPIO_ADC1_IN##n
|
||||
#define ADC1_CH(n) (n)
|
||||
#define ADC1_GPIO(n) GPIO_ADC1_IN##n
|
||||
|
||||
/* Define GPIO pins used as ADC N.B. Channel numbers must match below */
|
||||
|
||||
#define PX4_ADC_GPIO \
|
||||
/* PA0 */ ADC1_GPIO(0), \
|
||||
/* PC0 */ ADC1_GPIO(10), \
|
||||
/* PC1 */ ADC1_GPIO(11), \
|
||||
/* PC2 */ ADC1_GPIO(12), \
|
||||
/* PC3 */ ADC1_GPIO(13), \
|
||||
/* PC4 */ ADC1_GPIO(14)
|
||||
#define PX4_ADC_GPIO \
|
||||
/* PA0 */ ADC1_GPIO(0), /* PC0 */ ADC1_GPIO(10), /* PC1 */ ADC1_GPIO(11), /* PC2 */ ADC1_GPIO(12), \
|
||||
/* PC3 */ ADC1_GPIO(13), /* PC4 */ ADC1_GPIO(14)
|
||||
|
||||
/* Define Channel numbers must match above GPIO pin IN(n)*/
|
||||
#define ADC_BATTERY_VOLTAGE_CHANNEL /* PA0 */ ADC1_CH(0)
|
||||
#define ADC_BATTERY_VOLTAGE_CHANNEL /* PA0 */ ADC1_CH(0)
|
||||
#define ADC_BATTERY_CURRENT_CHANNEL 0
|
||||
#define ADC_SCALED_V5_CHANNEL /* PC0 */ ADC1_CH(10)
|
||||
#define ADC_SCALED_VDD_3V3_SENSORS_CHANNEL /* PC1 */ ADC1_CH(11)
|
||||
#define ADC_HW_VER_SENSE_CHANNEL /* PC2 */ ADC1_CH(12)
|
||||
#define ADC_HW_REV_SENSE_CHANNEL /* PC3 */ ADC1_CH(13)
|
||||
#define ADC1_SPARE_1_CHANNEL /* PC4 */ ADC1_CH(14) // POWER_AD
|
||||
#define ADC_SCALED_V5_CHANNEL /* PC0 */ ADC1_CH(10)
|
||||
#define ADC_SCALED_VDD_3V3_SENSORS_CHANNEL /* PC1 */ ADC1_CH(11)
|
||||
#define ADC_HW_VER_SENSE_CHANNEL /* PC2 */ ADC1_CH(12)
|
||||
#define ADC_HW_REV_SENSE_CHANNEL /* PC3 */ ADC1_CH(13)
|
||||
#define ADC1_SPARE_1_CHANNEL /* PC4 */ ADC1_CH(14) // POWER_AD
|
||||
|
||||
#define ADC_CHANNELS \
|
||||
((1 << ADC_BATTERY_VOLTAGE_CHANNEL) | \
|
||||
(1 << ADC_SCALED_V5_CHANNEL) | \
|
||||
(1 << ADC_SCALED_VDD_3V3_SENSORS_CHANNEL) | \
|
||||
(1 << ADC_HW_VER_SENSE_CHANNEL) | \
|
||||
(1 << ADC_HW_REV_SENSE_CHANNEL) | \
|
||||
(1 << ADC1_SPARE_1_CHANNEL))
|
||||
#define ADC_CHANNELS \
|
||||
((1 << ADC_BATTERY_VOLTAGE_CHANNEL) | (1 << ADC_SCALED_V5_CHANNEL) | \
|
||||
(1 << ADC_SCALED_VDD_3V3_SENSORS_CHANNEL) | (1 << ADC_HW_VER_SENSE_CHANNEL) | \
|
||||
(1 << ADC_HW_REV_SENSE_CHANNEL) | (1 << ADC1_SPARE_1_CHANNEL))
|
||||
|
||||
/* HW has to large of R termination on ADC todo:change when HW value is chosen */
|
||||
#define BOARD_ADC_OPEN_CIRCUIT_V (5.6f)
|
||||
#define BOARD_ADC_OPEN_CIRCUIT_V (5.6f)
|
||||
|
||||
/* HW Version and Revision drive signals Default to 1 to detect */
|
||||
#define BOARD_HAS_HW_VERSIONING
|
||||
|
||||
#define GPIO_HW_REV_DRIVE /* PH14 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTH|GPIO_PIN14)
|
||||
#define GPIO_HW_REV_SENSE /* PC3 */ ADC1_GPIO(13)
|
||||
#define GPIO_HW_VER_DRIVE /* PG0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN0)
|
||||
#define GPIO_HW_VER_SENSE /* PC2 */ ADC1_GPIO(12)
|
||||
#define HW_INFO_INIT {'V','5','x', 'x',0}
|
||||
#define HW_INFO_INIT_VER 2
|
||||
#define HW_INFO_INIT_REV 3
|
||||
#define GPIO_HW_REV_DRIVE /* PH14 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN14)
|
||||
#define GPIO_HW_REV_SENSE /* PC3 */ ADC1_GPIO(13)
|
||||
#define GPIO_HW_VER_DRIVE /* PG0 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTG | GPIO_PIN0)
|
||||
#define GPIO_HW_VER_SENSE /* PC2 */ ADC1_GPIO(12)
|
||||
#define HW_INFO_INIT \
|
||||
{ 'V', '5', 'x', 'x', 0 }
|
||||
#define HW_INFO_INIT_VER 2
|
||||
#define HW_INFO_INIT_REV 3
|
||||
|
||||
#define BOARD_TAP_ESC_MODE 2 // select closed-loop control mode for the esc
|
||||
#define BOARD_TAP_ESC_MODE 2 // select closed-loop control mode for the esc
|
||||
// #define BOARD_USE_ESC_CURRENT_REPORT
|
||||
|
||||
// LED mapping
|
||||
#define BOARD_FRONT_LED_MASK (1 << 0) | (1 << 3)
|
||||
#define BOARD_REAR_LED_MASK (1 << 1) | (1 << 2)
|
||||
#define BOARD_REAR_LED_MASK (1 << 1) | (1 << 2)
|
||||
|
||||
/* HEATER */
|
||||
#define GPIO_HEATER_OUTPUT /* PA7 T14CH1 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7)
|
||||
#define GPIO_HEATER_OUTPUT /* PA7 T14CH1 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN7)
|
||||
|
||||
#define BOARD_HAS_LED_PWM 1
|
||||
#define BOARD_HAS_LED_PWM 1
|
||||
#define BOARD_LED_PWM_DRIVE_ACTIVE_LOW 1
|
||||
|
||||
#define BOARD_UI_LED_PWM_DRIVE_ACTIVE_LOW 1
|
||||
|
||||
#define BOARD_ADC_BRICK_VALID 1
|
||||
#define BOARD_NUMBER_BRICKS 1
|
||||
#define BOARD_ADC_BRICK_VALID 1
|
||||
#define BOARD_NUMBER_BRICKS 1
|
||||
|
||||
#define GPIO_VDD_3V3_SD_CARD_EN /* PG7 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTG|GPIO_PIN7)
|
||||
#define VDD_3V3_SD_CARD_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SD_CARD_EN, (on_true))
|
||||
#define GPIO_VDD_3V3_SD_CARD_EN /* PG7 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTG | GPIO_PIN7)
|
||||
#define VDD_3V3_SD_CARD_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SD_CARD_EN, (on_true))
|
||||
|
||||
/* USB OTG FS */
|
||||
#define GPIO_OTGFS_VBUS /* PA9 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_OTGFS_VBUS /* PA9 */ (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_100MHz | GPIO_PORTA | GPIO_PIN9)
|
||||
|
||||
/* High-resolution timer */
|
||||
#define HRT_TIMER 8 /* use timer8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 3 /* use capture/compare channel 3 */
|
||||
#define HRT_TIMER 8 /* use timer8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 3 /* use capture/compare channel 3 */
|
||||
|
||||
/* RC Serial port */
|
||||
#define RC_SERIAL_PORT "/dev/ttyS5"
|
||||
#define RC_SERIAL_PORT "/dev/ttyS5"
|
||||
#define RC_SERIAL_SINGLEWIRE
|
||||
|
||||
/* power on/off */
|
||||
#define MS_PWR_BUTTON_DOWN 750
|
||||
#define KEY_AD_GPIO (GPIO_INPUT|GPIO_PULLUP|GPIO_EXTI|GPIO_PORTC|GPIO_PIN4)
|
||||
#define POWER_ON_GPIO (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5)
|
||||
#define POWER_OFF_GPIO (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTC|GPIO_PIN5)
|
||||
#define POWER_CHECK_GPIO (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTF|GPIO_PIN0)
|
||||
#define KEY_AD_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_EXTI | GPIO_PORTC | GPIO_PIN4)
|
||||
#define POWER_ON_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN5)
|
||||
#define POWER_OFF_GPIO (GPIO_INPUT | GPIO_PULLDOWN | GPIO_PORTC | GPIO_PIN5)
|
||||
#define POWER_CHECK_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTF | GPIO_PIN0)
|
||||
|
||||
#define SDIO_SLOTNO 0 /* Only one slot */
|
||||
#define SDIO_MINOR 0
|
||||
#define SDIO_SLOTNO 0 /* Only one slot */
|
||||
#define SDIO_MINOR 0
|
||||
|
||||
/* By Providing BOARD_ADC_USB_CONNECTED (using the px4_arch abstraction)
|
||||
* this board support the ADC system_power interface, and therefore
|
||||
* provides the true logic GPIO BOARD_ADC_xxxx macros.
|
||||
*/
|
||||
#define BOARD_ADC_USB_CONNECTED (px4_arch_gpioread(GPIO_OTGFS_VBUS))
|
||||
#define BOARD_ADC_USB_VALID BOARD_ADC_USB_CONNECTED
|
||||
#define BOARD_ADC_USB_VALID BOARD_ADC_USB_CONNECTED
|
||||
|
||||
/* FMUv5 never powers odd the Servo rail */
|
||||
#define BOARD_ADC_SERVO_VALID (1)
|
||||
#define BOARD_ADC_SERVO_VALID (1)
|
||||
|
||||
#define BOARD_ADC_BRICK1_VALID (!px4_arch_gpioread(GPIO_nVDD_BRICK1_VALID))
|
||||
#define BOARD_ADC_BRICK2_VALID (0)
|
||||
#define BOARD_ADC_BRICK1_VALID (!px4_arch_gpioread(GPIO_nVDD_BRICK1_VALID))
|
||||
#define BOARD_ADC_BRICK2_VALID (0)
|
||||
|
||||
/* This board provides a DMA pool and APIs */
|
||||
#define BOARD_DMA_ALLOC_POOL_SIZE 5120
|
||||
@@ -181,16 +181,15 @@
|
||||
#define BOARD_HAS_ON_RESET 1
|
||||
#define BOARD_HAS_POWER_CONTROL 1
|
||||
|
||||
#define GPIO_CAM_PWR_ON_H /* PB0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_CAM_PWR_ON_L /* PB0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0)
|
||||
#define GPIO_CAM_PWR_ON_H /* PB0 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0)
|
||||
#define GPIO_CAM_PWR_ON_L /* PB0 */ \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN0)
|
||||
|
||||
#define PX4_GPIO_INIT_LIST { \
|
||||
PX4_ADC_GPIO, \
|
||||
GPIO_HW_REV_DRIVE, \
|
||||
GPIO_HW_VER_DRIVE, \
|
||||
GPIO_HEATER_OUTPUT, \
|
||||
GPIO_VDD_3V3_SD_CARD_EN, \
|
||||
GPIO_OTGFS_VBUS \
|
||||
#define PX4_GPIO_INIT_LIST \
|
||||
{ \
|
||||
PX4_ADC_GPIO, GPIO_HW_REV_DRIVE, GPIO_HW_VER_DRIVE, GPIO_HEATER_OUTPUT, GPIO_VDD_3V3_SD_CARD_EN, \
|
||||
GPIO_OTGFS_VBUS \
|
||||
}
|
||||
|
||||
#define BOARD_ENABLE_CONSOLE_BUFFER
|
||||
|
||||
@@ -45,43 +45,42 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "board_config.h"
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/mm/gran.h>
|
||||
#include <chip.h>
|
||||
#include <stm32_uart.h>
|
||||
#include <arch/board/board.h>
|
||||
#include "arm_internal.h"
|
||||
|
||||
#include <px4_arch/io_timer.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <chip.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/mm/gran.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/io_timer.h>
|
||||
#include <px4_platform/board_determine_hw_info.h>
|
||||
#include <px4_platform/board_dma_alloc.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <stm32_uart.h>
|
||||
#include <string.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
|
||||
# if defined(FLASH_BASED_PARAMS)
|
||||
# include <parameters/flashparams/flashfs.h>
|
||||
#include "arm_internal.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#if defined(FLASH_BASED_PARAMS)
|
||||
#include <parameters/flashparams/flashfs.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
****************************************************************************/
|
||||
#define _GPIO_PULL_DOWN_INPUT(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz))
|
||||
#define _GPIO_PULL_DOWN_INPUT(def) \
|
||||
(((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz))
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
@@ -109,8 +108,7 @@ __END_DECLS
|
||||
* Not used
|
||||
*
|
||||
************************************************************************************/
|
||||
static void cam_pwr_on_pulse(void)
|
||||
{
|
||||
static void cam_pwr_on_pulse(void) {
|
||||
static bool pwr_on_flag = false;
|
||||
|
||||
if (pwr_on_flag == false) {
|
||||
@@ -130,9 +128,7 @@ static void cam_pwr_on_pulse(void)
|
||||
* Description:
|
||||
*
|
||||
************************************************************************************/
|
||||
__EXPORT void board_peripheral_reset(int ms)
|
||||
{
|
||||
}
|
||||
__EXPORT void board_peripheral_reset(int ms) {}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: board_on_reset
|
||||
@@ -145,9 +141,7 @@ __EXPORT void board_peripheral_reset(int ms)
|
||||
* 0 if just resetting
|
||||
*
|
||||
************************************************************************************/
|
||||
__EXPORT void board_on_reset(int status)
|
||||
{
|
||||
}
|
||||
__EXPORT void board_on_reset(int status) {}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_boardinitialize
|
||||
@@ -159,8 +153,7 @@ __EXPORT void board_on_reset(int status)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
/* Hold power state */
|
||||
board_pwr_init(0);
|
||||
|
||||
@@ -195,8 +188,7 @@ __EXPORT void stm32_boardinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
__EXPORT int board_app_initialize(uintptr_t arg) {
|
||||
/* Power on Interfaces */
|
||||
VDD_3V3_SD_CARD_EN(true);
|
||||
|
||||
@@ -230,7 +222,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
/* initial LED state */
|
||||
drv_led_start();
|
||||
led_off(LED_RED);
|
||||
led_on(LED_GREEN); // Indicate Power.
|
||||
led_on(LED_GREEN); // Indicate Power.
|
||||
led_off(LED_BLUE);
|
||||
|
||||
if (board_hardfault_init(2, true) != 0) {
|
||||
|
||||
@@ -37,16 +37,14 @@
|
||||
* PX4FMU LED backend.
|
||||
*/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
/*
|
||||
* Ideally we'd be able to get these from arm_internal.h,
|
||||
@@ -64,41 +62,29 @@ __END_DECLS
|
||||
|
||||
#define xlat(p) (p)
|
||||
static uint32_t g_ledmap[] = {
|
||||
GPIO_nLED_BLUE, // Indexed by LED_BLUE
|
||||
GPIO_nLED_RED, // Indexed by LED_RED, LED_AMBER
|
||||
GPIO_nLED_GREEN, // Indexed by LED_GREEN
|
||||
GPIO_nLED_BLUE, // Indexed by LED_BLUE
|
||||
GPIO_nLED_RED, // Indexed by LED_RED, LED_AMBER
|
||||
GPIO_nLED_GREEN, // Indexed by LED_GREEN
|
||||
};
|
||||
|
||||
__EXPORT void led_init(void)
|
||||
{
|
||||
__EXPORT void led_init(void) {
|
||||
for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
|
||||
stm32_configgpio(g_ledmap[l]);
|
||||
}
|
||||
}
|
||||
|
||||
static void phy_set_led(int led, bool state)
|
||||
{
|
||||
static void phy_set_led(int led, bool state) {
|
||||
/* Drive Low to switch on */
|
||||
stm32_gpiowrite(g_ledmap[led], !state);
|
||||
}
|
||||
|
||||
static bool phy_get_led(int led)
|
||||
{
|
||||
static bool phy_get_led(int led) {
|
||||
/* If Low it is on */
|
||||
return !stm32_gpioread(g_ledmap[led]);
|
||||
}
|
||||
|
||||
__EXPORT void led_on(int led)
|
||||
{
|
||||
phy_set_led(xlat(led), true);
|
||||
}
|
||||
__EXPORT void led_on(int led) { phy_set_led(xlat(led), true); }
|
||||
|
||||
__EXPORT void led_off(int led)
|
||||
{
|
||||
phy_set_led(xlat(led), false);
|
||||
}
|
||||
__EXPORT void led_off(int led) { phy_set_led(xlat(led), false); }
|
||||
|
||||
__EXPORT void led_toggle(int led)
|
||||
{
|
||||
phy_set_led(xlat(led), !phy_get_led(xlat(led)));
|
||||
}
|
||||
__EXPORT void led_toggle(int led) { phy_set_led(xlat(led), !phy_get_led(xlat(led))); }
|
||||
|
||||
@@ -42,36 +42,31 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <time.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <arm_arch.h>
|
||||
#include <debug.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32_pwr.h>
|
||||
#include <time.h>
|
||||
#include <uORB/uORB.h>
|
||||
|
||||
#include <uORB/Publication.hpp>
|
||||
|
||||
#include <arm_arch.h>
|
||||
#include "board_config.h"
|
||||
#include <stm32_pwr.h>
|
||||
|
||||
extern void led_on(int led);
|
||||
extern void led_off(int led);
|
||||
|
||||
static struct timespec time_down;
|
||||
|
||||
|
||||
static int default_power_button_state_notification(board_power_button_state_notification_e request)
|
||||
{
|
||||
// syslog(0,"%d\n", request);
|
||||
static int default_power_button_state_notification(board_power_button_state_notification_e request) {
|
||||
// syslog(0,"%d\n", request);
|
||||
return PWR_BUTTON_RESPONSE_SHUT_DOWN_NOW;
|
||||
}
|
||||
|
||||
|
||||
static power_button_state_notification_t power_state_notification = default_power_button_state_notification;
|
||||
|
||||
/****************************************************************************
|
||||
@@ -82,13 +77,9 @@ static power_button_state_notification_t power_state_notification = default_powe
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static bool board_pwr_button_down(void)
|
||||
{
|
||||
return 0 == stm32_gpioread(KEY_AD_GPIO);
|
||||
}
|
||||
static bool board_pwr_button_down(void) { return 0 == stm32_gpioread(KEY_AD_GPIO); }
|
||||
|
||||
int board_register_power_state_notification_cb(power_button_state_notification_t cb)
|
||||
{
|
||||
int board_register_power_state_notification_cb(power_button_state_notification_t cb) {
|
||||
power_state_notification = cb;
|
||||
|
||||
if (board_pwr_button_down() && (time_down.tv_nsec != 0 || time_down.tv_sec != 0)) {
|
||||
@@ -99,8 +90,7 @@ int board_register_power_state_notification_cb(power_button_state_notification_t
|
||||
return OK;
|
||||
}
|
||||
|
||||
int board_power_off(int status)
|
||||
{
|
||||
int board_power_off(int status) {
|
||||
led_on(BOARD_LED_BLUE);
|
||||
|
||||
// disable the interrups
|
||||
@@ -108,15 +98,14 @@ int board_power_off(int status)
|
||||
|
||||
stm32_configgpio(POWER_OFF_GPIO);
|
||||
|
||||
while (1);
|
||||
while (1)
|
||||
;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int board_button_irq(int irq, FAR void *context, FAR void *args)
|
||||
{
|
||||
static int board_button_irq(int irq, FAR void *context, FAR void *args) {
|
||||
if (board_pwr_button_down()) {
|
||||
|
||||
led_on(BOARD_LED_RED);
|
||||
clock_gettime(CLOCK_REALTIME, &time_down);
|
||||
power_state_notification(PWR_BUTTON_DOWN);
|
||||
@@ -134,10 +123,10 @@ static int board_button_irq(int irq, FAR void *context, FAR void *args)
|
||||
uint64_t tnow_ms = now.tv_sec * 1000 + now.tv_nsec / 1000000;
|
||||
|
||||
if (tdown_ms != 0 && (tnow_ms - tdown_ms) >= MS_PWR_BUTTON_DOWN) {
|
||||
|
||||
led_on(BOARD_LED_BLUE);
|
||||
|
||||
if (power_state_notification(PWR_BUTTON_REQUEST_SHUT_DOWN) == PWR_BUTTON_RESPONSE_SHUT_DOWN_NOW) {
|
||||
if (power_state_notification(PWR_BUTTON_REQUEST_SHUT_DOWN) ==
|
||||
PWR_BUTTON_RESPONSE_SHUT_DOWN_NOW) {
|
||||
up_mdelay(200);
|
||||
board_power_off(0);
|
||||
}
|
||||
@@ -145,7 +134,6 @@ static int board_button_irq(int irq, FAR void *context, FAR void *args)
|
||||
} else {
|
||||
power_state_notification(PWR_BUTTON_IDEL);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
return OK;
|
||||
@@ -162,8 +150,7 @@ static int board_button_irq(int irq, FAR void *context, FAR void *args)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void board_pwr_init(int stage)
|
||||
{
|
||||
void board_pwr_init(int stage) {
|
||||
if (stage == 0) {
|
||||
stm32_configgpio(POWER_ON_GPIO);
|
||||
stm32_configgpio(KEY_AD_GPIO);
|
||||
|
||||
@@ -36,34 +36,31 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <board_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/sdio.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_sdmmc.h"
|
||||
|
||||
#ifdef CONFIG_MMCSD
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Card detections requires card support and a card detection GPIO */
|
||||
|
||||
#define HAVE_NCD 1
|
||||
#define HAVE_NCD 1
|
||||
#if !defined(GPIO_SDMMC1_NCD)
|
||||
# undef HAVE_NCD
|
||||
#undef HAVE_NCD
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
@@ -88,8 +85,7 @@ static bool g_sd_inserted = 0xff; /* Impossible value */
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_NCD
|
||||
static int stm32_ncd_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
static int stm32_ncd_interrupt(int irq, FAR void *context) {
|
||||
bool present;
|
||||
|
||||
present = !stm32_gpioread(GPIO_SDMMC1_NCD);
|
||||
@@ -115,8 +111,7 @@ static int stm32_ncd_interrupt(int irq, FAR void *context)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_sdio_initialize(void)
|
||||
{
|
||||
int stm32_sdio_initialize(void) {
|
||||
int ret;
|
||||
|
||||
#ifdef HAVE_NCD
|
||||
|
||||
@@ -31,17 +31,19 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::SPI1, {
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM20602, SPI::CS{GPIO::PortF, GPIO::Pin3}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI4, {
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortF, GPIO::Pin10}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI1,
|
||||
{
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ICM20602, SPI::CS{GPIO::PortF, GPIO::Pin3}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI4,
|
||||
{
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortF, GPIO::Pin10}),
|
||||
}),
|
||||
};
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
|
||||
@@ -34,9 +34,9 @@
|
||||
#include <px4_arch/io_timer_hw_description.h>
|
||||
|
||||
constexpr io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
|
||||
# if defined(BOARD_HAS_LED_PWM) && !defined(BOARD_HAS_CONTROL_STATUS_LEDS)
|
||||
#if defined(BOARD_HAS_LED_PWM) && !defined(BOARD_HAS_CONTROL_STATUS_LEDS)
|
||||
initIOTimer(Timer::Timer3),
|
||||
# endif
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Support driving active low (preferred) or active high LED
|
||||
@@ -46,38 +46,37 @@ constexpr io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
|
||||
* if the LED has a 5 Volt supply that the LED will be
|
||||
* off when high.
|
||||
*/
|
||||
#define CCER_C1_NUM_BITS 4
|
||||
#define ACTIVE_LOW(c) (GTIM_CCER_CC1P << (((c)-1) * CCER_C1_NUM_BITS))
|
||||
#define ACTIVE_HIGH(c) 0
|
||||
#define CCER_C1_NUM_BITS 4
|
||||
#define ACTIVE_LOW(c) (GTIM_CCER_CC1P << (((c)-1) * CCER_C1_NUM_BITS))
|
||||
#define ACTIVE_HIGH(c) 0
|
||||
|
||||
#if defined(BOARD_LED_PWM_DRIVE_ACTIVE_LOW)
|
||||
# define POLARITY(c) ACTIVE_LOW(c)
|
||||
# define DRIVE_TYPE(p) ((p)|GPIO_OPENDRAIN)
|
||||
#define POLARITY(c) ACTIVE_LOW(c)
|
||||
#define DRIVE_TYPE(p) ((p) | GPIO_OPENDRAIN)
|
||||
#else
|
||||
# define POLARITY(c) ACTIVE_HIGH((c))
|
||||
# define DRIVE_TYPE(p) (p)
|
||||
#define POLARITY(c) ACTIVE_HIGH((c))
|
||||
#define DRIVE_TYPE(p) (p)
|
||||
#endif
|
||||
|
||||
#if defined(BOARD_UI_LED_PWM_DRIVE_ACTIVE_LOW)
|
||||
# define UI_POLARITY(c) ACTIVE_LOW(c)
|
||||
# define UI_DRIVE_TYPE(p) ((p)|GPIO_OPENDRAIN)
|
||||
#define UI_POLARITY(c) ACTIVE_LOW(c)
|
||||
#define UI_DRIVE_TYPE(p) ((p) | GPIO_OPENDRAIN)
|
||||
#else
|
||||
# define UI_POLARITY(c) ACTIVE_HIGH((c))
|
||||
# define UI_DRIVE_TYPE(p) (p)
|
||||
#define UI_POLARITY(c) ACTIVE_HIGH((c))
|
||||
#define UI_DRIVE_TYPE(p) (p)
|
||||
#endif
|
||||
|
||||
static inline constexpr timer_io_channels_t initIOTimerChannelUILED(const io_timers_t io_timers_conf[MAX_LED_TIMERS],
|
||||
Timer::TimerChannel timer, GPIO::GPIOPin pin, int ui_polarity)
|
||||
{
|
||||
Timer::TimerChannel timer, GPIO::GPIOPin pin,
|
||||
int ui_polarity) {
|
||||
timer_io_channels_t ret = initIOTimerChannel(io_timers_conf, timer, pin);
|
||||
ret.gpio_out = UI_DRIVE_TYPE(ret.gpio_out);
|
||||
ret.masks = UI_POLARITY(ui_polarity);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline constexpr timer_io_channels_t initIOTimerChannelControlLED(const io_timers_t
|
||||
io_timers_conf[MAX_LED_TIMERS], Timer::TimerChannel timer, GPIO::GPIOPin pin, int polarity)
|
||||
{
|
||||
static inline constexpr timer_io_channels_t initIOTimerChannelControlLED(
|
||||
const io_timers_t io_timers_conf[MAX_LED_TIMERS], Timer::TimerChannel timer, GPIO::GPIOPin pin, int polarity) {
|
||||
timer_io_channels_t ret = initIOTimerChannel(io_timers_conf, timer, pin);
|
||||
ret.gpio_out = DRIVE_TYPE(ret.gpio_out);
|
||||
ret.masks = POLARITY(polarity);
|
||||
@@ -85,9 +84,9 @@ static inline constexpr timer_io_channels_t initIOTimerChannelControlLED(const i
|
||||
}
|
||||
|
||||
constexpr timer_io_channels_t led_pwm_channels[MAX_TIMER_LED_CHANNELS] = {
|
||||
# if defined(BOARD_HAS_LED_PWM) && !defined(BOARD_HAS_CONTROL_STATUS_LEDS)
|
||||
#if defined(BOARD_HAS_LED_PWM) && !defined(BOARD_HAS_CONTROL_STATUS_LEDS)
|
||||
initIOTimerChannelControlLED(led_pwm_timers, {Timer::Timer3, Timer::Channel4}, {GPIO::PortB, GPIO::Pin1}, 4),
|
||||
initIOTimerChannelControlLED(led_pwm_timers, {Timer::Timer3, Timer::Channel1}, {GPIO::PortC, GPIO::Pin6}, 1),
|
||||
initIOTimerChannelControlLED(led_pwm_timers, {Timer::Timer3, Timer::Channel2}, {GPIO::PortC, GPIO::Pin7}, 2),
|
||||
# endif
|
||||
#endif
|
||||
};
|
||||
|
||||
@@ -37,13 +37,14 @@
|
||||
* Board-specific USB functions.
|
||||
*/
|
||||
|
||||
#include "board_config.h"
|
||||
#include <debug.h>
|
||||
#include <nuttx/usb/usbdev.h>
|
||||
#include <nuttx/usb/usbdev_trace.h>
|
||||
#include <stm32_otg.h>
|
||||
#include <debug.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include "board_config.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_usbsuspend
|
||||
*
|
||||
@@ -54,7 +55,4 @@
|
||||
* while the USB is suspended.
|
||||
*
|
||||
************************************************************************************/
|
||||
__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
|
||||
{
|
||||
uinfo("resume: %d\n", resume);
|
||||
}
|
||||
__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); }
|
||||
|
||||
@@ -37,12 +37,12 @@
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
#include "board_dma_map.h"
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "board_dma_map.h"
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include "stm32_rcc.h"
|
||||
@@ -65,12 +65,12 @@
|
||||
* HSE: 16 MHz crystal for HSE
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 16000000ul
|
||||
#define STM32_BOARD_XTAL 16000000ul
|
||||
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_LSE_FREQUENCY 0
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_LSE_FREQUENCY 0
|
||||
|
||||
/* Main PLL Configuration.
|
||||
*
|
||||
@@ -104,64 +104,61 @@
|
||||
* SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
|
||||
*/
|
||||
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
|
||||
|
||||
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 216)
|
||||
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
|
||||
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
|
||||
#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 216)
|
||||
#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
|
||||
#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
|
||||
|
||||
/* Configure factors for PLLSAI clock */
|
||||
|
||||
#define CONFIG_STM32F7_PLLSAI 1
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
|
||||
#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register */
|
||||
|
||||
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
|
||||
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
|
||||
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
|
||||
|
||||
|
||||
#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
|
||||
#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
|
||||
#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
|
||||
#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
|
||||
#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
|
||||
|
||||
/* Configure factors for PLLI2S clock */
|
||||
|
||||
#define CONFIG_STM32F7_PLLI2S 1
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
|
||||
#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
|
||||
|
||||
/* Configure Dedicated Clock Configuration Register 2 */
|
||||
|
||||
#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
|
||||
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
|
||||
|
||||
#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
|
||||
#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
|
||||
#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
|
||||
#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
|
||||
#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
|
||||
|
||||
/* Several prescalers allow the configuration of the two AHB buses, the
|
||||
* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
|
||||
@@ -172,39 +169,39 @@
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (216 MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 4)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 */
|
||||
|
||||
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
||||
/* Timers driven from APB2 will be twice PCLK2 */
|
||||
|
||||
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* SDMMC dividers. Note that slower clocking is required when DMA is disabled
|
||||
* in order to avoid RX overrun/TX underrun errors due to delayed responses
|
||||
@@ -220,27 +217,27 @@
|
||||
|
||||
#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
|
||||
|
||||
#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
|
||||
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
|
||||
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_STM32F7_SDMMC_DMA
|
||||
# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#else
|
||||
# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
|
||||
* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
|
||||
*/
|
||||
//TODO #warning "Check Freq for 24mHz"
|
||||
// TODO #warning "Check Freq for 24mHz"
|
||||
|
||||
#ifdef CONFIG_STM32F7_SDMMC_DMA
|
||||
# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#else
|
||||
# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
|
||||
#endif
|
||||
|
||||
/* FLASH wait states
|
||||
@@ -259,27 +256,27 @@
|
||||
|
||||
/* Alternate function pin selections ************************************************/
|
||||
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
|
||||
#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
|
||||
#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
|
||||
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
|
||||
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
|
||||
|
||||
#define GPIO_UART4_RX GPIO_UART4_RX_4 /* PD0 */
|
||||
#define GPIO_UART4_TX GPIO_UART4_TX_3 /* PA12 */
|
||||
#define GPIO_UART4_RS485_DIR GPIO_UART4_RTS_2 /* PB14 */
|
||||
#define GPIO_UART4_RX GPIO_UART4_RX_4 /* PD0 */
|
||||
#define GPIO_UART4_TX GPIO_UART4_TX_3 /* PA12 */
|
||||
#define GPIO_UART4_RS485_DIR GPIO_UART4_RTS_2 /* PB14 */
|
||||
|
||||
#define GPIO_UART5_RX GPIO_UART5_RX_4 /* PB8 */
|
||||
#define GPIO_UART5_TX GPIO_UART5_TX_4 /* PB9 */
|
||||
#define GPIO_UART5_RX GPIO_UART5_RX_4 /* PB8 */
|
||||
#define GPIO_UART5_TX GPIO_UART5_TX_4 /* PB9 */
|
||||
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */
|
||||
|
||||
#define GPIO_UART7_RX GPIO_UART7_RX_1 /* PE8 */
|
||||
#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE7 */
|
||||
#define GPIO_UART7_RX GPIO_UART7_RX_1 /* PE8 */
|
||||
#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE7 */
|
||||
|
||||
/* USART8: has no remap
|
||||
*
|
||||
@@ -291,28 +288,28 @@
|
||||
*
|
||||
* CAN1 is routed to transceiver.
|
||||
*/
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_5 /* PI9 */
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */
|
||||
#define GPIO_CAN1_RX GPIO_CAN1_RX_5 /* PI9 */
|
||||
#define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */
|
||||
|
||||
/* SPI
|
||||
* SPI1-SPI4 sensors
|
||||
*/
|
||||
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PB5 */
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */
|
||||
#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
|
||||
#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PB5 */
|
||||
#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1 /* PA5 */
|
||||
|
||||
#define GPIO_SPI2_MISO GPIO_SPI2_MISO_3 /* PI2 */
|
||||
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_3 /* PI3 */
|
||||
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_4 /* PD3 */
|
||||
#define GPIO_SPI2_MISO GPIO_SPI2_MISO_3 /* PI2 */
|
||||
#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_3 /* PI3 */
|
||||
#define GPIO_SPI2_SCK GPIO_SPI2_SCK_4 /* PD3 */
|
||||
|
||||
#define GPIO_SPI4_MISO GPIO_SPI4_MISO_1 /* PE5 */
|
||||
#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE6 */
|
||||
#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 /* PE2 */
|
||||
#define GPIO_SPI4_MISO GPIO_SPI4_MISO_1 /* PE5 */
|
||||
#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE6 */
|
||||
#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 /* PE2 */
|
||||
|
||||
#define GPIO_SPI5_MISO GPIO_SPI5_MISO_1 /* PF8 */
|
||||
#define GPIO_SPI5_MOSI GPIO_SPI5_MOSI_2 /* PF11 */
|
||||
#define GPIO_SPI5_SCK GPIO_SPI5_SCK_2 /* PH6 */
|
||||
#define GPIO_SPI5_MISO GPIO_SPI5_MISO_1 /* PF8 */
|
||||
#define GPIO_SPI5_MOSI GPIO_SPI5_MOSI_2 /* PF11 */
|
||||
#define GPIO_SPI5_SCK GPIO_SPI5_SCK_2 /* PH6 */
|
||||
|
||||
/* The STM32 F7 connects to a SMSC LAN8720A PHY using these pins:
|
||||
*
|
||||
@@ -337,31 +334,31 @@
|
||||
* receive errors can be detected using GPIO pin PD5
|
||||
*/
|
||||
|
||||
#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1
|
||||
#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_1
|
||||
#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1
|
||||
#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1
|
||||
#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_1
|
||||
#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1
|
||||
|
||||
/* I2C Mapping
|
||||
*
|
||||
*/
|
||||
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 /* PF1 */
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 /* PF0 */
|
||||
#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 /* PF1 */
|
||||
#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 /* PF0 */
|
||||
|
||||
#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET |GPIO_PORTF | GPIO_PIN1)
|
||||
#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET |GPIO_PORTF | GPIO_PIN0)
|
||||
#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN1)
|
||||
#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN0)
|
||||
|
||||
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_2 /* PH7 */
|
||||
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_2 /* PH8 */
|
||||
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_2 /* PH7 */
|
||||
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_2 /* PH8 */
|
||||
|
||||
#define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT |GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN7)
|
||||
#define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT |GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN8)
|
||||
#define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN7)
|
||||
#define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN8)
|
||||
|
||||
#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2 /* PF14 */
|
||||
#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2 /* PF15 */
|
||||
#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2 /* PF14 */
|
||||
#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2 /* PF15 */
|
||||
|
||||
#define GPIO_I2C4_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN14)
|
||||
#define GPIO_I2C4_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN15)
|
||||
#define GPIO_I2C4_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN14)
|
||||
#define GPIO_I2C4_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN15)
|
||||
|
||||
/* SDMMC1
|
||||
*
|
||||
@@ -374,4 +371,3 @@
|
||||
* SDMMC1_D2 PC10
|
||||
* SDMMC1_D3 PC11
|
||||
*/
|
||||
|
||||
|
||||
@@ -34,41 +34,51 @@
|
||||
#pragma once
|
||||
|
||||
/*
|
||||
| DMA1 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
|
||||
| DMA1 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5
|
||||
| Stream 6 | Stream 7 |
|
||||
|------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
|
||||
| Channel 0 | SPI3_RX_1 | SPDIFRX_DT | SPI3_RX_2 | SPI2_RX | SPI2_TX | SPI3_TX_1 | SPDIFRX_CS | SPI3_TX_2 |
|
||||
| Channel 1 | I2C1_RX | I2C3_RX | TIM7_UP_1 | - | TIM7_UP_2 | I2C1_RX_1 | I2C1_TX | I2C1_TX_1 |
|
||||
| Channel 2 | TIM4_CH1 | - | I2C4_RX | TIM4_CH2 | - | I2C4_RX | TIM4_UP | TIM4_CH3 |
|
||||
| Channel 3 | - | TIM2_UP_1 | I2C3_RX_1 | - | I2C3_TX | TIM2_CH1 | TIM2_CH2 | TIM2_UP_2 |
|
||||
| | | TIM2_CH3 | | | | | TIM2_CH4_1 | TIM2_CH4_2 |
|
||||
| Channel 4 | UART5_RX | USART3_RX | UART4_RX | USART3_TX_1 | UART4_TX | USART2_RX | USART2_TX | UART5_TX |
|
||||
| Channel 5 | UART8_TX | UART7_TX | TIM3_CH4 | UART7_RX | TIM3_CH1 | TIM3_CH2 | UART8_RX | TIM3_CH3 |
|
||||
| | | | TIM3_UP | | TIM3_TRIG | | | |
|
||||
| Channel 6 | TIM5_CH3 | TIM5_CH4_1 | TIM5_CH1 | TIM5_CH4_2 | TIM5_CH2 | - | TIM5_UP_2 | - |
|
||||
| | TIM5_UP_1 | TIM5_TRIG_1 | | TIM5_TRIG_2 | | | | |
|
||||
| Channel 7 | - | TIM6_UP | I2C2_RX | I2C2_RX_1 | USART3_TX_2 | DAC1 | DAC2 | I2C2_TX |
|
||||
| | | | | | | | | |
|
||||
| Usage | UART5_RX | USART3_RX | | SPI2_RX | SPI2_TX | USART2_RX | UART8_RX | |
|
||||
| Channel 0 | SPI3_RX_1 | SPDIFRX_DT | SPI3_RX_2 | SPI2_RX | SPI2_TX | SPI3_TX_1
|
||||
| SPDIFRX_CS | SPI3_TX_2 | | Channel 1 | I2C1_RX | I2C3_RX | TIM7_UP_1 | - |
|
||||
TIM7_UP_2 | I2C1_RX_1 | I2C1_TX | I2C1_TX_1 | | Channel 2 | TIM4_CH1 | - |
|
||||
I2C4_RX | TIM4_CH2 | - | I2C4_RX | TIM4_UP | TIM4_CH3 | |
|
||||
Channel 3 | - | TIM2_UP_1 | I2C3_RX_1 | - | I2C3_TX | TIM2_CH1 |
|
||||
TIM2_CH2 | TIM2_UP_2 | | | | TIM2_CH3 | | | | |
|
||||
TIM2_CH4_1 | TIM2_CH4_2 | | Channel 4 | UART5_RX | USART3_RX | UART4_RX | USART3_TX_1
|
||||
| UART4_TX | USART2_RX | USART2_TX | UART5_TX | | Channel 5 | UART8_TX | UART7_TX
|
||||
| TIM3_CH4 | UART7_RX | TIM3_CH1 | TIM3_CH2 | UART8_RX | TIM3_CH3 | | |
|
||||
| | TIM3_UP | | TIM3_TRIG | | | | |
|
||||
Channel 6 | TIM5_CH3 | TIM5_CH4_1 | TIM5_CH1 | TIM5_CH4_2 | TIM5_CH2 | - |
|
||||
TIM5_UP_2 | - | | | TIM5_UP_1 | TIM5_TRIG_1 | |
|
||||
TIM5_TRIG_2 | | | | | | Channel 7 | - | TIM6_UP
|
||||
| I2C2_RX | I2C2_RX_1 | USART3_TX_2 | DAC1 | DAC2 | I2C2_TX | | |
|
||||
| | | | | | | | |
|
||||
Usage | UART5_RX | USART3_RX | | SPI2_RX | SPI2_TX | USART2_RX |
|
||||
UART8_RX | |
|
||||
|
||||
|
||||
| DMA2 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5 | Stream 6 | Stream 7 |
|
||||
| DMA2 | Stream 0 | Stream 1 | Stream 2 | Stream 3 | Stream 4 | Stream 5
|
||||
| Stream 6 | Stream 7 |
|
||||
|------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
|
||||
| Channel 0 | ADC1_1 | SAI1_A | TIM8_CH1_1 | SAI1_A_1 | ADC1_2 | SAI1_B_1 | TIM1_CH1_1 | SAI2_B_2 |
|
||||
| | | | TIM8_CH2_1 | | | | TIM1_CH2_1 | |
|
||||
| | | | TIM8_CH3_1 | | | | TIM1_CH3_1 | |
|
||||
| Channel 1 | - | DCMI_1 | ADC2_1 | ADC2_2 | SAI1_B | SPI6_TX | SPI6_RX | DCMI_2 |
|
||||
| Channel 2 | ADC3_1 | ADC3_2 | - | SPI5_RX_1 | SPI5_TX_1 | CRYP_OUT | CRYP_IN | HASH_IN |
|
||||
| Channel 3 | SPI1_RX_1 | - | SPI1_RX_2 | SPI1_TX_1 | SAI2_A | SPI1_TX_2 | SAI2_B | QUADSPI |
|
||||
| Channel 4 | SPI4_RX_1 | SPI4_TX_1 | USART1_RX_1 | SDMMC1_1 | - | USART1_RX_2 | SDMMC1_2 | USART1_TX |
|
||||
| Channel 5 | - | USART6_RX_1 | USART6_RX_2 | SPI4_RX_2 | SPI4_TX_2 | - | USART6_TX_1 | USART6_TX_2 |
|
||||
| Channel 6 | TIM1_TRIG_1 | TIM1_CH1_2 | TIM1_CH2_2 | TIM1_CH1 | TIM1_CH4 | TIM1_UP | TIM1_CH3_2 | - |
|
||||
| | | | | | TIM1_TRIG_2 | | | |
|
||||
| | | | | | TIM1_COM | | | |
|
||||
| Channel 7 | - | TIM8_UP | TIM8_CH1_2 | TIM8_CH2_2 | TIM8_CH3_2 | SPI5_RX_2 | SPI5_TX_2 | TIM8_CH4 |
|
||||
| | | | | | | | | TIM8_TRIG |
|
||||
| | | | | | | | | TIM8_COM |
|
||||
| | | | | | | | | |
|
||||
| Usage | SPI1_RX_1 | | USART6_RX_2 | SPI1_TX_1 | | USART1_RX_2 | SDMMC1_2 | |
|
||||
| Channel 0 | ADC1_1 | SAI1_A | TIM8_CH1_1 | SAI1_A_1 | ADC1_2 | SAI1_B_1
|
||||
| TIM1_CH1_1 | SAI2_B_2 | | | | | TIM8_CH2_1 | | | |
|
||||
TIM1_CH2_1 | | | | | | TIM8_CH3_1 | | | |
|
||||
TIM1_CH3_1 | | | Channel 1 | - | DCMI_1 | ADC2_1 | ADC2_2 |
|
||||
SAI1_B | SPI6_TX | SPI6_RX | DCMI_2 | | Channel 2 | ADC3_1 | ADC3_2 | -
|
||||
| SPI5_RX_1 | SPI5_TX_1 | CRYP_OUT | CRYP_IN | HASH_IN | | Channel 3 |
|
||||
SPI1_RX_1 | - | SPI1_RX_2 | SPI1_TX_1 | SAI2_A | SPI1_TX_2 | SAI2_B
|
||||
| QUADSPI | | Channel 4 | SPI4_RX_1 | SPI4_TX_1 | USART1_RX_1 | SDMMC1_1 | - |
|
||||
USART1_RX_2 | SDMMC1_2 | USART1_TX | | Channel 5 | - | USART6_RX_1 |
|
||||
USART6_RX_2 | SPI4_RX_2 | SPI4_TX_2 | - | USART6_TX_1 | USART6_TX_2 | |
|
||||
Channel 6 | TIM1_TRIG_1 | TIM1_CH1_2 | TIM1_CH2_2 | TIM1_CH1 | TIM1_CH4 | TIM1_UP |
|
||||
TIM1_CH3_2 | - | | | | | | |
|
||||
TIM1_TRIG_2 | | | | | | | | | |
|
||||
TIM1_COM | | | | | Channel 7 | - | TIM8_UP |
|
||||
TIM8_CH1_2 | TIM8_CH2_2 | TIM8_CH3_2 | SPI5_RX_2 | SPI5_TX_2 | TIM8_CH4 | | | |
|
||||
| | | | | | TIM8_TRIG | | |
|
||||
| | | | | | |
|
||||
TIM8_COM | | | | | | | | | | | |
|
||||
Usage | SPI1_RX_1 | | USART6_RX_2 | SPI1_TX_1 | | USART1_RX_2
|
||||
| SDMMC1_2 | |
|
||||
*/
|
||||
|
||||
// DMA1 Channel/Stream Selections
|
||||
@@ -76,17 +86,17 @@
|
||||
// DMAMAP_UART5_RX // DMA1, Stream 0, Channel 4
|
||||
// DMAMAP_USART3_RX // DMA1, Stream 1, Channel 4
|
||||
// AVAILABLE // DMA1, Stream 2, Channel 4
|
||||
#define DMAMAP_SPI2_RX DMAMAP_SPI2_RX_2 // DMA1, Stream 3, Channel 0 (SPI2 RX)
|
||||
#define DMAMAP_SPI2_TX DMAMAP_SPI2_TX_2 // DMA1, Stream 4, Channel 0 (SPI2 TX)
|
||||
#define DMAMAP_SPI2_RX DMAMAP_SPI2_RX_2 // DMA1, Stream 3, Channel 0 (SPI2 RX)
|
||||
#define DMAMAP_SPI2_TX DMAMAP_SPI2_TX_2 // DMA1, Stream 4, Channel 0 (SPI2 TX)
|
||||
// DMAMAP_USART2_RX // DMA1, Stream 5, Channel 4
|
||||
// DMAMAP_UART8_RX // DMA1, Stream 6, Channel 5 (CONSOLE)
|
||||
|
||||
// DMA2 Channel/Stream Selections
|
||||
//--------------------------------------------//---------------------------//----------------
|
||||
#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1 // DMA2, Stream 0, Channel 3 (SPI1 RX)
|
||||
#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1 // DMA2, Stream 0, Channel 3 (SPI1 RX)
|
||||
// AVAILABLE // DMA2, Stream 1
|
||||
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 // DMA2, Stream 2, Channel 5
|
||||
#define DMAMAP_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI1 TX)
|
||||
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2 // DMA2, Stream 2, Channel 5
|
||||
#define DMAMAP_SPI1_TX DMAMAP_SPI1_TX_1 // DMA2, Stream 3, Channel 3 (SPI1 TX)
|
||||
// AVAILABLE // DMA2, Stream 4
|
||||
#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 // DMA2, Stream 5, Channel 4
|
||||
#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_2 // DMA2, Stream 6, Channel 4
|
||||
#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2 // DMA2, Stream 5, Channel 4
|
||||
#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_2 // DMA2, Stream 6, Channel 4
|
||||
|
||||
@@ -43,16 +43,15 @@
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <stm32_gpio.h>
|
||||
|
||||
/* Configuration ************************************************************************************/
|
||||
|
||||
#define BOARD_HAS_NBAT_V 1 // Only one Vbat to ADC
|
||||
#define BOARD_HAS_NBAT_I 0 // No Ibat ADC
|
||||
#define BOARD_HAS_NBAT_V 1 // Only one Vbat to ADC
|
||||
#define BOARD_HAS_NBAT_I 0 // No Ibat ADC
|
||||
|
||||
/*
|
||||
* ADC channels
|
||||
@@ -63,53 +62,44 @@
|
||||
|
||||
/* ADC defines to be used in sensors.cpp to read from a particular channel */
|
||||
|
||||
#define ADC1_CH(n) (n)
|
||||
#define ADC1_GPIO(n) GPIO_ADC1_IN##n
|
||||
#define ADC1_CH(n) (n)
|
||||
#define ADC1_GPIO(n) GPIO_ADC1_IN##n
|
||||
|
||||
/* Define GPIO pins used as ADC N.B. Channel numbers must match below */
|
||||
|
||||
#define PX4_ADC_GPIO \
|
||||
/* PA0 */ ADC1_GPIO(0), \
|
||||
/* PA1 */ ADC1_GPIO(1), \
|
||||
/* PA2 */ ADC1_GPIO(2), \
|
||||
/* PA3 */ ADC1_GPIO(3), \
|
||||
/* PA4 */ ADC1_GPIO(4), \
|
||||
/* PB8 */ ADC1_GPIO(8), \
|
||||
/* PC0 */ ADC1_GPIO(10), \
|
||||
/* PC1 */ ADC1_GPIO(11), \
|
||||
/* PC2 */ ADC1_GPIO(12), \
|
||||
/* PC3 */ ADC1_GPIO(13), \
|
||||
/* PC4 */ ADC1_GPIO(14)
|
||||
#define PX4_ADC_GPIO \
|
||||
/* PA0 */ ADC1_GPIO(0), /* PA1 */ ADC1_GPIO(1), /* PA2 */ ADC1_GPIO(2), /* PA3 */ ADC1_GPIO(3), \
|
||||
/* PA4 */ ADC1_GPIO(4), /* PB8 */ ADC1_GPIO(8), /* PC0 */ ADC1_GPIO(10), /* PC1 */ ADC1_GPIO(11), \
|
||||
/* PC2 */ ADC1_GPIO(12), /* PC3 */ ADC1_GPIO(13), /* PC4 */ ADC1_GPIO(14)
|
||||
|
||||
/* Define Channel numbers must match above GPIO pin IN(n)*/
|
||||
|
||||
#define ADC_BATTERY1_VOLTAGE_CHANNEL /* PA0 */ ADC1_CH(0)
|
||||
#define ADC_BATTERY1_VOLTAGE_CHANNEL /* PA0 */ ADC1_CH(0)
|
||||
|
||||
#define ADC_CHANNELS \
|
||||
((1 << ADC_BATTERY1_VOLTAGE_CHANNEL))
|
||||
#define ADC_CHANNELS ((1 << ADC_BATTERY1_VOLTAGE_CHANNEL))
|
||||
|
||||
/* HW has to large of R termination on ADC todo:change when HW value is chosen */
|
||||
|
||||
#define BOARD_ADC_OPEN_CIRCUIT_V (5.6f)
|
||||
#define BOARD_ADC_OPEN_CIRCUIT_V (5.6f)
|
||||
|
||||
/* PWM
|
||||
*/
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 9
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 9
|
||||
|
||||
#define BOARD_CAPTURE_GPIO /* PD14 */ (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN14)
|
||||
#define BOARD_CAPTURE_GPIO /* PD14 */ (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTD | GPIO_PIN14)
|
||||
|
||||
/* High-resolution timer */
|
||||
#define HRT_TIMER 5 /* use timer5 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel 3 */
|
||||
#define HRT_TIMER 5 /* use timer5 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel 3 */
|
||||
|
||||
/* RC Serial port */
|
||||
|
||||
#define RC_SERIAL_PORT "/dev/ttyS4"
|
||||
#define RC_SERIAL_PORT "/dev/ttyS4"
|
||||
|
||||
/* Power switch controls ******************************************************/
|
||||
|
||||
#define SDIO_SLOTNO 0 /* Only one slot */
|
||||
#define SDIO_MINOR 0
|
||||
#define SDIO_SLOTNO 0 /* Only one slot */
|
||||
#define SDIO_MINOR 0
|
||||
|
||||
/* SD card bringup does not work if performed on the IDLE thread because it
|
||||
* will cause waiting. Use either:
|
||||
@@ -119,20 +109,19 @@
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_BOARD_INITIALIZE) && !defined(CONFIG_LIB_BOARDCTL) && !defined(CONFIG_BOARD_INITTHREAD)
|
||||
# warning SDIO initialization cannot be perfomed on the IDLE thread
|
||||
#warning SDIO initialization cannot be perfomed on the IDLE thread
|
||||
#endif
|
||||
|
||||
/* AV-X_V1 never powers off the Servo rail */
|
||||
|
||||
#define BOARD_ADC_SERVO_VALID (1)
|
||||
#define BOARD_ADC_SERVO_VALID (1)
|
||||
|
||||
#define ADC_BATTERY_VOLTAGE_CHANNEL 0
|
||||
#define ADC_BATTERY_CURRENT_CHANNEL 1 // TODO: review
|
||||
#define ADC_BATTERY_VOLTAGE_CHANNEL 0
|
||||
#define ADC_BATTERY_CURRENT_CHANNEL 1 // TODO: review
|
||||
|
||||
#define BOARD_ADC_PERIPH_5V_OC (!px4_arch_gpioread(GPIO_nVDD_5V_PERIPH_OC))
|
||||
#define BOARD_ADC_PERIPH_5V_OC (!px4_arch_gpioread(GPIO_nVDD_5V_PERIPH_OC))
|
||||
#define BOARD_ADC_HIPOWER_5V_OC (!px4_arch_gpioread(GPIO_nVDD_5V_HIPOWER_OC))
|
||||
|
||||
|
||||
/* This board provides a DMA pool and APIs */
|
||||
#define BOARD_DMA_ALLOC_POOL_SIZE 5120
|
||||
|
||||
@@ -140,11 +129,8 @@
|
||||
|
||||
#define BOARD_HAS_ON_RESET 1
|
||||
|
||||
#define PX4_GPIO_INIT_LIST { \
|
||||
PX4_ADC_GPIO, \
|
||||
GPIO_CAN1_RX, \
|
||||
GPIO_CAN1_TX, \
|
||||
}
|
||||
#define PX4_GPIO_INIT_LIST \
|
||||
{ PX4_ADC_GPIO, GPIO_CAN1_RX, GPIO_CAN1_TX, }
|
||||
|
||||
#define BOARD_ENABLE_CONSOLE_BUFFER
|
||||
|
||||
@@ -188,7 +174,6 @@ extern void stm32_spiinitialize(void);
|
||||
|
||||
#define board_peripheral_reset(ms)
|
||||
|
||||
|
||||
#include <px4_platform_common/board_common.h>
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
+29
-37
@@ -45,35 +45,33 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "board_config.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <chip.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
#include <nuttx/mm/gran.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/io_timer.h>
|
||||
#include <px4_platform/board_dma_alloc.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/mm/gran.h>
|
||||
#include <chip.h>
|
||||
#include <stm32_uart.h>
|
||||
#include <arch/board/board.h>
|
||||
#include "arm_internal.h"
|
||||
|
||||
#include <px4_arch/io_timer.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <string.h>
|
||||
#include <syslog.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <px4_platform/board_dma_alloc.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "board_config.h"
|
||||
|
||||
static int configure_switch(void);
|
||||
|
||||
@@ -88,8 +86,7 @@ static int configure_switch(void);
|
||||
* 0 if just resetting
|
||||
*
|
||||
************************************************************************************/
|
||||
__EXPORT void board_on_reset(int status)
|
||||
{
|
||||
__EXPORT void board_on_reset(int status) {
|
||||
for (int i = 0; i < DIRECT_PWM_OUTPUT_CHANNELS; ++i) {
|
||||
px4_arch_configgpio(PX4_MAKE_GPIO_INPUT(io_timer_channel_get_as_pwm_input(i)));
|
||||
}
|
||||
@@ -109,9 +106,7 @@ __EXPORT void board_on_reset(int status)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void
|
||||
stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
board_on_reset(-1); /* Reset PWM first thing */
|
||||
|
||||
/* configure LEDs */
|
||||
@@ -150,9 +145,7 @@ stm32_boardinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
__EXPORT int board_app_initialize(uintptr_t arg) {
|
||||
px4_platform_init();
|
||||
|
||||
/* configure the DMA allocator */
|
||||
@@ -167,7 +160,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
hrt_call_every(&serial_dma_call, 1000, 1000, (hrt_callout)stm32_serial_dma_poll, NULL);
|
||||
#endif
|
||||
|
||||
(void) board_hardfault_init(2, true);
|
||||
(void)board_hardfault_init(2, true);
|
||||
|
||||
#ifdef CONFIG_MMCSD
|
||||
|
||||
@@ -195,8 +188,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
|
||||
* Configure KSZ9897R ethernet switch on i2c
|
||||
*
|
||||
************************************************************************************/
|
||||
static int configure_switch(void)
|
||||
{
|
||||
static int configure_switch(void) {
|
||||
int ret = PX4_ERROR;
|
||||
|
||||
// attach to the i2c bus (internal)
|
||||
@@ -207,7 +199,7 @@ static int configure_switch(void)
|
||||
}
|
||||
|
||||
// ethernet switch enable
|
||||
uint8_t txdata[] = {0x51, 0x00, 0x21, 0x00}; //0x5100, 0x2100 MSB to LSB here.
|
||||
uint8_t txdata[] = {0x51, 0x00, 0x21, 0x00}; // 0x5100, 0x2100 MSB to LSB here.
|
||||
|
||||
struct i2c_msg_s msgv;
|
||||
|
||||
|
||||
@@ -36,34 +36,31 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <board_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/sdio.h>
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/sdio.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "board_config.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_sdmmc.h"
|
||||
|
||||
#ifdef CONFIG_MMCSD
|
||||
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Card detections requires card support and a card detection GPIO */
|
||||
|
||||
#define HAVE_NCD 1
|
||||
#define HAVE_NCD 1
|
||||
#if !defined(GPIO_SDMMC1_NCD)
|
||||
# undef HAVE_NCD
|
||||
#undef HAVE_NCD
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
@@ -88,8 +85,7 @@ static bool g_sd_inserted = 0xff; /* Impossible value */
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_NCD
|
||||
static int stm32_ncd_interrupt(int irq, FAR void *context)
|
||||
{
|
||||
static int stm32_ncd_interrupt(int irq, FAR void *context) {
|
||||
bool present;
|
||||
|
||||
present = !stm32_gpioread(GPIO_SDMMC1_NCD);
|
||||
@@ -115,8 +111,7 @@ static int stm32_ncd_interrupt(int irq, FAR void *context)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_sdio_initialize(void)
|
||||
{
|
||||
int stm32_sdio_initialize(void) {
|
||||
int ret;
|
||||
|
||||
#ifdef HAVE_NCD
|
||||
|
||||
+22
-14
@@ -31,24 +31,32 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::SPI1, {
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ADIS16477, SPI::CS{GPIO::PortG, GPIO::Pin10}, SPI::DRDY{GPIO::PortJ, GPIO::Pin0}),
|
||||
}),
|
||||
initSPIBusExternal(SPI::Bus::SPI2, {
|
||||
initSPIConfigExternal(SPI::CS{GPIO::PortI, GPIO::Pin0}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI4, {
|
||||
initSPIDevice(DRV_BARO_DEVTYPE_LPS22HB, SPI::CS{GPIO::PortE, GPIO::Pin4}, SPI::DRDY{GPIO::PortK, GPIO::Pin1}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI5, {
|
||||
initSPIDevice(DRV_MAG_DEVTYPE_LSM303AGR, SPI::CS{GPIO::PortH, GPIO::Pin5}, SPI::DRDY{GPIO::PortK, GPIO::Pin7}),
|
||||
initSPIDevice(DRV_ACC_DEVTYPE_LSM303AGR, SPI::CS{GPIO::PortB, GPIO::Pin0}, SPI::DRDY{GPIO::PortD, GPIO::Pin12}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI1,
|
||||
{
|
||||
initSPIDevice(DRV_IMU_DEVTYPE_ADIS16477, SPI::CS{GPIO::PortG, GPIO::Pin10},
|
||||
SPI::DRDY{GPIO::PortJ, GPIO::Pin0}),
|
||||
}),
|
||||
initSPIBusExternal(SPI::Bus::SPI2,
|
||||
{
|
||||
initSPIConfigExternal(SPI::CS{GPIO::PortI, GPIO::Pin0}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI4,
|
||||
{
|
||||
initSPIDevice(DRV_BARO_DEVTYPE_LPS22HB, SPI::CS{GPIO::PortE, GPIO::Pin4},
|
||||
SPI::DRDY{GPIO::PortK, GPIO::Pin1}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI5,
|
||||
{
|
||||
initSPIDevice(DRV_MAG_DEVTYPE_LSM303AGR, SPI::CS{GPIO::PortH, GPIO::Pin5},
|
||||
SPI::DRDY{GPIO::PortK, GPIO::Pin7}),
|
||||
initSPIDevice(DRV_ACC_DEVTYPE_LSM303AGR, SPI::CS{GPIO::PortB, GPIO::Pin0},
|
||||
SPI::DRDY{GPIO::PortD, GPIO::Pin12}),
|
||||
}),
|
||||
};
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
|
||||
@@ -34,12 +34,8 @@
|
||||
#include <px4_arch/io_timer_hw_description.h>
|
||||
|
||||
constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
|
||||
initIOTimer(Timer::Timer1),
|
||||
initIOTimer(Timer::Timer2),
|
||||
initIOTimer(Timer::Timer8),
|
||||
initIOTimer(Timer::Timer11),
|
||||
initIOTimer(Timer::Timer10),
|
||||
initIOTimer(Timer::Timer4),
|
||||
initIOTimer(Timer::Timer1), initIOTimer(Timer::Timer2), initIOTimer(Timer::Timer8),
|
||||
initIOTimer(Timer::Timer11), initIOTimer(Timer::Timer10), initIOTimer(Timer::Timer4),
|
||||
};
|
||||
|
||||
constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
|
||||
|
||||
@@ -32,12 +32,9 @@
|
||||
****************************************************************************/
|
||||
|
||||
#include <board_config.h>
|
||||
|
||||
#include <drivers/drv_adc.h>
|
||||
|
||||
#include <px4_platform_common/log.h>
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <px4_platform_common/log.h>
|
||||
#include <stdint.h>
|
||||
#include <unistd.h>
|
||||
|
||||
@@ -45,8 +42,7 @@
|
||||
#define ADC_MAX_CHAN 8
|
||||
int _channels_fd[ADC_MAX_CHAN];
|
||||
|
||||
int px4_arch_adc_init(uint32_t base_address)
|
||||
{
|
||||
int px4_arch_adc_init(uint32_t base_address) {
|
||||
for (int i = 0; i < ADC_MAX_CHAN; i++) {
|
||||
_channels_fd[i] = -1;
|
||||
}
|
||||
@@ -54,50 +50,46 @@ int px4_arch_adc_init(uint32_t base_address)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void px4_arch_adc_uninit(uint32_t base_address)
|
||||
{
|
||||
void px4_arch_adc_uninit(uint32_t base_address) {
|
||||
for (int i = 0; i < ADC_MAX_CHAN; i++) {
|
||||
::close(_channels_fd[i]);
|
||||
_channels_fd[i] = -1;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t px4_arch_adc_sample(uint32_t base_address, unsigned channel)
|
||||
{
|
||||
uint32_t px4_arch_adc_sample(uint32_t base_address, unsigned channel) {
|
||||
if (channel > ADC_MAX_CHAN) {
|
||||
PX4_ERR("channel %d out of range: %d", channel, ADC_MAX_CHAN);
|
||||
return UINT32_MAX; // error
|
||||
return UINT32_MAX; // error
|
||||
}
|
||||
|
||||
// open channel if necessary
|
||||
if (_channels_fd[channel] == -1) {
|
||||
// ADC_SYSFS_PATH
|
||||
char channel_path[strlen(ADC_SYSFS_PATH) + 20] {};
|
||||
char channel_path[strlen(ADC_SYSFS_PATH) + 20]{};
|
||||
|
||||
if (sprintf(channel_path, "%s/in_voltage%d_raw", ADC_SYSFS_PATH, channel) == -1) {
|
||||
PX4_ERR("adc channel: %d\n", channel);
|
||||
return UINT32_MAX; // error
|
||||
return UINT32_MAX; // error
|
||||
}
|
||||
|
||||
_channels_fd[channel] = ::open(channel_path, O_RDONLY);
|
||||
}
|
||||
|
||||
char buffer[10] {};
|
||||
char buffer[10]{};
|
||||
|
||||
if (::pread(_channels_fd[channel], buffer, sizeof(buffer), 0) < 0) {
|
||||
PX4_ERR("read channel %d failed", channel);
|
||||
return UINT32_MAX; // error
|
||||
return UINT32_MAX; // error
|
||||
}
|
||||
|
||||
return atoi(buffer);
|
||||
}
|
||||
|
||||
float px4_arch_adc_reference_v()
|
||||
{
|
||||
return BOARD_ADC_POS_REF_V; // 12-bit 1.8V ADC
|
||||
float px4_arch_adc_reference_v() {
|
||||
return BOARD_ADC_POS_REF_V; // 12-bit 1.8V ADC
|
||||
}
|
||||
|
||||
uint32_t px4_arch_adc_dn_fullcount()
|
||||
{
|
||||
return 1 << 12; // 12 bit ADC
|
||||
uint32_t px4_arch_adc_dn_fullcount() {
|
||||
return 1 << 12; // 12 bit ADC
|
||||
}
|
||||
|
||||
@@ -33,6 +33,6 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#define SYSTEM_ADC_BASE 0 // not used
|
||||
#define SYSTEM_ADC_BASE 0 // not used
|
||||
|
||||
#define px4_arch_adc_temp_sensor_mask() (0)
|
||||
|
||||
@@ -39,39 +39,35 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#define BOARD_OVERRIDE_UUID "BBBLUEID00000000" // must be of length 16
|
||||
#define PX4_SOC_ARCH_ID PX4_SOC_ARCH_ID_BBBLUE
|
||||
|
||||
#define BOARD_MAX_LEDS 4 // Number external of LED's this board has
|
||||
#define BOARD_OVERRIDE_UUID "BBBLUEID00000000" // must be of length 16
|
||||
#define PX4_SOC_ARCH_ID PX4_SOC_ARCH_ID_BBBLUE
|
||||
|
||||
#define BOARD_MAX_LEDS 4 // Number external of LED's this board has
|
||||
|
||||
// I2C
|
||||
#define CONFIG_I2C 1
|
||||
#define PX4_NUMBER_I2C_BUSES 2
|
||||
#define PX4_NUMBER_I2C_BUSES 2
|
||||
|
||||
#define PX4_I2C_OBDEV_MPU9250 0x68
|
||||
|
||||
|
||||
// SPI
|
||||
#define CONFIG_SPI 1
|
||||
|
||||
|
||||
// ADC channels:
|
||||
#define ADC_CHANNELS (1 << 5)
|
||||
#define BOARD_ADC_POS_REF_V (1.8f)
|
||||
|
||||
#define ADC_BATTERY_VOLTAGE_CHANNEL 5
|
||||
#define ADC_BATTERY_CURRENT_CHANNEL ((uint8_t)(-1))
|
||||
#define ADC_BATTERY_VOLTAGE_CHANNEL 5
|
||||
#define ADC_BATTERY_CURRENT_CHANNEL ((uint8_t)(-1))
|
||||
|
||||
|
||||
#include <system_config.h>
|
||||
#include <px4_platform_common/board_common.h>
|
||||
#include <system_config.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int rc_init(void);
|
||||
int rc_init(void);
|
||||
void rc_cleaning(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
@@ -79,16 +75,16 @@ void rc_cleaning(void);
|
||||
#endif
|
||||
|
||||
#ifdef __RC_V0_3
|
||||
#define rc_i2c_lock_bus rc_i2c_claim_bus
|
||||
#define rc_i2c_unlock_bus rc_i2c_release_bus
|
||||
#define rc_i2c_get_lock rc_i2c_get_in_use_state
|
||||
#define rc_i2c_lock_bus rc_i2c_claim_bus
|
||||
#define rc_i2c_unlock_bus rc_i2c_release_bus
|
||||
#define rc_i2c_get_lock rc_i2c_get_in_use_state
|
||||
|
||||
#define rc_servo_send_pulse_us rc_send_servo_pulse_us
|
||||
#define rc_servo_send_pulse_us rc_send_servo_pulse_us
|
||||
|
||||
#define rc_filter_empty rc_empty_filter
|
||||
#define rc_filter_march rc_march_filter
|
||||
#define rc_filter_prefill_inputs rc_prefill_filter_inputs
|
||||
#define rc_filter_prefill_outputs rc_prefill_filter_outputs
|
||||
#define rc_filter_butterworth_lowpass rc_butterworth_lowpass
|
||||
#define rc_filter_empty rc_empty_filter
|
||||
#define rc_filter_march rc_march_filter
|
||||
#define rc_filter_prefill_inputs rc_prefill_filter_inputs
|
||||
#define rc_filter_prefill_outputs rc_prefill_filter_outputs
|
||||
#define rc_filter_butterworth_lowpass rc_butterworth_lowpass
|
||||
|
||||
#endif
|
||||
|
||||
@@ -35,39 +35,32 @@
|
||||
#define MODULE_NAME "bbblue_pwm_out"
|
||||
#endif
|
||||
|
||||
#include <fcntl.h>
|
||||
#include <errno.h>
|
||||
#include <px4_platform_common/log.h>
|
||||
|
||||
#include <robotcontrol.h>
|
||||
#include <board_config.h>
|
||||
|
||||
#include "board_pwm_out.h"
|
||||
|
||||
#include <board_config.h>
|
||||
#include <errno.h>
|
||||
#include <fcntl.h>
|
||||
#include <px4_platform_common/log.h>
|
||||
#include <robotcontrol.h>
|
||||
|
||||
using namespace pwm_out;
|
||||
|
||||
BBBlueRcPWMOut::BBBlueRcPWMOut(int max_num_outputs) : _num_outputs(max_num_outputs)
|
||||
{
|
||||
BBBlueRcPWMOut::BBBlueRcPWMOut(int max_num_outputs) : _num_outputs(max_num_outputs) {
|
||||
if (_num_outputs > MAX_NUM_PWM) {
|
||||
PX4_WARN("number of outputs too large. Setting to %i", MAX_NUM_PWM);
|
||||
_num_outputs = MAX_NUM_PWM;
|
||||
}
|
||||
}
|
||||
|
||||
BBBlueRcPWMOut::~BBBlueRcPWMOut()
|
||||
{
|
||||
rc_cleaning();
|
||||
}
|
||||
BBBlueRcPWMOut::~BBBlueRcPWMOut() { rc_cleaning(); }
|
||||
|
||||
int BBBlueRcPWMOut::init()
|
||||
{
|
||||
int BBBlueRcPWMOut::init() {
|
||||
rc_init();
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int BBBlueRcPWMOut::send_output_pwm(const uint16_t *pwm, int num_outputs)
|
||||
{
|
||||
int BBBlueRcPWMOut::send_output_pwm(const uint16_t *pwm, int num_outputs) {
|
||||
if (num_outputs > _num_outputs) {
|
||||
num_outputs = _num_outputs;
|
||||
}
|
||||
@@ -76,9 +69,8 @@ int BBBlueRcPWMOut::send_output_pwm(const uint16_t *pwm, int num_outputs)
|
||||
|
||||
// pwm[ch] is duty_cycle in us
|
||||
for (int ch = 0; ch < num_outputs; ++ch) {
|
||||
ret += rc_servo_send_pulse_us(ch + 1, pwm[ch]); // converts to 1-based channel #
|
||||
ret += rc_servo_send_pulse_us(ch + 1, pwm[ch]); // converts to 1-based channel #
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@@ -37,8 +37,7 @@
|
||||
|
||||
#define BOARD_PWM_OUT_IMPL BBBlueRcPWMOut
|
||||
|
||||
namespace pwm_out
|
||||
{
|
||||
namespace pwm_out {
|
||||
|
||||
/**
|
||||
** class BBBlueRcPWMOut
|
||||
@@ -47,8 +46,7 @@ namespace pwm_out
|
||||
* Ref: https://github.com/StrawsonDesign/Robotics_Cape_Installer
|
||||
* http://www.strawsondesign.com/#!manual-servos
|
||||
*/
|
||||
class BBBlueRcPWMOut : public PWMOutBase
|
||||
{
|
||||
class BBBlueRcPWMOut : public PWMOutBase {
|
||||
public:
|
||||
BBBlueRcPWMOut(int max_num_outputs);
|
||||
virtual ~BBBlueRcPWMOut();
|
||||
@@ -64,4 +62,4 @@ private:
|
||||
int _num_outputs;
|
||||
};
|
||||
|
||||
}
|
||||
} // namespace pwm_out
|
||||
|
||||
@@ -34,6 +34,6 @@
|
||||
#include <px4_arch/i2c_hw_description.h>
|
||||
|
||||
constexpr px4_i2c_bus_t px4_i2c_buses[I2C_BUS_MAX_BUS_ITEMS] = {
|
||||
initI2CBusExternal(1), // i2c-1: pins P9 17,18
|
||||
initI2CBusInternal(2), // i2c-2: pins P9 19,20 - bmp280, mpu9250
|
||||
initI2CBusExternal(1), // i2c-1: pins P9 17,18
|
||||
initI2CBusInternal(2), // i2c-2: pins P9 19,20 - bmp280, mpu9250
|
||||
};
|
||||
|
||||
@@ -36,21 +36,21 @@
|
||||
*
|
||||
* BBBLUE specific initialization
|
||||
*/
|
||||
#include <stddef.h>
|
||||
#include <px4_platform_common/log.h>
|
||||
|
||||
#include <robotcontrol.h>
|
||||
#include <stddef.h>
|
||||
|
||||
#include "board_config.h"
|
||||
|
||||
// initialize roboticscape library similar to the deprecated rc_initialize()
|
||||
int rc_init(void)
|
||||
{
|
||||
int rc_init(void) {
|
||||
#ifdef __RC_V0_3
|
||||
return rc_initialize();
|
||||
#else
|
||||
|
||||
if (rc_get_state() == RUNNING) { return 0; }
|
||||
if (rc_get_state() == RUNNING) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
PX4_INFO("Initializing librobotcontrol ...");
|
||||
|
||||
@@ -102,12 +102,12 @@ int rc_init(void)
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (rc_servo_power_rail_en(1)) { // Turning On 6V Servo Power Rail
|
||||
if (rc_servo_power_rail_en(1)) { // Turning On 6V Servo Power Rail
|
||||
PX4_ERR("rc_init failed to run rc_servo_power_rail_en(1)");
|
||||
return -1;
|
||||
}
|
||||
|
||||
//i2c, barometer and mpu will be initialized later
|
||||
// i2c, barometer and mpu will be initialized later
|
||||
|
||||
rc_set_state(RUNNING);
|
||||
|
||||
@@ -115,14 +115,15 @@ int rc_init(void)
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
void rc_cleaning(void)
|
||||
{
|
||||
void rc_cleaning(void) {
|
||||
#ifdef __RC_V0_3
|
||||
rc_cleanup(); return ;
|
||||
rc_cleanup();
|
||||
return;
|
||||
#else
|
||||
|
||||
if (rc_get_state() == EXITING) { return; }
|
||||
if (rc_get_state() == EXITING) {
|
||||
return;
|
||||
}
|
||||
|
||||
rc_set_state(EXITING);
|
||||
|
||||
|
||||
@@ -31,12 +31,13 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(1, {
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, 1), // spidev1.1
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, 2), // spidev1.2
|
||||
}),
|
||||
initSPIBus(1,
|
||||
{
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, 1), // spidev1.1
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, 2), // spidev1.2
|
||||
}),
|
||||
};
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include "stm32.h"
|
||||
@@ -83,11 +83,11 @@
|
||||
* LSE - not installed
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
//#define STM32_LSE_FREQUENCY 32768
|
||||
|
||||
/* Main PLL Configuration.
|
||||
@@ -103,68 +103,68 @@
|
||||
* = 48,000,000
|
||||
*/
|
||||
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
|
||||
|
||||
#define STM32_SYSCLK_FREQUENCY 168000000ul
|
||||
#define STM32_SYSCLK_FREQUENCY 168000000ul
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (168MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 4)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 */
|
||||
|
||||
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
||||
/* Timers driven from APB2 will be twice PCLK2 */
|
||||
|
||||
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
||||
* otherwise frequency is 2xAPBx.
|
||||
* Note: TIM1,8-11 are on APB2, others on APB1
|
||||
*/
|
||||
|
||||
#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN
|
||||
#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN
|
||||
#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN
|
||||
#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN
|
||||
#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN
|
||||
#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN
|
||||
#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN
|
||||
#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN
|
||||
#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN
|
||||
#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN
|
||||
#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN
|
||||
#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN
|
||||
#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN
|
||||
#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN
|
||||
#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN
|
||||
#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN
|
||||
|
||||
/* Alternate function pin selections ************************************************/
|
||||
|
||||
@@ -173,16 +173,16 @@
|
||||
*
|
||||
*/
|
||||
/* E_TX2 / E_RX2 */
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
|
||||
/* E_TX1 / E_RX1 */
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_2
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_2
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_2
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_2
|
||||
|
||||
/* NRF51 via syslink */
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_1
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_1
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_1
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_1
|
||||
|
||||
/* UART DMA configuration for USART6 */
|
||||
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
|
||||
@@ -194,24 +194,24 @@
|
||||
* reset the bus to clear stuck slaves. They match the pin configuration,
|
||||
* but are normally-high GPIOs.
|
||||
*/
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
|
||||
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
|
||||
#define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
|
||||
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
|
||||
#define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN8)
|
||||
#define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN9)
|
||||
|
||||
/*
|
||||
* SPI
|
||||
*
|
||||
* E_MISO, E_MOSI, E_SCK exposed on headers
|
||||
*/
|
||||
#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1 | GPIO_SPEED_50MHz)
|
||||
|
||||
/* XXX since we allocate the HP work stack from CCM RAM on normal system startup,
|
||||
SPI1 will never run in DMA mode - so we can just give it a random config here.
|
||||
@@ -220,4 +220,4 @@
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_2
|
||||
|
||||
#endif /* __CONFIG_CRAZYFLIE_INCLUDE_BOARD_H */
|
||||
#endif /* __CONFIG_CRAZYFLIE_INCLUDE_BOARD_H */
|
||||
|
||||
@@ -43,8 +43,8 @@
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************************************
|
||||
@@ -55,93 +55,87 @@
|
||||
/* Crazyflie GPIOs **********************************************************************************/
|
||||
/* LEDs */
|
||||
|
||||
|
||||
/* Radio TX indicator */
|
||||
#define GPIO_LED_RED_L (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_LED_RED_L (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN0)
|
||||
/* Radio RX indicator */
|
||||
#define GPIO_LED_GREEN_L (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_LED_GREEN_R (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_LED_RED_R (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_LED_GREEN_L (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN1)
|
||||
#define GPIO_LED_GREEN_R (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN2)
|
||||
#define GPIO_LED_RED_R (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN3)
|
||||
|
||||
/* PX4: armed state indicator ; Stock FW: Blinking while charging */
|
||||
#define GPIO_LED_BLUE_L (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_LED_BLUE_L (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTD | GPIO_PIN2)
|
||||
|
||||
#define BOARD_HAS_CONTROL_STATUS_LEDS 1
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_LED LED_BLUE
|
||||
#define BOARD_ARMED_STATE_LED LED_GREEN
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_LED LED_BLUE
|
||||
#define BOARD_ARMED_STATE_LED LED_GREEN
|
||||
|
||||
#define LED_TX 4
|
||||
#define LED_RX 5
|
||||
|
||||
#define GPIO_FSYNC_MPU9250 (GPIO_OUTPUT|GPIO_PORTC|GPIO_PIN14) // Needs to be set low
|
||||
#define GPIO_DRDY_MPU9250 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
|
||||
|
||||
|
||||
#define GPIO_NRF_TXEN (GPIO_INPUT|GPIO_PULLUP|GPIO_EXTI|GPIO_PORTA|GPIO_PIN4)
|
||||
#define GPIO_FSYNC_MPU9250 (GPIO_OUTPUT | GPIO_PORTC | GPIO_PIN14) // Needs to be set low
|
||||
#define GPIO_DRDY_MPU9250 (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
|
||||
|
||||
#define GPIO_NRF_TXEN (GPIO_INPUT | GPIO_PULLUP | GPIO_EXTI | GPIO_PORTA | GPIO_PIN4)
|
||||
|
||||
/*
|
||||
* I2C busses
|
||||
*/
|
||||
#define PX4_I2C_BUS_ONBOARD_HZ 400000
|
||||
#define PX4_I2C_BUS_EXPANSION_HZ 400000
|
||||
#define PX4_I2C_BUS_ONBOARD_HZ 400000
|
||||
#define PX4_I2C_BUS_EXPANSION_HZ 400000
|
||||
|
||||
#define PX4_I2C_BUS_MTD 1
|
||||
|
||||
#define BOARD_NUMBER_I2C_BUSES 3
|
||||
#define BOARD_I2C_BUS_CLOCK_INIT {PX4_I2C_BUS_ONBOARD_HZ, 100000, PX4_I2C_BUS_EXPANSION_HZ}
|
||||
#define PX4_I2C_BUS_MTD 1
|
||||
|
||||
#define BOARD_NUMBER_I2C_BUSES 3
|
||||
#define BOARD_I2C_BUS_CLOCK_INIT \
|
||||
{ PX4_I2C_BUS_ONBOARD_HZ, 100000, PX4_I2C_BUS_EXPANSION_HZ }
|
||||
|
||||
/* Devices on the onboard bus.
|
||||
*
|
||||
* Note that these are unshifted addresses.
|
||||
*/
|
||||
#define PX4_I2C_OBDEV_MPU9250 0x69
|
||||
#define PX4_I2C_OBDEV_MPU9250 0x69
|
||||
|
||||
/* USB OTG FS
|
||||
*
|
||||
* PA9 OTG_FS_VBUS VBUS sensing
|
||||
*/
|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT | GPIO_FLOAT | GPIO_SPEED_100MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN9)
|
||||
|
||||
/*
|
||||
* ADC channels
|
||||
*
|
||||
* These are the channel numbers of the ADCs of the microcontroller that can be used by the Px4 Firmware in the adc driver
|
||||
* These are the channel numbers of the ADCs of the microcontroller that can be used by the Px4 Firmware in the adc
|
||||
* driver
|
||||
*/
|
||||
#define ADC_CHANNELS 0
|
||||
|
||||
/* Tone alarm output : These are only applicable when the buzzer deck is attached */
|
||||
#define TONE_ALARM_TIMER 5 /* timer 5 */
|
||||
#define TONE_ALARM_CHANNEL 3 /* channel 3 */
|
||||
#define GPIO_TONE_ALARM_IDLE (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TONE_ALARM (GPIO_ALT|GPIO_AF2|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TONE_ALARM_NEG (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN3)
|
||||
#define TONE_ALARM_TIMER 5 /* timer 5 */
|
||||
#define TONE_ALARM_CHANNEL 3 /* channel 3 */
|
||||
#define GPIO_TONE_ALARM_IDLE \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_TONE_ALARM (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_2MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_TONE_ALARM_NEG (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN3)
|
||||
|
||||
/* PWM
|
||||
*/
|
||||
*/
|
||||
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 4
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 4
|
||||
|
||||
/* This board overrides the defaults by providing
|
||||
* PX4_PWM_ALTERNATE_RANGES and a replacement set of
|
||||
* constants
|
||||
*/
|
||||
|
||||
|
||||
/* PWM directly wired to transistor. Duty cycle directly corresponds to power
|
||||
* So we need to override the defaults
|
||||
*/
|
||||
|
||||
#define PX4_PWM_ALTERNATE_RANGES
|
||||
#define PWM_LOWEST_MIN 0
|
||||
#define PWM_MOTOR_OFF 0
|
||||
#define PWM_SERVO_STOP 0
|
||||
#define PWM_MOTOR_OFF 0
|
||||
#define PWM_SERVO_STOP 0
|
||||
#define PWM_DEFAULT_MIN 20
|
||||
#define PWM_HIGHEST_MIN 0
|
||||
#define PWM_HIGHEST_MAX 255
|
||||
@@ -149,14 +143,12 @@
|
||||
#define PWM_LOWEST_MAX 255
|
||||
#define PWM_DEFAULT_TRIM 1500
|
||||
|
||||
|
||||
/* High-resolution timer */
|
||||
#define HRT_TIMER 8 /* use timer8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel */
|
||||
|
||||
#define HRT_TIMER 8 /* use timer8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel */
|
||||
|
||||
#define BOARD_ENABLE_CONSOLE_BUFFER
|
||||
#define BOARD_CONSOLE_BUFFER_SIZE (1024*3)
|
||||
#define BOARD_CONSOLE_BUFFER_SIZE (1024 * 3)
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
@@ -224,7 +216,6 @@ extern void stm32_spiinitialize(void);
|
||||
|
||||
extern int stm32_spi_bus_initialize(void);
|
||||
|
||||
|
||||
#include <px4_platform_common/board_common.h>
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
@@ -45,30 +45,25 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/tasks.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <stm32_uart.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
|
||||
#include "board_config.h"
|
||||
#include <stm32_uart.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
@@ -105,9 +100,7 @@ __END_DECLS
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void
|
||||
stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
/* configure LEDs */
|
||||
|
||||
board_autoled_initialize();
|
||||
@@ -127,8 +120,7 @@ stm32_boardinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
__EXPORT int board_app_initialize(uintptr_t arg) {
|
||||
px4_platform_init();
|
||||
|
||||
#if defined(SERIAL_HAVE_RXDMA)
|
||||
|
||||
@@ -37,14 +37,12 @@
|
||||
* Crazyflie LED backend.
|
||||
*/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "stm32.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include "stm32.h"
|
||||
|
||||
/*
|
||||
* Ideally we'd be able to get these from arm_internal.h,
|
||||
@@ -61,17 +59,15 @@ extern void led_toggle(int led);
|
||||
__END_DECLS
|
||||
|
||||
static uint32_t g_ledmap[] = {
|
||||
GPIO_LED_BLUE_L, // Indexed by LED_BLUE
|
||||
GPIO_LED_RED_R, // Indexed by LED_RED, LED_AMBER
|
||||
0, // Indexed by LED_SAFETY
|
||||
GPIO_LED_GREEN_R, // Indexed by LED_GREEN
|
||||
GPIO_LED_RED_L, // Indexed by LED_TX
|
||||
GPIO_LED_GREEN_L // Indexed by LED_RX
|
||||
GPIO_LED_BLUE_L, // Indexed by LED_BLUE
|
||||
GPIO_LED_RED_R, // Indexed by LED_RED, LED_AMBER
|
||||
0, // Indexed by LED_SAFETY
|
||||
GPIO_LED_GREEN_R, // Indexed by LED_GREEN
|
||||
GPIO_LED_RED_L, // Indexed by LED_TX
|
||||
GPIO_LED_GREEN_L // Indexed by LED_RX
|
||||
};
|
||||
|
||||
|
||||
__EXPORT void led_init()
|
||||
{
|
||||
__EXPORT void led_init() {
|
||||
/* Configure LED1 GPIO for output */
|
||||
for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
|
||||
if (g_ledmap[l]) {
|
||||
@@ -80,20 +76,17 @@ __EXPORT void led_init()
|
||||
}
|
||||
}
|
||||
|
||||
__EXPORT void led_on(int led)
|
||||
{
|
||||
__EXPORT void led_on(int led) {
|
||||
/* Pull down to switch on */
|
||||
px4_arch_gpiowrite(g_ledmap[led], g_ledmap[led] & GPIO_OUTPUT_SET ? true : false);
|
||||
}
|
||||
|
||||
__EXPORT void led_off(int led)
|
||||
{
|
||||
__EXPORT void led_off(int led) {
|
||||
/* Pull up to switch off */
|
||||
px4_arch_gpiowrite(g_ledmap[led], g_ledmap[led] & GPIO_OUTPUT_SET ? false : true);
|
||||
}
|
||||
|
||||
__EXPORT void led_toggle(int led)
|
||||
{
|
||||
__EXPORT void led_toggle(int led) {
|
||||
if (px4_arch_gpioread(g_ledmap[led])) {
|
||||
px4_arch_gpiowrite(g_ledmap[led], false);
|
||||
|
||||
|
||||
@@ -34,48 +34,29 @@
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_platform_common/px4_manifest.h>
|
||||
// KiB BS nB
|
||||
static const px4_mft_device_t i2c1 = { // 24AA64FT on Base 8K 32 X 256
|
||||
static const px4_mft_device_t i2c1 = { // 24AA64FT on Base 8K 32 X 256
|
||||
.bus_type = px4_mft_device_t::I2C,
|
||||
.devid = PX4_MK_I2C_DEVID(1, 0x50)
|
||||
};
|
||||
|
||||
.devid = PX4_MK_I2C_DEVID(1, 0x50)};
|
||||
|
||||
static const px4_mtd_entry_t fmu_eeprom = {
|
||||
.device = &i2c1,
|
||||
.npart = 2,
|
||||
.partd = {
|
||||
{
|
||||
.type = MTD_PARAMETERS,
|
||||
.path = "/fs/mtd_params",
|
||||
.nblocks = 128
|
||||
},
|
||||
{
|
||||
.type = MTD_WAYPOINTS,
|
||||
.path = "/fs/mtd_waypoints",
|
||||
.nblocks = 128
|
||||
.partd = {{.type = MTD_PARAMETERS, .path = "/fs/mtd_params", .nblocks = 128},
|
||||
{.type = MTD_WAYPOINTS, .path = "/fs/mtd_waypoints", .nblocks = 128
|
||||
|
||||
}
|
||||
},
|
||||
}},
|
||||
};
|
||||
|
||||
static const px4_mtd_manifest_t board_mtd_config = {
|
||||
.nconfigs = 1,
|
||||
.entries = {
|
||||
&fmu_eeprom,
|
||||
}
|
||||
};
|
||||
static const px4_mtd_manifest_t board_mtd_config = {.nconfigs = 1,
|
||||
.entries = {
|
||||
&fmu_eeprom,
|
||||
}};
|
||||
|
||||
static const px4_mft_entry_s mtd_mft = {
|
||||
.type = MTD,
|
||||
.pmft = (void *) &board_mtd_config,
|
||||
.pmft = (void *)&board_mtd_config,
|
||||
};
|
||||
|
||||
static const px4_mft_s mft = {
|
||||
.nmft = 1,
|
||||
.mfts = &mtd_mft
|
||||
};
|
||||
static const px4_mft_s mft = {.nmft = 1, .mfts = &mtd_mft};
|
||||
|
||||
const px4_mft_s *board_get_manifest(void)
|
||||
{
|
||||
return &mft;
|
||||
}
|
||||
const px4_mft_s *board_get_manifest(void) { return &mft; }
|
||||
|
||||
@@ -31,34 +31,31 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <arch/board/board.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
|
||||
#include <arm_arch.h>
|
||||
#include <chip.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32_gpio.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "board_config.h"
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::SPI1, {
|
||||
initSPIDevice(SPIDEV_MMCSD(0), SPI::CS{GPIO::PortC, GPIO::Pin12}),
|
||||
initSPIDevice(DRV_FLOW_DEVTYPE_PMW3901, SPI::CS{GPIO::PortB, GPIO::Pin4}),
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortB, GPIO::Pin5}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI1,
|
||||
{
|
||||
initSPIDevice(SPIDEV_MMCSD(0), SPI::CS{GPIO::PortC, GPIO::Pin12}),
|
||||
initSPIDevice(DRV_FLOW_DEVTYPE_PMW3901, SPI::CS{GPIO::PortB, GPIO::Pin4}),
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortB, GPIO::Pin5}),
|
||||
}),
|
||||
};
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
@@ -72,8 +69,7 @@ static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
************************************************************************************/
|
||||
static struct spi_dev_s *spi_expansion;
|
||||
|
||||
__EXPORT int stm32_spi_bus_initialize(void)
|
||||
{
|
||||
__EXPORT int stm32_spi_bus_initialize(void) {
|
||||
/* Configure SPI-based devices */
|
||||
|
||||
/* Get the external SPI port */
|
||||
|
||||
@@ -39,8 +39,7 @@
|
||||
*/
|
||||
#define TIMx_CLKIN 1000000
|
||||
|
||||
static inline constexpr io_timers_t initIOTimerOverrideClockFreq(Timer::Timer timer)
|
||||
{
|
||||
static inline constexpr io_timers_t initIOTimerOverrideClockFreq(Timer::Timer timer) {
|
||||
io_timers_t ret = initIOTimer(timer);
|
||||
ret.clock_freq = TIMx_CLKIN;
|
||||
return ret;
|
||||
|
||||
@@ -41,18 +41,16 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <arm_arch.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/usb/usbdev.h>
|
||||
#include <nuttx/usb/usbdev_trace.h>
|
||||
|
||||
#include <arm_arch.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "board_config.h"
|
||||
|
||||
/************************************************************************************
|
||||
@@ -75,8 +73,7 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_usbinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_usbinitialize(void) {
|
||||
/* The OTG FS has an internal soft pull-up */
|
||||
|
||||
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
|
||||
@@ -101,8 +98,4 @@ __EXPORT void stm32_usbinitialize(void)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
|
||||
{
|
||||
uinfo("resume: %d\n", resume);
|
||||
}
|
||||
|
||||
__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); }
|
||||
|
||||
@@ -33,16 +33,15 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define CRTP_PORT_CONSOLE 0x00
|
||||
#define CRTP_PORT_PARAM 0x02
|
||||
#define CRTP_PORT_COMMANDER 0x03
|
||||
#define CRTP_PORT_PARAM 0x02
|
||||
#define CRTP_PORT_COMMANDER 0x03
|
||||
#define CRTP_PORT_MEM 0x04
|
||||
#define CRTP_PORT_LOG 0x05
|
||||
|
||||
#define CRTP_PORT_MAVLINK 0x08 // Non-standard port for transmitting mavlink messages
|
||||
#define CRTP_PORT_MAVLINK 0x08 // Non-standard port for transmitting mavlink messages
|
||||
|
||||
#define CRTP_PORT_PLATFORM 0x0D
|
||||
#define CRTP_PORT_DEBUG 0x0E
|
||||
@@ -55,7 +54,8 @@
|
||||
#define CRTP_MAX_DATA_SIZE 31
|
||||
|
||||
typedef struct {
|
||||
uint8_t size; // Total size of this message, including the header (placed here to overlap with syslink length field)
|
||||
uint8_t size; // Total size of this message, including the header (placed here to overlap with syslink length
|
||||
// field)
|
||||
union {
|
||||
uint8_t header;
|
||||
struct {
|
||||
@@ -68,10 +68,9 @@ typedef struct {
|
||||
uint8_t data[CRTP_MAX_DATA_SIZE];
|
||||
} __attribute__((packed)) crtp_message_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
float roll; // -20 to 20
|
||||
float roll; // -20 to 20
|
||||
float pitch;
|
||||
float yaw; // -150 to 150
|
||||
float yaw; // -150 to 150
|
||||
uint16_t thrust;
|
||||
} crtp_commander;
|
||||
|
||||
@@ -40,14 +40,11 @@
|
||||
#include <stdint.h>
|
||||
#include <sys/ioctl.h>
|
||||
|
||||
|
||||
#define DECK_DEVICE_PATH "/dev/deck"
|
||||
|
||||
|
||||
#define DECK_DEVICE_PATH "/dev/deck"
|
||||
|
||||
/* structure of the data stored in deck memory */
|
||||
typedef struct {
|
||||
uint8_t header; // Should be 0xEB
|
||||
uint8_t header; // Should be 0xEB
|
||||
uint32_t pins;
|
||||
uint8_t vendorId;
|
||||
uint8_t productId;
|
||||
@@ -56,24 +53,19 @@ typedef struct {
|
||||
|
||||
} __attribute__((packed)) deck_descriptor_t;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* ioctl() definitions
|
||||
*/
|
||||
|
||||
#define _DECKIOCBASE (0x4100)
|
||||
#define _DECKIOC(_n) (_PX4_IOC(_DECKIOCBASE, _n))
|
||||
#define _DECKIOCBASE (0x4100)
|
||||
#define _DECKIOC(_n) (_PX4_IOC(_DECKIOCBASE, _n))
|
||||
|
||||
/** get the number of connected deck memory devices */
|
||||
#define DECKIOGNUM _DECKIOC(0)
|
||||
#define DECKIOGNUM _DECKIOC(0)
|
||||
|
||||
/** set the index of the current deck memory being accessed */
|
||||
#define DECKIOSNUM _DECKIOC(1)
|
||||
|
||||
#define DECKIOID _DECKIOC(2)
|
||||
|
||||
|
||||
#define DECKIOSNUM _DECKIOC(1)
|
||||
|
||||
#define DECKIOID _DECKIOC(2)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -38,59 +38,35 @@
|
||||
*/
|
||||
|
||||
#include "ringbuffer.h"
|
||||
|
||||
#include <string.h>
|
||||
|
||||
namespace ringbuffer
|
||||
{
|
||||
namespace ringbuffer {
|
||||
|
||||
RingBuffer::RingBuffer(unsigned num_items, size_t item_size) :
|
||||
_num_items(num_items),
|
||||
_item_size(item_size),
|
||||
_buf(new char[(_num_items + 1) * item_size]),
|
||||
_head(_num_items),
|
||||
_tail(_num_items)
|
||||
{}
|
||||
RingBuffer::RingBuffer(unsigned num_items, size_t item_size)
|
||||
: _num_items(num_items),
|
||||
_item_size(item_size),
|
||||
_buf(new char[(_num_items + 1) * item_size]),
|
||||
_head(_num_items),
|
||||
_tail(_num_items) {}
|
||||
|
||||
RingBuffer::~RingBuffer()
|
||||
{
|
||||
delete[] _buf;
|
||||
}
|
||||
RingBuffer::~RingBuffer() { delete[] _buf; }
|
||||
|
||||
unsigned
|
||||
RingBuffer::_next(unsigned index)
|
||||
{
|
||||
return (0 == index) ? _num_items : (index - 1);
|
||||
}
|
||||
unsigned RingBuffer::_next(unsigned index) { return (0 == index) ? _num_items : (index - 1); }
|
||||
|
||||
bool
|
||||
RingBuffer::empty()
|
||||
{
|
||||
return _tail == _head;
|
||||
}
|
||||
bool RingBuffer::empty() { return _tail == _head; }
|
||||
|
||||
bool
|
||||
RingBuffer::full()
|
||||
{
|
||||
return _next(_head) == _tail;
|
||||
}
|
||||
bool RingBuffer::full() { return _next(_head) == _tail; }
|
||||
|
||||
unsigned
|
||||
RingBuffer::size()
|
||||
{
|
||||
return (_buf != nullptr) ? _num_items : 0;
|
||||
}
|
||||
unsigned RingBuffer::size() { return (_buf != nullptr) ? _num_items : 0; }
|
||||
|
||||
void
|
||||
RingBuffer::flush()
|
||||
{
|
||||
void RingBuffer::flush() {
|
||||
while (!empty()) {
|
||||
get(nullptr);
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
RingBuffer::put(const void *val, size_t val_size)
|
||||
{
|
||||
bool RingBuffer::put(const void *val, size_t val_size) {
|
||||
unsigned next = _next(_head);
|
||||
|
||||
if (next != _tail) {
|
||||
@@ -107,69 +83,27 @@ RingBuffer::put(const void *val, size_t val_size)
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
RingBuffer::put(int8_t val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(int8_t val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::put(uint8_t val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(uint8_t val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::put(int16_t val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(int16_t val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::put(uint16_t val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(uint16_t val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::put(int32_t val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(int32_t val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::put(uint32_t val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(uint32_t val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::put(int64_t val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(int64_t val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::put(uint64_t val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(uint64_t val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::put(float val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(float val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::put(double val)
|
||||
{
|
||||
return put(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::put(double val) { return put(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(const void *val, size_t val_size)
|
||||
{
|
||||
bool RingBuffer::force(const void *val, size_t val_size) {
|
||||
bool overwrote = false;
|
||||
|
||||
for (;;) {
|
||||
@@ -184,69 +118,27 @@ RingBuffer::force(const void *val, size_t val_size)
|
||||
return overwrote;
|
||||
}
|
||||
|
||||
bool
|
||||
RingBuffer::force(int8_t val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(int8_t val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(uint8_t val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(uint8_t val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(int16_t val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(int16_t val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(uint16_t val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(uint16_t val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(int32_t val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(int32_t val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(uint32_t val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(uint32_t val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(int64_t val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(int64_t val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(uint64_t val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(uint64_t val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(float val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(float val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::force(double val)
|
||||
{
|
||||
return force(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::force(double val) { return force(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(void *val, size_t val_size)
|
||||
{
|
||||
bool RingBuffer::get(void *val, size_t val_size) {
|
||||
if (_tail != _head) {
|
||||
unsigned candidate;
|
||||
unsigned next;
|
||||
@@ -277,69 +169,27 @@ RingBuffer::get(void *val, size_t val_size)
|
||||
}
|
||||
}
|
||||
|
||||
bool
|
||||
RingBuffer::get(int8_t &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(int8_t &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(uint8_t &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(uint8_t &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(int16_t &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(int16_t &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(uint16_t &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(uint16_t &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(int32_t &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(int32_t &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(uint32_t &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(uint32_t &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(int64_t &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(int64_t &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(uint64_t &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(uint64_t &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(float &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(float &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
bool
|
||||
RingBuffer::get(double &val)
|
||||
{
|
||||
return get(&val, sizeof(val));
|
||||
}
|
||||
bool RingBuffer::get(double &val) { return get(&val, sizeof(val)); }
|
||||
|
||||
unsigned
|
||||
RingBuffer::space()
|
||||
{
|
||||
unsigned RingBuffer::space() {
|
||||
unsigned tail, head;
|
||||
|
||||
/*
|
||||
@@ -358,9 +208,7 @@ RingBuffer::space()
|
||||
return (tail >= head) ? (_num_items - (tail - head)) : (head - tail - 1);
|
||||
}
|
||||
|
||||
unsigned
|
||||
RingBuffer::count()
|
||||
{
|
||||
unsigned RingBuffer::count() {
|
||||
/*
|
||||
* Note that due to the conservative nature of space(), this may
|
||||
* over-estimate the number of items in the buffer.
|
||||
@@ -368,11 +216,9 @@ RingBuffer::count()
|
||||
return _num_items - space();
|
||||
}
|
||||
|
||||
bool
|
||||
RingBuffer::resize(unsigned new_size)
|
||||
{
|
||||
bool RingBuffer::resize(unsigned new_size) {
|
||||
char *old_buffer;
|
||||
char *new_buffer = new char [(new_size + 1) * _item_size];
|
||||
char *new_buffer = new char[(new_size + 1) * _item_size];
|
||||
|
||||
if (new_buffer == nullptr) {
|
||||
return false;
|
||||
@@ -387,16 +233,9 @@ RingBuffer::resize(unsigned new_size)
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
RingBuffer::print_info(const char *name)
|
||||
{
|
||||
printf("%s %u/%lu (%u/%u @ %p)\n",
|
||||
name,
|
||||
_num_items,
|
||||
(unsigned long)_num_items * _item_size,
|
||||
_head,
|
||||
_tail,
|
||||
void RingBuffer::print_info(const char *name) {
|
||||
printf("%s %u/%lu (%u/%u @ %p)\n", name, _num_items, (unsigned long)_num_items * _item_size, _head, _tail,
|
||||
_buf);
|
||||
}
|
||||
|
||||
} // namespace ringbuffer
|
||||
} // namespace ringbuffer
|
||||
|
||||
@@ -43,11 +43,9 @@
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
namespace ringbuffer __EXPORT
|
||||
{
|
||||
namespace ringbuffer __EXPORT {
|
||||
|
||||
class RingBuffer
|
||||
{
|
||||
class RingBuffer {
|
||||
public:
|
||||
RingBuffer(unsigned num_items, size_t item_size);
|
||||
virtual ~RingBuffer();
|
||||
@@ -58,18 +56,18 @@ public:
|
||||
* @param val Item to put
|
||||
* @return true if the item was put, false if the buffer is full
|
||||
*/
|
||||
bool put(const void *val, size_t val_size = 0);
|
||||
bool put(const void *val, size_t val_size = 0);
|
||||
|
||||
bool put(int8_t val);
|
||||
bool put(uint8_t val);
|
||||
bool put(int16_t val);
|
||||
bool put(uint16_t val);
|
||||
bool put(int32_t val);
|
||||
bool put(uint32_t val);
|
||||
bool put(int64_t val);
|
||||
bool put(uint64_t val);
|
||||
bool put(float val);
|
||||
bool put(double val);
|
||||
bool put(int8_t val);
|
||||
bool put(uint8_t val);
|
||||
bool put(int16_t val);
|
||||
bool put(uint16_t val);
|
||||
bool put(int32_t val);
|
||||
bool put(uint32_t val);
|
||||
bool put(int64_t val);
|
||||
bool put(uint64_t val);
|
||||
bool put(float val);
|
||||
bool put(double val);
|
||||
|
||||
/**
|
||||
* Force an item into the buffer, discarding an older item if there is not space.
|
||||
@@ -77,18 +75,18 @@ public:
|
||||
* @param val Item to put
|
||||
* @return true if an item was discarded to make space
|
||||
*/
|
||||
bool force(const void *val, size_t val_size = 0);
|
||||
bool force(const void *val, size_t val_size = 0);
|
||||
|
||||
bool force(int8_t val);
|
||||
bool force(uint8_t val);
|
||||
bool force(int16_t val);
|
||||
bool force(uint16_t val);
|
||||
bool force(int32_t val);
|
||||
bool force(uint32_t val);
|
||||
bool force(int64_t val);
|
||||
bool force(uint64_t val);
|
||||
bool force(float val);
|
||||
bool force(double val);
|
||||
bool force(int8_t val);
|
||||
bool force(uint8_t val);
|
||||
bool force(int16_t val);
|
||||
bool force(uint16_t val);
|
||||
bool force(int32_t val);
|
||||
bool force(uint32_t val);
|
||||
bool force(int64_t val);
|
||||
bool force(uint64_t val);
|
||||
bool force(float val);
|
||||
bool force(double val);
|
||||
|
||||
/**
|
||||
* Get an item from the buffer.
|
||||
@@ -96,18 +94,18 @@ public:
|
||||
* @param val Item that was gotten
|
||||
* @return true if an item was got, false if the buffer was empty.
|
||||
*/
|
||||
bool get(void *val, size_t val_size = 0);
|
||||
bool get(void *val, size_t val_size = 0);
|
||||
|
||||
bool get(int8_t &val);
|
||||
bool get(uint8_t &val);
|
||||
bool get(int16_t &val);
|
||||
bool get(uint16_t &val);
|
||||
bool get(int32_t &val);
|
||||
bool get(uint32_t &val);
|
||||
bool get(int64_t &val);
|
||||
bool get(uint64_t &val);
|
||||
bool get(float &val);
|
||||
bool get(double &val);
|
||||
bool get(int8_t &val);
|
||||
bool get(uint8_t &val);
|
||||
bool get(int16_t &val);
|
||||
bool get(uint16_t &val);
|
||||
bool get(int32_t &val);
|
||||
bool get(uint32_t &val);
|
||||
bool get(int64_t &val);
|
||||
bool get(uint64_t &val);
|
||||
bool get(float &val);
|
||||
bool get(double &val);
|
||||
|
||||
/*
|
||||
* Get the number of slots free in the buffer.
|
||||
@@ -115,7 +113,7 @@ public:
|
||||
* @return The number of items that can be put into the buffer before
|
||||
* it becomes full.
|
||||
*/
|
||||
unsigned space(void);
|
||||
unsigned space(void);
|
||||
|
||||
/*
|
||||
* Get the number of items in the buffer.
|
||||
@@ -123,28 +121,28 @@ public:
|
||||
* @return The number of items that can be got from the buffer before
|
||||
* it becomes empty.
|
||||
*/
|
||||
unsigned count(void);
|
||||
unsigned count(void);
|
||||
|
||||
/*
|
||||
* Returns true if the buffer is empty.
|
||||
*/
|
||||
bool empty();
|
||||
bool empty();
|
||||
|
||||
/*
|
||||
* Returns true if the buffer is full.
|
||||
*/
|
||||
bool full();
|
||||
bool full();
|
||||
|
||||
/*
|
||||
* Returns the capacity of the buffer, or zero if the buffer could
|
||||
* not be allocated.
|
||||
*/
|
||||
unsigned size();
|
||||
unsigned size();
|
||||
|
||||
/*
|
||||
* Empties the buffer.
|
||||
*/
|
||||
void flush();
|
||||
void flush();
|
||||
|
||||
/*
|
||||
* resize the buffer. This is unsafe to be called while
|
||||
@@ -155,25 +153,25 @@ public:
|
||||
* @return true if the resize succeeds, false if
|
||||
* not (allocation error)
|
||||
*/
|
||||
bool resize(unsigned new_size);
|
||||
bool resize(unsigned new_size);
|
||||
|
||||
/*
|
||||
* printf() some info on the buffer
|
||||
*/
|
||||
void print_info(const char *name);
|
||||
void print_info(const char *name);
|
||||
|
||||
private:
|
||||
unsigned _num_items;
|
||||
const size_t _item_size;
|
||||
char *_buf;
|
||||
volatile unsigned _head; /**< insertion point in _item_size units */
|
||||
volatile unsigned _tail; /**< removal point in _item_size units */
|
||||
unsigned _num_items;
|
||||
const size_t _item_size;
|
||||
char *_buf;
|
||||
volatile unsigned _head; /**< insertion point in _item_size units */
|
||||
volatile unsigned _tail; /**< removal point in _item_size units */
|
||||
|
||||
unsigned _next(unsigned index);
|
||||
unsigned _next(unsigned index);
|
||||
|
||||
/* we don't want this class to be copied */
|
||||
RingBuffer(const RingBuffer &);
|
||||
RingBuffer operator=(const RingBuffer &);
|
||||
};
|
||||
|
||||
} // namespace ringbuffer
|
||||
} // namespace __EXPORT
|
||||
|
||||
@@ -39,97 +39,88 @@
|
||||
* @author Dennis Shtatnov <densht@gmail.com>
|
||||
*/
|
||||
|
||||
#include "syslink.h"
|
||||
|
||||
#include <px4_platform_common/defines.h>
|
||||
#include <fcntl.h>
|
||||
#include <poll.h>
|
||||
#include <px4_platform_common/defines.h>
|
||||
#include <stdio.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <systemlib/err.h>
|
||||
#include <poll.h>
|
||||
#include <termios.h>
|
||||
|
||||
|
||||
#include "syslink.h"
|
||||
|
||||
|
||||
const char *syslink_magic = "\xbc\xcf";
|
||||
|
||||
void syslink_parse_init(syslink_parse_state *state)
|
||||
{
|
||||
void syslink_parse_init(syslink_parse_state *state) {
|
||||
state->state = SYSLINK_STATE_START;
|
||||
state->index = 0;
|
||||
}
|
||||
|
||||
|
||||
int syslink_parse_char(syslink_parse_state *state, char c, syslink_message_t *msg)
|
||||
{
|
||||
|
||||
int syslink_parse_char(syslink_parse_state *state, char c, syslink_message_t *msg) {
|
||||
switch (state->state) {
|
||||
case SYSLINK_STATE_START:
|
||||
if (c == syslink_magic[state->index]) {
|
||||
state->index++;
|
||||
case SYSLINK_STATE_START:
|
||||
if (c == syslink_magic[state->index]) {
|
||||
state->index++;
|
||||
|
||||
} else {
|
||||
state->index = 0;
|
||||
}
|
||||
} else {
|
||||
state->index = 0;
|
||||
}
|
||||
|
||||
if (syslink_magic[state->index] == '\x00') {
|
||||
state->state = SYSLINK_STATE_TYPE;
|
||||
}
|
||||
if (syslink_magic[state->index] == '\x00') {
|
||||
state->state = SYSLINK_STATE_TYPE;
|
||||
}
|
||||
|
||||
break;
|
||||
break;
|
||||
|
||||
case SYSLINK_STATE_TYPE:
|
||||
msg->type = c;
|
||||
state->state = SYSLINK_STATE_LENGTH;
|
||||
break;
|
||||
case SYSLINK_STATE_TYPE:
|
||||
msg->type = c;
|
||||
state->state = SYSLINK_STATE_LENGTH;
|
||||
break;
|
||||
|
||||
case SYSLINK_STATE_LENGTH:
|
||||
msg->length = c;
|
||||
case SYSLINK_STATE_LENGTH:
|
||||
msg->length = c;
|
||||
|
||||
if (c > SYSLINK_MAX_DATA_LEN) { // Too long
|
||||
state->state = SYSLINK_STATE_START;
|
||||
if (c > SYSLINK_MAX_DATA_LEN) { // Too long
|
||||
state->state = SYSLINK_STATE_START;
|
||||
|
||||
} else {
|
||||
state->state = c > 0 ? SYSLINK_STATE_DATA : SYSLINK_STATE_CKSUM;
|
||||
}
|
||||
} else {
|
||||
state->state = c > 0 ? SYSLINK_STATE_DATA : SYSLINK_STATE_CKSUM;
|
||||
}
|
||||
|
||||
state->index = 0;
|
||||
break;
|
||||
|
||||
case SYSLINK_STATE_DATA:
|
||||
msg->data[state->index++] = c;
|
||||
|
||||
if (state->index >= msg->length) {
|
||||
state->state = SYSLINK_STATE_CKSUM;
|
||||
state->index = 0;
|
||||
syslink_compute_cksum(msg);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case SYSLINK_STATE_CKSUM:
|
||||
if (c != msg->cksum[state->index]) {
|
||||
PX4_INFO("Bad checksum");
|
||||
state->state = SYSLINK_STATE_START;
|
||||
state->index = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
state->index++;
|
||||
case SYSLINK_STATE_DATA:
|
||||
msg->data[state->index++] = c;
|
||||
|
||||
if (state->index >= (int)sizeof(msg->cksum)) {
|
||||
state->state = SYSLINK_STATE_START;
|
||||
state->index = 0;
|
||||
return 1;
|
||||
}
|
||||
if (state->index >= msg->length) {
|
||||
state->state = SYSLINK_STATE_CKSUM;
|
||||
state->index = 0;
|
||||
syslink_compute_cksum(msg);
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
break;
|
||||
case SYSLINK_STATE_CKSUM:
|
||||
if (c != msg->cksum[state->index]) {
|
||||
PX4_INFO("Bad checksum");
|
||||
state->state = SYSLINK_STATE_START;
|
||||
state->index = 0;
|
||||
break;
|
||||
}
|
||||
|
||||
state->index++;
|
||||
|
||||
if (state->index >= (int)sizeof(msg->cksum)) {
|
||||
state->state = SYSLINK_STATE_START;
|
||||
state->index = 0;
|
||||
return 1;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -137,8 +128,7 @@ int syslink_parse_char(syslink_parse_state *state, char c, syslink_message_t *ms
|
||||
A := A + D[i]
|
||||
B := B + A
|
||||
*/
|
||||
void syslink_compute_cksum(syslink_message_t *msg)
|
||||
{
|
||||
void syslink_compute_cksum(syslink_message_t *msg) {
|
||||
uint8_t a = 0, b = 0;
|
||||
uint8_t *Di = (uint8_t *)msg, *end = Di + (2 + msg->length) * sizeof(uint8_t);
|
||||
|
||||
|
||||
@@ -35,40 +35,38 @@
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
extern const char *syslink_magic;
|
||||
|
||||
#define SYSLINK_GROUP 0xF0
|
||||
#define SYSLINK_GROUP 0xF0
|
||||
|
||||
#define SYSLINK_RADIO 0x00
|
||||
#define SYSLINK_RADIO_RAW 0x00
|
||||
#define SYSLINK_RADIO_CHANNEL 0x01
|
||||
#define SYSLINK_RADIO_DATARATE 0x02
|
||||
#define SYSLINK_RADIO_CONTWAVE 0x03
|
||||
#define SYSLINK_RADIO_RSSI 0x04
|
||||
#define SYSLINK_RADIO_ADDRESS 0x05
|
||||
#define SYSLINK_RADIO 0x00
|
||||
#define SYSLINK_RADIO_RAW 0x00
|
||||
#define SYSLINK_RADIO_CHANNEL 0x01
|
||||
#define SYSLINK_RADIO_DATARATE 0x02
|
||||
#define SYSLINK_RADIO_CONTWAVE 0x03
|
||||
#define SYSLINK_RADIO_RSSI 0x04
|
||||
#define SYSLINK_RADIO_ADDRESS 0x05
|
||||
|
||||
#define SYSLINK_PM 0x10
|
||||
#define SYSLINK_PM_SOURCE 0x10
|
||||
#define SYSLINK_PM_ONOFF_SWITCHOFF 0x11
|
||||
#define SYSLINK_PM_BATTERY_VOLTAGE 0x12
|
||||
#define SYSLINK_PM_BATTERY_STATE 0x13
|
||||
#define SYSLINK_PM_BATTERY_AUTOUPDATE 0x14
|
||||
#define SYSLINK_PM 0x10
|
||||
#define SYSLINK_PM_SOURCE 0x10
|
||||
#define SYSLINK_PM_ONOFF_SWITCHOFF 0x11
|
||||
#define SYSLINK_PM_BATTERY_VOLTAGE 0x12
|
||||
#define SYSLINK_PM_BATTERY_STATE 0x13
|
||||
#define SYSLINK_PM_BATTERY_AUTOUPDATE 0x14
|
||||
|
||||
#define SYSLINK_OW 0x20
|
||||
#define SYSLINK_OW_SCAN 0x20
|
||||
#define SYSLINK_OW_GETINFO 0x21
|
||||
#define SYSLINK_OW_READ 0x22
|
||||
#define SYSLINK_OW_WRITE 0x23
|
||||
#define SYSLINK_OW 0x20
|
||||
#define SYSLINK_OW_SCAN 0x20
|
||||
#define SYSLINK_OW_GETINFO 0x21
|
||||
#define SYSLINK_OW_READ 0x22
|
||||
#define SYSLINK_OW_WRITE 0x23
|
||||
|
||||
// Limited by the CRTP packet which is limited by the ESB protocol used by the NRF
|
||||
#define SYSLINK_MAX_DATA_LEN 32
|
||||
#define SYSLINK_MAX_DATA_LEN 32
|
||||
|
||||
#define SYSLINK_RADIO_RATE_250K 0
|
||||
#define SYSLINK_RADIO_RATE_1M 1
|
||||
#define SYSLINK_RADIO_RATE_2M 2
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint8_t type;
|
||||
uint8_t length;
|
||||
@@ -76,17 +74,16 @@ typedef struct {
|
||||
uint8_t cksum[2];
|
||||
} __attribute__((packed)) syslink_message_t;
|
||||
|
||||
|
||||
#define OW_SIZE 112
|
||||
#define OW_READ_BLOCK 29
|
||||
#define OW_WRITE_BLOCK 26 // TODO: Use even, but can be up to 27
|
||||
#define OW_WRITE_BLOCK 26 // TODO: Use even, but can be up to 27
|
||||
|
||||
typedef struct {
|
||||
uint8_t nmems;
|
||||
} __attribute__((packed)) syslink_ow_scan_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t family; // Should by 0x0D for most chips
|
||||
uint8_t family; // Should by 0x0D for most chips
|
||||
uint8_t sn[6];
|
||||
uint8_t crc;
|
||||
} __attribute__((packed)) syslink_ow_id_t;
|
||||
@@ -109,7 +106,6 @@ typedef struct {
|
||||
uint8_t data[OW_WRITE_BLOCK];
|
||||
} __attribute__((packed)) syslink_ow_write_t;
|
||||
|
||||
|
||||
typedef enum {
|
||||
SYSLINK_STATE_START = 0,
|
||||
SYSLINK_STATE_TYPE,
|
||||
@@ -118,13 +114,12 @@ typedef enum {
|
||||
SYSLINK_STATE_CKSUM
|
||||
} SYSLINK_STATE;
|
||||
|
||||
typedef struct {
|
||||
typedef struct {
|
||||
SYSLINK_STATE state;
|
||||
int index;
|
||||
|
||||
} syslink_parse_state;
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
@@ -31,33 +31,27 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
/**
|
||||
* @file syslink_bridge.cpp
|
||||
*
|
||||
* Character device for talking to the radio as a plain serial port
|
||||
*/
|
||||
|
||||
#include "syslink_main.h"
|
||||
#include <cstring>
|
||||
|
||||
#include "syslink_main.h"
|
||||
|
||||
|
||||
SyslinkBridge::SyslinkBridge(Syslink *link) :
|
||||
CDev("/dev/bridge0"),
|
||||
_link(link),
|
||||
_readbuffer(16, sizeof(crtp_message_t))
|
||||
{
|
||||
SyslinkBridge::SyslinkBridge(Syslink *link)
|
||||
: CDev("/dev/bridge0"), _link(link), _readbuffer(16, sizeof(crtp_message_t)) {
|
||||
_msg_to_send.header = 0;
|
||||
_msg_to_send.size = sizeof(_msg_to_send.header);
|
||||
_msg_to_send.port = CRTP_PORT_MAVLINK;
|
||||
_msg_to_send_size_remaining = CRTP_MAX_DATA_SIZE - 1; // to send 30 bytes of data
|
||||
//ideally _msg_to_send.data size should be CRTP_MAX_DATA_SIZE but cfbridge does not receive 31 bytes of data due to a bug somewhere
|
||||
_msg_to_send_size_remaining = CRTP_MAX_DATA_SIZE - 1; // to send 30 bytes of data
|
||||
// ideally _msg_to_send.data size should be CRTP_MAX_DATA_SIZE but cfbridge does not receive 31 bytes of data
|
||||
// due to a bug somewhere
|
||||
}
|
||||
|
||||
int
|
||||
SyslinkBridge::init()
|
||||
{
|
||||
int SyslinkBridge::init() {
|
||||
int ret = CDev::init();
|
||||
|
||||
/* if init failed, bail now */
|
||||
@@ -66,13 +60,10 @@ SyslinkBridge::init()
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
pollevent_t
|
||||
SyslinkBridge::poll_state(struct file *filp)
|
||||
{
|
||||
pollevent_t SyslinkBridge::poll_state(struct file *filp) {
|
||||
pollevent_t state = 0;
|
||||
|
||||
if (!_readbuffer.empty()) {
|
||||
@@ -86,9 +77,7 @@ SyslinkBridge::poll_state(struct file *filp)
|
||||
return state;
|
||||
}
|
||||
|
||||
ssize_t
|
||||
SyslinkBridge::read(struct file *filp, char *buffer, size_t buflen)
|
||||
{
|
||||
ssize_t SyslinkBridge::read(struct file *filp, char *buffer, size_t buflen) {
|
||||
int nread = 0;
|
||||
crtp_message_t msg;
|
||||
|
||||
@@ -105,13 +94,10 @@ SyslinkBridge::read(struct file *filp, char *buffer, size_t buflen)
|
||||
return nread;
|
||||
}
|
||||
|
||||
ssize_t
|
||||
SyslinkBridge::write(struct file *filp, const char *buffer, size_t buflen)
|
||||
{
|
||||
ssize_t SyslinkBridge::write(struct file *filp, const char *buffer, size_t buflen) {
|
||||
int buflen_rem = buflen;
|
||||
|
||||
while (buflen_rem > 0) {
|
||||
|
||||
int datasize = MIN(_msg_to_send_size_remaining, buflen_rem);
|
||||
_msg_to_send.size += datasize;
|
||||
memcpy(&_msg_to_send.data[CRTP_MAX_DATA_SIZE - 1 - _msg_to_send_size_remaining], buffer, datasize);
|
||||
@@ -120,9 +106,7 @@ SyslinkBridge::write(struct file *filp, const char *buffer, size_t buflen)
|
||||
_msg_to_send_size_remaining -= datasize;
|
||||
buflen_rem -= datasize;
|
||||
|
||||
|
||||
if (_msg_to_send_size_remaining == 0) {
|
||||
|
||||
if (_link->_writebuffer.force(&_msg_to_send, sizeof(crtp_message_t))) {
|
||||
PX4_WARN("write buffer overflow");
|
||||
}
|
||||
@@ -135,28 +119,22 @@ SyslinkBridge::write(struct file *filp, const char *buffer, size_t buflen)
|
||||
return buflen;
|
||||
}
|
||||
|
||||
int
|
||||
SyslinkBridge::ioctl(struct file *filp, int cmd, unsigned long arg)
|
||||
{
|
||||
int SyslinkBridge::ioctl(struct file *filp, int cmd, unsigned long arg) {
|
||||
// All termios commands should be silently ignored as they are handled
|
||||
|
||||
switch (cmd) {
|
||||
case FIONSPACE:
|
||||
*((int *)arg) = _link->_writebuffer.space() * CRTP_MAX_DATA_SIZE;
|
||||
return 0;
|
||||
|
||||
case FIONSPACE:
|
||||
*((int *) arg) = _link->_writebuffer.space() * CRTP_MAX_DATA_SIZE;
|
||||
return 0;
|
||||
|
||||
default:
|
||||
/* give it to the superclass */
|
||||
CDev::ioctl(filp, cmd, arg);
|
||||
return 0;
|
||||
default:
|
||||
/* give it to the superclass */
|
||||
CDev::ioctl(filp, cmd, arg);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
SyslinkBridge::pipe_message(crtp_message_t *msg)
|
||||
{
|
||||
void SyslinkBridge::pipe_message(crtp_message_t *msg) {
|
||||
_readbuffer.force(msg, sizeof(msg->size) + msg->size);
|
||||
poll_notify(POLLIN);
|
||||
}
|
||||
|
||||
@@ -36,35 +36,29 @@
|
||||
* Entry point for syslink module used to communicate with the NRF module on a Crazyflie
|
||||
*/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/tasks.h>
|
||||
#include <px4_platform_common/posix.h>
|
||||
#include <px4_platform_common/defines.h>
|
||||
|
||||
#include <unistd.h>
|
||||
#include <stdio.h>
|
||||
#include <poll.h>
|
||||
#include <string.h>
|
||||
#include <fcntl.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <termios.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <mqueue.h>
|
||||
|
||||
#include <drivers/drv_board_led.h>
|
||||
|
||||
#include <systemlib/err.h>
|
||||
#include "syslink_main.h"
|
||||
|
||||
#include <board_config.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <fcntl.h>
|
||||
#include <mqueue.h>
|
||||
#include <poll.h>
|
||||
#include <px4_platform_common/defines.h>
|
||||
#include <px4_platform_common/posix.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/tasks.h>
|
||||
#include <stdio.h>
|
||||
#include <string.h>
|
||||
#include <sys/ioctl.h>
|
||||
#include <sys/stat.h>
|
||||
#include <sys/types.h>
|
||||
#include <systemlib/err.h>
|
||||
#include <termios.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "crtp.h"
|
||||
#include "syslink_main.h"
|
||||
#include "drv_deck.h"
|
||||
|
||||
|
||||
|
||||
__BEGIN_DECLS
|
||||
extern void led_init(void);
|
||||
extern void led_on(int led);
|
||||
@@ -72,58 +66,46 @@ extern void led_off(int led);
|
||||
extern void led_toggle(int led);
|
||||
__END_DECLS
|
||||
|
||||
extern "C" { __EXPORT int syslink_main(int argc, char *argv[]); }
|
||||
|
||||
extern "C" {
|
||||
__EXPORT int syslink_main(int argc, char *argv[]);
|
||||
}
|
||||
|
||||
Syslink *g_syslink = nullptr;
|
||||
|
||||
Syslink::Syslink() :
|
||||
pktrate(0),
|
||||
nullrate(0),
|
||||
rxrate(0),
|
||||
txrate(0),
|
||||
_syslink_task(-1),
|
||||
_task_running(false),
|
||||
_bootloader_mode(false),
|
||||
_count(0),
|
||||
_null_count(0),
|
||||
_count_in(0),
|
||||
_count_out(0),
|
||||
_lasttime(0),
|
||||
_lasttxtime(0),
|
||||
_lastrxtime(0),
|
||||
_fd(0),
|
||||
_queue(2, sizeof(syslink_message_t)),
|
||||
_writebuffer(16, sizeof(crtp_message_t)),
|
||||
_rssi(input_rc_s::RSSI_MAX),
|
||||
_bstate(BAT_DISCHARGING)
|
||||
{
|
||||
Syslink::Syslink()
|
||||
: pktrate(0),
|
||||
nullrate(0),
|
||||
rxrate(0),
|
||||
txrate(0),
|
||||
_syslink_task(-1),
|
||||
_task_running(false),
|
||||
_bootloader_mode(false),
|
||||
_count(0),
|
||||
_null_count(0),
|
||||
_count_in(0),
|
||||
_count_out(0),
|
||||
_lasttime(0),
|
||||
_lasttxtime(0),
|
||||
_lastrxtime(0),
|
||||
_fd(0),
|
||||
_queue(2, sizeof(syslink_message_t)),
|
||||
_writebuffer(16, sizeof(crtp_message_t)),
|
||||
_rssi(input_rc_s::RSSI_MAX),
|
||||
_bstate(BAT_DISCHARGING) {
|
||||
px4_sem_init(&memory_sem, 0, 0);
|
||||
/* memory_sem use case is a signal */
|
||||
px4_sem_setprotocol(&memory_sem, SEM_PRIO_NONE);
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
Syslink::start()
|
||||
{
|
||||
int Syslink::start() {
|
||||
_task_running = true;
|
||||
_syslink_task = px4_task_spawn_cmd(
|
||||
"syslink",
|
||||
SCHED_DEFAULT,
|
||||
SCHED_PRIORITY_DEFAULT,
|
||||
1500,
|
||||
Syslink::task_main_trampoline,
|
||||
NULL
|
||||
);
|
||||
_syslink_task = px4_task_spawn_cmd("syslink", SCHED_DEFAULT, SCHED_PRIORITY_DEFAULT, 1500,
|
||||
Syslink::task_main_trampoline, NULL);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int
|
||||
Syslink::set_datarate(uint8_t datarate)
|
||||
{
|
||||
int Syslink::set_datarate(uint8_t datarate) {
|
||||
syslink_message_t msg;
|
||||
msg.type = SYSLINK_RADIO_DATARATE;
|
||||
msg.length = 1;
|
||||
@@ -131,9 +113,7 @@ Syslink::set_datarate(uint8_t datarate)
|
||||
return send_message(&msg);
|
||||
}
|
||||
|
||||
int
|
||||
Syslink::set_channel(uint8_t channel)
|
||||
{
|
||||
int Syslink::set_channel(uint8_t channel) {
|
||||
syslink_message_t msg;
|
||||
msg.type = SYSLINK_RADIO_CHANNEL;
|
||||
msg.length = 1;
|
||||
@@ -141,9 +121,7 @@ Syslink::set_channel(uint8_t channel)
|
||||
return send_message(&msg);
|
||||
}
|
||||
|
||||
int
|
||||
Syslink::set_address(uint64_t addr)
|
||||
{
|
||||
int Syslink::set_address(uint64_t addr) {
|
||||
syslink_message_t msg;
|
||||
msg.type = SYSLINK_RADIO_ADDRESS;
|
||||
msg.length = 5;
|
||||
@@ -151,9 +129,7 @@ Syslink::set_address(uint64_t addr)
|
||||
return send_message(&msg);
|
||||
}
|
||||
|
||||
int
|
||||
Syslink::send_queued_raw_message()
|
||||
{
|
||||
int Syslink::send_queued_raw_message() {
|
||||
if (_writebuffer.empty()) {
|
||||
return 0;
|
||||
}
|
||||
@@ -170,16 +146,12 @@ Syslink::send_queued_raw_message()
|
||||
return send_message(&msg);
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
Syslink::update_params(bool force_set)
|
||||
{
|
||||
void Syslink::update_params(bool force_set) {
|
||||
param_t _param_radio_channel = param_find("SLNK_RADIO_CHAN");
|
||||
param_t _param_radio_rate = param_find("SLNK_RADIO_RATE");
|
||||
param_t _param_radio_addr1 = param_find("SLNK_RADIO_ADDR1");
|
||||
param_t _param_radio_addr2 = param_find("SLNK_RADIO_ADDR2");
|
||||
|
||||
|
||||
// reading parameter values into temp variables
|
||||
|
||||
int32_t channel, rate, addr1, addr2;
|
||||
@@ -193,7 +165,6 @@ Syslink::update_params(bool force_set)
|
||||
memcpy(&addr, &addr2, 4);
|
||||
memcpy(((char *)&addr) + 4, &addr1, 4);
|
||||
|
||||
|
||||
hrt_abstime t = hrt_absolute_time();
|
||||
|
||||
// request updates if needed
|
||||
@@ -221,9 +192,7 @@ Syslink::update_params(bool force_set)
|
||||
}
|
||||
|
||||
// 1M 8N1 serial connection to NRF51
|
||||
int
|
||||
Syslink::open_serial(const char *dev)
|
||||
{
|
||||
int Syslink::open_serial(const char *dev) {
|
||||
#ifndef B1000000
|
||||
#define B1000000 1000000
|
||||
#endif
|
||||
@@ -250,7 +219,6 @@ Syslink::open_serial(const char *dev)
|
||||
// Disable hardware flow control
|
||||
config.c_cflag &= ~CRTSCTS;
|
||||
|
||||
|
||||
/* Set baud rate */
|
||||
if (cfsetispeed(&config, rate) < 0 || cfsetospeed(&config, rate) < 0) {
|
||||
warnx("ERR SET BAUD %s: %d\n", dev, termios_state);
|
||||
@@ -267,18 +235,12 @@ Syslink::open_serial(const char *dev)
|
||||
return fd;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int
|
||||
Syslink::task_main_trampoline(int argc, char *argv[])
|
||||
{
|
||||
int Syslink::task_main_trampoline(int argc, char *argv[]) {
|
||||
g_syslink->task_main();
|
||||
return 0;
|
||||
}
|
||||
|
||||
void
|
||||
Syslink::task_main()
|
||||
{
|
||||
void Syslink::task_main() {
|
||||
_bridge = new SyslinkBridge(this);
|
||||
_bridge->init();
|
||||
|
||||
@@ -296,7 +258,6 @@ Syslink::task_main()
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/* Set non-blocking */
|
||||
/*
|
||||
int flags = fcntl(_fd, F_GETFL, 0);
|
||||
@@ -323,7 +284,7 @@ Syslink::task_main()
|
||||
|
||||
syslink_parse_init(&state);
|
||||
|
||||
//setup initial parameters
|
||||
// setup initial parameters
|
||||
update_params(true);
|
||||
|
||||
while (_task_running) {
|
||||
@@ -337,8 +298,7 @@ Syslink::task_main()
|
||||
/* this is seriously bad - should be an emergency */
|
||||
if (error_counter < 10 || error_counter % 50 == 0) {
|
||||
/* use a counter to prevent flooding (and slowing us down) */
|
||||
PX4_ERR("[syslink] ERROR return value from poll(): %d"
|
||||
, poll_ret);
|
||||
PX4_ERR("[syslink] ERROR return value from poll(): %d", poll_ret);
|
||||
}
|
||||
|
||||
error_counter++;
|
||||
@@ -362,15 +322,12 @@ Syslink::task_main()
|
||||
update_params(false);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
close(_fd);
|
||||
}
|
||||
|
||||
void
|
||||
Syslink::handle_message(syslink_message_t *msg)
|
||||
{
|
||||
void Syslink::handle_message(syslink_message_t *msg) {
|
||||
hrt_abstime t = hrt_absolute_time();
|
||||
|
||||
if (t - _lasttime > 1000000) {
|
||||
@@ -391,7 +348,6 @@ Syslink::handle_message(syslink_message_t *msg)
|
||||
if (msg->type == SYSLINK_PM_ONOFF_SWITCHOFF) {
|
||||
// When the power button is hit
|
||||
} else if (msg->type == SYSLINK_PM_BATTERY_STATE) {
|
||||
|
||||
if (msg->length != 9) {
|
||||
return;
|
||||
}
|
||||
@@ -400,9 +356,9 @@ Syslink::handle_message(syslink_message_t *msg)
|
||||
int charging = flags & 1;
|
||||
int powered = flags & 2;
|
||||
|
||||
float vbat; //, iset;
|
||||
float vbat; //, iset;
|
||||
memcpy(&vbat, &msg->data[1], sizeof(float));
|
||||
//memcpy(&iset, &msg->data[5], sizeof(float));
|
||||
// memcpy(&iset, &msg->data[5], sizeof(float));
|
||||
|
||||
_battery.setConnected(true);
|
||||
_battery.updateVoltage(vbat);
|
||||
@@ -413,7 +369,8 @@ Syslink::handle_message(syslink_message_t *msg)
|
||||
_bstate = BAT_CHARGING;
|
||||
}
|
||||
|
||||
/* With the usb plugged in and battery disconnected, it appears to be charged. The voltage check ensures that a battery is connected */
|
||||
/* With the usb plugged in and battery disconnected, it appears to be charged. The voltage check ensures
|
||||
that a battery is connected */
|
||||
else if (powered && !charging && vbat > 3.7f) {
|
||||
_bstate = BAT_CHARGED;
|
||||
|
||||
@@ -422,7 +379,7 @@ Syslink::handle_message(syslink_message_t *msg)
|
||||
}
|
||||
|
||||
} else if (msg->type == SYSLINK_RADIO_RSSI) {
|
||||
uint8_t rssi = msg->data[0]; // Between 40 and 100 meaning -40 dBm to -100 dBm
|
||||
uint8_t rssi = msg->data[0]; // Between 40 and 100 meaning -40 dBm to -100 dBm
|
||||
_rssi = 140 - rssi * 100 / (100 - 40);
|
||||
|
||||
} else if (msg->type == SYSLINK_RADIO_RAW) {
|
||||
@@ -440,13 +397,12 @@ Syslink::handle_message(syslink_message_t *msg)
|
||||
PX4_INFO("GOT %" PRIu8, msg->type);
|
||||
}
|
||||
|
||||
//Send queued messages
|
||||
// Send queued messages
|
||||
if (!_queue.empty()) {
|
||||
_queue.get(msg, sizeof(syslink_message_t));
|
||||
send_message(msg);
|
||||
}
|
||||
|
||||
|
||||
float p = (t % 500000) / 500000.0f;
|
||||
|
||||
/* Use LED_GREEN for charging indicator */
|
||||
@@ -461,9 +417,7 @@ Syslink::handle_message(syslink_message_t *msg)
|
||||
}
|
||||
|
||||
/* Alternate RX/TX LEDS when transfering */
|
||||
bool rx = t - _lastrxtime < 200000,
|
||||
tx = t - _lasttxtime < 200000;
|
||||
|
||||
bool rx = t - _lastrxtime < 200000, tx = t - _lasttxtime < 200000;
|
||||
|
||||
if (rx && p < 0.25f) {
|
||||
led_on(LED_RX);
|
||||
@@ -479,7 +433,6 @@ Syslink::handle_message(syslink_message_t *msg)
|
||||
led_off(LED_TX);
|
||||
}
|
||||
|
||||
|
||||
// resend parameters if they haven't been acknowledged
|
||||
if (_params_ack[0] == 0 && t - _params_update[0] > 10000) {
|
||||
set_channel(_channel);
|
||||
@@ -492,9 +445,7 @@ Syslink::handle_message(syslink_message_t *msg)
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
Syslink::handle_radio(syslink_message_t *sys)
|
||||
{
|
||||
void Syslink::handle_radio(syslink_message_t *sys) {
|
||||
hrt_abstime t = hrt_absolute_time();
|
||||
|
||||
// record acknowlegements to parameter messages
|
||||
@@ -509,10 +460,8 @@ Syslink::handle_radio(syslink_message_t *sys)
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
Syslink::handle_raw(syslink_message_t *sys)
|
||||
{
|
||||
crtp_message_t *c = (crtp_message_t *) &sys->length;
|
||||
void Syslink::handle_raw(syslink_message_t *sys) {
|
||||
crtp_message_t *c = (crtp_message_t *)&sys->length;
|
||||
|
||||
if (CRTP_NULL(*c)) {
|
||||
if (c->size >= 3) {
|
||||
@@ -522,8 +471,7 @@ Syslink::handle_raw(syslink_message_t *sys)
|
||||
_null_count++;
|
||||
|
||||
} else if (c->port == CRTP_PORT_COMMANDER) {
|
||||
|
||||
crtp_commander *cmd = (crtp_commander *) &c->data[0];
|
||||
crtp_commander *cmd = (crtp_commander *)&c->data[0];
|
||||
|
||||
input_rc_s rc = {};
|
||||
|
||||
@@ -538,7 +486,6 @@ Syslink::handle_raw(syslink_message_t *sys)
|
||||
rc.input_source = input_rc_s::RC_INPUT_SOURCE_MAVLINK;
|
||||
rc.rssi = _rssi;
|
||||
|
||||
|
||||
double pitch = cmd->pitch, roll = cmd->roll, yaw = cmd->yaw;
|
||||
|
||||
/* channels (scaled to rc limits) */
|
||||
@@ -546,7 +493,7 @@ Syslink::handle_raw(syslink_message_t *sys)
|
||||
rc.values[1] = roll * 500 / 20 + 1500;
|
||||
rc.values[2] = yaw * 500 / 150 + 1500;
|
||||
rc.values[3] = cmd->thrust * 1000 / USHRT_MAX + 1000;
|
||||
rc.values[4] = 1000; // Dummy channel as px4 needs at least 5
|
||||
rc.values[4] = 1000; // Dummy channel as px4 needs at least 5
|
||||
|
||||
_rc_pub.publish(rc);
|
||||
|
||||
@@ -568,81 +515,76 @@ Syslink::handle_raw(syslink_message_t *sys)
|
||||
send_queued_raw_message();
|
||||
}
|
||||
|
||||
void
|
||||
Syslink::handle_bootloader(syslink_message_t *sys)
|
||||
{
|
||||
void Syslink::handle_bootloader(syslink_message_t *sys) {
|
||||
// Minimal bootloader emulation for being detectable
|
||||
// To the bitcraze utilities, the STM32 will appear to have no flashable pages
|
||||
// Upon receiving a bootloader message, all outbound packets are blocked in 'bootloader mode' due to how fragile the aforementioned utilities are to extra packets
|
||||
// Upon receiving a bootloader message, all outbound packets are blocked in 'bootloader mode' due to how fragile
|
||||
// the aforementioned utilities are to extra packets
|
||||
|
||||
crtp_message_t *c = (crtp_message_t *) &sys->length;
|
||||
crtp_message_t *c = (crtp_message_t *)&sys->length;
|
||||
|
||||
uint8_t target = c->data[0];
|
||||
uint8_t cmd = c->data[1];
|
||||
|
||||
if (target != 0xFF) { // CF2 STM32 target
|
||||
if (target != 0xFF) { // CF2 STM32 target
|
||||
return;
|
||||
}
|
||||
|
||||
_bootloader_mode = true;
|
||||
|
||||
if (cmd == 0x10) { // GET_INFO
|
||||
if (cmd == 0x10) { // GET_INFO
|
||||
|
||||
c->size = 1 + 23;
|
||||
memset(&c->data[2], 0, 21);
|
||||
c->data[22] = 0x10; // Protocol version
|
||||
c->data[22] = 0x10; // Protocol version
|
||||
send_message(sys);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
Syslink::handle_raw_other(syslink_message_t *sys)
|
||||
{
|
||||
void Syslink::handle_raw_other(syslink_message_t *sys) {
|
||||
// This function doesn't actually do anything
|
||||
// It is just here to return null responses to most standard messages
|
||||
|
||||
crtp_message_t *c = (crtp_message_t *) &sys->length;
|
||||
crtp_message_t *c = (crtp_message_t *)&sys->length;
|
||||
|
||||
if (c->port == CRTP_PORT_LOG) {
|
||||
|
||||
PX4_INFO("Log: %" PRIu8 " %" PRIu8, c->channel, c->data[0]);
|
||||
|
||||
if (c->channel == 0) { // Table of Contents Access
|
||||
if (c->channel == 0) { // Table of Contents Access
|
||||
|
||||
uint8_t cmd = c->data[0];
|
||||
|
||||
if (cmd == 0) { // GET_ITEM
|
||||
//int id = c->data[1];
|
||||
if (cmd == 0) { // GET_ITEM
|
||||
// int id = c->data[1];
|
||||
memset(&c->data[2], 0, 3);
|
||||
c->data[2] = 1; // type
|
||||
c->data[2] = 1; // type
|
||||
c->size = 1 + 5;
|
||||
send_message(sys);
|
||||
|
||||
} else if (cmd == 1) { // GET_INFO
|
||||
} else if (cmd == 1) { // GET_INFO
|
||||
memset(&c->data[1], 0, 7);
|
||||
c->size = 1 + 8;
|
||||
send_message(sys);
|
||||
}
|
||||
|
||||
} else if (c->channel == 1) { // Log control
|
||||
} else if (c->channel == 1) { // Log control
|
||||
|
||||
uint8_t cmd = c->data[0];
|
||||
|
||||
PX4_INFO("Responding to cmd: %" PRIu8, cmd);
|
||||
c->data[2] = 0; // Success
|
||||
c->data[2] = 0; // Success
|
||||
c->size = 3 + 1;
|
||||
|
||||
// resend message
|
||||
send_message(sys);
|
||||
|
||||
} else if (c->channel == 2) { // Log data
|
||||
|
||||
} else if (c->channel == 2) { // Log data
|
||||
}
|
||||
} else if (c->port == CRTP_PORT_MEM) {
|
||||
if (c->channel == 0) { // Info
|
||||
if (c->channel == 0) { // Info
|
||||
int cmd = c->data[0];
|
||||
|
||||
if (cmd == 1) { // GET_NBR_OF_MEMS
|
||||
if (cmd == 1) { // GET_NBR_OF_MEMS
|
||||
c->data[1] = 0;
|
||||
c->size = 2 + 1;
|
||||
|
||||
@@ -652,18 +594,18 @@ Syslink::handle_raw_other(syslink_message_t *sys)
|
||||
}
|
||||
|
||||
} else if (c->port == CRTP_PORT_PARAM) {
|
||||
if (c->channel == 0) { // TOC Access
|
||||
if (c->channel == 0) { // TOC Access
|
||||
// uint8_t msgId = c->data[0];
|
||||
|
||||
c->data[1] = 0; // Last parameter (id = 0)
|
||||
c->data[1] = 0; // Last parameter (id = 0)
|
||||
memset(&c->data[2], 0, 10);
|
||||
c->size = 1 + 8;
|
||||
send_message(sys);
|
||||
}
|
||||
|
||||
else if (c->channel == 1) { // Param read
|
||||
else if (c->channel == 1) { // Param read
|
||||
// 0 is ok
|
||||
c->data[1] = 0; // value
|
||||
c->data[1] = 0; // value
|
||||
c->size = 1 + 2;
|
||||
send_message(sys);
|
||||
}
|
||||
@@ -673,14 +615,13 @@ Syslink::handle_raw_other(syslink_message_t *sys)
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
Syslink::send_bytes(const void *data, size_t len)
|
||||
{
|
||||
int Syslink::send_bytes(const void *data, size_t len) {
|
||||
// TODO: This could be way more efficient
|
||||
// Using interrupts/DMA/polling would be much better
|
||||
for (size_t i = 0; i < len; i++) {
|
||||
// Block until we can send a byte
|
||||
while (px4_arch_gpioread(GPIO_NRF_TXEN)) ;
|
||||
while (px4_arch_gpioread(GPIO_NRF_TXEN))
|
||||
;
|
||||
|
||||
write(_fd, ((const char *)data) + i, 1);
|
||||
}
|
||||
@@ -688,9 +629,7 @@ Syslink::send_bytes(const void *data, size_t len)
|
||||
return 0;
|
||||
}
|
||||
|
||||
int
|
||||
Syslink::send_message(syslink_message_t *msg)
|
||||
{
|
||||
int Syslink::send_message(syslink_message_t *msg) {
|
||||
syslink_compute_cksum(msg);
|
||||
send_bytes(syslink_magic, 2);
|
||||
send_bytes(&msg->type, sizeof(msg->type));
|
||||
@@ -700,9 +639,7 @@ Syslink::send_message(syslink_message_t *msg)
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
namespace syslink
|
||||
{
|
||||
namespace syslink {
|
||||
|
||||
void usage();
|
||||
void start();
|
||||
@@ -710,13 +647,9 @@ void status();
|
||||
void test();
|
||||
void attached(int pid);
|
||||
|
||||
void usage()
|
||||
{
|
||||
warnx("missing command: try 'start', 'status', 'attached', 'test'");
|
||||
}
|
||||
void usage() { warnx("missing command: try 'start', 'status', 'attached', 'test'"); }
|
||||
|
||||
void start()
|
||||
{
|
||||
void start() {
|
||||
if (g_syslink != nullptr) {
|
||||
printf("Already started\n");
|
||||
exit(1);
|
||||
@@ -728,14 +661,11 @@ void start()
|
||||
// Wait for task and bridge to start
|
||||
usleep(5000);
|
||||
|
||||
|
||||
warnx("Started syslink on /dev/ttyS2\n");
|
||||
exit(0);
|
||||
|
||||
}
|
||||
|
||||
void status()
|
||||
{
|
||||
void status() {
|
||||
if (g_syslink == nullptr) {
|
||||
printf("Please start syslink first\n");
|
||||
exit(1);
|
||||
@@ -753,16 +683,16 @@ void status()
|
||||
printf("- data rate: %s\n", g_syslink->is_good(1) != 0 ? goodParam : badParam);
|
||||
printf("- address: %s\n\n", g_syslink->is_good(2) != 0 ? goodParam : badParam);
|
||||
|
||||
|
||||
int deckfd = open(DECK_DEVICE_PATH, O_RDONLY);
|
||||
int ndecks = 0; ioctl(deckfd, DECKIOGNUM, (unsigned long) &ndecks);
|
||||
int ndecks = 0;
|
||||
ioctl(deckfd, DECKIOGNUM, (unsigned long)&ndecks);
|
||||
printf("Deck scan: (found %d)\n", ndecks);
|
||||
|
||||
for (int i = 0; i < ndecks; i++) {
|
||||
ioctl(deckfd, DECKIOSNUM, (unsigned long) &i);
|
||||
ioctl(deckfd, DECKIOSNUM, (unsigned long)&i);
|
||||
|
||||
uint8_t *id;
|
||||
int idlen = ioctl(deckfd, DECKIOID, (unsigned long) &id);
|
||||
int idlen = ioctl(deckfd, DECKIOID, (unsigned long)&id);
|
||||
|
||||
// TODO: Validate the ID
|
||||
printf("%i: ROM ID: ", i);
|
||||
@@ -774,7 +704,8 @@ void status()
|
||||
deck_descriptor_t desc;
|
||||
read(deckfd, &desc, sizeof(desc));
|
||||
|
||||
printf("HDR:%02" PRIx8 ", VID: %02" PRIx8 " , PID: %02" PRIx8 "\n", desc.header, desc.vendorId, desc.productId);
|
||||
printf("HDR:%02" PRIx8 ", VID: %02" PRIx8 " , PID: %02" PRIx8 "\n", desc.header, desc.vendorId,
|
||||
desc.productId);
|
||||
|
||||
// Print pages of memory
|
||||
for (size_t di = 0; di < sizeof(desc); di++) {
|
||||
@@ -783,7 +714,6 @@ void status()
|
||||
}
|
||||
|
||||
printf("%02" PRIX8 " ", ((uint8_t *)&desc)[di]);
|
||||
|
||||
}
|
||||
|
||||
printf("\n\n");
|
||||
@@ -793,15 +723,15 @@ void status()
|
||||
exit(0);
|
||||
}
|
||||
|
||||
void attached(int pid)
|
||||
{
|
||||
void attached(int pid) {
|
||||
bool found = false;
|
||||
|
||||
int deckfd = open(DECK_DEVICE_PATH, O_RDONLY);
|
||||
int ndecks = 0; ioctl(deckfd, DECKIOGNUM, (unsigned long) &ndecks);
|
||||
int ndecks = 0;
|
||||
ioctl(deckfd, DECKIOGNUM, (unsigned long)&ndecks);
|
||||
|
||||
for (int i = 0; i < ndecks; i++) {
|
||||
ioctl(deckfd, DECKIOSNUM, (unsigned long) &i);
|
||||
ioctl(deckfd, DECKIOSNUM, (unsigned long)&i);
|
||||
|
||||
deck_descriptor_t desc;
|
||||
read(deckfd, &desc, sizeof(desc));
|
||||
@@ -816,16 +746,14 @@ void attached(int pid)
|
||||
exit(found ? 1 : 0);
|
||||
}
|
||||
|
||||
void test()
|
||||
{
|
||||
void test() {
|
||||
// TODO: Ensure battery messages are recent
|
||||
// TODO: Read and write from memory to ensure it is working
|
||||
}
|
||||
|
||||
} // namespace syslink
|
||||
} // namespace syslink
|
||||
|
||||
int syslink_main(int argc, char *argv[])
|
||||
{
|
||||
int syslink_main(int argc, char *argv[]) {
|
||||
if (argc < 2) {
|
||||
syslink::usage();
|
||||
exit(1);
|
||||
|
||||
@@ -33,37 +33,29 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <battery/battery.h>
|
||||
|
||||
#include <drivers/device/device.h>
|
||||
#include "ringbuffer.h"
|
||||
|
||||
#include <uORB/PublicationMulti.hpp>
|
||||
#include <uORB/topics/parameter_update.h>
|
||||
#include <stdint.h>
|
||||
#include <uORB/topics/battery_status.h>
|
||||
#include <uORB/topics/input_rc.h>
|
||||
#include <uORB/topics/parameter_update.h>
|
||||
|
||||
#include <uORB/PublicationMulti.hpp>
|
||||
|
||||
#include "syslink.h"
|
||||
#include "crtp.h"
|
||||
#include "ringbuffer.h"
|
||||
#include "syslink.h"
|
||||
|
||||
using namespace time_literals;
|
||||
|
||||
#define MIN(X, Y) (((X) < (Y)) ? (X) : (Y))
|
||||
|
||||
typedef enum {
|
||||
BAT_DISCHARGING = 0,
|
||||
BAT_CHARGING = 1,
|
||||
BAT_CHARGED = 2
|
||||
} battery_state;
|
||||
|
||||
typedef enum { BAT_DISCHARGING = 0, BAT_CHARGING = 1, BAT_CHARGED = 2 } battery_state;
|
||||
|
||||
class SyslinkBridge;
|
||||
class SyslinkMemory;
|
||||
|
||||
class Syslink
|
||||
{
|
||||
class Syslink {
|
||||
public:
|
||||
Syslink();
|
||||
|
||||
@@ -114,8 +106,8 @@ private:
|
||||
int _count_in;
|
||||
int _count_out;
|
||||
hrt_abstime _lasttime;
|
||||
hrt_abstime _lasttxtime; // Last time a radio message was sent
|
||||
hrt_abstime _lastrxtime; // Last time a radio message was recieved
|
||||
hrt_abstime _lasttxtime; // Last time a radio message was sent
|
||||
hrt_abstime _lastrxtime; // Last time a radio message was recieved
|
||||
|
||||
int _fd;
|
||||
|
||||
@@ -132,10 +124,10 @@ private:
|
||||
// Current parameter values
|
||||
int32_t _channel, _rate;
|
||||
uint64_t _addr;
|
||||
hrt_abstime _params_update[3]; // Time at which the parameters were updated
|
||||
hrt_abstime _params_ack[3]; // Time at which the parameters were acknowledged by the nrf module
|
||||
hrt_abstime _params_update[3]; // Time at which the parameters were updated
|
||||
hrt_abstime _params_ack[3]; // Time at which the parameters were acknowledged by the nrf module
|
||||
|
||||
uORB::PublicationMulti<input_rc_s> _rc_pub{ORB_ID(input_rc)};
|
||||
uORB::PublicationMulti<input_rc_s> _rc_pub{ORB_ID(input_rc)};
|
||||
|
||||
// nrf chip schedules battery updates with SYSLINK_SEND_PERIOD_MS
|
||||
static constexpr uint32_t SYSLINK_BATTERY_STATUS_INTERVAL_US = 10_ms;
|
||||
@@ -153,19 +145,16 @@ private:
|
||||
void task_main();
|
||||
};
|
||||
|
||||
|
||||
class SyslinkBridge : public cdev::CDev
|
||||
{
|
||||
|
||||
class SyslinkBridge : public cdev::CDev {
|
||||
public:
|
||||
SyslinkBridge(Syslink *link);
|
||||
virtual ~SyslinkBridge() = default;
|
||||
|
||||
virtual int init();
|
||||
virtual int init();
|
||||
|
||||
virtual ssize_t read(struct file *filp, char *buffer, size_t buflen);
|
||||
virtual ssize_t write(struct file *filp, const char *buffer, size_t buflen);
|
||||
virtual int ioctl(struct file *filp, int cmd, unsigned long arg);
|
||||
virtual ssize_t read(struct file *filp, char *buffer, size_t buflen);
|
||||
virtual ssize_t write(struct file *filp, const char *buffer, size_t buflen);
|
||||
virtual int ioctl(struct file *filp, int cmd, unsigned long arg);
|
||||
|
||||
// Makes the message available for reading to processes reading from the bridge
|
||||
void pipe_message(crtp_message_t *msg);
|
||||
@@ -183,19 +172,16 @@ private:
|
||||
int _msg_to_send_size_remaining;
|
||||
};
|
||||
|
||||
|
||||
class SyslinkMemory : public cdev::CDev
|
||||
{
|
||||
|
||||
class SyslinkMemory : public cdev::CDev {
|
||||
public:
|
||||
SyslinkMemory(Syslink *link);
|
||||
virtual ~SyslinkMemory() = default;
|
||||
|
||||
virtual int init();
|
||||
virtual int init();
|
||||
|
||||
virtual ssize_t read(struct file *filp, char *buffer, size_t buflen);
|
||||
virtual ssize_t write(struct file *filp, const char *buffer, size_t buflen);
|
||||
virtual int ioctl(struct file *filp, int cmd, unsigned long arg);
|
||||
virtual ssize_t read(struct file *filp, char *buffer, size_t buflen);
|
||||
virtual ssize_t write(struct file *filp, const char *buffer, size_t buflen);
|
||||
virtual int ioctl(struct file *filp, int cmd, unsigned long arg);
|
||||
|
||||
private:
|
||||
friend class Syslink;
|
||||
|
||||
@@ -31,25 +31,14 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
|
||||
#include "syslink_main.h"
|
||||
|
||||
#include "drv_deck.h"
|
||||
|
||||
#include <cstring>
|
||||
|
||||
#include "drv_deck.h"
|
||||
#include "syslink_main.h"
|
||||
|
||||
SyslinkMemory::SyslinkMemory(Syslink *link) :
|
||||
CDev(DECK_DEVICE_PATH),
|
||||
_link(link),
|
||||
_activeI(0)
|
||||
{
|
||||
}
|
||||
SyslinkMemory::SyslinkMemory(Syslink *link) : CDev(DECK_DEVICE_PATH), _link(link), _activeI(0) {}
|
||||
|
||||
|
||||
int
|
||||
SyslinkMemory::init()
|
||||
{
|
||||
int SyslinkMemory::init() {
|
||||
int ret = CDev::init();
|
||||
|
||||
/* if init failed, bail now */
|
||||
@@ -58,54 +47,44 @@ SyslinkMemory::init()
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
ssize_t
|
||||
SyslinkMemory::read(struct file *filp, char *buffer, size_t buflen)
|
||||
{
|
||||
ssize_t SyslinkMemory::read(struct file *filp, char *buffer, size_t buflen) {
|
||||
return read(_activeI, 0, buffer, buflen);
|
||||
}
|
||||
|
||||
ssize_t
|
||||
SyslinkMemory::write(struct file *filp, const char *buffer, size_t buflen)
|
||||
{
|
||||
ssize_t SyslinkMemory::write(struct file *filp, const char *buffer, size_t buflen) {
|
||||
// For now, unsupported
|
||||
return -1;
|
||||
// return buflen;
|
||||
// return buflen;
|
||||
}
|
||||
|
||||
int
|
||||
SyslinkMemory::ioctl(struct file *filp, int cmd, unsigned long arg)
|
||||
{
|
||||
int SyslinkMemory::ioctl(struct file *filp, int cmd, unsigned long arg) {
|
||||
switch (cmd) {
|
||||
case DECKIOGNUM:
|
||||
*((int *) arg) = scan();
|
||||
return 0;
|
||||
case DECKIOGNUM:
|
||||
*((int *)arg) = scan();
|
||||
return 0;
|
||||
|
||||
case DECKIOSNUM:
|
||||
_activeI = *((int *) arg);
|
||||
return 0;
|
||||
case DECKIOSNUM:
|
||||
_activeI = *((int *)arg);
|
||||
return 0;
|
||||
|
||||
case DECKIOID: {
|
||||
syslink_ow_getinfo_t *data = (syslink_ow_getinfo_t *) &msgbuf.data;
|
||||
case DECKIOID: {
|
||||
syslink_ow_getinfo_t *data = (syslink_ow_getinfo_t *)&msgbuf.data;
|
||||
getinfo(_activeI);
|
||||
*((uint8_t **)arg) = data->id;
|
||||
return 8;
|
||||
}
|
||||
|
||||
default:
|
||||
CDev::ioctl(filp, cmd, arg);
|
||||
return 0;
|
||||
default:
|
||||
CDev::ioctl(filp, cmd, arg);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
uint8_t
|
||||
SyslinkMemory::scan()
|
||||
{
|
||||
syslink_ow_scan_t *data = (syslink_ow_scan_t *) &msgbuf.data;
|
||||
uint8_t SyslinkMemory::scan() {
|
||||
syslink_ow_scan_t *data = (syslink_ow_scan_t *)&msgbuf.data;
|
||||
msgbuf.type = SYSLINK_OW_SCAN;
|
||||
msgbuf.length = 0;
|
||||
sendAndWait();
|
||||
@@ -113,26 +92,21 @@ SyslinkMemory::scan()
|
||||
return data->nmems;
|
||||
}
|
||||
|
||||
void
|
||||
SyslinkMemory::getinfo(int i)
|
||||
{
|
||||
syslink_ow_getinfo_t *data = (syslink_ow_getinfo_t *) &msgbuf.data;
|
||||
void SyslinkMemory::getinfo(int i) {
|
||||
syslink_ow_getinfo_t *data = (syslink_ow_getinfo_t *)&msgbuf.data;
|
||||
msgbuf.type = SYSLINK_OW_GETINFO;
|
||||
msgbuf.length = 1;
|
||||
data->idx = i;
|
||||
sendAndWait();
|
||||
}
|
||||
|
||||
int
|
||||
SyslinkMemory::read(int i, uint16_t addr, char *buf, int length)
|
||||
{
|
||||
syslink_ow_read_t *data = (syslink_ow_read_t *) &msgbuf.data;
|
||||
int SyslinkMemory::read(int i, uint16_t addr, char *buf, int length) {
|
||||
syslink_ow_read_t *data = (syslink_ow_read_t *)&msgbuf.data;
|
||||
msgbuf.type = SYSLINK_OW_READ;
|
||||
|
||||
int nread = 0;
|
||||
|
||||
while (nread < length) {
|
||||
|
||||
msgbuf.length = 3;
|
||||
data->idx = i;
|
||||
data->addr = addr;
|
||||
@@ -154,16 +128,12 @@ SyslinkMemory::read(int i, uint16_t addr, char *buf, int length)
|
||||
return nread;
|
||||
}
|
||||
|
||||
int
|
||||
SyslinkMemory::write(int i, uint16_t addr, const char *buf, int length)
|
||||
{
|
||||
int SyslinkMemory::write(int i, uint16_t addr, const char *buf, int length) {
|
||||
// TODO: Unimplemented
|
||||
return -1;
|
||||
}
|
||||
|
||||
void
|
||||
SyslinkMemory::sendAndWait()
|
||||
{
|
||||
void SyslinkMemory::sendAndWait() {
|
||||
// TODO: Force the syslink thread to wake up
|
||||
_link->_queue.force(&msgbuf, sizeof(msgbuf));
|
||||
px4_sem_wait(&_link->memory_sem);
|
||||
|
||||
@@ -62,11 +62,11 @@ PARAM_DEFINE_INT32(SLNK_RADIO_RATE, 2);
|
||||
*
|
||||
* @group Syslink
|
||||
*/
|
||||
PARAM_DEFINE_INT32(SLNK_RADIO_ADDR1, 231); // 0xE7
|
||||
PARAM_DEFINE_INT32(SLNK_RADIO_ADDR1, 231); // 0xE7
|
||||
|
||||
/**
|
||||
* Operating address of the NRF51 (least significant 4 bytes)
|
||||
*
|
||||
* @group Syslink
|
||||
*/
|
||||
PARAM_DEFINE_INT32(SLNK_RADIO_ADDR2, 3890735079); // 0xE7E7E7E7
|
||||
PARAM_DEFINE_INT32(SLNK_RADIO_ADDR2, 3890735079); // 0xE7E7E7E7
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#include <stdint.h>
|
||||
#endif
|
||||
|
||||
#include "stm32.h"
|
||||
@@ -83,11 +83,11 @@
|
||||
* LSE - not installed
|
||||
*/
|
||||
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
#define STM32_BOARD_XTAL 8000000ul
|
||||
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
#define STM32_HSI_FREQUENCY 16000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
|
||||
//#define STM32_LSE_FREQUENCY 32768
|
||||
|
||||
/* Main PLL Configuration.
|
||||
@@ -103,68 +103,68 @@
|
||||
* = 48,000,000
|
||||
*/
|
||||
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
|
||||
#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
|
||||
#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
|
||||
#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
|
||||
#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
|
||||
|
||||
#define STM32_SYSCLK_FREQUENCY 168000000ul
|
||||
#define STM32_SYSCLK_FREQUENCY 168000000ul
|
||||
|
||||
/* AHB clock (HCLK) is SYSCLK (168MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
|
||||
|
||||
/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
|
||||
#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 4)
|
||||
|
||||
/* Timers driven from APB1 will be twice PCLK1 */
|
||||
|
||||
#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
|
||||
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
|
||||
#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
|
||||
|
||||
/* Timers driven from APB2 will be twice PCLK2 */
|
||||
|
||||
#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
|
||||
* otherwise frequency is 2xAPBx.
|
||||
* Note: TIM1,8-11 are on APB2, others on APB1
|
||||
*/
|
||||
|
||||
#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN
|
||||
#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN
|
||||
#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN
|
||||
#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN
|
||||
#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN
|
||||
#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN
|
||||
#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN
|
||||
#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN
|
||||
#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN
|
||||
#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN
|
||||
#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN
|
||||
#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN
|
||||
#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN
|
||||
#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN
|
||||
#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN
|
||||
#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN
|
||||
#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN
|
||||
#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN
|
||||
#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN
|
||||
#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN
|
||||
#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN
|
||||
#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN
|
||||
|
||||
/* Alternate function pin selections ************************************************/
|
||||
|
||||
@@ -173,16 +173,16 @@
|
||||
*
|
||||
*/
|
||||
/* E_TX2 / E_RX2 */
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
#define GPIO_USART2_RX GPIO_USART2_RX_1
|
||||
#define GPIO_USART2_TX GPIO_USART2_TX_1
|
||||
|
||||
/* E_TX1 / E_RX1 */
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_2
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_2
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_2
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_2
|
||||
|
||||
/* NRF51 via syslink */
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_1
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_1
|
||||
#define GPIO_USART6_RX GPIO_USART6_RX_1
|
||||
#define GPIO_USART6_TX GPIO_USART6_TX_1
|
||||
|
||||
/* UART DMA configuration for USART6 */
|
||||
#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2
|
||||
@@ -194,24 +194,24 @@
|
||||
* reset the bus to clear stuck slaves. They match the pin configuration,
|
||||
* but are normally-high GPIOs.
|
||||
*/
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN7)
|
||||
#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
|
||||
#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
|
||||
#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
|
||||
#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
|
||||
|
||||
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
|
||||
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
|
||||
#define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN8)
|
||||
#define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN9)
|
||||
#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
|
||||
#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
|
||||
#define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN8)
|
||||
#define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN9)
|
||||
|
||||
/*
|
||||
* SPI
|
||||
*
|
||||
* E_MISO, E_MOSI, E_SCK exposed on headers
|
||||
*/
|
||||
#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_1 | GPIO_SPEED_50MHz)
|
||||
#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1 | GPIO_SPEED_50MHz)
|
||||
|
||||
/* XXX since we allocate the HP work stack from CCM RAM on normal system startup,
|
||||
SPI1 will never run in DMA mode - so we can just give it a random config here.
|
||||
@@ -220,4 +220,4 @@
|
||||
#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1
|
||||
#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_2
|
||||
|
||||
#endif /* __CONFIG_CRAZYFLIE_INCLUDE_BOARD_H */
|
||||
#endif /* __CONFIG_CRAZYFLIE_INCLUDE_BOARD_H */
|
||||
|
||||
@@ -43,8 +43,8 @@
|
||||
* Included Files
|
||||
****************************************************************************************************/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/****************************************************************************************************
|
||||
@@ -55,94 +55,89 @@
|
||||
/* Crazyflie GPIOs **********************************************************************************/
|
||||
/* LEDs */
|
||||
|
||||
|
||||
/* Radio TX indicator */
|
||||
#define GPIO_LED_RED_L (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN0)
|
||||
#define GPIO_LED_RED_L (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN0)
|
||||
/* Radio RX indicator */
|
||||
#define GPIO_LED_GREEN_L (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN1)
|
||||
#define GPIO_LED_GREEN_R (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN2)
|
||||
#define GPIO_LED_RED_R (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
|
||||
GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN3)
|
||||
#define GPIO_LED_GREEN_L (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN1)
|
||||
#define GPIO_LED_GREEN_R (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN2)
|
||||
#define GPIO_LED_RED_R (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN3)
|
||||
|
||||
/* PX4: armed state indicator ; Stock FW: Blinking while charging */
|
||||
#define GPIO_LED_BLUE_L (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTD|GPIO_PIN2)
|
||||
#define GPIO_LED_BLUE_L (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTD | GPIO_PIN2)
|
||||
|
||||
#define BOARD_HAS_CONTROL_STATUS_LEDS 1
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_LED LED_BLUE
|
||||
#define BOARD_ARMED_STATE_LED LED_GREEN
|
||||
#define BOARD_OVERLOAD_LED LED_RED
|
||||
#define BOARD_ARMED_LED LED_BLUE
|
||||
#define BOARD_ARMED_STATE_LED LED_GREEN
|
||||
|
||||
#define LED_TX 4
|
||||
#define LED_RX 5
|
||||
|
||||
#define GPIO_FSYNC_MPU9250 (GPIO_OUTPUT|GPIO_PORTC|GPIO_PIN14) // Needs to be set low
|
||||
#define GPIO_DRDY_MPU9250 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
|
||||
#define GPIO_FSYNC_MPU9250 (GPIO_OUTPUT | GPIO_PORTC | GPIO_PIN14) // Needs to be set low
|
||||
#define GPIO_DRDY_MPU9250 (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTC | GPIO_PIN13)
|
||||
|
||||
#define GPIO_NRF_TXEN (GPIO_INPUT | GPIO_PULLUP | GPIO_EXTI | GPIO_PORTA | GPIO_PIN4)
|
||||
|
||||
#define GPIO_NRF_TXEN (GPIO_INPUT|GPIO_PULLUP|GPIO_EXTI|GPIO_PORTA|GPIO_PIN4)
|
||||
|
||||
#define GPIO_I2C4_DRDY1_BMP388 (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTG|GPIO_PIN5)
|
||||
#define GPIO_I2C4_DRDY1_BMP388 (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTG | GPIO_PIN5)
|
||||
|
||||
/*
|
||||
* I2C busses
|
||||
*/
|
||||
#define PX4_I2C_BUS_ONBOARD_HZ 400000
|
||||
#define PX4_I2C_BUS_EXPANSION_HZ 400000
|
||||
#define PX4_I2C_BUS_ONBOARD_HZ 400000
|
||||
#define PX4_I2C_BUS_EXPANSION_HZ 400000
|
||||
|
||||
#define PX4_I2C_BUS_MTD 1
|
||||
|
||||
#define BOARD_NUMBER_I2C_BUSES 3
|
||||
#define BOARD_I2C_BUS_CLOCK_INIT {PX4_I2C_BUS_ONBOARD_HZ, 400000, PX4_I2C_BUS_EXPANSION_HZ}
|
||||
#define PX4_I2C_BUS_MTD 1
|
||||
|
||||
#define BOARD_NUMBER_I2C_BUSES 3
|
||||
#define BOARD_I2C_BUS_CLOCK_INIT \
|
||||
{ PX4_I2C_BUS_ONBOARD_HZ, 400000, PX4_I2C_BUS_EXPANSION_HZ }
|
||||
|
||||
/* Devices on the onboard bus.
|
||||
*
|
||||
* Note that these are unshifted addresses.
|
||||
*/
|
||||
#define PX4_I2C_OBDEV_MPU9250 0x69
|
||||
#define PX4_I2C_OBDEV_MPU9250 0x69
|
||||
|
||||
/* USB OTG FS
|
||||
*
|
||||
* PA9 OTG_FS_VBUS VBUS sensing
|
||||
*/
|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
|
||||
#define GPIO_OTGFS_VBUS (GPIO_INPUT | GPIO_FLOAT | GPIO_SPEED_100MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN9)
|
||||
|
||||
/*
|
||||
* ADC channels
|
||||
*
|
||||
* These are the channel numbers of the ADCs of the microcontroller that can be used by the Px4 Firmware in the adc driver
|
||||
* These are the channel numbers of the ADCs of the microcontroller that can be used by the Px4 Firmware in the adc
|
||||
* driver
|
||||
*/
|
||||
#define ADC_CHANNELS 0
|
||||
|
||||
/* Tone alarm output : These are only applicable when the buzzer deck is attached */
|
||||
#define TONE_ALARM_TIMER 5 /* timer 5 */
|
||||
#define TONE_ALARM_CHANNEL 3 /* channel 3 */
|
||||
#define GPIO_TONE_ALARM_IDLE (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TONE_ALARM (GPIO_ALT|GPIO_AF2|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
|
||||
#define GPIO_TONE_ALARM_NEG (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN3)
|
||||
#define TONE_ALARM_TIMER 5 /* timer 5 */
|
||||
#define TONE_ALARM_CHANNEL 3 /* channel 3 */
|
||||
#define GPIO_TONE_ALARM_IDLE \
|
||||
(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_TONE_ALARM (GPIO_ALT | GPIO_AF2 | GPIO_SPEED_2MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN2)
|
||||
#define GPIO_TONE_ALARM_NEG (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN3)
|
||||
|
||||
/* PWM
|
||||
*/
|
||||
*/
|
||||
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 4
|
||||
#define DIRECT_PWM_OUTPUT_CHANNELS 4
|
||||
|
||||
/* This board overrides the defaults by providing
|
||||
* PX4_PWM_ALTERNATE_RANGES and a replacement set of
|
||||
* constants
|
||||
*/
|
||||
|
||||
|
||||
/* PWM directly wired to transistor. Duty cycle directly corresponds to power
|
||||
* So we need to override the defaults
|
||||
*/
|
||||
|
||||
#define PX4_PWM_ALTERNATE_RANGES
|
||||
#define PWM_LOWEST_MIN 0
|
||||
#define PWM_MOTOR_OFF 0
|
||||
#define PWM_SERVO_STOP 0
|
||||
#define PWM_MOTOR_OFF 0
|
||||
#define PWM_SERVO_STOP 0
|
||||
#define PWM_DEFAULT_MIN 20
|
||||
#define PWM_HIGHEST_MIN 0
|
||||
#define PWM_HIGHEST_MAX 255
|
||||
@@ -150,14 +145,12 @@
|
||||
#define PWM_LOWEST_MAX 255
|
||||
#define PWM_DEFAULT_TRIM 1500
|
||||
|
||||
|
||||
/* High-resolution timer */
|
||||
#define HRT_TIMER 8 /* use timer8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel */
|
||||
|
||||
#define HRT_TIMER 8 /* use timer8 for the HRT */
|
||||
#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel */
|
||||
|
||||
#define BOARD_ENABLE_CONSOLE_BUFFER
|
||||
#define BOARD_CONSOLE_BUFFER_SIZE (1024*3)
|
||||
#define BOARD_CONSOLE_BUFFER_SIZE (1024 * 3)
|
||||
|
||||
__BEGIN_DECLS
|
||||
|
||||
@@ -225,7 +218,6 @@ extern void stm32_spiinitialize(void);
|
||||
|
||||
extern int stm32_spi_bus_initialize(void);
|
||||
|
||||
|
||||
#include <px4_platform_common/board_common.h>
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
@@ -45,30 +45,25 @@
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <errno.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform_common/tasks.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdio.h>
|
||||
#include <stm32_uart.h>
|
||||
#include <string.h>
|
||||
#include <debug.h>
|
||||
#include <errno.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/analog/adc.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
|
||||
#include "board_config.h"
|
||||
#include <stm32_uart.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include <drivers/drv_hrt.h>
|
||||
#include <drivers/drv_board_led.h>
|
||||
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <px4_platform_common/init.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Definitions
|
||||
@@ -105,9 +100,7 @@ __END_DECLS
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void
|
||||
stm32_boardinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_boardinitialize(void) {
|
||||
/* configure LEDs */
|
||||
|
||||
board_autoled_initialize();
|
||||
@@ -127,8 +120,7 @@ stm32_boardinitialize(void)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
__EXPORT int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
__EXPORT int board_app_initialize(uintptr_t arg) {
|
||||
px4_platform_init();
|
||||
|
||||
#if defined(SERIAL_HAVE_RXDMA)
|
||||
|
||||
@@ -37,14 +37,12 @@
|
||||
* Crazyflie LED backend.
|
||||
*/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "stm32.h"
|
||||
#include "board_config.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include "stm32.h"
|
||||
|
||||
/*
|
||||
* Ideally we'd be able to get these from arm_internal.h,
|
||||
@@ -61,17 +59,15 @@ extern void led_toggle(int led);
|
||||
__END_DECLS
|
||||
|
||||
static uint32_t g_ledmap[] = {
|
||||
GPIO_LED_BLUE_L, // Indexed by LED_BLUE
|
||||
GPIO_LED_RED_R, // Indexed by LED_RED, LED_AMBER
|
||||
0, // Indexed by LED_SAFETY
|
||||
GPIO_LED_GREEN_R, // Indexed by LED_GREEN
|
||||
GPIO_LED_RED_L, // Indexed by LED_TX
|
||||
GPIO_LED_GREEN_L // Indexed by LED_RX
|
||||
GPIO_LED_BLUE_L, // Indexed by LED_BLUE
|
||||
GPIO_LED_RED_R, // Indexed by LED_RED, LED_AMBER
|
||||
0, // Indexed by LED_SAFETY
|
||||
GPIO_LED_GREEN_R, // Indexed by LED_GREEN
|
||||
GPIO_LED_RED_L, // Indexed by LED_TX
|
||||
GPIO_LED_GREEN_L // Indexed by LED_RX
|
||||
};
|
||||
|
||||
|
||||
__EXPORT void led_init()
|
||||
{
|
||||
__EXPORT void led_init() {
|
||||
/* Configure LED1 GPIO for output */
|
||||
for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
|
||||
if (g_ledmap[l]) {
|
||||
@@ -80,20 +76,17 @@ __EXPORT void led_init()
|
||||
}
|
||||
}
|
||||
|
||||
__EXPORT void led_on(int led)
|
||||
{
|
||||
__EXPORT void led_on(int led) {
|
||||
/* Pull down to switch on */
|
||||
px4_arch_gpiowrite(g_ledmap[led], g_ledmap[led] & GPIO_OUTPUT_SET ? true : false);
|
||||
}
|
||||
|
||||
__EXPORT void led_off(int led)
|
||||
{
|
||||
__EXPORT void led_off(int led) {
|
||||
/* Pull up to switch off */
|
||||
px4_arch_gpiowrite(g_ledmap[led], g_ledmap[led] & GPIO_OUTPUT_SET ? false : true);
|
||||
}
|
||||
|
||||
__EXPORT void led_toggle(int led)
|
||||
{
|
||||
__EXPORT void led_toggle(int led) {
|
||||
if (px4_arch_gpioread(g_ledmap[led])) {
|
||||
px4_arch_gpiowrite(g_ledmap[led], false);
|
||||
|
||||
|
||||
@@ -31,34 +31,31 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <arch/board/board.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
|
||||
#include <arm_arch.h>
|
||||
#include <chip.h>
|
||||
#include <debug.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/mmcsd.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <px4_platform/gpio.h>
|
||||
#include <px4_platform_common/px4_config.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32_gpio.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "board_config.h"
|
||||
|
||||
#include <px4_arch/spi_hw_description.h>
|
||||
#include <drivers/drv_sensor.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
|
||||
constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
|
||||
initSPIBus(SPI::Bus::SPI1, {
|
||||
initSPIDevice(SPIDEV_MMCSD(0), SPI::CS{GPIO::PortC, GPIO::Pin12}),
|
||||
initSPIDevice(DRV_FLOW_DEVTYPE_PMW3901, SPI::CS{GPIO::PortB, GPIO::Pin4}),
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortB, GPIO::Pin5}),
|
||||
}),
|
||||
initSPIBus(SPI::Bus::SPI1,
|
||||
{
|
||||
initSPIDevice(SPIDEV_MMCSD(0), SPI::CS{GPIO::PortC, GPIO::Pin12}),
|
||||
initSPIDevice(DRV_FLOW_DEVTYPE_PMW3901, SPI::CS{GPIO::PortB, GPIO::Pin4}),
|
||||
initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortB, GPIO::Pin5}),
|
||||
}),
|
||||
};
|
||||
|
||||
static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
@@ -72,8 +69,7 @@ static constexpr bool unused = validateSPIConfig(px4_spi_buses);
|
||||
************************************************************************************/
|
||||
static struct spi_dev_s *spi_expansion;
|
||||
|
||||
__EXPORT int stm32_spi_bus_initialize(void)
|
||||
{
|
||||
__EXPORT int stm32_spi_bus_initialize(void) {
|
||||
/* Configure SPI-based devices */
|
||||
|
||||
/* Get the external SPI port */
|
||||
|
||||
@@ -39,8 +39,7 @@
|
||||
*/
|
||||
#define TIMx_CLKIN 1000000
|
||||
|
||||
static inline constexpr io_timers_t initIOTimerOverrideClockFreq(Timer::Timer timer)
|
||||
{
|
||||
static inline constexpr io_timers_t initIOTimerOverrideClockFreq(Timer::Timer timer) {
|
||||
io_timers_t ret = initIOTimer(timer);
|
||||
ret.clock_freq = TIMx_CLKIN;
|
||||
return ret;
|
||||
|
||||
@@ -41,18 +41,16 @@
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <arm_arch.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/usb/usbdev.h>
|
||||
#include <nuttx/usb/usbdev_trace.h>
|
||||
|
||||
#include <arm_arch.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include <stm32.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "board_config.h"
|
||||
|
||||
/************************************************************************************
|
||||
@@ -75,8 +73,7 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_usbinitialize(void)
|
||||
{
|
||||
__EXPORT void stm32_usbinitialize(void) {
|
||||
/* The OTG FS has an internal soft pull-up */
|
||||
|
||||
/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
|
||||
@@ -101,8 +98,4 @@ __EXPORT void stm32_usbinitialize(void)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
|
||||
{
|
||||
uinfo("resume: %d\n", resume);
|
||||
}
|
||||
|
||||
__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); }
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user