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Improve QMC5883P magnetometer stability by optimizing OSR and ODR settings. (#26350)
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@ -244,6 +244,8 @@ void QMC5883P::RunImpl()
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bool QMC5883P::Configure()
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{
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RegisterWrite(Register::REG_29, 0x06);
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// first set and clear all configured register bits
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for (const auto ®_cfg : _register_cfg) {
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RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
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@ -107,7 +107,7 @@ private:
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static constexpr uint8_t size_register_cfg{2};
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register_config_t _register_cfg[size_register_cfg] {
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// Register | Set bits, Clear bits
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{ Register::CNTL1, CNTL1_BIT::MODE_CONTINUOUS | CNTL1_BIT::OSR1_8 | CNTL1_BIT::ODR_50HZ, CNTL1_BIT::OSR2_8},
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{ Register::CNTL1, CNTL1_BIT::MODE_CONTINUOUS | CNTL1_BIT::OSR2_4 | CNTL1_BIT::ODR_200HZ, CNTL1_BIT::OSR1_8},
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{ Register::CNTL2, CNTL2_BIT::RNG_2G, CNTL2_BIT::SOFT_RST | CNTL2_BIT::SELF_TEST},
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};
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};
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@ -79,6 +79,8 @@ enum class Register : uint8_t {
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CNTL2 = 0x0B, // Control Register 2
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CHIP_ID = 0x00,
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REG_29 = 0x29,
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};
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// STATUS
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@ -90,11 +92,11 @@ enum STATUS_BIT : uint8_t {
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// CNTL1
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enum CNTL1_BIT : uint8_t {
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// OSR2[7:6]
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OSR2_8 = Bit7 | Bit6, // 00
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OSR2_4 = Bit7, // 10
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// OSR1[5:4]
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OSR1_8 = Bit5 | Bit4, // 11
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// ODR[3:2]
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ODR_50HZ = Bit2, // 01
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ODR_200HZ = Bit3 | Bit2, // 11
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// MODE[1:0]
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MODE_CONTINUOUS = Bit1 | Bit0, // 11
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};
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