Improve QMC5883P magnetometer stability by optimizing OSR and ODR settings. (#26350)

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tompsontan 2026-01-30 12:38:20 +08:00 committed by GitHub
parent 6be1a14e06
commit f8c1e8b81f
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3 changed files with 7 additions and 3 deletions

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@ -244,6 +244,8 @@ void QMC5883P::RunImpl()
bool QMC5883P::Configure()
{
RegisterWrite(Register::REG_29, 0x06);
// first set and clear all configured register bits
for (const auto &reg_cfg : _register_cfg) {
RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);

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@ -107,7 +107,7 @@ private:
static constexpr uint8_t size_register_cfg{2};
register_config_t _register_cfg[size_register_cfg] {
// Register | Set bits, Clear bits
{ Register::CNTL1, CNTL1_BIT::MODE_CONTINUOUS | CNTL1_BIT::OSR1_8 | CNTL1_BIT::ODR_50HZ, CNTL1_BIT::OSR2_8},
{ Register::CNTL1, CNTL1_BIT::MODE_CONTINUOUS | CNTL1_BIT::OSR2_4 | CNTL1_BIT::ODR_200HZ, CNTL1_BIT::OSR1_8},
{ Register::CNTL2, CNTL2_BIT::RNG_2G, CNTL2_BIT::SOFT_RST | CNTL2_BIT::SELF_TEST},
};
};

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@ -79,6 +79,8 @@ enum class Register : uint8_t {
CNTL2 = 0x0B, // Control Register 2
CHIP_ID = 0x00,
REG_29 = 0x29,
};
// STATUS
@ -90,11 +92,11 @@ enum STATUS_BIT : uint8_t {
// CNTL1
enum CNTL1_BIT : uint8_t {
// OSR2[7:6]
OSR2_8 = Bit7 | Bit6, // 00
OSR2_4 = Bit7, // 10
// OSR1[5:4]
OSR1_8 = Bit5 | Bit4, // 11
// ODR[3:2]
ODR_50HZ = Bit2, // 01
ODR_200HZ = Bit3 | Bit2, // 11
// MODE[1:0]
MODE_CONTINUOUS = Bit1 | Bit0, // 11
};