From f8c1e8b81f9eabdffb17082aa6ea58200ad65905 Mon Sep 17 00:00:00 2001 From: tompsontan <1153614092@qq.com> Date: Fri, 30 Jan 2026 12:38:20 +0800 Subject: [PATCH] Improve QMC5883P magnetometer stability by optimizing OSR and ODR settings. (#26350) --- src/drivers/magnetometer/qmc5883p/QMC5883P.cpp | 2 ++ src/drivers/magnetometer/qmc5883p/QMC5883P.hpp | 2 +- .../magnetometer/qmc5883p/QST_QMC5883P_registers.hpp | 6 ++++-- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/drivers/magnetometer/qmc5883p/QMC5883P.cpp b/src/drivers/magnetometer/qmc5883p/QMC5883P.cpp index b0d9693b19..e508e8863e 100644 --- a/src/drivers/magnetometer/qmc5883p/QMC5883P.cpp +++ b/src/drivers/magnetometer/qmc5883p/QMC5883P.cpp @@ -244,6 +244,8 @@ void QMC5883P::RunImpl() bool QMC5883P::Configure() { + RegisterWrite(Register::REG_29, 0x06); + // first set and clear all configured register bits for (const auto ®_cfg : _register_cfg) { RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits); diff --git a/src/drivers/magnetometer/qmc5883p/QMC5883P.hpp b/src/drivers/magnetometer/qmc5883p/QMC5883P.hpp index 3ad532d0fb..1663fd88f4 100644 --- a/src/drivers/magnetometer/qmc5883p/QMC5883P.hpp +++ b/src/drivers/magnetometer/qmc5883p/QMC5883P.hpp @@ -107,7 +107,7 @@ private: static constexpr uint8_t size_register_cfg{2}; register_config_t _register_cfg[size_register_cfg] { // Register | Set bits, Clear bits - { Register::CNTL1, CNTL1_BIT::MODE_CONTINUOUS | CNTL1_BIT::OSR1_8 | CNTL1_BIT::ODR_50HZ, CNTL1_BIT::OSR2_8}, + { Register::CNTL1, CNTL1_BIT::MODE_CONTINUOUS | CNTL1_BIT::OSR2_4 | CNTL1_BIT::ODR_200HZ, CNTL1_BIT::OSR1_8}, { Register::CNTL2, CNTL2_BIT::RNG_2G, CNTL2_BIT::SOFT_RST | CNTL2_BIT::SELF_TEST}, }; }; diff --git a/src/drivers/magnetometer/qmc5883p/QST_QMC5883P_registers.hpp b/src/drivers/magnetometer/qmc5883p/QST_QMC5883P_registers.hpp index 57fffa6579..ff9428d48d 100644 --- a/src/drivers/magnetometer/qmc5883p/QST_QMC5883P_registers.hpp +++ b/src/drivers/magnetometer/qmc5883p/QST_QMC5883P_registers.hpp @@ -79,6 +79,8 @@ enum class Register : uint8_t { CNTL2 = 0x0B, // Control Register 2 CHIP_ID = 0x00, + + REG_29 = 0x29, }; // STATUS @@ -90,11 +92,11 @@ enum STATUS_BIT : uint8_t { // CNTL1 enum CNTL1_BIT : uint8_t { // OSR2[7:6] - OSR2_8 = Bit7 | Bit6, // 00 + OSR2_4 = Bit7, // 10 // OSR1[5:4] OSR1_8 = Bit5 | Bit4, // 11 // ODR[3:2] - ODR_50HZ = Bit2, // 01 + ODR_200HZ = Bit3 | Bit2, // 11 // MODE[1:0] MODE_CONTINUOUS = Bit1 | Bit0, // 11 };