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mpu9250: set accel DLPF to 41 Hz (#5177)
Previously, the accel DLPF was not set, so it's not clear what the settings are or should be.
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@@ -169,6 +169,8 @@
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#define BITS_DLPF_CFG_3600HZ 0x07
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#define BITS_DLPF_CFG_3600HZ 0x07
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#define BITS_DLPF_CFG_MASK 0x07
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#define BITS_DLPF_CFG_MASK 0x07
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#define BITS_ACCEL_CONFIG2_41HZ 0x03
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#define BIT_RAW_RDY_EN 0x01
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#define BIT_RAW_RDY_EN 0x01
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#define BIT_INT_ANYRD_2CLEAR 0x10
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#define BIT_INT_ANYRD_2CLEAR 0x10
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@@ -471,6 +473,9 @@ int MPU9250::reset()
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write_checked_reg(MPUREG_INT_PIN_CFG, BIT_INT_ANYRD_2CLEAR); // INT: Clear on any read
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write_checked_reg(MPUREG_INT_PIN_CFG, BIT_INT_ANYRD_2CLEAR); // INT: Clear on any read
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usleep(1000);
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usleep(1000);
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write_checked_reg(MPUREG_ACCEL_CONFIG2, BITS_ACCEL_CONFIG2_41HZ);
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usleep(1000);
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uint8_t retries = 10;
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uint8_t retries = 10;
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while (retries--) {
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while (retries--) {
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