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Re-partition Stellaris vector logic
git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5499 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
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/************************************************************************************
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* arch/arm/src/lm/chip/lm3s_vectors.S
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*
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* Copyright (C) 2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/************************************************************************************
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* Preprocessor Definitions
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************************************************************************************/
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/************************************************************************************
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* Vectors
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************************************************************************************/
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/* This file is included by lm_vectors.S. It provides the macro VECTOR that
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* supplies ach Stellaris vector in terms of a (lower-case) ISR label and an
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* (upper-case) IRQ number as defined in arch/arm/include/lm/lm3s_irq.h.
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* lm_vectors.S will define the VECTOR in different ways in order to generate
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* the interrupt vectors and handlers in their final form.
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*/
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#if defined(CONFIG_ARCH_CHIP_LM3S6918)
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/* If the common ARMv7-M vector handling is used, then all it needs is the following
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* definition that provides the number of supported vectors.
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*/
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#ifdef CONFIG_ARMV7M_CMNVECTOR
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/* Reserve 71 interrupt table entries for I/O interrupts. */
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# define ARMV7M_PERIPHERAL_INTERRUPTS 71
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#else
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VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
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VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
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VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
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VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
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VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
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VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
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VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
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VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
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VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
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UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */
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UNUSED(LM_RESERVED_26) /* Vector 26: Reserved */
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UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */
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UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */
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UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */
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VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
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VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
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VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
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VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
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VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
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VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
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VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
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VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
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VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
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VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
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VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
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VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
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VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
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UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
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VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
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VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
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VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
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VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
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VECTOR(lm_gpioh, LM_IRQ_GPIOH) /* Vector 48: GPIO Port H */
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UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */
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VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: SSI 1 */
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VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
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VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
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VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
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UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */
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UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */
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UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
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UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
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VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
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VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
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UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */
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UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
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UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */
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UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */
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UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */
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UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */
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UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */
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UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */
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UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
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UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
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UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
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#endif
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#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
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/* If the common ARMv7-M vector handling is used, then all it needs is the following
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* definition that provides the number of supported vectors.
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*/
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#ifdef CONFIG_ARMV7M_CMNVECTOR
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/* Reserve 71 interrupt table entries for I/O interrupts. */
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# define ARMV7M_PERIPHERAL_INTERRUPTS 71
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#else
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VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
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VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
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VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
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VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
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VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
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VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
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VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
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VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
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VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
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UNUSED(LM_RESERVED_25) /* Vector 25: Reserved */
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VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
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UNUSED(LM_RESERVED_27) /* Vector 27: Reserved */
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UNUSED(LM_RESERVED_28) /* Vector 28: Reserved */
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UNUSED(LM_RESERVED_29) /* Vector 29: Reserved */
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VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
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VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
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VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
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VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
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VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
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VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
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VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
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VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
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VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
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VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
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VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
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VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
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VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
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UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
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VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
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VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
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VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
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VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
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UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */
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UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */
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UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */
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UNUSED(LM_RESERVED_51) /* Vector 51: Reserved */
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UNUSED(LM_RESERVED_52) /* Vector 52: Reserved */
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UNUSED(LM_RESERVED_53) /* Vector 53: Reserved */
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UNUSED(LM_RESERVED_54) /* Vector 54: Reserved */
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UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */
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UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
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UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
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VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
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UNUSED(LM_RESERVED_59) /* Vector 59: Reserved */
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UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */
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UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
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UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */
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UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */
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UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */
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UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */
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UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */
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UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */
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UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
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UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
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UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
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#endif
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#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
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/* If the common ARMv7-M vector handling is used, then all it needs is the following
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* definition that provides the number of supported vectors.
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*/
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#ifdef CONFIG_ARMV7M_CMNVECTOR
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/* Reserve 71 interrupt table entries for I/O interrupts. */
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# define ARMV7M_PERIPHERAL_INTERRUPTS 71
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#else
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VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
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VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
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VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
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VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
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VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
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VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
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VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
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VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
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VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
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VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
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VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
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VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */
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VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */
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VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */
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VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
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VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
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VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
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VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
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VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
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VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
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VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
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VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
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VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
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VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
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VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
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VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
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VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
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UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
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VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
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VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
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VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
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VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
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UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */
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VECTOR(lm_uart2, LM_IRQ_UART1) /* Vector 49: UART 1 */
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UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */
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VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
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VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
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VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
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VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */
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UNUSED(LM_RESERVED_55) /* Vector 55: Reserved */
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UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
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UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
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VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
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VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
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UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */
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UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
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UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */
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UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */
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UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */
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UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */
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UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */
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UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */
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UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
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UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
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UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
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#endif
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#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
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/* If the common ARMv7-M vector handling is used, then all it needs is the following
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* definition that provides the number of supported vectors.
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*/
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#ifdef CONFIG_ARMV7M_CMNVECTOR
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/* Reserve 71 interrupt table entries for I/O interrupts. */
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# define ARMV7M_PERIPHERAL_INTERRUPTS 71
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#else
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VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
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VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
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VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
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VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
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VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
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VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
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VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
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VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
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VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
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VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
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VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
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VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */
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VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */
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VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */
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VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
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VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
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VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
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VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
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VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
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VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
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VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
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VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
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VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
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VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
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VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
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VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
|
||||
UNUSED(LM_RESERVED_42) /* Vector 42: Reserved */
|
||||
UNUSED(LM_RESERVED_43) /* Vector 43: Reserved */
|
||||
VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
|
||||
VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
|
||||
VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
|
||||
VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
|
||||
UNUSED(LM_RESERVED_48) /* Vector 48: Reserved */
|
||||
UNUSED(LM_RESERVED_49) /* Vector 49: Reserved */
|
||||
|
||||
UNUSED(LM_RESERVED_50) /* Vector 50: Reserved */
|
||||
VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
|
||||
VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
|
||||
VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
|
||||
VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */
|
||||
VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */
|
||||
UNUSED(LM_RESERVED_56) /* Vector 56: Reserved */
|
||||
UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
|
||||
VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
|
||||
VECTOR(lm_hib, LM_IRQ_HIBERNATE) /* Vector 59: Hibernation Module */
|
||||
|
||||
UNUSED(LM_RESERVED_60) /* Vector 60: Reserved */
|
||||
UNUSED(LM_RESERVED_61) /* Vector 61: Reserved */
|
||||
UNUSED(LM_RESERVED_62) /* Vector 62: Reserved */
|
||||
UNUSED(LM_RESERVED_63) /* Vector 63: Reserved */
|
||||
UNUSED(LM_RESERVED_64) /* Vector 64: Reserved */
|
||||
UNUSED(LM_RESERVED_65) /* Vector 65: Reserved */
|
||||
UNUSED(LM_RESERVED_66) /* Vector 66: Reserved */
|
||||
UNUSED(LM_RESERVED_67) /* Vector 67: Reserved */
|
||||
UNUSED(LM_RESERVED_68) /* Vector 68: Reserved */
|
||||
UNUSED(LM_RESERVED_69) /* Vector 69: Reserved */
|
||||
|
||||
UNUSED(LM_RESERVED_70) /* Vector 70: Reserved */
|
||||
#endif
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
|
||||
|
||||
/* If the common ARMv7-M vector handling is used, then all it needs is the following
|
||||
* definition that provides the number of supported vectors.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARMV7M_CMNVECTOR
|
||||
|
||||
/* Reserve 72 interrupt table entries for I/O interrupts. */
|
||||
|
||||
# define ARMV7M_PERIPHERAL_INTERRUPTS 72
|
||||
|
||||
#else
|
||||
|
||||
VECTOR(lm_gpioa, LM_IRQ_GPIOA) /* Vector 16: GPIO Port A */
|
||||
VECTOR(lm_gpiob, LM_IRQ_GPIOB) /* Vector 17: GPIO Port B */
|
||||
VECTOR(lm_gpioc, LM_IRQ_GPIOC) /* Vector 18: GPIO Port C */
|
||||
VECTOR(lm_gpiod, LM_IRQ_GPIOD) /* Vector 19: GPIO Port D */
|
||||
VECTOR(lm_gpioe, LM_IRQ_GPIOE) /* Vector 20: GPIO Port E */
|
||||
|
||||
VECTOR(lm_uart0, LM_IRQ_UART0) /* Vector 21: UART 0 */
|
||||
VECTOR(lm_uart1, LM_IRQ_UART1) /* Vector 22: UART 1 */
|
||||
VECTOR(lm_ssi0, LM_IRQ_SSI0) /* Vector 23: SSI 0 */
|
||||
VECTOR(lm_i2c0, LM_IRQ_I2C0) /* Vector 24: I2C 0 */
|
||||
VECTOR(lm_pwmfault, LM_IRQ_PWMFAULT) /* Vector 25: PWM Fault */
|
||||
VECTOR(lm_pwm0, LM_IRQ_PWM0) /* Vector 26: PWM Generator 0 */
|
||||
VECTOR(lm_pwm1, LM_IRQ_PWM1) /* Vector 27: PWM Generator 1 */
|
||||
VECTOR(lm_pwm2, LM_IRQ_PWM2) /* Vector 28: PWM Generator 2 */
|
||||
VECTOR(lm_qei0, LM_IRQ_QEI0) /* Vector 29: QEI 0 */
|
||||
|
||||
VECTOR(lm_adc0, LM_IRQ_ADC0) /* Vector 30: ADC Sequence 0 */
|
||||
VECTOR(lm_adc1, LM_IRQ_ADC1) /* Vector 31: ADC Sequence 1 */
|
||||
VECTOR(lm_adc2, LM_IRQ_ADC2) /* Vector 32: ADC Sequence 2 */
|
||||
VECTOR(lm_adc3, LM_IRQ_ADC3) /* Vector 33: ADC Sequence 3 */
|
||||
VECTOR(lm_wdog, LM_IRQ_WDOG) /* Vector 34: Watchdog Timer */
|
||||
VECTOR(lm_tmr0a, LM_IRQ_TIMER0A) /* Vector 35: Timer 0 A */
|
||||
VECTOR(lm_tmr0b, LM_IRQ_TIMER0B) /* Vector 36: Timer 0 B */
|
||||
VECTOR(lm_tmr1a, LM_IRQ_TIMER1A) /* Vector 37: Timer 1 A */
|
||||
VECTOR(lm_tmr1b, LM_IRQ_TIMER1B) /* Vector 38: Timer 1 B */
|
||||
VECTOR(lm_tmr2a, LM_IRQ_TIMER2A) /* Vector 39: Timer 2 A */
|
||||
|
||||
VECTOR(lm_tmr2b, LM_IRQ_TIMER2B) /* Vector 40: Timer 3 B */
|
||||
VECTOR(lm_cmp0, LM_IRQ_COMPARE0) /* Vector 41: Analog Comparator 0 */
|
||||
VECTOR(lm_cmp1, LM_IRQ_COMPARE1) /* Vector 42: Analog Comparator 1 */
|
||||
VECTOR(lm_cmp2, LM_IRQ_COMPARE2) /* Vector 43: Analog Comparator 2 */
|
||||
VECTOR(lm_syscon, LM_IRQ_SYSCON) /* Vector 44: System Control */
|
||||
VECTOR(lm_flashcon, LM_IRQ_FLASHCON) /* Vector 45: FLASH Control */
|
||||
VECTOR(lm_gpiof, LM_IRQ_GPIOF) /* Vector 46: GPIO Port F */
|
||||
VECTOR(lm_gpiog, LM_IRQ_GPIOG) /* Vector 47: GPIO Port G */
|
||||
VECTOR(lm_gpioh, LM_IRQ_GPIOH) /* Vector 48: GPIO Port H */
|
||||
VECTOR(lm_uart2, LM_IRQ_UART2) /* Vector 49: UART 2 */
|
||||
|
||||
VECTOR(lm_ssi1, LM_IRQ_SSI1) /* Vector 50: GPIO Port H */
|
||||
VECTOR(lm_tmr3a, LM_IRQ_TIMER3A) /* Vector 51: Timer 3 A */
|
||||
VECTOR(lm_tmr3b, LM_IRQ_TIMER3B) /* Vector 52: Timer 3 B */
|
||||
VECTOR(lm_i2c1, LM_IRQ_I2C1) /* Vector 53: I2C 1 */
|
||||
VECTOR(lm_qei1, LM_IRQ_QEI1) /* Vector 54: QEI 1 */
|
||||
VECTOR(lm_can0, LM_IRQ_CAN0) /* Vector 55: CAN 0 */
|
||||
VECTOR(lm_can1, LM_IRQ_CAN1) /* Vector 56: CAN 1 */
|
||||
UNUSED(LM_RESERVED_57) /* Vector 57: Reserved */
|
||||
VECTOR(lm_eth, LM_IRQ_ETHCON) /* Vector 58: Ethernet Controller */
|
||||
UNUSED(LM_RESERVED_59) /* Vector 59: Reserved */
|
||||
|
||||
VECTOR(lm_usb, LM_IRQ_USB) /* Vector 60: USB */
|
||||
VECTOR(lm_pwm3, LM_IRQ_PWM3) /* Vector 61: PWM 3 */
|
||||
VECTOR(lm_udmasoft, LM_IRQ_UDMASOFT) /* Vector 62: uDMA Software */
|
||||
VECTOR(lm_udmaerror, LM_IRQ_UDMAERROR) /* Vector 63: uDMA Error */
|
||||
VECTOR(lm_adc1_0, LM_IRQ_ADC1_0) /* Vector 64: ADC1 Sequence 0 */
|
||||
VECTOR(lm_adc1_1, LM_IRQ_ADC1_1) /* Vector 65: ADC1 Sequence 1 */
|
||||
VECTOR(lm_adc1_2, LM_IRQ_ADC1_2) /* Vector 66: ADC1 Sequence 2 */
|
||||
VECTOR(lm_adc1_3, LM_IRQ_ADC1_3) /* Vector 67: ADC1 Sequence 3 */
|
||||
VECTOR(lm_i2s0, LM_IRQ_I2S0) /* Vector 68: I2S 0 */
|
||||
VECTOR(lm_epi, LM_IRQ_EPI) /* Vector 69: EPI */
|
||||
|
||||
VECTOR(lm_gpioj, LM_IRQ_GPIOJ) /* Vector 70: GPIO Port J */
|
||||
UNUSED(LM_RESERVED_71) /* Vector 71: Reserved */
|
||||
#endif
|
||||
|
||||
#else
|
||||
# error "Vectors not specified for this Stellaris chip"
|
||||
#endif
|
||||
@@ -44,8 +44,10 @@
|
||||
|
||||
/* Include the memory map file for the specific Stellaris chip */
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_LM3S
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S)
|
||||
# include "chip/lm3s_memorymap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM4F)
|
||||
# include "chip/lm4f_memorymap.h"
|
||||
#else
|
||||
# error "Unsupported Stellaris memory map"
|
||||
#endif
|
||||
|
||||
@@ -44,8 +44,10 @@
|
||||
|
||||
/* Include the pin mapping file for the specific Stellaris chip */
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_LM3S
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S)
|
||||
# include "chip/lm3s_pinmap.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM4F)
|
||||
# include "chip/lm4f_pinmap.h"
|
||||
#else
|
||||
# error "Unsupported Stellaris PIN mapping"
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lm/chip/lm_vectors.h
|
||||
*
|
||||
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/* Include the vector file for the specific Stellaris chip */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S)
|
||||
# include "chip/lm3s_vectors.h"
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM4F)
|
||||
# include "chip/lm4f_vectors.h"
|
||||
#else
|
||||
# error "Unsupported Stellaris vector file"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
@@ -127,290 +127,15 @@ lm_vectors:
|
||||
|
||||
/* External Interrupts */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
|
||||
.word lm_gpioa /* Vector 16: GPIO Port A */
|
||||
.word lm_gpiob /* Vector 17: GPIO Port B */
|
||||
.word lm_gpioc /* Vector 18: GPIO Port C */
|
||||
.word lm_gpiod /* Vector 19: GPIO Port D */
|
||||
.word lm_gpioe /* Vector 20: GPIO Port E */
|
||||
.word lm_uart0 /* Vector 21: UART 0 */
|
||||
.word lm_uart1 /* Vector 22: UART 1 */
|
||||
.word lm_ssi0 /* Vector 23: SSI 0 */
|
||||
.word lm_i2c0 /* Vector 24: I2C 0 */
|
||||
.word lm_reserved /* Vector 25: Reserved */
|
||||
.word lm_reserved /* Vector 26: Reserved */
|
||||
.word lm_reserved /* Vector 27: Reserved */
|
||||
.word lm_reserved /* Vector 28: Reserved */
|
||||
.word lm_reserved /* Vector 29: Reserved */
|
||||
.word lm_adc0 /* Vector 30: ADC Sequence 0 */
|
||||
.word lm_adc1 /* Vector 31: ADC Sequence 1 */
|
||||
.word lm_adc2 /* Vector 32: ADC Sequence 2 */
|
||||
.word lm_adc3 /* Vector 33: ADC Sequence 3 */
|
||||
.word lm_wdog /* Vector 34: Watchdog Timer */
|
||||
.word lm_tmr0a /* Vector 35: Timer 0 A */
|
||||
.word lm_tmr0b /* Vector 36: Timer 0 B */
|
||||
.word lm_tmr1a /* Vector 37: Timer 1 A */
|
||||
.word lm_tmr1b /* Vector 38: Timer 1 B */
|
||||
.word lm_tmr2a /* Vector 39: Timer 2 A */
|
||||
.word lm_tmr2b /* Vector 40: Timer 3 B */
|
||||
.word lm_cmp0 /* Vector 41: Analog Comparator 0 */
|
||||
.word lm_cmp1 /* Vector 42: Analog Comparator 1 */
|
||||
.word lm_reserved /* Vector 43: Reserved */
|
||||
.word lm_syscon /* Vector 44: System Control */
|
||||
.word lm_flashcon /* Vector 45: FLASH Control */
|
||||
.word lm_gpiof /* Vector 46: GPIO Port F */
|
||||
.word lm_gpiog /* Vector 47: GPIO Port G */
|
||||
.word lm_gpioh /* Vector 48: GPIO Port H */
|
||||
.word lm_reserved /* Vector 49: Reserved */
|
||||
.word lm_ssi1 /* Vector 50: SSI 1 */
|
||||
.word lm_tmr3a /* Vector 51: Timer 3 A */
|
||||
.word lm_tmr3b /* Vector 52: Timer 3 B */
|
||||
.word lm_i2c1 /* Vector 53: I2C 1 */
|
||||
.word lm_reserved /* Vector 54: Reserved */
|
||||
.word lm_reserved /* Vector 55: Reserved */
|
||||
.word lm_reserved /* Vector 56: Reserved */
|
||||
.word lm_reserved /* Vector 57: Reserved */
|
||||
.word lm_eth /* Vector 58: Ethernet Controller */
|
||||
.word lm_hib /* Vector 59: Hibernation Module */
|
||||
.word lm_reserved /* Vector 60: Reserved */
|
||||
.word lm_reserved /* Vector 61: Reserved */
|
||||
.word lm_reserved /* Vector 62: Reserved */
|
||||
.word lm_reserved /* Vector 63: Reserved */
|
||||
.word lm_reserved /* Vector 64: Reserved */
|
||||
.word lm_reserved /* Vector 65: Reserved */
|
||||
.word lm_reserved /* Vector 66: Reserved */
|
||||
.word lm_reserved /* Vector 67: Reserved */
|
||||
.word lm_reserved /* Vector 68: Reserved */
|
||||
.word lm_reserved /* Vector 69: Reserved */
|
||||
.word lm_reserved /* Vector 70: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
.word lm_gpioa /* Vector 16: GPIO Port A */
|
||||
.word lm_gpiob /* Vector 17: GPIO Port B */
|
||||
.word lm_gpioc /* Vector 18: GPIO Port C */
|
||||
.word lm_gpiod /* Vector 19: GPIO Port D */
|
||||
.word lm_gpioe /* Vector 20: GPIO Port E */
|
||||
.word lm_uart0 /* Vector 21: UART 0 */
|
||||
.word lm_uart1 /* Vector 22: UART 1 */
|
||||
.word lm_ssi0 /* Vector 23: SSI 0 */
|
||||
.word lm_i2c0 /* Vector 24: I2C 0 */
|
||||
.word lm_reserved /* Vector 25: Reserved */
|
||||
.word lm_pwm0 /* Vector 26: PWM Generator 0 */
|
||||
.word lm_reserved /* Vector 27: Reserved */
|
||||
.word lm_reserved /* Vector 28: Reserved */
|
||||
.word lm_reserved /* Vector 29: Reserved */
|
||||
.word lm_adc0 /* Vector 30: ADC Sequence 0 */
|
||||
.word lm_adc1 /* Vector 31: ADC Sequence 1 */
|
||||
.word lm_adc2 /* Vector 32: ADC Sequence 2 */
|
||||
.word lm_adc3 /* Vector 33: ADC Sequence 3 */
|
||||
.word lm_wdog /* Vector 34: Watchdog Timer */
|
||||
.word lm_tmr0a /* Vector 35: Timer 0 A */
|
||||
.word lm_tmr0b /* Vector 36: Timer 0 B */
|
||||
.word lm_tmr1a /* Vector 37: Timer 1 A */
|
||||
.word lm_tmr1b /* Vector 38: Timer 1 B */
|
||||
.word lm_tmr2a /* Vector 39: Timer 2 A */
|
||||
.word lm_tmr2b /* Vector 40: Timer 3 B */
|
||||
.word lm_cmp0 /* Vector 41: Analog Comparator 0 */
|
||||
.word lm_cmp1 /* Vector 42: Analog Comparator 1 */
|
||||
.word lm_reserved /* Vector 43: Reserved */
|
||||
.word lm_syscon /* Vector 44: System Control */
|
||||
.word lm_flashcon /* Vector 45: FLASH Control */
|
||||
.word lm_gpiof /* Vector 46: GPIO Port F */
|
||||
.word lm_gpiog /* Vector 47: GPIO Port G */
|
||||
.word lm_reserved /* Vector 48: Reserved */
|
||||
.word lm_reserved /* Vector 49: Reserved */
|
||||
.word lm_reserved /* Vector 50: Reserved */
|
||||
.word lm_reserved /* Vector 51: Reserved */
|
||||
.word lm_reserved /* Vector 52: Reserved */
|
||||
.word lm_reserved /* Vector 53: Reserved */
|
||||
.word lm_reserved /* Vector 54: Reserved */
|
||||
.word lm_reserved /* Vector 55: Reserved */
|
||||
.word lm_reserved /* Vector 56: Reserved */
|
||||
.word lm_reserved /* Vector 57: Reserved */
|
||||
.word lm_eth /* Vector 58: Ethernet Controller */
|
||||
.word lm_reserved /* Vector 59: Reserved */
|
||||
.word lm_reserved /* Vector 60: Reserved */
|
||||
.word lm_reserved /* Vector 61: Reserved */
|
||||
.word lm_reserved /* Vector 62: Reserved */
|
||||
.word lm_reserved /* Vector 63: Reserved */
|
||||
.word lm_reserved /* Vector 64: Reserved */
|
||||
.word lm_reserved /* Vector 65: Reserved */
|
||||
.word lm_reserved /* Vector 66: Reserved */
|
||||
.word lm_reserved /* Vector 67: Reserved */
|
||||
.word lm_reserved /* Vector 68: Reserved */
|
||||
.word lm_reserved /* Vector 69: Reserved */
|
||||
.word lm_reserved /* Vector 70: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
.word lm_gpioa /* Vector 16: GPIO Port A */
|
||||
.word lm_gpiob /* Vector 17: GPIO Port B */
|
||||
.word lm_gpioc /* Vector 18: GPIO Port C */
|
||||
.word lm_gpiod /* Vector 19: GPIO Port D */
|
||||
.word lm_gpioe /* Vector 20: GPIO Port E */
|
||||
.word lm_uart0 /* Vector 21: UART 0 */
|
||||
.word lm_uart1 /* Vector 22: UART 1 */
|
||||
.word lm_ssi0 /* Vector 23: SSI 0 */
|
||||
.word lm_i2c0 /* Vector 24: I2C 0 */
|
||||
.word lm_pwmfault /* Vector 25: PWM Fault */
|
||||
.word lm_pwm0 /* Vector 26: PWM Generator 0 */
|
||||
.word lm_pwm1 /* Vector 27: PWM Generator 1 */
|
||||
.word lm_pwm2 /* Vector 28: PWM Generator 2 */
|
||||
.word lm_qei0 /* Vector 29: QEI0 */
|
||||
.word lm_adc0 /* Vector 30: ADC Sequence 0 */
|
||||
.word lm_adc1 /* Vector 31: ADC Sequence 1 */
|
||||
.word lm_adc2 /* Vector 32: ADC Sequence 2 */
|
||||
.word lm_adc3 /* Vector 33: ADC Sequence 3 */
|
||||
.word lm_wdog /* Vector 34: Watchdog Timer */
|
||||
.word lm_tmr0a /* Vector 35: Timer 0 A */
|
||||
.word lm_tmr0b /* Vector 36: Timer 0 B */
|
||||
.word lm_tmr1a /* Vector 37: Timer 1 A */
|
||||
.word lm_tmr1b /* Vector 38: Timer 1 B */
|
||||
.word lm_tmr2a /* Vector 39: Timer 2 A */
|
||||
.word lm_tmr2b /* Vector 40: Timer 3 B */
|
||||
.word lm_cmp0 /* Vector 41: Analog Comparator 0 */
|
||||
.word lm_cmp1 /* Vector 42: Analog Comparator 1 */
|
||||
.word lm_reserved /* Vector 43: Reserved */
|
||||
.word lm_syscon /* Vector 44: System Control */
|
||||
.word lm_flashcon /* Vector 45: FLASH Control */
|
||||
.word lm_gpiof /* Vector 46: GPIO Port F */
|
||||
.word lm_gpiog /* Vector 47: GPIO Port G */
|
||||
.word lm_reserved /* Vector 48: Reserved */
|
||||
.word lm_uart2 /* Vector 49: UART 2 */
|
||||
.word lm_reserved /* Vector 50: Reserved */
|
||||
.word lm_tmr3a /* Vector 51: Timer 3 A */
|
||||
.word lm_tmr3b /* Vector 52: Timer 3 B */
|
||||
.word lm_i2c1 /* Vector 53: I2C 1 */
|
||||
.word lm_qei1 /* Vector 54: QEI1 */
|
||||
.word lm_reserved /* Vector 55: Reserved */
|
||||
.word lm_reserved /* Vector 56: Reserved */
|
||||
.word lm_reserved /* Vector 57: Reserved */
|
||||
.word lm_eth /* Vector 58: Ethernet Controller */
|
||||
.word lm_hib /* Vector 59: Hibernation Module */
|
||||
.word lm_reserved /* Vector 60: Reserved */
|
||||
.word lm_reserved /* Vector 61: Reserved */
|
||||
.word lm_reserved /* Vector 62: Reserved */
|
||||
.word lm_reserved /* Vector 63: Reserved */
|
||||
.word lm_reserved /* Vector 64: Reserved */
|
||||
.word lm_reserved /* Vector 65: Reserved */
|
||||
.word lm_reserved /* Vector 66: Reserved */
|
||||
.word lm_reserved /* Vector 67: Reserved */
|
||||
.word lm_reserved /* Vector 68: Reserved */
|
||||
.word lm_reserved /* Vector 69: Reserved */
|
||||
.word lm_reserved /* Vector 70: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
|
||||
.word lm_gpioa /* Vector 16: GPIO Port A */
|
||||
.word lm_gpiob /* Vector 17: GPIO Port B */
|
||||
.word lm_gpioc /* Vector 18: GPIO Port C */
|
||||
.word lm_gpiod /* Vector 19: GPIO Port D */
|
||||
.word lm_gpioe /* Vector 20: GPIO Port E */
|
||||
.word lm_uart0 /* Vector 21: UART 0 */
|
||||
.word lm_uart1 /* Vector 22: UART 1 */
|
||||
.word lm_ssi0 /* Vector 23: SSI 0 */
|
||||
.word lm_i2c0 /* Vector 24: I2C 0 */
|
||||
.word lm_pwmfault /* Vector 25: PWM Fault */
|
||||
.word lm_pwm0 /* Vector 26: PWM Generator 0 */
|
||||
.word lm_pwm1 /* Vector 27: PWM Generator 1 */
|
||||
.word lm_pwm2 /* Vector 28: PWM Generator 2 */
|
||||
.word lm_qei0 /* Vector 29: QEI0 */
|
||||
.word lm_adc0 /* Vector 30: ADC Sequence 0 */
|
||||
.word lm_adc1 /* Vector 31: ADC Sequence 1 */
|
||||
.word lm_adc2 /* Vector 32: ADC Sequence 2 */
|
||||
.word lm_adc3 /* Vector 33: ADC Sequence 3 */
|
||||
.word lm_wdog /* Vector 34: Watchdog Timer */
|
||||
.word lm_tmr0a /* Vector 35: Timer 0 A */
|
||||
.word lm_tmr0b /* Vector 36: Timer 0 B */
|
||||
.word lm_tmr1a /* Vector 37: Timer 1 A */
|
||||
.word lm_tmr1b /* Vector 38: Timer 1 B */
|
||||
.word lm_tmr2a /* Vector 39: Timer 2 A */
|
||||
.word lm_tmr2b /* Vector 40: Timer 3 B */
|
||||
.word lm_cmp0 /* Vector 41: Analog Comparator 0 */
|
||||
.word lm_cmp1 /* Vector 42: Analog Comparator 1 */
|
||||
.word lm_cmp2 /* Vector 43: Reserved */
|
||||
.word lm_syscon /* Vector 44: System Control */
|
||||
.word lm_flashcon /* Vector 45: FLASH Control */
|
||||
.word lm_gpiof /* Vector 46: GPIO Port F */
|
||||
.word lm_gpiog /* Vector 47: GPIO Port G */
|
||||
.word lm_gpioh /* Vector 48: GPIO Port H */
|
||||
.word lm_uart2 /* Vector 49: UART 2 */
|
||||
.word lm_ssi1 /* Vector 50: SSI 1 */
|
||||
.word lm_tmr3a /* Vector 51: Timer 3 A */
|
||||
.word lm_tmr3b /* Vector 52: Timer 3 B */
|
||||
.word lm_i2c1 /* Vector 53: I2C 1 */
|
||||
.word lm_qei1 /* Vector 54: QEI1 */
|
||||
.word lm_can0 /* Vector 55: CAN 0 */
|
||||
.word lm_can1 /* Vector 56: CAN 1 */
|
||||
.word lm_reserved /* Vector 57: Reserved */
|
||||
.word lm_eth /* Vector 58: Ethernet Controller */
|
||||
.word lm_reserved /* Vector 59: Reserved */
|
||||
.word lm_usb /* Vector 60: USB */
|
||||
.word lm_pwm3 /* Vector 61: PWM 3 */
|
||||
.word lm_udmasoft /* Vector 62: uDMA Software */
|
||||
.word lm_udmaerror /* Vector 63: uDMA Error */
|
||||
.word lm_adc1_0 /* Vector 64: ADC1 Sequence 0 */
|
||||
.word lm_adc1_1 /* Vector 65: ADC1 Sequence 1 */
|
||||
.word lm_adc1_2 /* Vector 66: ADC1 Sequence 2 */
|
||||
.word lm_adc1_3 /* Vector 67: ADC1 Sequence 3 */
|
||||
.word lm_i2s0 /* Vector 68: I2S 0 */
|
||||
.word lm_epi /* Vector 69: Reserved */
|
||||
.word lm_gpioj /* Vector 70: GPIO J */
|
||||
.word lm_reserved /* Vector 71: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
|
||||
.word lm_gpioa /* Vector 16: GPIO Port A */
|
||||
.word lm_gpiob /* Vector 17: GPIO Port B */
|
||||
.word lm_gpioc /* Vector 18: GPIO Port C */
|
||||
.word lm_gpiod /* Vector 19: GPIO Port D */
|
||||
.word lm_gpioe /* Vector 20: GPIO Port E */
|
||||
.word lm_uart0 /* Vector 21: UART 0 */
|
||||
.word lm_uart1 /* Vector 22: UART 1 */
|
||||
.word lm_ssi0 /* Vector 23: SSI 0 */
|
||||
.word lm_i2c0 /* Vector 24: I2C 0 */
|
||||
.word lm_pwmfault /* Vector 25: PWM Fault */
|
||||
.word lm_pwm0 /* Vector 26: PWM Generator 0 */
|
||||
.word lm_pwm1 /* Vector 27: PWM Generator 1 */
|
||||
.word lm_pwm2 /* Vector 28: PWM Generator 2 */
|
||||
.word lm_qei0 /* Vector 29: QEI0 */
|
||||
.word lm_adc0 /* Vector 30: ADC Sequence 0 */
|
||||
.word lm_adc1 /* Vector 31: ADC Sequence 1 */
|
||||
.word lm_adc2 /* Vector 32: ADC Sequence 2 */
|
||||
.word lm_adc3 /* Vector 33: ADC Sequence 3 */
|
||||
.word lm_wdog /* Vector 34: Watchdog Timer */
|
||||
.word lm_tmr0a /* Vector 35: Timer 0 A */
|
||||
.word lm_tmr0b /* Vector 36: Timer 0 B */
|
||||
.word lm_tmr1a /* Vector 37: Timer 1 A */
|
||||
.word lm_tmr1b /* Vector 38: Timer 1 B */
|
||||
.word lm_tmr2a /* Vector 39: Timer 2 A */
|
||||
.word lm_tmr2b /* Vector 40: Timer 3 B */
|
||||
.word lm_cmp0 /* Vector 41: Analog Comparator 0 */
|
||||
.word lm_reserved /* Vector 42: Reserved */
|
||||
.word lm_reserved /* Vector 43: Reserved */
|
||||
.word lm_syscon /* Vector 44: System Control */
|
||||
.word lm_flashcon /* Vector 45: FLASH Control */
|
||||
.word lm_gpiof /* Vector 46: GPIO Port F */
|
||||
.word lm_gpiog /* Vector 47: GPIO Port G */
|
||||
.word lm_reserved /* Vector 48: Reserved */
|
||||
.word lm_reserved /* Vector 49: Reserved */
|
||||
.word lm_reserved /* Vector 50: Reserved */
|
||||
.word lm_tmr3a /* Vector 51: Timer 3 A */
|
||||
.word lm_tmr3b /* Vector 52: Timer 3 B */
|
||||
.word lm_reserved /* Vector 53: Reserved*/
|
||||
.word lm_qei1 /* Vector 54: QEI1 */
|
||||
.word lm_can0 /* Vector 55: Can Controller */
|
||||
.word lm_reserved /* Vector 56: Reserved */
|
||||
.word lm_reserved /* Vector 57: Reserved */
|
||||
.word lm_eth /* Vector 58: Ethernet Controller */
|
||||
.word lm_hib /* Vector 59: Hibernation Module */
|
||||
.word lm_reserved /* Vector 60: Reserved */
|
||||
.word lm_reserved /* Vector 61: Reserved */
|
||||
.word lm_reserved /* Vector 62: Reserved */
|
||||
.word lm_reserved /* Vector 63: Reserved */
|
||||
.word lm_reserved /* Vector 64: Reserved */
|
||||
.word lm_reserved /* Vector 65: Reserved */
|
||||
.word lm_reserved /* Vector 66: Reserved */
|
||||
.word lm_reserved /* Vector 67: Reserved */
|
||||
.word lm_reserved /* Vector 68: Reserved */
|
||||
.word lm_reserved /* Vector 69: Reserved */
|
||||
.word lm_reserved /* Vector 70: Reserved */
|
||||
#else
|
||||
# error "Vectors not specified for this LM3S chip"
|
||||
#endif
|
||||
/* External Interrupts */
|
||||
|
||||
#undef VECTOR
|
||||
#define VECTOR(l,i) .word l
|
||||
|
||||
#undef UNUSED
|
||||
#define UNUSED(i) .word lm_reserved
|
||||
|
||||
#include "chip/chip/lm_vectors.h"
|
||||
.size lm_vectors, .-lm_vectors
|
||||
|
||||
/************************************************************************************
|
||||
@@ -432,204 +157,13 @@ handlers:
|
||||
HANDLER lm_pendsv, LM_IRQ_PENDSV /* Vector 14: Penable system service request */
|
||||
HANDLER lm_systick, LM_IRQ_SYSTICK /* Vector 15: System tick */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */
|
||||
HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: SSI 1 */
|
||||
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */
|
||||
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
|
||||
HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
|
||||
HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */
|
||||
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */
|
||||
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
|
||||
HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
|
||||
HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */
|
||||
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */
|
||||
HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */
|
||||
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
|
||||
HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
|
||||
HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_cmp2, LM_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */
|
||||
HANDLER lm_uart2, LM_IRQ_UART2 /* Vector 49: UART 2 */
|
||||
HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: GPIO Port H */
|
||||
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */
|
||||
HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */
|
||||
HANDLER lm_can1, LM_IRQ_CAN1 /* Vector 56: CAN 1 */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_usb, LM_IRQ_USB /* Vector 60: USB */
|
||||
HANDLER lm_pwm3, LM_IRQ_PWM3 /* Vector 61: PWM 3 */
|
||||
HANDLER lm_udmasoft, LM_IRQ_UDMASOFT /* Vector 62: uDMA Software */
|
||||
HANDLER lm_udmaerror, LM_IRQ_UDMAERROR /* Vector 63: uDMA Error */
|
||||
HANDLER lm_adc1_0, LM_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */
|
||||
HANDLER lm_adc1_1, LM_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */
|
||||
HANDLER lm_adc1_2, LM_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */
|
||||
HANDLER lm_adc1_3, LM_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */
|
||||
HANDLER lm_i2s0, LM_IRQ_I2S0 /* Vector 68: I2S 0 */
|
||||
HANDLER lm_epi, LM_IRQ_EPI /* Vector 69: EPI */
|
||||
HANDLER lm_gpioj, LM_IRQ_GPIOJ /* Vector 70: GPIO Port J */
|
||||
#else
|
||||
# error "Vectors not specified for this Stellaris chip"
|
||||
#endif
|
||||
#undef VECTOR
|
||||
#define VECTOR(l,i) HANDLER l, i
|
||||
|
||||
#undef UNUSED
|
||||
#define UNUSED(i)
|
||||
|
||||
#include "chip/chip/lm_vectors.h"
|
||||
|
||||
/* Common IRQ handling logic. On entry here, the return stack is on either
|
||||
* the PSP or the MSP and looks like the following:
|
||||
|
||||
Reference in New Issue
Block a user