mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-06-30 11:30:36 +08:00
Change naming of all Stellaris pre-processor symbols from LM3S_ to LM_ to make room in the namespace for LM4F
git-svn-id: http://svn.code.sf.net/p/nuttx/code/trunk@5498 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -49,63 +49,63 @@
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/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
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#if defined(CONFIG_ARCH_CHIP_LM3S6918)
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# define LM3S_NTIMERS 4 /* Four general purpose timers */
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# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM3S_ETHTS /* No timestamp register */
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# define LM3S_NSSI 2 /* Two SSI modules */
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# define LM3S_NUARTS 2 /* Two UART modules */
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# define LM3S_NI2C 2 /* Two I2C modules */
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# define LM3S_NADC 1 /* One ADC module */
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# define LM2S_NPWM 0 /* No PWM generator modules */
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# define LM3S_NQEI 0 /* No quadrature encoders */
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# define LM3S_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 2 /* Two SSI modules */
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# define LM_NUARTS 2 /* Two UART modules */
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# define LM_NI2C 2 /* Two I2C modules */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 0 /* No PWM generator modules */
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# define LM_NQEI 0 /* No quadrature encoders */
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# define LM_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
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# define LM3S_NTIMERS 3 /* Three general purpose timers */
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# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM3S_ETHTS /* No timestamp register */
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# define LM3S_NSSI 1 /* One SSI module */
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# define LM3S_NUARTS 2 /* Two UART modules */
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# define LM3S_NI2C 1 /* Two I2C modules */
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# define LM3S_NADC 1 /* One ADC module */
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# define LM2S_NPWM 1 /* One PWM generator module */
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# define LM3S_NQEI 0 /* No quadrature encoders */
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# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define LM_NTIMERS 3 /* Three general purpose timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 1 /* One SSI module */
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# define LM_NUARTS 2 /* Two UART modules */
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# define LM_NI2C 1 /* Two I2C modules */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 1 /* One PWM generator module */
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# define LM_NQEI 0 /* No quadrature encoders */
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# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
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# define LM3S_NTIMERS 4 /* Four general purpose timers */
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# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM3S_ETHTS /* No timestamp register */
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# define LM3S_NSSI 1 /* One SSI module */
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# define LM3S_NUARTS 3 /* Three UART modules */
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# define LM3S_NI2C 2 /* Two I2C modules */
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# define LM3S_NADC 1 /* One ADC module */
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# define LM2S_NPWM 3 /* Three PWM generator modules */
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# define LM3S_NQEI 2 /* Two quadrature encoders */
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# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 1 /* One SSI module */
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# define LM_NUARTS 3 /* Three UART modules */
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# define LM_NI2C 2 /* Two I2C modules */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 3 /* Three PWM generator modules */
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# define LM_NQEI 2 /* Two quadrature encoders */
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# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
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#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
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# define LM3S_NTIMERS 4 /* Four general purpose timers */
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# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM3S_ETHTS /* No timestamp register */
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# define LM3S_NSSI 2 /* Two SSI modules */
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# define LM3S_NUARTS 3 /* Three UART modules */
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# define LM3S_NI2C 2 /* Two I2C modules */
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# define LM3S_NADC 2 /* Two ADC module */
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# define LM3S_CAN 2 /* Two CAN module */
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# define LM3S_NPWM 4 /* Four PWM generator modules */
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# define LM3S_NQEI 2 /* Two quadrature encoders */
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# define LM3S_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# undef LM_ETHTS /* No timestamp register */
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# define LM_NSSI 2 /* Two SSI modules */
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# define LM_NUARTS 3 /* Three UART modules */
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# define LM_NI2C 2 /* Two I2C modules */
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# define LM_NADC 2 /* Two ADC module */
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# define LM_CAN 2 /* Two CAN module */
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# define LM_NPWM 4 /* Four PWM generator modules */
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# define LM_NQEI 2 /* Two quadrature encoders */
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# define LM_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
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#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
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# define LM3S_NTIMERS 4 /* Four general purpose timers */
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# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define LM3S_NSSI 1 /* One SSI module */
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# define LM3S_NUARTS 3 /* Two UART modules */
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# define LM3S_NI2C 2 /* One I2C module */
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# define LM3S_NADC 1 /* One ADC module */
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# define LM2S_NPWM 3 /* Three PWM generator modules */
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# define LM3S_NQEI 2 /* Two quadrature encoders */
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# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
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# define LC3S_CANCONTROLLER 1 /* One CAN controller */
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# define LM_NTIMERS 4 /* Four general purpose timers */
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# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
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# define LM_NSSI 1 /* One SSI module */
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# define LM_NUARTS 3 /* Two UART modules */
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# define LM_NI2C 2 /* One I2C module */
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# define LM_NADC 1 /* One ADC module */
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# define LM_NPWM 3 /* Three PWM generator modules */
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# define LM_NQEI 2 /* Two quadrature encoders */
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# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
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# define LM_CANCONTROLLER 1 /* One CAN controller */
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#else
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# error "Capabilities not specified for this LM3S chip"
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# error "Capabilities not specified for this Stellaris chip"
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#endif
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/************************************************************************************
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+325
-325
@@ -58,250 +58,250 @@
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/* Processor Exceptions (vectors 0-15) */
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#define LM3S_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define LM3S_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define LM3S_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define LM3S_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define LM3S_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define LM3S_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define LM3S_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define LM3S_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define LM3S_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define LM3S_IRQ_SYSTICK (15) /* Vector 15: System tick */
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#define LM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define LM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define LM_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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#define LM_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
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#define LM_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
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#define LM_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
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#define LM_IRQ_SVCALL (11) /* Vector 11: SVC call */
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#define LM_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
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/* Vector 13: Reserved */
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#define LM_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define LM_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16) */
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#define LM3S_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
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#define LM_IRQ_INTERRUPTS (16) /* Vector number of the first external interrupt */
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#if defined(CONFIG_ARCH_CHIP_LM3S6918)
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# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
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# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
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# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
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# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
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# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
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# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */
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# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */
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# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
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# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
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/* Vector 25-29: Reserved */
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# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
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# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
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# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
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# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
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# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
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# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
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# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
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# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
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# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
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# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
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# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
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# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
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# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
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/* Vector 43: Reserved */
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# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */
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# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
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# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
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# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
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# define LM3S_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
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/* Vector 49: Reserved */
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# define LM3S_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
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# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
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# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
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# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
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/* Vectors 54-57: Reserved */
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# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
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# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
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/* Vectors 60-70: Reserved */
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# define NR_IRQS (60) /* (Really less because of reserved vectors) */
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# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
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# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
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# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
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# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
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# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
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# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
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# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
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# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
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# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
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/* Vector 25-29: Reserved */
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# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
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# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
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# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
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# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
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# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
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# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
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# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
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# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
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# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
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# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
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# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
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# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
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# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
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/* Vector 43: Reserved */
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# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
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# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
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# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
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# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
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# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
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/* Vector 49: Reserved */
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# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
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# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
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# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
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# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
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/* Vectors 54-57: Reserved */
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# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
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# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
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/* Vectors 60-70: Reserved */
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# define NR_IRQS (60) /* (Really less because of reserved vectors) */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
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# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
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# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
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# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
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# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
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# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
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# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */
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# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */
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# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
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# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
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/* Vector 25: Reserved */
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# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
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/* Vectors 27-29: Reserved */
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# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
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# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
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# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
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# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
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# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
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# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
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# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
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# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
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# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
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# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
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# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
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# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
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# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
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/* Vector 43: Reserved */
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# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */
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# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
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# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
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# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
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/* Vectors 48-57: Reserved */
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# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
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/* Vectors 59-70: Reserved */
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# define NR_IRQS (60) /* (Really less because of reserved vectors) */
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# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
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# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
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# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
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# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
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# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
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# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
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# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
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# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
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# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
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/* Vector 25: Reserved */
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# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
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/* Vectors 27-29: Reserved */
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# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
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# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
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# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
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# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
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# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
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# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
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# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
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# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
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# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
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# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
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# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
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# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
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# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
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/* Vector 43: Reserved */
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# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
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# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
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# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
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# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
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/* Vectors 48-57: Reserved */
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# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
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/* Vectors 59-70: Reserved */
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# define NR_IRQS (60) /* (Really less because of reserved vectors) */
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#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
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# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
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# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
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# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
|
||||
# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
|
||||
# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */
|
||||
# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */
|
||||
# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
|
||||
# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
|
||||
# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
|
||||
# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
|
||||
# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
|
||||
# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
|
||||
# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */
|
||||
# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
|
||||
# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
|
||||
# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
|
||||
# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
|
||||
# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
|
||||
# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
|
||||
# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
|
||||
# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
|
||||
# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
|
||||
# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
|
||||
# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
|
||||
# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
|
||||
# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
|
||||
/* Vector 43: Reserved */
|
||||
# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */
|
||||
# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
|
||||
# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
|
||||
# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
|
||||
/* Vector 48: Reserved */
|
||||
# define LM3S_IRQ_UART2 (49) /* Vector 49: UART 2 */
|
||||
/* Vector 50: Reserved */
|
||||
# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
|
||||
# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
|
||||
# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
|
||||
# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */
|
||||
/* Vectors 55-57: Reserved */
|
||||
# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
|
||||
# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
|
||||
/* Vectors 60-70: Reserved */
|
||||
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
|
||||
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
|
||||
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
|
||||
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
|
||||
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
|
||||
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
|
||||
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
|
||||
# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
|
||||
# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
|
||||
# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
|
||||
# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
|
||||
# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */
|
||||
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
|
||||
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
|
||||
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
|
||||
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
|
||||
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
|
||||
# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
|
||||
# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
|
||||
# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
|
||||
# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
|
||||
# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
|
||||
# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
|
||||
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
|
||||
# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
|
||||
/* Vector 43: Reserved */
|
||||
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
|
||||
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
|
||||
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
|
||||
# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
|
||||
/* Vector 48: Reserved */
|
||||
# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */
|
||||
/* Vector 50: Reserved */
|
||||
# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
|
||||
# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
|
||||
# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
|
||||
# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */
|
||||
/* Vectors 55-57: Reserved */
|
||||
# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
|
||||
# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
|
||||
/* Vectors 60-70: Reserved */
|
||||
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
|
||||
# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
|
||||
# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
|
||||
# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */
|
||||
# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */
|
||||
# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
|
||||
# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
|
||||
# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
|
||||
# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
|
||||
# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
|
||||
# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
|
||||
# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */
|
||||
# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */
|
||||
# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */
|
||||
# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */
|
||||
# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */
|
||||
# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
|
||||
# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
|
||||
# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
|
||||
# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
|
||||
# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
|
||||
# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
|
||||
# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
|
||||
# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
|
||||
# define LM3S_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
|
||||
# define LM3S_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */
|
||||
# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */
|
||||
# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
|
||||
# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
|
||||
# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
|
||||
# define LM3S_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
|
||||
# define LM3S_IRQ_UART2 (49) /* Vector 49: UART 2 */
|
||||
# define LM3S_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
|
||||
# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
|
||||
# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
|
||||
# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
|
||||
# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */
|
||||
# define LM3S_IRQ_CAN0 (55) /* Vector 55: CAN 1 */
|
||||
# define LM3S_IRQ_CAN1 (56) /* Vector 56: CAN 2 */
|
||||
/* Vector 57: Reserved */
|
||||
# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
|
||||
/* Vector 59: Reserved */
|
||||
# define LM3S_IRQ_USB (60) /* Vector 60: USB */
|
||||
# define LM3S_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */
|
||||
# define LM3S_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
|
||||
# define LM3S_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
|
||||
# define LM3S_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
|
||||
# define LM3S_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
|
||||
# define LM3S_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
|
||||
# define LM3S_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
|
||||
# define LM3S_IRQ_I2S0 (68) /* Vector 68: I2S0 */
|
||||
# define LM3S_IRQ_EPI (69) /* Vector 69: EPI */
|
||||
# define LM3S_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
|
||||
/* Vector 71: Reserved */
|
||||
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
|
||||
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
|
||||
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
|
||||
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
|
||||
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
|
||||
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
|
||||
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
|
||||
# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
|
||||
# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
|
||||
# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
|
||||
# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
|
||||
# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */
|
||||
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC0 Sequence 0 */
|
||||
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC0 Sequence 1 */
|
||||
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC0 Sequence 2 */
|
||||
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC0 Sequence 3 */
|
||||
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
|
||||
# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
|
||||
# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
|
||||
# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
|
||||
# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
|
||||
# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
|
||||
# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
|
||||
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
|
||||
# define LM_IRQ_COMPARE1 (42) /* Vector 42: Analog Comparator 1 */
|
||||
# define LM_IRQ_COMPARE2 (43) /* Vector 43: Analog Comparator 3 */
|
||||
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
|
||||
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
|
||||
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
|
||||
# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
|
||||
# define LM_IRQ_GPIOH (48) /* Vector 48: GPIO Port H */
|
||||
# define LM_IRQ_UART2 (49) /* Vector 49: UART 2 */
|
||||
# define LM_IRQ_SSI1 (50) /* Vector 50: SSI 1 */
|
||||
# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
|
||||
# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
|
||||
# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
|
||||
# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */
|
||||
# define LM_IRQ_CAN0 (55) /* Vector 55: CAN 1 */
|
||||
# define LM_IRQ_CAN1 (56) /* Vector 56: CAN 2 */
|
||||
/* Vector 57: Reserved */
|
||||
# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
|
||||
/* Vector 59: Reserved */
|
||||
# define LM_IRQ_USB (60) /* Vector 60: USB */
|
||||
# define LM_IRQ_PWM3 (61) /* Vector 61: PWM Generator 3 */
|
||||
# define LM_IRQ_UDMASOFT (62) /* Vector 62: uDMA Software */
|
||||
# define LM_IRQ_UDMAERROR (63) /* Vector 63: uDMA Error */
|
||||
# define LM_IRQ_ADC1_0 (64) /* Vector 64: ADC1 Sequence 0 */
|
||||
# define LM_IRQ_ADC1_1 (65) /* Vector 65: ADC1 Sequence 1 */
|
||||
# define LM_IRQ_ADC1_2 (66) /* Vector 66: ADC1 Sequence 2 */
|
||||
# define LM_IRQ_ADC1_3 (67) /* Vector 67: ADC1 Sequence 3 */
|
||||
# define LM_IRQ_I2S0 (68) /* Vector 68: I2S0 */
|
||||
# define LM_IRQ_EPI (69) /* Vector 69: EPI */
|
||||
# define LM_IRQ_GPIOJ (70) /* Vector 70: GPIO Port J */
|
||||
/* Vector 71: Reserved */
|
||||
# define NR_IRQS (71) /* (Really less because of reserved vectors) */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
|
||||
# define LM3S_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define LM3S_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
# define LM3S_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
# define LM3S_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
|
||||
# define LM3S_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
|
||||
# define LM3S_IRQ_UART0 (21) /* Vector 21: UART 0 */
|
||||
# define LM3S_IRQ_UART1 (22) /* Vector 22: UART 1 */
|
||||
# define LM3S_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
|
||||
# define LM3S_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
|
||||
# define LM3S_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
|
||||
# define LM3S_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
|
||||
# define LM3S_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
|
||||
# define LM3S_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
|
||||
# define LM3S_IRQ_QEI0 (29) /* Vector 29: QEI0 */
|
||||
# define LM3S_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
|
||||
# define LM3S_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
|
||||
# define LM3S_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
|
||||
# define LM3S_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
|
||||
# define LM3S_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
|
||||
# define LM3S_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
|
||||
# define LM3S_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
|
||||
# define LM3S_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
|
||||
# define LM3S_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
|
||||
# define LM3S_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
|
||||
# define LM3S_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
|
||||
# define LM3S_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
|
||||
/* Vector 42: Reserved */
|
||||
/* Vector 43: Reserved */
|
||||
# define LM3S_IRQ_SYSCON (44) /* Vector 44: System Control */
|
||||
# define LM3S_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
|
||||
# define LM3S_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
|
||||
# define LM3S_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
|
||||
/* Vector 48: Reserved */
|
||||
/* Vector 49: Reserved */
|
||||
/* Vector 50: Reserved */
|
||||
# define LM3S_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
|
||||
# define LM3S_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
|
||||
# define LM3S_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
|
||||
# define LM3S_IRQ_QEI1 (54) /* Vector 54: QEI1 */
|
||||
# define LM3S_IRQ_CAN0 (54) /* Vector 55: CAN0 */
|
||||
/* Vectors 56-57: Reserved */
|
||||
# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
|
||||
# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
|
||||
/* Vectors 60-70: Reserved */
|
||||
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
|
||||
# define LM_IRQ_GPIOA (16) /* Vector 16: GPIO Port A */
|
||||
# define LM_IRQ_GPIOB (17) /* Vector 17: GPIO Port B */
|
||||
# define LM_IRQ_GPIOC (18) /* Vector 18: GPIO Port C */
|
||||
# define LM_IRQ_GPIOD (19) /* Vector 19: GPIO Port D */
|
||||
# define LM_IRQ_GPIOE (20) /* Vector 20: GPIO Port E */
|
||||
# define LM_IRQ_UART0 (21) /* Vector 21: UART 0 */
|
||||
# define LM_IRQ_UART1 (22) /* Vector 22: UART 1 */
|
||||
# define LM_IRQ_SSI0 (23) /* Vector 23: SSI 0 */
|
||||
# define LM_IRQ_I2C0 (24) /* Vector 24: I2C 0 */
|
||||
# define LM_IRQ_PWMFAULT (25) /* Vector 25: PWM Fault */
|
||||
# define LM_IRQ_PWM0 (26) /* Vector 26: PWM Generator 0 */
|
||||
# define LM_IRQ_PWM1 (27) /* Vector 27: PWM Generator 1 */
|
||||
# define LM_IRQ_PWM2 (28) /* Vector 28: PWM Generator 2 */
|
||||
# define LM_IRQ_QEI0 (29) /* Vector 29: QEI0 */
|
||||
# define LM_IRQ_ADC0 (30) /* Vector 30: ADC Sequence 0 */
|
||||
# define LM_IRQ_ADC1 (31) /* Vector 31: ADC Sequence 1 */
|
||||
# define LM_IRQ_ADC2 (32) /* Vector 32: ADC Sequence 2 */
|
||||
# define LM_IRQ_ADC3 (33) /* Vector 33: ADC Sequence 3 */
|
||||
# define LM_IRQ_WDOG (34) /* Vector 34: Watchdog Timer */
|
||||
# define LM_IRQ_TIMER0A (35) /* Vector 35: Timer 0 A */
|
||||
# define LM_IRQ_TIMER0B (36) /* Vector 36: Timer 0 B */
|
||||
# define LM_IRQ_TIMER1A (37) /* Vector 37: Timer 1 A */
|
||||
# define LM_IRQ_TIMER1B (38) /* Vector 38: Timer 1 B */
|
||||
# define LM_IRQ_TIMER2A (39) /* Vector 39: Timer 2 A */
|
||||
# define LM_IRQ_TIMER2B (40) /* Vector 40: Timer 3 B */
|
||||
# define LM_IRQ_COMPARE0 (41) /* Vector 41: Analog Comparator 0 */
|
||||
/* Vector 42: Reserved */
|
||||
/* Vector 43: Reserved */
|
||||
# define LM_IRQ_SYSCON (44) /* Vector 44: System Control */
|
||||
# define LM_IRQ_FLASHCON (45) /* Vector 45: FLASH Control */
|
||||
# define LM_IRQ_GPIOF (46) /* Vector 46: GPIO Port F */
|
||||
# define LM_IRQ_GPIOG (47) /* Vector 47: GPIO Port G */
|
||||
/* Vector 48: Reserved */
|
||||
/* Vector 49: Reserved */
|
||||
/* Vector 50: Reserved */
|
||||
# define LM_IRQ_TIMER3A (51) /* Vector 51: Timer 3 A */
|
||||
# define LM_IRQ_TIMER3B (52) /* Vector 52: Timer 3 B */
|
||||
# define LM_IRQ_I2C1 (53) /* Vector 53: I2C 1 */
|
||||
# define LM_IRQ_QEI1 (54) /* Vector 54: QEI1 */
|
||||
# define LM_IRQ_CAN0 (54) /* Vector 55: CAN0 */
|
||||
/* Vectors 56-57: Reserved */
|
||||
# define LM_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
|
||||
# define LM_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
|
||||
/* Vectors 60-70: Reserved */
|
||||
# define NR_IRQS (60) /* (Really less because of reserved vectors) */
|
||||
#else
|
||||
# error "IRQ Numbers not specified for this LM3S chip"
|
||||
# error "IRQ Numbers not specified for this Stellaris chip"
|
||||
#endif
|
||||
|
||||
/* GPIO IRQs -- Note that support for individual GPIO ports can
|
||||
@@ -309,132 +309,132 @@
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
|
||||
# define LM3S_IRQ_GPIOA_0 (NR_IRQS + 0)
|
||||
# define LM3S_IRQ_GPIOA_1 (NR_IRQS + 1)
|
||||
# define LM3S_IRQ_GPIOA_2 (NR_IRQS + 2)
|
||||
# define LM3S_IRQ_GPIOA_3 (NR_IRQS + 3)
|
||||
# define LM3S_IRQ_GPIOA_4 (NR_IRQS + 4)
|
||||
# define LM3S_IRQ_GPIOA_5 (NR_IRQS + 5)
|
||||
# define LM3S_IRQ_GPIOA_6 (NR_IRQS + 6)
|
||||
# define LM3S_IRQ_GPIOA_7 (NR_IRQS + 7)
|
||||
# define _NGPIOAIRQS (NR_IRQS + 8)
|
||||
# define LM_IRQ_GPIOA_0 (NR_IRQS + 0)
|
||||
# define LM_IRQ_GPIOA_1 (NR_IRQS + 1)
|
||||
# define LM_IRQ_GPIOA_2 (NR_IRQS + 2)
|
||||
# define LM_IRQ_GPIOA_3 (NR_IRQS + 3)
|
||||
# define LM_IRQ_GPIOA_4 (NR_IRQS + 4)
|
||||
# define LM_IRQ_GPIOA_5 (NR_IRQS + 5)
|
||||
# define LM_IRQ_GPIOA_6 (NR_IRQS + 6)
|
||||
# define LM_IRQ_GPIOA_7 (NR_IRQS + 7)
|
||||
# define _NGPIOAIRQS (NR_IRQS + 8)
|
||||
#else
|
||||
# define _NGPIOAIRQS NR_IRQS
|
||||
# define _NGPIOAIRQS NR_IRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
|
||||
# define LM3S_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
|
||||
# define LM3S_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
|
||||
# define LM3S_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
|
||||
# define LM3S_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
|
||||
# define LM3S_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
|
||||
# define LM3S_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
|
||||
# define LM3S_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
|
||||
# define LM3S_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
|
||||
# define _NGPIOBIRQS (_NGPIOAIRQS + 8)
|
||||
# define LM_IRQ_GPIOB_0 (_NGPIOAIRQS + 0)
|
||||
# define LM_IRQ_GPIOB_1 (_NGPIOAIRQS + 1)
|
||||
# define LM_IRQ_GPIOB_2 (_NGPIOAIRQS + 2)
|
||||
# define LM_IRQ_GPIOB_3 (_NGPIOAIRQS + 3)
|
||||
# define LM_IRQ_GPIOB_4 (_NGPIOAIRQS + 4)
|
||||
# define LM_IRQ_GPIOB_5 (_NGPIOAIRQS + 5)
|
||||
# define LM_IRQ_GPIOB_6 (_NGPIOAIRQS + 6)
|
||||
# define LM_IRQ_GPIOB_7 (_NGPIOAIRQS + 7)
|
||||
# define _NGPIOBIRQS (_NGPIOAIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOBIRQS _NGPIOAIRQS
|
||||
# define _NGPIOBIRQS _NGPIOAIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
|
||||
# define LM3S_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
|
||||
# define LM3S_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
|
||||
# define LM3S_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
|
||||
# define LM3S_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
|
||||
# define LM3S_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
|
||||
# define LM3S_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
|
||||
# define LM3S_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
|
||||
# define LM3S_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
|
||||
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
|
||||
# define LM_IRQ_GPIOC_0 (_NGPIOBIRQS + 0)
|
||||
# define LM_IRQ_GPIOC_1 (_NGPIOBIRQS + 1)
|
||||
# define LM_IRQ_GPIOC_2 (_NGPIOBIRQS + 2)
|
||||
# define LM_IRQ_GPIOC_3 (_NGPIOBIRQS + 3)
|
||||
# define LM_IRQ_GPIOC_4 (_NGPIOBIRQS + 4)
|
||||
# define LM_IRQ_GPIOC_5 (_NGPIOBIRQS + 5)
|
||||
# define LM_IRQ_GPIOC_6 (_NGPIOBIRQS + 6)
|
||||
# define LM_IRQ_GPIOC_7 (_NGPIOBIRQS + 7)
|
||||
# define _NGPIOCIRQS (_NGPIOBIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOCIRQS _NGPIOBIRQS
|
||||
# define _NGPIOCIRQS _NGPIOBIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
|
||||
# define LM3S_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
|
||||
# define LM3S_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
|
||||
# define LM3S_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
|
||||
# define LM3S_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
|
||||
# define LM3S_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
|
||||
# define LM3S_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
|
||||
# define LM3S_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
|
||||
# define LM3S_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
|
||||
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
|
||||
# define LM_IRQ_GPIOD_0 (_NGPIOCIRQS + 0)
|
||||
# define LM_IRQ_GPIOD_1 (_NGPIOCIRQS + 1)
|
||||
# define LM_IRQ_GPIOD_2 (_NGPIOCIRQS + 2)
|
||||
# define LM_IRQ_GPIOD_3 (_NGPIOCIRQS + 3)
|
||||
# define LM_IRQ_GPIOD_4 (_NGPIOCIRQS + 4)
|
||||
# define LM_IRQ_GPIOD_5 (_NGPIOCIRQS + 5)
|
||||
# define LM_IRQ_GPIOD_6 (_NGPIOCIRQS + 6)
|
||||
# define LM_IRQ_GPIOD_7 (_NGPIOCIRQS + 7)
|
||||
# define _NGPIODIRQS (_NGPIOCIRQS + 8)
|
||||
#else
|
||||
# define _NGPIODIRQS _NGPIOCIRQS
|
||||
# define _NGPIODIRQS _NGPIOCIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
|
||||
# define LM3S_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
|
||||
# define LM3S_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
|
||||
# define LM3S_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
|
||||
# define LM3S_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
|
||||
# define LM3S_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
|
||||
# define LM3S_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
|
||||
# define LM3S_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
|
||||
# define LM3S_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
|
||||
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
|
||||
# define LM_IRQ_GPIOE_0 (_NGPIODIRQS + 0)
|
||||
# define LM_IRQ_GPIOE_1 (_NGPIODIRQS + 1)
|
||||
# define LM_IRQ_GPIOE_2 (_NGPIODIRQS + 2)
|
||||
# define LM_IRQ_GPIOE_3 (_NGPIODIRQS + 3)
|
||||
# define LM_IRQ_GPIOE_4 (_NGPIODIRQS + 4)
|
||||
# define LM_IRQ_GPIOE_5 (_NGPIODIRQS + 5)
|
||||
# define LM_IRQ_GPIOE_6 (_NGPIODIRQS + 6)
|
||||
# define LM_IRQ_GPIOE_7 (_NGPIODIRQS + 7)
|
||||
# define _NGPIOEIRQS (_NGPIODIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOEIRQS _NGPIODIRQS
|
||||
# define _NGPIOEIRQS _NGPIODIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
|
||||
# define LM3S_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
|
||||
# define LM3S_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
|
||||
# define LM3S_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
|
||||
# define LM3S_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
|
||||
# define LM3S_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
|
||||
# define LM3S_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
|
||||
# define LM3S_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
|
||||
# define LM3S_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
|
||||
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
|
||||
# define LM_IRQ_GPIOF_0 (_NGPIOEIRQS + 0)
|
||||
# define LM_IRQ_GPIOF_1 (_NGPIOEIRQS + 1)
|
||||
# define LM_IRQ_GPIOF_2 (_NGPIOEIRQS + 2)
|
||||
# define LM_IRQ_GPIOF_3 (_NGPIOEIRQS + 3)
|
||||
# define LM_IRQ_GPIOF_4 (_NGPIOEIRQS + 4)
|
||||
# define LM_IRQ_GPIOF_5 (_NGPIOEIRQS + 5)
|
||||
# define LM_IRQ_GPIOF_6 (_NGPIOEIRQS + 6)
|
||||
# define LM_IRQ_GPIOF_7 (_NGPIOEIRQS + 7)
|
||||
# define _NGPIOFIRQS (_NGPIOEIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOFIRQS _NGPIOEIRQS
|
||||
# define _NGPIOFIRQS _NGPIOEIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
|
||||
# define LM3S_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
|
||||
# define LM3S_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
|
||||
# define LM3S_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
|
||||
# define LM3S_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
|
||||
# define LM3S_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
|
||||
# define LM3S_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
|
||||
# define LM3S_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
|
||||
# define LM3S_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
|
||||
# define _NGPIOGIRQS (_NGPIOFIRQS + 8)
|
||||
# define LM_IRQ_GPIOG_0 (_NGPIOFIRQS + 0)
|
||||
# define LM_IRQ_GPIOG_1 (_NGPIOFIRQS + 1)
|
||||
# define LM_IRQ_GPIOG_2 (_NGPIOFIRQS + 2)
|
||||
# define LM_IRQ_GPIOG_3 (_NGPIOFIRQS + 3)
|
||||
# define LM_IRQ_GPIOG_4 (_NGPIOFIRQS + 4)
|
||||
# define LM_IRQ_GPIOG_5 (_NGPIOFIRQS + 5)
|
||||
# define LM_IRQ_GPIOG_6 (_NGPIOFIRQS + 6)
|
||||
# define LM_IRQ_GPIOG_7 (_NGPIOFIRQS + 7)
|
||||
# define _NGPIOGIRQS (_NGPIOFIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOGIRQS _NGPIOFIRQS
|
||||
# define _NGPIOGIRQS _NGPIOFIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
|
||||
# define LM3S_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
|
||||
# define LM3S_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
|
||||
# define LM3S_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
|
||||
# define LM3S_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
|
||||
# define LM3S_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
|
||||
# define LM3S_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
|
||||
# define LM3S_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
|
||||
# define LM3S_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
|
||||
# define _NGPIOHIRQS (_NGPIOGIRQS + 8)
|
||||
# define LM_IRQ_GPIOH_0 (_NGPIOGIRQS + 0)
|
||||
# define LM_IRQ_GPIOH_1 (_NGPIOGIRQS + 1)
|
||||
# define LM_IRQ_GPIOH_2 (_NGPIOGIRQS + 2)
|
||||
# define LM_IRQ_GPIOH_3 (_NGPIOGIRQS + 3)
|
||||
# define LM_IRQ_GPIOH_4 (_NGPIOGIRQS + 4)
|
||||
# define LM_IRQ_GPIOH_5 (_NGPIOGIRQS + 5)
|
||||
# define LM_IRQ_GPIOH_6 (_NGPIOGIRQS + 6)
|
||||
# define LM_IRQ_GPIOH_7 (_NGPIOGIRQS + 7)
|
||||
# define _NGPIOHIRQS (_NGPIOGIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOHIRQS _NGPIOGIRQS
|
||||
# define _NGPIOHIRQS _NGPIOGIRQS
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
|
||||
# define LM3S_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
|
||||
# define LM3S_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
|
||||
# define LM3S_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
|
||||
# define LM3S_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
|
||||
# define LM3S_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
|
||||
# define LM3S_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
|
||||
# define LM3S_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
|
||||
# define LM3S_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
|
||||
# define _NGPIOJIRQS (_NGPIOHIRQS + 8)
|
||||
# define LM_IRQ_GPIOJ_0 (_NGPIOHIRQS + 0)
|
||||
# define LM_IRQ_GPIOJ_1 (_NGPIOHIRQS + 1)
|
||||
# define LM_IRQ_GPIOJ_2 (_NGPIOHIRQS + 2)
|
||||
# define LM_IRQ_GPIOJ_3 (_NGPIOHIRQS + 3)
|
||||
# define LM_IRQ_GPIOJ_4 (_NGPIOHIRQS + 4)
|
||||
# define LM_IRQ_GPIOJ_5 (_NGPIOHIRQS + 5)
|
||||
# define LM_IRQ_GPIOJ_6 (_NGPIOHIRQS + 6)
|
||||
# define LM_IRQ_GPIOJ_7 (_NGPIOHIRQS + 7)
|
||||
# define _NGPIOJIRQS (_NGPIOHIRQS + 8)
|
||||
#else
|
||||
# define _NGPIOJIRQS _NGPIOHIRQS
|
||||
# define _NGPIOJIRQS _NGPIOHIRQS
|
||||
#endif
|
||||
|
||||
#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS)
|
||||
#define NR_GPIO_IRQS (_NGPIOJIRQS - NR_IRQS)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
|
||||
@@ -50,44 +50,44 @@
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6432) || \
|
||||
defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
|
||||
# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
|
||||
/* -0x1fffffff: Reserved */
|
||||
# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
|
||||
/* -0x21ffffff: Reserved */
|
||||
# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
|
||||
/* -0x3fffffff: Reserved */
|
||||
# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
|
||||
/* -0x41ffffff: Peripherals */
|
||||
# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
|
||||
/* -0xdfffffff: Reserved */
|
||||
# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
|
||||
# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
|
||||
# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
|
||||
/* -0xe000dfff: Reserved */
|
||||
# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
|
||||
/* -0xe003ffff: Reserved */
|
||||
# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
|
||||
/* -0xffffffff: Reserved */
|
||||
# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
|
||||
/* -0x1fffffff: Reserved */
|
||||
# define LM_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
|
||||
/* -0x21ffffff: Reserved */
|
||||
# define LM_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
|
||||
/* -0x3fffffff: Reserved */
|
||||
# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
|
||||
/* -0x41ffffff: Peripherals */
|
||||
# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
|
||||
/* -0xdfffffff: Reserved */
|
||||
# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
|
||||
# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
|
||||
# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
|
||||
/* -0xe000dfff: Reserved */
|
||||
# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
|
||||
/* -0xe003ffff: Reserved */
|
||||
# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
|
||||
/* -0xffffffff: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
|
||||
# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
|
||||
/* -0x1fffffff: Reserved */
|
||||
# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
|
||||
/* -0x21ffffff: Reserved */
|
||||
# define LM3S_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
|
||||
/* -0x3fffffff: Reserved */
|
||||
# define LM3S_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
|
||||
/* -0x41ffffff: Peripherals */
|
||||
# define LM3S_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
|
||||
/* -0x5fffffff: Reserved */
|
||||
# define LM3S_EPI0RAM_BASE 0x60000000 /* -0xDfffffff: EPI0 mapped peripheral and RAM */
|
||||
# define LM3S_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
|
||||
# define LM3S_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
|
||||
# define LM3S_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
|
||||
/* -0xe000dfff: Reserved */
|
||||
# define LM3S_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
|
||||
/* -0xe003ffff: Reserved */
|
||||
# define LM3S_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
|
||||
/* -0xffffffff: Reserved */
|
||||
# define LM_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
|
||||
/* -0x1fffffff: Reserved */
|
||||
# define LM_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
|
||||
/* -0x21ffffff: Reserved */
|
||||
# define LM_ASRAM_BASE 0x22000000 /* -0x221fffff: Bit-band alias of 20000000- */
|
||||
/* -0x3fffffff: Reserved */
|
||||
# define LM_PERIPH_BASE 0x40000000 /* -0x4001ffff: FiRM Peripherals */
|
||||
/* -0x41ffffff: Peripherals */
|
||||
# define LM_APERIPH_BASE 0x42000000 /* -0x43ffffff: Bit-band alise of 40000000- */
|
||||
/* -0x5fffffff: Reserved */
|
||||
# define LM_EPI0RAM_BASE 0x60000000 /* -0xdfffffff: EPI0 mapped peripheral and RAM */
|
||||
# define LM_ITM_BASE 0xe0000000 /* -0xe0000fff: Instrumentation Trace Macrocell */
|
||||
# define LM_DWT_BASE 0xe0001000 /* -0xe0001fff: Data Watchpoint and Trace */
|
||||
# define LM_FPB_BASE 0xe0002000 /* -0xe0002fff: Flash Patch and Breakpoint */
|
||||
/* -0xe000dfff: Reserved */
|
||||
# define LM_NVIC_BASE 0xe000e000 /* -0xe000efff: Nested Vectored Interrupt Controller */
|
||||
/* -0xe003ffff: Reserved */
|
||||
# define LM_TPIU_BASE 0xe0040000 /* -0xe0040fff: Trace Port Interface Unit */
|
||||
/* -0xffffffff: Reserved */
|
||||
#else
|
||||
# error "Memory map not specified for this LM3S chip"
|
||||
#endif
|
||||
@@ -102,247 +102,247 @@
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
|
||||
/* FiRM Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
/* -0x1ffff: Reserved */
|
||||
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI1 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
/* -0x1ffff: Reserved */
|
||||
/* Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
|
||||
# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */
|
||||
# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
|
||||
# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
# define LM_GPIOH_BASE (LM_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */
|
||||
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
/* FiRM Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
/* -0x1ffff: Reserved */
|
||||
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
/* -0x1ffff: Reserved */
|
||||
/* Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
/* -0x27fff: Reserved */
|
||||
# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */
|
||||
# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
/* -0x27fff: Reserved */
|
||||
# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */
|
||||
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
/* FiRM Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
|
||||
/* -0x1ffff: Reserved */
|
||||
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
|
||||
/* -0x1ffff: Reserved */
|
||||
/* Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
|
||||
# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
/* -0x27fff: Reserved */
|
||||
# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
|
||||
/* -0x2bfff: Reserved */
|
||||
# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
|
||||
# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */
|
||||
# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
|
||||
# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
/* -0x27fff: Reserved */
|
||||
# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
|
||||
/* -0x2bfff: Reserved */
|
||||
# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
|
||||
# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */
|
||||
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
|
||||
/* FiRM Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
/* -0x1ffff: Reserved */
|
||||
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
/* -0x1ffff: Reserved */
|
||||
/* Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
/* -0x27fff: Reserved */
|
||||
# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
|
||||
/* -0x2bfff: Reserved */
|
||||
# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
|
||||
# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x3fffff: Reserved */
|
||||
# define LM3S_CANCON_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
|
||||
# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
/* -0x27fff: Reserved */
|
||||
# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
|
||||
/* -0x2bfff: Reserved */
|
||||
# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
|
||||
# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM_ADC_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
/* -0x3fffff: Reserved */
|
||||
# define LM_CANCON_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM_HIBERNATE_BASE (LM_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
|
||||
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
|
||||
/* FiRM Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
# define LM3S_SSI1_BASE (LM3S_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
# define LM3S_UART2_BASE (LM3S_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
|
||||
/* -0x1ffff: Reserved */
|
||||
# define LM_WDOG_BASE (LM_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
|
||||
/* -0x03fff: Reserved */
|
||||
# define LM_GPIOA_BASE (LM_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
|
||||
# define LM_GPIOB_BASE (LM_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
|
||||
# define LM_GPIOC_BASE (LM_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
|
||||
# define LM_GPIOD_BASE (LM_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
|
||||
# define LM_SSI0_BASE (LM_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
|
||||
# define LM_SSI1_BASE (LM_PERIPH_BASE + 0x09000) /* -0x09fff: SSI0 */
|
||||
/* -0x0bfff: Reserved */
|
||||
# define LM_UART0_BASE (LM_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
|
||||
# define LM_UART1_BASE (LM_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
|
||||
# define LM_UART2_BASE (LM_PERIPH_BASE + 0x0e000) /* -0x0dfff: UART2 */
|
||||
/* -0x1ffff: Reserved */
|
||||
/* Peripheral Base Addresses */
|
||||
|
||||
# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
# define LM3S_I2CM1_BASE (LM3S_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
|
||||
# define LM3S_I2CS1_BASE (LM3S_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
# define LM3S_GPIOH_BASE (LM3S_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
|
||||
# define LM_I2CM0_BASE (LM_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
|
||||
# define LM_I2CS0_BASE (LM_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
|
||||
# define LM_I2CM1_BASE (LM_PERIPH_BASE + 0x21000) /* -0x217ff: I2C Master 1 */
|
||||
# define LM_I2CS1_BASE (LM_PERIPH_BASE + 0x21800) /* -0x21fff: I2C Slave 1 */
|
||||
/* -0x23fff: Reserved */
|
||||
# define LM_GPIOE_BASE (LM_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
|
||||
# define LM_GPIOF_BASE (LM_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
|
||||
# define LM_GPIOG_BASE (LM_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
|
||||
# define LM_GPIOH_BASE (LM_PERIPH_BASE + 0x27000) /* -0x27fff: GPIO Port H */
|
||||
|
||||
# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
|
||||
/* -0x2bfff: Reserved */
|
||||
# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
|
||||
# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM3S_ADC0_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
|
||||
# define LM3S_ADC1_BASE (LM3S_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
# define LM3S_GPIOJ_BASE (LM3S_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */
|
||||
/* -0x3ffff: Reserved */
|
||||
# define LM3S_CAN0_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */
|
||||
# define LM3S_CAN1_BASE (LM3S_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0x49fff: Reserved */
|
||||
# define LM3S_USB_BASE (LM3S_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
|
||||
/* -0x53fff: Reserved */
|
||||
# define LM3S_I2S0_BASE (LM3S_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */
|
||||
/* -0x57fff: Reserved */
|
||||
# define LM3S_GPIOAAHB_BASE (LM3S_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
|
||||
# define LM3S_GPIOBAHB_BASE (LM3S_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
|
||||
# define LM3S_GPIOCAHB_BASE (LM3S_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */
|
||||
# define LM3S_GPIODAHB_BASE (LM3S_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */
|
||||
# define LM3S_GPIOEAHB_BASE (LM3S_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */
|
||||
# define LM3S_GPIOFAHB_BASE (LM3S_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */
|
||||
# define LM3S_GPIOGAHB_BASE (LM3S_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */
|
||||
# define LM3S_GPIOHAHB_BASE (LM3S_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */
|
||||
# define LM3S_GPIOJAHB_BASE (LM3S_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */
|
||||
/* -0xcffff: Reserved */
|
||||
# define LM3S_EPI0_BASE (LM3S_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
# define LM3S_UDMA_BASE (LM3S_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
# define LM_PWM0_BASE (LM_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
|
||||
/* -0x2bfff: Reserved */
|
||||
# define LM_QEI0_BASE (LM_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
|
||||
# define LM_QEI1_BASE (LM_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
|
||||
/* -0x2ffff: Reserved */
|
||||
# define LM_TIMER0_BASE (LM_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
|
||||
# define LM_TIMER1_BASE (LM_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
|
||||
# define LM_TIMER2_BASE (LM_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
|
||||
# define LM_TIMER3_BASE (LM_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
|
||||
/* -0x37fff: Reserved */
|
||||
# define LM_ADC0_BASE (LM_PERIPH_BASE + 0x38000) /* -0x38fff: ADC 0 */
|
||||
# define LM_ADC1_BASE (LM_PERIPH_BASE + 0x39000) /* -0x39fff: ADC 1 */
|
||||
/* -0x3bfff: Reserved */
|
||||
# define LM_COMPARE_BASE (LM_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
|
||||
# define LM_GPIOJ_BASE (LM_PERIPH_BASE + 0x3d000) /* -0x3dfff: GPIO Port J */
|
||||
/* -0x3ffff: Reserved */
|
||||
# define LM_CAN0_BASE (LM_PERIPH_BASE + 0x40000) /* -0x40fff: CAN 0 */
|
||||
# define LM_CAN1_BASE (LM_PERIPH_BASE + 0x41000) /* -0x41fff: CAN 1 */
|
||||
/* -0x47fff: Reserved */
|
||||
# define LM_ETHCON_BASE (LM_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
|
||||
/* -0x49fff: Reserved */
|
||||
# define LM_USB_BASE (LM_PERIPH_BASE + 0x50000) /* -0x50fff: USB */
|
||||
/* -0x53fff: Reserved */
|
||||
# define LM_I2S0_BASE (LM_PERIPH_BASE + 0x54000) /* -0x54fff: I2S 0 */
|
||||
/* -0x57fff: Reserved */
|
||||
# define LM_GPIOAAHB_BASE (LM_PERIPH_BASE + 0x58000) /* -0x58fff: GPIO Port A (AHB aperture) */
|
||||
# define LM_GPIOBAHB_BASE (LM_PERIPH_BASE + 0x59000) /* -0x59fff: GPIO Port B (AHB aperture) */
|
||||
# define LM_GPIOCAHB_BASE (LM_PERIPH_BASE + 0x5A000) /* -0x5afff: GPIO Port C (AHB aperture) */
|
||||
# define LM_GPIODAHB_BASE (LM_PERIPH_BASE + 0x5B000) /* -0x5bfff: GPIO Port D (AHB aperture) */
|
||||
# define LM_GPIOEAHB_BASE (LM_PERIPH_BASE + 0x5C000) /* -0x5cfff: GPIO Port E (AHB aperture) */
|
||||
# define LM_GPIOFAHB_BASE (LM_PERIPH_BASE + 0x5D000) /* -0x5dfff: GPIO Port F (AHB aperture) */
|
||||
# define LM_GPIOGAHB_BASE (LM_PERIPH_BASE + 0x5E000) /* -0x5efff: GPIO Port G (AHB aperture) */
|
||||
# define LM_GPIOHAHB_BASE (LM_PERIPH_BASE + 0x5F000) /* -0x5ffff: GPIO Port H (AHB aperture) */
|
||||
# define LM_GPIOJAHB_BASE (LM_PERIPH_BASE + 0x60000) /* -0x60fff: GPIO Port J (AHB aperture) */
|
||||
/* -0xcffff: Reserved */
|
||||
# define LM_EPI0_BASE (LM_PERIPH_BASE + 0xD0000) /* -0xd0fff: EPI 0 */
|
||||
/* -0xfcfff: Reserved */
|
||||
# define LM_FLASHCON_BASE (LM_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
|
||||
# define LM_SYSCON_BASE (LM_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
|
||||
# define LM_UDMA_BASE (LM_PERIPH_BASE + 0xff000) /* -0xfffff: System Control */
|
||||
/* -0x1ffffff: Reserved */
|
||||
#else
|
||||
# error "Peripheral base addresses not specified for this LM3S chip"
|
||||
# error "Peripheral base addresses not specified for this Stellaris chip"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
@@ -263,7 +263,7 @@
|
||||
# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
|
||||
# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */
|
||||
#else
|
||||
# error "Unknown LM3S chip"
|
||||
# error "Unknown Stellaris chip"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -46,19 +46,19 @@
|
||||
|
||||
/* External Peripheral Interface Register Offsets ***********************************/
|
||||
|
||||
#define LM3S_EPI_CFG_OFFSET 0x000
|
||||
#define LM3S_EPI_SDRAMCFG_OFFSET 0x010
|
||||
#define LM3S_EPI_ADDRMAP_OFFSET 0x01C
|
||||
#define LM3S_EPI_STAT_OFFSET 0x060
|
||||
#define LM3S_EPI_BAUD_OFFSET 0x004
|
||||
#define LM_EPI_CFG_OFFSET 0x000
|
||||
#define LM_EPI_SDRAMCFG_OFFSET 0x010
|
||||
#define LM_EPI_ADDRMAP_OFFSET 0x01C
|
||||
#define LM_EPI_STAT_OFFSET 0x060
|
||||
#define LM_EPI_BAUD_OFFSET 0x004
|
||||
|
||||
/* External Peripheral Interface Register Addresses *********************************/
|
||||
|
||||
#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
|
||||
#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
|
||||
#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
|
||||
#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
|
||||
#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
|
||||
#define LM_EPI0_CFG (LM_EPI0_BASE + LM_EPI_CFG_OFFSET)
|
||||
#define LM_EPI0_SDRAMCFG (LM_EPI0_BASE + LM_EPI_SDRAMCFG_OFFSET)
|
||||
#define LM_EPI0_ADDRMAP (LM_EPI0_BASE + LM_EPI_ADDRMAP_OFFSET)
|
||||
#define LM_EPI0_STAT (LM_EPI0_BASE + LM_EPI_STAT_OFFSET)
|
||||
#define LM_EPI0_BAUD (LM_EPI0_BASE + LM_EPI_BAUD_OFFSET)
|
||||
|
||||
/* External Peripheral Interface Register Bit Definitions ***************************/
|
||||
|
||||
@@ -110,4 +110,4 @@
|
||||
#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
|
||||
# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H */
|
||||
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -53,63 +53,63 @@
|
||||
|
||||
/* Ethernet MAC Register Offsets */
|
||||
|
||||
#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
|
||||
#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
|
||||
#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
|
||||
#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
|
||||
#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
|
||||
#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
|
||||
#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
|
||||
#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
|
||||
#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
|
||||
#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
|
||||
#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
|
||||
#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
|
||||
#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
|
||||
#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
|
||||
#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
|
||||
#ifdef LM3S_ETHTS
|
||||
# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
|
||||
#define LM_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
|
||||
#define LM_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
|
||||
#define LM_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
|
||||
#define LM_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
|
||||
#define LM_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
|
||||
#define LM_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
|
||||
#define LM_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
|
||||
#define LM_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
|
||||
#define LM_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
|
||||
#define LM_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
|
||||
#define LM_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
|
||||
#define LM_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
|
||||
#define LM_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
|
||||
#define LM_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
|
||||
#define LM_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
|
||||
#ifdef LM_ETHTS
|
||||
# define LM_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
|
||||
#endif
|
||||
|
||||
/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
|
||||
|
||||
/* Ethernet Controller Register Addresses *******************************************/
|
||||
|
||||
#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
|
||||
#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
|
||||
#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
|
||||
#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
|
||||
#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
|
||||
#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
|
||||
#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
|
||||
#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
|
||||
#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
|
||||
#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
|
||||
#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
|
||||
#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
|
||||
#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
|
||||
#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
|
||||
#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
|
||||
#ifdef LM3S_ETHTS
|
||||
# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
|
||||
#define LM_MAC_RIS (LM_ETHCON_BASE + LM_MAC_RIS_OFFSET)
|
||||
#define LM_MAC_IACK (LM_ETHCON_BASE + LM_MAC_IACK_OFFSET)
|
||||
#define LM_MAC_IM (LM_ETHCON_BASE + LM_MAC_IM_OFFSET)
|
||||
#define LM_MAC_RCTL (LM_ETHCON_BASE + LM_MAC_RCTL_OFFSET)
|
||||
#define LM_MAC_TCTL (LM_ETHCON_BASE + LM_MAC_TCTL_OFFSET)
|
||||
#define LM_MAC_DATA (LM_ETHCON_BASE + LM_MAC_DATA_OFFSET)
|
||||
#define LM_MAC_IA0 (LM_ETHCON_BASE + LM_MAC_IA0_OFFSET)
|
||||
#define LM_MAC_IA1 (LM_ETHCON_BASE + LM_MAC_IA1_OFFSET)
|
||||
#define LM_MAC_THR (LM_ETHCON_BASE + LM_MAC_THR_OFFSET)
|
||||
#define LM_MAC_MCTL (LM_ETHCON_BASE + LM_MAC_MCTL_OFFSET)
|
||||
#define LM_MAC_MDV (LM_ETHCON_BASE + LM_MAC_MDV_OFFSET)
|
||||
#define LM_MAC_MTXD (LM_ETHCON_BASE + LM_MAC_MTXD_OFFSET)
|
||||
#define LM_MAC_MRXD (LM_ETHCON_BASE + LM_MAC_MRXD_OFFSET)
|
||||
#define LM_MAC_NP (LM_ETHCON_BASE + LM_MAC_NP_OFFSET)
|
||||
#define LM_MAC_TR (LM_ETHCON_BASE + LM_MAC_TR_OFFSET)
|
||||
#ifdef LM_ETHTS
|
||||
# define LM_MAC_TS (LM_ETHCON_BASE + LM_MAC_TS_OFFSET)
|
||||
#endif
|
||||
|
||||
/* Memory Mapped MII Management Registers */
|
||||
|
||||
#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR)
|
||||
#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR)
|
||||
#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1)
|
||||
#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2)
|
||||
#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE)
|
||||
#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA)
|
||||
#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION)
|
||||
#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
|
||||
#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
|
||||
#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
|
||||
#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
|
||||
#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
|
||||
#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
|
||||
#define MAC_MII_MCR (LM_ETHCON_BASE + MII_MCR)
|
||||
#define MAC_MII_MSR (LM_ETHCON_BASE + MII_MSR)
|
||||
#define MAC_MII_PHYID1 (LM_ETHCON_BASE + MII_PHYID1)
|
||||
#define MAC_MII_PHYID2 (LM_ETHCON_BASE + MII_PHYID2)
|
||||
#define MAC_MII_ADVERTISE (LM_ETHCON_BASE + MII_ADVERTISE)
|
||||
#define MAC_MII_LPA (LM_ETHCON_BASE + MII_LPA)
|
||||
#define MAC_MII_EXPANSION (LM_ETHCON_BASE + MII_EXPANSION)
|
||||
#define MAC_MII_VSPECIFIC (LM_ETHCON_BASE + MII_LM_VSPECIFIC)
|
||||
#define MAC_MII_INTCS (LM_ETHCON_BASE + MII_LM_INTCS)
|
||||
#define MAC_MII_DIAGNOSTIC (LM_ETHCON_BASE + MII_LM_DIAGNOSTIC)
|
||||
#define MAC_MII_XCVRCONTROL (LM_ETHCON_BASE + MII_LM_XCVRCONTROL)
|
||||
#define MAC_MII_LEDCONFIG (LM_ETHCON_BASE + MII_LM_LEDCONFIG)
|
||||
#define MAC_MII_MDICONTROL (LM_ETHCON_BASE + MII_LM_MDICONTROL)
|
||||
|
||||
/* Ethernet Controller Register Bit Definitions *************************************/
|
||||
|
||||
@@ -200,4 +200,4 @@
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H */
|
||||
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -49,66 +49,66 @@
|
||||
/* FLASH register offsets ***********************************************************/
|
||||
|
||||
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
|
||||
* control base address of LM3S_FLASHCON_BASE.
|
||||
* control base address of LM_FLASHCON_BASE.
|
||||
*/
|
||||
|
||||
#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
|
||||
#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
|
||||
#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
|
||||
#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
|
||||
#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
|
||||
#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */
|
||||
#define LM_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
|
||||
#define LM_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
|
||||
#define LM_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
|
||||
#define LM_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
|
||||
#define LM_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
|
||||
#define LM_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */
|
||||
|
||||
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
|
||||
* System Control base address of LM3S_SYSCON_BASE
|
||||
* System Control base address of LM_SYSCON_BASE
|
||||
*/
|
||||
|
||||
#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
|
||||
#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
|
||||
#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
|
||||
#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
|
||||
#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
|
||||
#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
|
||||
#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
|
||||
#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
|
||||
#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
|
||||
#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
|
||||
#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
|
||||
#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
|
||||
#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
|
||||
#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
|
||||
#define LM_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
|
||||
#define LM_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
|
||||
#define LM_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
|
||||
#define LM_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
|
||||
#define LM_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
|
||||
#define LM_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
|
||||
#define LM_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
|
||||
#define LM_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
|
||||
#define LM_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
|
||||
#define LM_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
|
||||
#define LM_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
|
||||
#define LM_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
|
||||
#define LM_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
|
||||
#define LM_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
|
||||
|
||||
/* FLASH register addresses *********************************************************/
|
||||
|
||||
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
|
||||
* control base address of LM3S_FLASHCON_BASE.
|
||||
* control base address of LM_FLASHCON_BASE.
|
||||
*/
|
||||
|
||||
#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
|
||||
#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
|
||||
#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
|
||||
#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
|
||||
#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
|
||||
#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
|
||||
#define LM_FLASH_FMA (LM_FLASHCON_BASE + LM_FLASH_FMA_OFFSET)
|
||||
#define LM_FLASH_FMD (LM_FLASHCON_BASE + LM_FLASH_FMD_OFFSET)
|
||||
#define LM_FLASH_FMC (LM_FLASHCON_BASE + LM_FLASH_FMC_OFFSET)
|
||||
#define LM_FLASH_FCRIS (LM_FLASHCON_BASE + LM_FLASH_FCRIS_OFFSET)
|
||||
#define LM_FLASH_FCIM (LM_FLASHCON_BASE + LM_FLASH_FCIM_OFFSET)
|
||||
#define LM_FLASH_FCMISC (LM_FLASHCON_BASE + LM_FLASH_FCMISC_OFFSET)
|
||||
|
||||
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
|
||||
* System Control base address of LM3S_SYSCON_BASE
|
||||
* System Control base address of LM_SYSCON_BASE
|
||||
*/
|
||||
|
||||
#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
|
||||
#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
|
||||
#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
|
||||
#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
|
||||
#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
|
||||
#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
|
||||
#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
|
||||
#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
|
||||
#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
|
||||
#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
|
||||
#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
|
||||
#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
|
||||
#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
|
||||
#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
|
||||
#define LM_FLASH_FMPRE (LM_SYSCON_BASE + LM_FLASH_FMPRE_OFFSET)
|
||||
#define LM_FLASH_FMPPE (LM_SYSCON_BASE + LM_FLASH_FMPPE_OFFSET)
|
||||
#define LM_FLASH_USECRL (LM_SYSCON_BASE + LM_FLASH_USECRL_OFFSET)
|
||||
#define LM_FLASH_USERDBG (LM_SYSCON_BASE + LM_FLASH_USERDBG_OFFSET)
|
||||
#define LM_FLASH_USERREG0 (LM_SYSCON_BASE + LM_FLASH_USERREG0_OFFSET)
|
||||
#define LM_FLASH_USERREG1 (LM_SYSCON_BASE + LM_FLASH_USERREG1_OFFSET)
|
||||
#define LM_FLASH_FMPRE0 (LM_SYSCON_BASE + LM_FLASH_FMPRE0_OFFSET)
|
||||
#define LM_FLASH_FMPRE1 (LM_SYSCON_BASE + LM_FLASH_FMPRE1_OFFSET)
|
||||
#define LM_FLASH_FMPRE2 (LM_SYSCON_BASE + LM_FLASH_FMPRE2_OFFSET)
|
||||
#define LM_FLASH_FMPRE3 (LM_SYSCON_BASE + LM_FLASH_FMPRE3_OFFSET)
|
||||
#define LM_FLASH_FMPPE0 (LM_SYSCON_BASE + LM_FLASH_FMPPE0_OFFSET)
|
||||
#define LM_FLASH_FMPPE1 (LM_SYSCON_BASE + LM_FLASH_FMPPE1_OFFSET)
|
||||
#define LM_FLASH_FMPPE2 (LM_SYSCON_BASE + LM_FLASH_FMPPE2_OFFSET)
|
||||
#define LM_FLASH_FMPPE3 (LM_SYSCON_BASE + LM_FLASH_FMPPE3_OFFSET)
|
||||
|
||||
/* FLASH register bit defitiions ****************************************************/
|
||||
/* To be provided */
|
||||
@@ -125,4 +125,4 @@
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H */
|
||||
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -48,337 +48,337 @@
|
||||
|
||||
/* GPIO Register Offsets ************************************************************/
|
||||
|
||||
#define LM3S_GPIO_DATA_OFFSET 0x000 /* GPIO Data */
|
||||
#define LM3S_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */
|
||||
#define LM3S_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */
|
||||
#define LM3S_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */
|
||||
#define LM3S_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */
|
||||
#define LM3S_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */
|
||||
#define LM3S_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */
|
||||
#define LM3S_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */
|
||||
#define LM3S_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */
|
||||
#define LM3S_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */
|
||||
#define LM3S_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */
|
||||
#define LM3S_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */
|
||||
#define LM3S_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */
|
||||
#define LM3S_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */
|
||||
#define LM3S_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */
|
||||
#define LM3S_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */
|
||||
#define LM3S_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */
|
||||
#define LM3S_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */
|
||||
#define LM3S_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */
|
||||
#define LM3S_GPIO_CR_OFFSET 0x524 /* GPIO Commit */
|
||||
#define LM3S_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */
|
||||
#define LM3S_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */
|
||||
#define LM3S_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */
|
||||
#define LM3S_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */
|
||||
#define LM3S_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */
|
||||
#define LM3S_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */
|
||||
#define LM3S_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */
|
||||
#define LM3S_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */
|
||||
#define LM3S_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */
|
||||
#define LM3S_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */
|
||||
#define LM3S_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */
|
||||
#define LM3S_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/
|
||||
#define LM_GPIO_DATA_OFFSET 0x000 /* GPIO Data */
|
||||
#define LM_GPIO_DIR_OFFSET 0x400 /* GPIO Direction */
|
||||
#define LM_GPIO_IS_OFFSET 0x404 /* GPIO Interrupt Sense */
|
||||
#define LM_GPIO_IBE_OFFSET 0x408 /* GPIO Interrupt Both Edges */
|
||||
#define LM_GPIO_IEV_OFFSET 0x40c /* GPIO Interrupt Event */
|
||||
#define LM_GPIO_IM_OFFSET 0x410 /* GPIO Interrupt Mask */
|
||||
#define LM_GPIO_RIS_OFFSET 0x414 /* GPIO Raw Interrupt Status */
|
||||
#define LM_GPIO_MIS_OFFSET 0x418 /* GPIO Masked Interrupt Status */
|
||||
#define LM_GPIO_ICR_OFFSET 0x41c /* GPIO Interrupt Clear */
|
||||
#define LM_GPIO_AFSEL_OFFSET 0x420 /* GPIO Alternate Function */
|
||||
#define LM_GPIO_DR2R_OFFSET 0x500 /* Select GPIO 2-mA Drive Select */
|
||||
#define LM_GPIO_DR4R_OFFSET 0x504 /* GPIO 4-mA Drive Select */
|
||||
#define LM_GPIO_DR8R_OFFSET 0x508 /* GPIO 8-mA Drive Select */
|
||||
#define LM_GPIO_ODR_OFFSET 0x50c /* GPIO Open Drain Select */
|
||||
#define LM_GPIO_PUR_OFFSET 0x510 /* GPIO Pull-Up Select */
|
||||
#define LM_GPIO_PDR_OFFSET 0x514 /* GPIO Pull-Down Select */
|
||||
#define LM_GPIO_SLR_OFFSET 0x518 /* GPIO Slew Rate Control Select */
|
||||
#define LM_GPIO_DEN_OFFSET 0x51C /* GPIO Digital Enable */
|
||||
#define LM_GPIO_LOCK_OFFSET 0x520 /* GPIO Lock */
|
||||
#define LM_GPIO_CR_OFFSET 0x524 /* GPIO Commit */
|
||||
#define LM_GPIO_PERIPHID4_OFFSET 0xfd0 /* GPIO Peripheral Identification 4 */
|
||||
#define LM_GPIO_PERIPHID5_OFFSET 0xfd4 /* GPIO Peripheral Identification 5 */
|
||||
#define LM_GPIO_PERIPHID6_OFFSET 0xfd8 /* GPIO Peripheral Identification 6 */
|
||||
#define LM_GPIO_PERIPHID7_OFFSET 0xfdc /* GPIO Peripheral Identification 7 */
|
||||
#define LM_GPIO_PERIPHID0_OFFSET 0xfe0 /* GPIO Peripheral Identification 0 */
|
||||
#define LM_GPIO_PERIPHID1_OFFSET 0xfe4 /* GPIO Peripheral Identification 1 */
|
||||
#define LM_GPIO_PERIPHID2_OFFSET 0xfe8 /* GPIO Peripheral Identification 2 */
|
||||
#define LM_GPIO_PERIPHID3_OFFSET 0xfec /* GPIO Peripheral Identification 3 */
|
||||
#define LM_GPIO_PCELLID0_OFFSET 0xff0 /* GPIO PrimeCell Identification 0 */
|
||||
#define LM_GPIO_PCELLID1_OFFSET 0xff4 /* GPIO PrimeCell Identification 1 */
|
||||
#define LM_GPIO_PCELLID2_OFFSET 0xff8 /* GPIO PrimeCell Identification 2 */
|
||||
#define LM_GPIO_PCELLID3_OFFSET 0xffc /* GPIO PrimeCell Identification 3*/
|
||||
|
||||
/* GPIO Register Addresses **********************************************************/
|
||||
|
||||
#define LM3S_GPIOA_DATA (LM3S_GPIOA_BASE + LM3S_GPIO_DATA_OFFSET)
|
||||
#define LM3S_GPIOA_DIR (LM3S_GPIOA_BASE + LM3S_GPIO_DIR_OFFSET)
|
||||
#define LM3S_GPIOA_IS (LM3S_GPIOA_BASE + LM3S_GPIO_IS_OFFSET)
|
||||
#define LM3S_GPIOA_IBE (LM3S_GPIOA_BASE + LM3S_GPIO_IBE_OFFSET)
|
||||
#define LM3S_GPIOA_IEV (LM3S_GPIOA_BASE + LM3S_GPIO_IEV_OFFSET)
|
||||
#define LM3S_GPIOA_IM (LM3S_GPIOA_BASE + LM3S_GPIO_IM_OFFSET)
|
||||
#define LM3S_GPIOA_RIS (LM3S_GPIOA_BASE + LM3S_GPIO_RIS_OFFSET)
|
||||
#define LM3S_GPIOA_MIS (LM3S_GPIOA_BASE + LM3S_GPIO_MIS_OFFSET)
|
||||
#define LM3S_GPIOA_ICR (LM3S_GPIOA_BASE + LM3S_GPIO_ICR_OFFSET)
|
||||
#define LM3S_GPIOA_AFSEL (LM3S_GPIOA_BASE + LM3S_GPIO_AFSEL_OFFSET)
|
||||
#define LM3S_GPIOA_DR2R (LM3S_GPIOA_BASE + LM3S_GPIO_DR2R_OFFSET)
|
||||
#define LM3S_GPIOA_DR4R (LM3S_GPIOA_BASE + LM3S_GPIO_DR4R_OFFSET)
|
||||
#define LM3S_GPIOA_DR8R (LM3S_GPIOA_BASE + LM3S_GPIO_DR8R_OFFSET)
|
||||
#define LM3S_GPIOA_ODR (LM3S_GPIOA_BASE + LM3S_GPIO_ODR_OFFSET)
|
||||
#define LM3S_GPIOA_PUR (LM3S_GPIOA_BASE + LM3S_GPIO_PUR_OFFSET)
|
||||
#define LM3S_GPIOA_PDR (LM3S_GPIOA_BASE + LM3S_GPIO_PDR_OFFSET)
|
||||
#define LM3S_GPIOA_SLR (LM3S_GPIOA_BASE + LM3S_GPIO_SLR_OFFSET)
|
||||
#define LM3S_GPIOA_DEN (LM3S_GPIOA_BASE + LM3S_GPIO_DEN_OFFSET)
|
||||
#define LM3S_GPIOA_LOCK (LM3S_GPIOA_BASE + LM3S_GPIO_LOCK_OFFSET)
|
||||
#define LM3S_GPIOA_CR (LM3S_GPIOA_BASE + LM3S_GPIO_CR_OFFSET)
|
||||
#define LM3S_GPIOA_PERIPHID4 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM3S_GPIOA_PERIPHID5 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM3S_GPIOA_PERIPHID6 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM3S_GPIOA_PERIPHID7 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM3S_GPIOA_PERIPHID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM3S_GPIOA_PERIPHID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM3S_GPIOA_PERIPHID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM3S_GPIOA_PERIPHID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM3S_GPIOA_PCELLID0 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID0_OFFSET)
|
||||
#define LM3S_GPIOA_PCELLID1 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID1_OFFSET)
|
||||
#define LM3S_GPIOA_PCELLID2 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID2_OFFSET)
|
||||
#define LM3S_GPIOA_PCELLID3 (LM3S_GPIOA_BASE + LM3S_GPIO_PCELLID3_OFFSET)
|
||||
#define LM_GPIOA_DATA (LM_GPIOA_BASE + LM_GPIO_DATA_OFFSET)
|
||||
#define LM_GPIOA_DIR (LM_GPIOA_BASE + LM_GPIO_DIR_OFFSET)
|
||||
#define LM_GPIOA_IS (LM_GPIOA_BASE + LM_GPIO_IS_OFFSET)
|
||||
#define LM_GPIOA_IBE (LM_GPIOA_BASE + LM_GPIO_IBE_OFFSET)
|
||||
#define LM_GPIOA_IEV (LM_GPIOA_BASE + LM_GPIO_IEV_OFFSET)
|
||||
#define LM_GPIOA_IM (LM_GPIOA_BASE + LM_GPIO_IM_OFFSET)
|
||||
#define LM_GPIOA_RIS (LM_GPIOA_BASE + LM_GPIO_RIS_OFFSET)
|
||||
#define LM_GPIOA_MIS (LM_GPIOA_BASE + LM_GPIO_MIS_OFFSET)
|
||||
#define LM_GPIOA_ICR (LM_GPIOA_BASE + LM_GPIO_ICR_OFFSET)
|
||||
#define LM_GPIOA_AFSEL (LM_GPIOA_BASE + LM_GPIO_AFSEL_OFFSET)
|
||||
#define LM_GPIOA_DR2R (LM_GPIOA_BASE + LM_GPIO_DR2R_OFFSET)
|
||||
#define LM_GPIOA_DR4R (LM_GPIOA_BASE + LM_GPIO_DR4R_OFFSET)
|
||||
#define LM_GPIOA_DR8R (LM_GPIOA_BASE + LM_GPIO_DR8R_OFFSET)
|
||||
#define LM_GPIOA_ODR (LM_GPIOA_BASE + LM_GPIO_ODR_OFFSET)
|
||||
#define LM_GPIOA_PUR (LM_GPIOA_BASE + LM_GPIO_PUR_OFFSET)
|
||||
#define LM_GPIOA_PDR (LM_GPIOA_BASE + LM_GPIO_PDR_OFFSET)
|
||||
#define LM_GPIOA_SLR (LM_GPIOA_BASE + LM_GPIO_SLR_OFFSET)
|
||||
#define LM_GPIOA_DEN (LM_GPIOA_BASE + LM_GPIO_DEN_OFFSET)
|
||||
#define LM_GPIOA_LOCK (LM_GPIOA_BASE + LM_GPIO_LOCK_OFFSET)
|
||||
#define LM_GPIOA_CR (LM_GPIOA_BASE + LM_GPIO_CR_OFFSET)
|
||||
#define LM_GPIOA_PERIPHID4 (LM_GPIOA_BASE + LM_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM_GPIOA_PERIPHID5 (LM_GPIOA_BASE + LM_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM_GPIOA_PERIPHID6 (LM_GPIOA_BASE + LM_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM_GPIOA_PERIPHID7 (LM_GPIOA_BASE + LM_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM_GPIOA_PERIPHID0 (LM_GPIOA_BASE + LM_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM_GPIOA_PERIPHID1 (LM_GPIOA_BASE + LM_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM_GPIOA_PERIPHID2 (LM_GPIOA_BASE + LM_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM_GPIOA_PERIPHID3 (LM_GPIOA_BASE + LM_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM_GPIOA_PCELLID0 (LM_GPIOA_BASE + LM_GPIO_PCELLID0_OFFSET)
|
||||
#define LM_GPIOA_PCELLID1 (LM_GPIOA_BASE + LM_GPIO_PCELLID1_OFFSET)
|
||||
#define LM_GPIOA_PCELLID2 (LM_GPIOA_BASE + LM_GPIO_PCELLID2_OFFSET)
|
||||
#define LM_GPIOA_PCELLID3 (LM_GPIOA_BASE + LM_GPIO_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_GPIOB_DATA (LM3S_GPIOB_BASE + LM3S_GPIO_DATA_OFFSET)
|
||||
#define LM3S_GPIOB_DIR (LM3S_GPIOB_BASE + LM3S_GPIO_DIR_OFFSET)
|
||||
#define LM3S_GPIOB_IS (LM3S_GPIOB_BASE + LM3S_GPIO_IS_OFFSET)
|
||||
#define LM3S_GPIOB_IBE (LM3S_GPIOB_BASE + LM3S_GPIO_IBE_OFFSET)
|
||||
#define LM3S_GPIOB_IEV (LM3S_GPIOB_BASE + LM3S_GPIO_IEV_OFFSET)
|
||||
#define LM3S_GPIOB_IM (LM3S_GPIOB_BASE + LM3S_GPIO_IM_OFFSET)
|
||||
#define LM3S_GPIOB_RIS (LM3S_GPIOB_BASE + LM3S_GPIO_RIS_OFFSET)
|
||||
#define LM3S_GPIOB_MIS (LM3S_GPIOB_BASE + LM3S_GPIO_MIS_OFFSET)
|
||||
#define LM3S_GPIOB_ICR (LM3S_GPIOB_BASE + LM3S_GPIO_ICR_OFFSET)
|
||||
#define LM3S_GPIOB_AFSEL (LM3S_GPIOB_BASE + LM3S_GPIO_AFSEL_OFFSET)
|
||||
#define LM3S_GPIOB_DR2R (LM3S_GPIOB_BASE + LM3S_GPIO_DR2R_OFFSET)
|
||||
#define LM3S_GPIOB_DR4R (LM3S_GPIOB_BASE + LM3S_GPIO_DR4R_OFFSET)
|
||||
#define LM3S_GPIOB_DR8R (LM3S_GPIOB_BASE + LM3S_GPIO_DR8R_OFFSET)
|
||||
#define LM3S_GPIOB_ODR (LM3S_GPIOB_BASE + LM3S_GPIO_ODR_OFFSET)
|
||||
#define LM3S_GPIOB_PUR (LM3S_GPIOB_BASE + LM3S_GPIO_PUR_OFFSET)
|
||||
#define LM3S_GPIOB_PDR (LM3S_GPIOB_BASE + LM3S_GPIO_PDR_OFFSET)
|
||||
#define LM3S_GPIOB_SLR (LM3S_GPIOB_BASE + LM3S_GPIO_SLR_OFFSET)
|
||||
#define LM3S_GPIOB_DEN (LM3S_GPIOB_BASE + LM3S_GPIO_DEN_OFFSET)
|
||||
#define LM3S_GPIOB_LOCK (LM3S_GPIOB_BASE + LM3S_GPIO_LOCK_OFFSET)
|
||||
#define LM3S_GPIOB_CR (LM3S_GPIOB_BASE + LM3S_GPIO_CR_OFFSET)
|
||||
#define LM3S_GPIOB_PERIPHID4 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM3S_GPIOB_PERIPHID5 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM3S_GPIOB_PERIPHID6 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM3S_GPIOB_PERIPHID7 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM3S_GPIOB_PERIPHID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM3S_GPIOB_PERIPHID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM3S_GPIOB_PERIPHID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM3S_GPIOB_PERIPHID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM3S_GPIOB_PCELLID0 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID0_OFFSET)
|
||||
#define LM3S_GPIOB_PCELLID1 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID1_OFFSET)
|
||||
#define LM3S_GPIOB_PCELLID2 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID2_OFFSET)
|
||||
#define LM3S_GPIOB_PCELLID3 (LM3S_GPIOB_BASE + LM3S_GPIO_PCELLID3_OFFSET)
|
||||
#define LM_GPIOB_DATA (LM_GPIOB_BASE + LM_GPIO_DATA_OFFSET)
|
||||
#define LM_GPIOB_DIR (LM_GPIOB_BASE + LM_GPIO_DIR_OFFSET)
|
||||
#define LM_GPIOB_IS (LM_GPIOB_BASE + LM_GPIO_IS_OFFSET)
|
||||
#define LM_GPIOB_IBE (LM_GPIOB_BASE + LM_GPIO_IBE_OFFSET)
|
||||
#define LM_GPIOB_IEV (LM_GPIOB_BASE + LM_GPIO_IEV_OFFSET)
|
||||
#define LM_GPIOB_IM (LM_GPIOB_BASE + LM_GPIO_IM_OFFSET)
|
||||
#define LM_GPIOB_RIS (LM_GPIOB_BASE + LM_GPIO_RIS_OFFSET)
|
||||
#define LM_GPIOB_MIS (LM_GPIOB_BASE + LM_GPIO_MIS_OFFSET)
|
||||
#define LM_GPIOB_ICR (LM_GPIOB_BASE + LM_GPIO_ICR_OFFSET)
|
||||
#define LM_GPIOB_AFSEL (LM_GPIOB_BASE + LM_GPIO_AFSEL_OFFSET)
|
||||
#define LM_GPIOB_DR2R (LM_GPIOB_BASE + LM_GPIO_DR2R_OFFSET)
|
||||
#define LM_GPIOB_DR4R (LM_GPIOB_BASE + LM_GPIO_DR4R_OFFSET)
|
||||
#define LM_GPIOB_DR8R (LM_GPIOB_BASE + LM_GPIO_DR8R_OFFSET)
|
||||
#define LM_GPIOB_ODR (LM_GPIOB_BASE + LM_GPIO_ODR_OFFSET)
|
||||
#define LM_GPIOB_PUR (LM_GPIOB_BASE + LM_GPIO_PUR_OFFSET)
|
||||
#define LM_GPIOB_PDR (LM_GPIOB_BASE + LM_GPIO_PDR_OFFSET)
|
||||
#define LM_GPIOB_SLR (LM_GPIOB_BASE + LM_GPIO_SLR_OFFSET)
|
||||
#define LM_GPIOB_DEN (LM_GPIOB_BASE + LM_GPIO_DEN_OFFSET)
|
||||
#define LM_GPIOB_LOCK (LM_GPIOB_BASE + LM_GPIO_LOCK_OFFSET)
|
||||
#define LM_GPIOB_CR (LM_GPIOB_BASE + LM_GPIO_CR_OFFSET)
|
||||
#define LM_GPIOB_PERIPHID4 (LM_GPIOB_BASE + LM_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM_GPIOB_PERIPHID5 (LM_GPIOB_BASE + LM_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM_GPIOB_PERIPHID6 (LM_GPIOB_BASE + LM_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM_GPIOB_PERIPHID7 (LM_GPIOB_BASE + LM_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM_GPIOB_PERIPHID0 (LM_GPIOB_BASE + LM_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM_GPIOB_PERIPHID1 (LM_GPIOB_BASE + LM_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM_GPIOB_PERIPHID2 (LM_GPIOB_BASE + LM_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM_GPIOB_PERIPHID3 (LM_GPIOB_BASE + LM_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM_GPIOB_PCELLID0 (LM_GPIOB_BASE + LM_GPIO_PCELLID0_OFFSET)
|
||||
#define LM_GPIOB_PCELLID1 (LM_GPIOB_BASE + LM_GPIO_PCELLID1_OFFSET)
|
||||
#define LM_GPIOB_PCELLID2 (LM_GPIOB_BASE + LM_GPIO_PCELLID2_OFFSET)
|
||||
#define LM_GPIOB_PCELLID3 (LM_GPIOB_BASE + LM_GPIO_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_GPIOC_DATA (LM3S_GPIOC_BASE + LM3S_GPIO_DATA_OFFSET)
|
||||
#define LM3S_GPIOC_DIR (LM3S_GPIOC_BASE + LM3S_GPIO_DIR_OFFSET)
|
||||
#define LM3S_GPIOC_IS (LM3S_GPIOC_BASE + LM3S_GPIO_IS_OFFSET)
|
||||
#define LM3S_GPIOC_IBE (LM3S_GPIOC_BASE + LM3S_GPIO_IBE_OFFSET)
|
||||
#define LM3S_GPIOC_IEV (LM3S_GPIOC_BASE + LM3S_GPIO_IEV_OFFSET)
|
||||
#define LM3S_GPIOC_IM (LM3S_GPIOC_BASE + LM3S_GPIO_IM_OFFSET)
|
||||
#define LM3S_GPIOC_RIS (LM3S_GPIOC_BASE + LM3S_GPIO_RIS_OFFSET)
|
||||
#define LM3S_GPIOC_MIS (LM3S_GPIOC_BASE + LM3S_GPIO_MIS_OFFSET)
|
||||
#define LM3S_GPIOC_ICR (LM3S_GPIOC_BASE + LM3S_GPIO_ICR_OFFSET)
|
||||
#define LM3S_GPIOC_AFSEL (LM3S_GPIOC_BASE + LM3S_GPIO_AFSEL_OFFSET)
|
||||
#define LM3S_GPIOC_DR2R (LM3S_GPIOC_BASE + LM3S_GPIO_DR2R_OFFSET)
|
||||
#define LM3S_GPIOC_DR4R (LM3S_GPIOC_BASE + LM3S_GPIO_DR4R_OFFSET)
|
||||
#define LM3S_GPIOC_DR8R (LM3S_GPIOC_BASE + LM3S_GPIO_DR8R_OFFSET)
|
||||
#define LM3S_GPIOC_ODR (LM3S_GPIOC_BASE + LM3S_GPIO_ODR_OFFSET)
|
||||
#define LM3S_GPIOC_PUR (LM3S_GPIOC_BASE + LM3S_GPIO_PUR_OFFSET)
|
||||
#define LM3S_GPIOC_PDR (LM3S_GPIOC_BASE + LM3S_GPIO_PDR_OFFSET)
|
||||
#define LM3S_GPIOC_SLR (LM3S_GPIOC_BASE + LM3S_GPIO_SLR_OFFSET)
|
||||
#define LM3S_GPIOC_DEN (LM3S_GPIOC_BASE + LM3S_GPIO_DEN_OFFSET)
|
||||
#define LM3S_GPIOC_LOCK (LM3S_GPIOC_BASE + LM3S_GPIO_LOCK_OFFSET)
|
||||
#define LM3S_GPIOC_CR (LM3S_GPIOC_BASE + LM3S_GPIO_CR_OFFSET)
|
||||
#define LM3S_GPIOC_PERIPHID4 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM3S_GPIOC_PERIPHID5 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM3S_GPIOC_PERIPHID6 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM3S_GPIOC_PERIPHID7 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM3S_GPIOC_PERIPHID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM3S_GPIOC_PERIPHID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM3S_GPIOC_PERIPHID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM3S_GPIOC_PERIPHID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM3S_GPIOC_PCELLID0 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID0_OFFSET)
|
||||
#define LM3S_GPIOC_PCELLID1 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID1_OFFSET)
|
||||
#define LM3S_GPIOC_PCELLID2 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID2_OFFSET)
|
||||
#define LM3S_GPIOC_PCELLID3 (LM3S_GPIOC_BASE + LM3S_GPIO_PCELLID3_OFFSET)
|
||||
#define LM_GPIOC_DATA (LM_GPIOC_BASE + LM_GPIO_DATA_OFFSET)
|
||||
#define LM_GPIOC_DIR (LM_GPIOC_BASE + LM_GPIO_DIR_OFFSET)
|
||||
#define LM_GPIOC_IS (LM_GPIOC_BASE + LM_GPIO_IS_OFFSET)
|
||||
#define LM_GPIOC_IBE (LM_GPIOC_BASE + LM_GPIO_IBE_OFFSET)
|
||||
#define LM_GPIOC_IEV (LM_GPIOC_BASE + LM_GPIO_IEV_OFFSET)
|
||||
#define LM_GPIOC_IM (LM_GPIOC_BASE + LM_GPIO_IM_OFFSET)
|
||||
#define LM_GPIOC_RIS (LM_GPIOC_BASE + LM_GPIO_RIS_OFFSET)
|
||||
#define LM_GPIOC_MIS (LM_GPIOC_BASE + LM_GPIO_MIS_OFFSET)
|
||||
#define LM_GPIOC_ICR (LM_GPIOC_BASE + LM_GPIO_ICR_OFFSET)
|
||||
#define LM_GPIOC_AFSEL (LM_GPIOC_BASE + LM_GPIO_AFSEL_OFFSET)
|
||||
#define LM_GPIOC_DR2R (LM_GPIOC_BASE + LM_GPIO_DR2R_OFFSET)
|
||||
#define LM_GPIOC_DR4R (LM_GPIOC_BASE + LM_GPIO_DR4R_OFFSET)
|
||||
#define LM_GPIOC_DR8R (LM_GPIOC_BASE + LM_GPIO_DR8R_OFFSET)
|
||||
#define LM_GPIOC_ODR (LM_GPIOC_BASE + LM_GPIO_ODR_OFFSET)
|
||||
#define LM_GPIOC_PUR (LM_GPIOC_BASE + LM_GPIO_PUR_OFFSET)
|
||||
#define LM_GPIOC_PDR (LM_GPIOC_BASE + LM_GPIO_PDR_OFFSET)
|
||||
#define LM_GPIOC_SLR (LM_GPIOC_BASE + LM_GPIO_SLR_OFFSET)
|
||||
#define LM_GPIOC_DEN (LM_GPIOC_BASE + LM_GPIO_DEN_OFFSET)
|
||||
#define LM_GPIOC_LOCK (LM_GPIOC_BASE + LM_GPIO_LOCK_OFFSET)
|
||||
#define LM_GPIOC_CR (LM_GPIOC_BASE + LM_GPIO_CR_OFFSET)
|
||||
#define LM_GPIOC_PERIPHID4 (LM_GPIOC_BASE + LM_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM_GPIOC_PERIPHID5 (LM_GPIOC_BASE + LM_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM_GPIOC_PERIPHID6 (LM_GPIOC_BASE + LM_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM_GPIOC_PERIPHID7 (LM_GPIOC_BASE + LM_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM_GPIOC_PERIPHID0 (LM_GPIOC_BASE + LM_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM_GPIOC_PERIPHID1 (LM_GPIOC_BASE + LM_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM_GPIOC_PERIPHID2 (LM_GPIOC_BASE + LM_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM_GPIOC_PERIPHID3 (LM_GPIOC_BASE + LM_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM_GPIOC_PCELLID0 (LM_GPIOC_BASE + LM_GPIO_PCELLID0_OFFSET)
|
||||
#define LM_GPIOC_PCELLID1 (LM_GPIOC_BASE + LM_GPIO_PCELLID1_OFFSET)
|
||||
#define LM_GPIOC_PCELLID2 (LM_GPIOC_BASE + LM_GPIO_PCELLID2_OFFSET)
|
||||
#define LM_GPIOC_PCELLID3 (LM_GPIOC_BASE + LM_GPIO_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_GPIOD_DATA (LM3S_GPIOD_BASE + LM3S_GPIO_DATA_OFFSET)
|
||||
#define LM3S_GPIOD_DIR (LM3S_GPIOD_BASE + LM3S_GPIO_DIR_OFFSET)
|
||||
#define LM3S_GPIOD_IS (LM3S_GPIOD_BASE + LM3S_GPIO_IS_OFFSET)
|
||||
#define LM3S_GPIOD_IBE (LM3S_GPIOD_BASE + LM3S_GPIO_IBE_OFFSET)
|
||||
#define LM3S_GPIOD_IEV (LM3S_GPIOD_BASE + LM3S_GPIO_IEV_OFFSET)
|
||||
#define LM3S_GPIOD_IM (LM3S_GPIOD_BASE + LM3S_GPIO_IM_OFFSET)
|
||||
#define LM3S_GPIOD_RIS (LM3S_GPIOD_BASE + LM3S_GPIO_RIS_OFFSET)
|
||||
#define LM3S_GPIOD_MIS (LM3S_GPIOD_BASE + LM3S_GPIO_MIS_OFFSET)
|
||||
#define LM3S_GPIOD_ICR (LM3S_GPIOD_BASE + LM3S_GPIO_ICR_OFFSET)
|
||||
#define LM3S_GPIOD_AFSEL (LM3S_GPIOD_BASE + LM3S_GPIO_AFSEL_OFFSET)
|
||||
#define LM3S_GPIOD_DR2R (LM3S_GPIOD_BASE + LM3S_GPIO_DR2R_OFFSET)
|
||||
#define LM3S_GPIOD_DR4R (LM3S_GPIOD_BASE + LM3S_GPIO_DR4R_OFFSET)
|
||||
#define LM3S_GPIOD_DR8R (LM3S_GPIOD_BASE + LM3S_GPIO_DR8R_OFFSET)
|
||||
#define LM3S_GPIOD_ODR (LM3S_GPIOD_BASE + LM3S_GPIO_ODR_OFFSET)
|
||||
#define LM3S_GPIOD_PUR (LM3S_GPIOD_BASE + LM3S_GPIO_PUR_OFFSET)
|
||||
#define LM3S_GPIOD_PDR (LM3S_GPIOD_BASE + LM3S_GPIO_PDR_OFFSET)
|
||||
#define LM3S_GPIOD_SLR (LM3S_GPIOD_BASE + LM3S_GPIO_SLR_OFFSET)
|
||||
#define LM3S_GPIOD_DEN (LM3S_GPIOD_BASE + LM3S_GPIO_DEN_OFFSET)
|
||||
#define LM3S_GPIOD_LOCK (LM3S_GPIOD_BASE + LM3S_GPIO_LOCK_OFFSET)
|
||||
#define LM3S_GPIOD_CR (LM3S_GPIOD_BASE + LM3S_GPIO_CR_OFFSET)
|
||||
#define LM3S_GPIOD_PERIPHID4 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM3S_GPIOD_PERIPHID5 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM3S_GPIOD_PERIPHID6 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM3S_GPIOD_PERIPHID7 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM3S_GPIOD_PERIPHID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM3S_GPIOD_PERIPHID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM3S_GPIOD_PERIPHID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM3S_GPIOD_PERIPHID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM3S_GPIOD_PCELLID0 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID0_OFFSET)
|
||||
#define LM3S_GPIOD_PCELLID1 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID1_OFFSET)
|
||||
#define LM3S_GPIOD_PCELLID2 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID2_OFFSET)
|
||||
#define LM3S_GPIOD_PCELLID3 (LM3S_GPIOD_BASE + LM3S_GPIO_PCELLID3_OFFSET)
|
||||
#define LM_GPIOD_DATA (LM_GPIOD_BASE + LM_GPIO_DATA_OFFSET)
|
||||
#define LM_GPIOD_DIR (LM_GPIOD_BASE + LM_GPIO_DIR_OFFSET)
|
||||
#define LM_GPIOD_IS (LM_GPIOD_BASE + LM_GPIO_IS_OFFSET)
|
||||
#define LM_GPIOD_IBE (LM_GPIOD_BASE + LM_GPIO_IBE_OFFSET)
|
||||
#define LM_GPIOD_IEV (LM_GPIOD_BASE + LM_GPIO_IEV_OFFSET)
|
||||
#define LM_GPIOD_IM (LM_GPIOD_BASE + LM_GPIO_IM_OFFSET)
|
||||
#define LM_GPIOD_RIS (LM_GPIOD_BASE + LM_GPIO_RIS_OFFSET)
|
||||
#define LM_GPIOD_MIS (LM_GPIOD_BASE + LM_GPIO_MIS_OFFSET)
|
||||
#define LM_GPIOD_ICR (LM_GPIOD_BASE + LM_GPIO_ICR_OFFSET)
|
||||
#define LM_GPIOD_AFSEL (LM_GPIOD_BASE + LM_GPIO_AFSEL_OFFSET)
|
||||
#define LM_GPIOD_DR2R (LM_GPIOD_BASE + LM_GPIO_DR2R_OFFSET)
|
||||
#define LM_GPIOD_DR4R (LM_GPIOD_BASE + LM_GPIO_DR4R_OFFSET)
|
||||
#define LM_GPIOD_DR8R (LM_GPIOD_BASE + LM_GPIO_DR8R_OFFSET)
|
||||
#define LM_GPIOD_ODR (LM_GPIOD_BASE + LM_GPIO_ODR_OFFSET)
|
||||
#define LM_GPIOD_PUR (LM_GPIOD_BASE + LM_GPIO_PUR_OFFSET)
|
||||
#define LM_GPIOD_PDR (LM_GPIOD_BASE + LM_GPIO_PDR_OFFSET)
|
||||
#define LM_GPIOD_SLR (LM_GPIOD_BASE + LM_GPIO_SLR_OFFSET)
|
||||
#define LM_GPIOD_DEN (LM_GPIOD_BASE + LM_GPIO_DEN_OFFSET)
|
||||
#define LM_GPIOD_LOCK (LM_GPIOD_BASE + LM_GPIO_LOCK_OFFSET)
|
||||
#define LM_GPIOD_CR (LM_GPIOD_BASE + LM_GPIO_CR_OFFSET)
|
||||
#define LM_GPIOD_PERIPHID4 (LM_GPIOD_BASE + LM_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM_GPIOD_PERIPHID5 (LM_GPIOD_BASE + LM_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM_GPIOD_PERIPHID6 (LM_GPIOD_BASE + LM_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM_GPIOD_PERIPHID7 (LM_GPIOD_BASE + LM_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM_GPIOD_PERIPHID0 (LM_GPIOD_BASE + LM_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM_GPIOD_PERIPHID1 (LM_GPIOD_BASE + LM_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM_GPIOD_PERIPHID2 (LM_GPIOD_BASE + LM_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM_GPIOD_PERIPHID3 (LM_GPIOD_BASE + LM_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM_GPIOD_PCELLID0 (LM_GPIOD_BASE + LM_GPIO_PCELLID0_OFFSET)
|
||||
#define LM_GPIOD_PCELLID1 (LM_GPIOD_BASE + LM_GPIO_PCELLID1_OFFSET)
|
||||
#define LM_GPIOD_PCELLID2 (LM_GPIOD_BASE + LM_GPIO_PCELLID2_OFFSET)
|
||||
#define LM_GPIOD_PCELLID3 (LM_GPIOD_BASE + LM_GPIO_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_GPIOE_DATA (LM3S_GPIOE_BASE + LM3S_GPIO_DATA_OFFSET)
|
||||
#define LM3S_GPIOE_DIR (LM3S_GPIOE_BASE + LM3S_GPIO_DIR_OFFSET)
|
||||
#define LM3S_GPIOE_IS (LM3S_GPIOE_BASE + LM3S_GPIO_IS_OFFSET)
|
||||
#define LM3S_GPIOE_IBE (LM3S_GPIOE_BASE + LM3S_GPIO_IBE_OFFSET)
|
||||
#define LM3S_GPIOE_IEV (LM3S_GPIOE_BASE + LM3S_GPIO_IEV_OFFSET)
|
||||
#define LM3S_GPIOE_IM (LM3S_GPIOE_BASE + LM3S_GPIO_IM_OFFSET)
|
||||
#define LM3S_GPIOE_RIS (LM3S_GPIOE_BASE + LM3S_GPIO_RIS_OFFSET)
|
||||
#define LM3S_GPIOE_MIS (LM3S_GPIOE_BASE + LM3S_GPIO_MIS_OFFSET)
|
||||
#define LM3S_GPIOE_ICR (LM3S_GPIOE_BASE + LM3S_GPIO_ICR_OFFSET)
|
||||
#define LM3S_GPIOE_AFSEL (LM3S_GPIOE_BASE + LM3S_GPIO_AFSEL_OFFSET)
|
||||
#define LM3S_GPIOE_DR2R (LM3S_GPIOE_BASE + LM3S_GPIO_DR2R_OFFSET)
|
||||
#define LM3S_GPIOE_DR4R (LM3S_GPIOE_BASE + LM3S_GPIO_DR4R_OFFSET)
|
||||
#define LM3S_GPIOE_DR8R (LM3S_GPIOE_BASE + LM3S_GPIO_DR8R_OFFSET)
|
||||
#define LM3S_GPIOE_ODR (LM3S_GPIOE_BASE + LM3S_GPIO_ODR_OFFSET)
|
||||
#define LM3S_GPIOE_PUR (LM3S_GPIOE_BASE + LM3S_GPIO_PUR_OFFSET)
|
||||
#define LM3S_GPIOE_PDR (LM3S_GPIOE_BASE + LM3S_GPIO_PDR_OFFSET)
|
||||
#define LM3S_GPIOE_SLR (LM3S_GPIOE_BASE + LM3S_GPIO_SLR_OFFSET)
|
||||
#define LM3S_GPIOE_DEN (LM3S_GPIOE_BASE + LM3S_GPIO_DEN_OFFSET)
|
||||
#define LM3S_GPIOE_LOCK (LM3S_GPIOE_BASE + LM3S_GPIO_LOCK_OFFSET)
|
||||
#define LM3S_GPIOE_CR (LM3S_GPIOE_BASE + LM3S_GPIO_CR_OFFSET)
|
||||
#define LM3S_GPIOE_PERIPHID4 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM3S_GPIOE_PERIPHID5 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM3S_GPIOE_PERIPHID6 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM3S_GPIOE_PERIPHID7 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM3S_GPIOE_PERIPHID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM3S_GPIOE_PERIPHID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM3S_GPIOE_PERIPHID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM3S_GPIOE_PERIPHID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM3S_GPIOE_PCELLID0 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID0_OFFSET)
|
||||
#define LM3S_GPIOE_PCELLID1 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID1_OFFSET)
|
||||
#define LM3S_GPIOE_PCELLID2 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID2_OFFSET)
|
||||
#define LM3S_GPIOE_PCELLID3 (LM3S_GPIOE_BASE + LM3S_GPIO_PCELLID3_OFFSET)
|
||||
#define LM_GPIOE_DATA (LM_GPIOE_BASE + LM_GPIO_DATA_OFFSET)
|
||||
#define LM_GPIOE_DIR (LM_GPIOE_BASE + LM_GPIO_DIR_OFFSET)
|
||||
#define LM_GPIOE_IS (LM_GPIOE_BASE + LM_GPIO_IS_OFFSET)
|
||||
#define LM_GPIOE_IBE (LM_GPIOE_BASE + LM_GPIO_IBE_OFFSET)
|
||||
#define LM_GPIOE_IEV (LM_GPIOE_BASE + LM_GPIO_IEV_OFFSET)
|
||||
#define LM_GPIOE_IM (LM_GPIOE_BASE + LM_GPIO_IM_OFFSET)
|
||||
#define LM_GPIOE_RIS (LM_GPIOE_BASE + LM_GPIO_RIS_OFFSET)
|
||||
#define LM_GPIOE_MIS (LM_GPIOE_BASE + LM_GPIO_MIS_OFFSET)
|
||||
#define LM_GPIOE_ICR (LM_GPIOE_BASE + LM_GPIO_ICR_OFFSET)
|
||||
#define LM_GPIOE_AFSEL (LM_GPIOE_BASE + LM_GPIO_AFSEL_OFFSET)
|
||||
#define LM_GPIOE_DR2R (LM_GPIOE_BASE + LM_GPIO_DR2R_OFFSET)
|
||||
#define LM_GPIOE_DR4R (LM_GPIOE_BASE + LM_GPIO_DR4R_OFFSET)
|
||||
#define LM_GPIOE_DR8R (LM_GPIOE_BASE + LM_GPIO_DR8R_OFFSET)
|
||||
#define LM_GPIOE_ODR (LM_GPIOE_BASE + LM_GPIO_ODR_OFFSET)
|
||||
#define LM_GPIOE_PUR (LM_GPIOE_BASE + LM_GPIO_PUR_OFFSET)
|
||||
#define LM_GPIOE_PDR (LM_GPIOE_BASE + LM_GPIO_PDR_OFFSET)
|
||||
#define LM_GPIOE_SLR (LM_GPIOE_BASE + LM_GPIO_SLR_OFFSET)
|
||||
#define LM_GPIOE_DEN (LM_GPIOE_BASE + LM_GPIO_DEN_OFFSET)
|
||||
#define LM_GPIOE_LOCK (LM_GPIOE_BASE + LM_GPIO_LOCK_OFFSET)
|
||||
#define LM_GPIOE_CR (LM_GPIOE_BASE + LM_GPIO_CR_OFFSET)
|
||||
#define LM_GPIOE_PERIPHID4 (LM_GPIOE_BASE + LM_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM_GPIOE_PERIPHID5 (LM_GPIOE_BASE + LM_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM_GPIOE_PERIPHID6 (LM_GPIOE_BASE + LM_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM_GPIOE_PERIPHID7 (LM_GPIOE_BASE + LM_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM_GPIOE_PERIPHID0 (LM_GPIOE_BASE + LM_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM_GPIOE_PERIPHID1 (LM_GPIOE_BASE + LM_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM_GPIOE_PERIPHID2 (LM_GPIOE_BASE + LM_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM_GPIOE_PERIPHID3 (LM_GPIOE_BASE + LM_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM_GPIOE_PCELLID0 (LM_GPIOE_BASE + LM_GPIO_PCELLID0_OFFSET)
|
||||
#define LM_GPIOE_PCELLID1 (LM_GPIOE_BASE + LM_GPIO_PCELLID1_OFFSET)
|
||||
#define LM_GPIOE_PCELLID2 (LM_GPIOE_BASE + LM_GPIO_PCELLID2_OFFSET)
|
||||
#define LM_GPIOE_PCELLID3 (LM_GPIOE_BASE + LM_GPIO_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_GPIOF_DATA (LM3S_GPIOF_BASE + LM3S_GPIO_DATA_OFFSET)
|
||||
#define LM3S_GPIOF_DIR (LM3S_GPIOF_BASE + LM3S_GPIO_DIR_OFFSET)
|
||||
#define LM3S_GPIOF_IS (LM3S_GPIOF_BASE + LM3S_GPIO_IS_OFFSET)
|
||||
#define LM3S_GPIOF_IBE (LM3S_GPIOF_BASE + LM3S_GPIO_IBE_OFFSET)
|
||||
#define LM3S_GPIOF_IEV (LM3S_GPIOF_BASE + LM3S_GPIO_IEV_OFFSET)
|
||||
#define LM3S_GPIOF_IM (LM3S_GPIOF_BASE + LM3S_GPIO_IM_OFFSET)
|
||||
#define LM3S_GPIOF_RIS (LM3S_GPIOF_BASE + LM3S_GPIO_RIS_OFFSET)
|
||||
#define LM3S_GPIOF_MIS (LM3S_GPIOF_BASE + LM3S_GPIO_MIS_OFFSET)
|
||||
#define LM3S_GPIOF_ICR (LM3S_GPIOF_BASE + LM3S_GPIO_ICR_OFFSET)
|
||||
#define LM3S_GPIOF_AFSEL (LM3S_GPIOF_BASE + LM3S_GPIO_AFSEL_OFFSET)
|
||||
#define LM3S_GPIOF_DR2R (LM3S_GPIOF_BASE + LM3S_GPIO_DR2R_OFFSET)
|
||||
#define LM3S_GPIOF_DR4R (LM3S_GPIOF_BASE + LM3S_GPIO_DR4R_OFFSET)
|
||||
#define LM3S_GPIOF_DR8R (LM3S_GPIOF_BASE + LM3S_GPIO_DR8R_OFFSET)
|
||||
#define LM3S_GPIOF_ODR (LM3S_GPIOF_BASE + LM3S_GPIO_ODR_OFFSET)
|
||||
#define LM3S_GPIOF_PUR (LM3S_GPIOF_BASE + LM3S_GPIO_PUR_OFFSET)
|
||||
#define LM3S_GPIOF_PDR (LM3S_GPIOF_BASE + LM3S_GPIO_PDR_OFFSET)
|
||||
#define LM3S_GPIOF_SLR (LM3S_GPIOF_BASE + LM3S_GPIO_SLR_OFFSET)
|
||||
#define LM3S_GPIOF_DEN (LM3S_GPIOF_BASE + LM3S_GPIO_DEN_OFFSET)
|
||||
#define LM3S_GPIOF_LOCK (LM3S_GPIOF_BASE + LM3S_GPIO_LOCK_OFFSET)
|
||||
#define LM3S_GPIOF_CR (LM3S_GPIOF_BASE + LM3S_GPIO_CR_OFFSET)
|
||||
#define LM3S_GPIOF_PERIPHID4 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM3S_GPIOF_PERIPHID5 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM3S_GPIOF_PERIPHID6 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM3S_GPIOF_PERIPHID7 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM3S_GPIOF_PERIPHID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM3S_GPIOF_PERIPHID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM3S_GPIOF_PERIPHID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM3S_GPIOF_PERIPHID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM3S_GPIOF_PCELLID0 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID0_OFFSET)
|
||||
#define LM3S_GPIOF_PCELLID1 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID1_OFFSET)
|
||||
#define LM3S_GPIOF_PCELLID2 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID2_OFFSET)
|
||||
#define LM3S_GPIOF_PCELLID3 (LM3S_GPIOF_BASE + LM3S_GPIO_PCELLID3_OFFSET)
|
||||
#define LM_GPIOF_DATA (LM_GPIOF_BASE + LM_GPIO_DATA_OFFSET)
|
||||
#define LM_GPIOF_DIR (LM_GPIOF_BASE + LM_GPIO_DIR_OFFSET)
|
||||
#define LM_GPIOF_IS (LM_GPIOF_BASE + LM_GPIO_IS_OFFSET)
|
||||
#define LM_GPIOF_IBE (LM_GPIOF_BASE + LM_GPIO_IBE_OFFSET)
|
||||
#define LM_GPIOF_IEV (LM_GPIOF_BASE + LM_GPIO_IEV_OFFSET)
|
||||
#define LM_GPIOF_IM (LM_GPIOF_BASE + LM_GPIO_IM_OFFSET)
|
||||
#define LM_GPIOF_RIS (LM_GPIOF_BASE + LM_GPIO_RIS_OFFSET)
|
||||
#define LM_GPIOF_MIS (LM_GPIOF_BASE + LM_GPIO_MIS_OFFSET)
|
||||
#define LM_GPIOF_ICR (LM_GPIOF_BASE + LM_GPIO_ICR_OFFSET)
|
||||
#define LM_GPIOF_AFSEL (LM_GPIOF_BASE + LM_GPIO_AFSEL_OFFSET)
|
||||
#define LM_GPIOF_DR2R (LM_GPIOF_BASE + LM_GPIO_DR2R_OFFSET)
|
||||
#define LM_GPIOF_DR4R (LM_GPIOF_BASE + LM_GPIO_DR4R_OFFSET)
|
||||
#define LM_GPIOF_DR8R (LM_GPIOF_BASE + LM_GPIO_DR8R_OFFSET)
|
||||
#define LM_GPIOF_ODR (LM_GPIOF_BASE + LM_GPIO_ODR_OFFSET)
|
||||
#define LM_GPIOF_PUR (LM_GPIOF_BASE + LM_GPIO_PUR_OFFSET)
|
||||
#define LM_GPIOF_PDR (LM_GPIOF_BASE + LM_GPIO_PDR_OFFSET)
|
||||
#define LM_GPIOF_SLR (LM_GPIOF_BASE + LM_GPIO_SLR_OFFSET)
|
||||
#define LM_GPIOF_DEN (LM_GPIOF_BASE + LM_GPIO_DEN_OFFSET)
|
||||
#define LM_GPIOF_LOCK (LM_GPIOF_BASE + LM_GPIO_LOCK_OFFSET)
|
||||
#define LM_GPIOF_CR (LM_GPIOF_BASE + LM_GPIO_CR_OFFSET)
|
||||
#define LM_GPIOF_PERIPHID4 (LM_GPIOF_BASE + LM_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM_GPIOF_PERIPHID5 (LM_GPIOF_BASE + LM_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM_GPIOF_PERIPHID6 (LM_GPIOF_BASE + LM_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM_GPIOF_PERIPHID7 (LM_GPIOF_BASE + LM_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM_GPIOF_PERIPHID0 (LM_GPIOF_BASE + LM_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM_GPIOF_PERIPHID1 (LM_GPIOF_BASE + LM_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM_GPIOF_PERIPHID2 (LM_GPIOF_BASE + LM_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM_GPIOF_PERIPHID3 (LM_GPIOF_BASE + LM_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM_GPIOF_PCELLID0 (LM_GPIOF_BASE + LM_GPIO_PCELLID0_OFFSET)
|
||||
#define LM_GPIOF_PCELLID1 (LM_GPIOF_BASE + LM_GPIO_PCELLID1_OFFSET)
|
||||
#define LM_GPIOF_PCELLID2 (LM_GPIOF_BASE + LM_GPIO_PCELLID2_OFFSET)
|
||||
#define LM_GPIOF_PCELLID3 (LM_GPIOF_BASE + LM_GPIO_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_GPIOG_DATA (LM3S_GPIOG_BASE + LM3S_GPIO_DATA_OFFSET)
|
||||
#define LM3S_GPIOG_DIR (LM3S_GPIOG_BASE + LM3S_GPIO_DIR_OFFSET)
|
||||
#define LM3S_GPIOG_IS (LM3S_GPIOG_BASE + LM3S_GPIO_IS_OFFSET)
|
||||
#define LM3S_GPIOG_IBE (LM3S_GPIOG_BASE + LM3S_GPIO_IBE_OFFSET)
|
||||
#define LM3S_GPIOG_IEV (LM3S_GPIOG_BASE + LM3S_GPIO_IEV_OFFSET)
|
||||
#define LM3S_GPIOG_IM (LM3S_GPIOG_BASE + LM3S_GPIO_IM_OFFSET)
|
||||
#define LM3S_GPIOG_RIS (LM3S_GPIOG_BASE + LM3S_GPIO_RIS_OFFSET)
|
||||
#define LM3S_GPIOG_MIS (LM3S_GPIOG_BASE + LM3S_GPIO_MIS_OFFSET)
|
||||
#define LM3S_GPIOG_ICR (LM3S_GPIOG_BASE + LM3S_GPIO_ICR_OFFSET)
|
||||
#define LM3S_GPIOG_AFSEL (LM3S_GPIOG_BASE + LM3S_GPIO_AFSEL_OFFSET)
|
||||
#define LM3S_GPIOG_DR2R (LM3S_GPIOG_BASE + LM3S_GPIO_DR2R_OFFSET)
|
||||
#define LM3S_GPIOG_DR4R (LM3S_GPIOG_BASE + LM3S_GPIO_DR4R_OFFSET)
|
||||
#define LM3S_GPIOG_DR8R (LM3S_GPIOG_BASE + LM3S_GPIO_DR8R_OFFSET)
|
||||
#define LM3S_GPIOG_ODR (LM3S_GPIOG_BASE + LM3S_GPIO_ODR_OFFSET)
|
||||
#define LM3S_GPIOG_PUR (LM3S_GPIOG_BASE + LM3S_GPIO_PUR_OFFSET)
|
||||
#define LM3S_GPIOG_PDR (LM3S_GPIOG_BASE + LM3S_GPIO_PDR_OFFSET)
|
||||
#define LM3S_GPIOG_SLR (LM3S_GPIOG_BASE + LM3S_GPIO_SLR_OFFSET)
|
||||
#define LM3S_GPIOG_DEN (LM3S_GPIOG_BASE + LM3S_GPIO_DEN_OFFSET)
|
||||
#define LM3S_GPIOG_LOCK (LM3S_GPIOG_BASE + LM3S_GPIO_LOCK_OFFSET)
|
||||
#define LM3S_GPIOG_CR (LM3S_GPIOG_BASE + LM3S_GPIO_CR_OFFSET)
|
||||
#define LM3S_GPIOG_PERIPHID4 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM3S_GPIOG_PERIPHID5 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM3S_GPIOG_PERIPHID6 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM3S_GPIOG_PERIPHID7 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM3S_GPIOG_PERIPHID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM3S_GPIOG_PERIPHID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM3S_GPIOG_PERIPHID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM3S_GPIOG_PERIPHID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM3S_GPIOG_PCELLID0 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID0_OFFSET)
|
||||
#define LM3S_GPIOG_PCELLID1 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID1_OFFSET)
|
||||
#define LM3S_GPIOG_PCELLID2 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID2_OFFSET)
|
||||
#define LM3S_GPIOG_PCELLID3 (LM3S_GPIOG_BASE + LM3S_GPIO_PCELLID3_OFFSET)
|
||||
#define LM_GPIOG_DATA (LM_GPIOG_BASE + LM_GPIO_DATA_OFFSET)
|
||||
#define LM_GPIOG_DIR (LM_GPIOG_BASE + LM_GPIO_DIR_OFFSET)
|
||||
#define LM_GPIOG_IS (LM_GPIOG_BASE + LM_GPIO_IS_OFFSET)
|
||||
#define LM_GPIOG_IBE (LM_GPIOG_BASE + LM_GPIO_IBE_OFFSET)
|
||||
#define LM_GPIOG_IEV (LM_GPIOG_BASE + LM_GPIO_IEV_OFFSET)
|
||||
#define LM_GPIOG_IM (LM_GPIOG_BASE + LM_GPIO_IM_OFFSET)
|
||||
#define LM_GPIOG_RIS (LM_GPIOG_BASE + LM_GPIO_RIS_OFFSET)
|
||||
#define LM_GPIOG_MIS (LM_GPIOG_BASE + LM_GPIO_MIS_OFFSET)
|
||||
#define LM_GPIOG_ICR (LM_GPIOG_BASE + LM_GPIO_ICR_OFFSET)
|
||||
#define LM_GPIOG_AFSEL (LM_GPIOG_BASE + LM_GPIO_AFSEL_OFFSET)
|
||||
#define LM_GPIOG_DR2R (LM_GPIOG_BASE + LM_GPIO_DR2R_OFFSET)
|
||||
#define LM_GPIOG_DR4R (LM_GPIOG_BASE + LM_GPIO_DR4R_OFFSET)
|
||||
#define LM_GPIOG_DR8R (LM_GPIOG_BASE + LM_GPIO_DR8R_OFFSET)
|
||||
#define LM_GPIOG_ODR (LM_GPIOG_BASE + LM_GPIO_ODR_OFFSET)
|
||||
#define LM_GPIOG_PUR (LM_GPIOG_BASE + LM_GPIO_PUR_OFFSET)
|
||||
#define LM_GPIOG_PDR (LM_GPIOG_BASE + LM_GPIO_PDR_OFFSET)
|
||||
#define LM_GPIOG_SLR (LM_GPIOG_BASE + LM_GPIO_SLR_OFFSET)
|
||||
#define LM_GPIOG_DEN (LM_GPIOG_BASE + LM_GPIO_DEN_OFFSET)
|
||||
#define LM_GPIOG_LOCK (LM_GPIOG_BASE + LM_GPIO_LOCK_OFFSET)
|
||||
#define LM_GPIOG_CR (LM_GPIOG_BASE + LM_GPIO_CR_OFFSET)
|
||||
#define LM_GPIOG_PERIPHID4 (LM_GPIOG_BASE + LM_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM_GPIOG_PERIPHID5 (LM_GPIOG_BASE + LM_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM_GPIOG_PERIPHID6 (LM_GPIOG_BASE + LM_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM_GPIOG_PERIPHID7 (LM_GPIOG_BASE + LM_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM_GPIOG_PERIPHID0 (LM_GPIOG_BASE + LM_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM_GPIOG_PERIPHID1 (LM_GPIOG_BASE + LM_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM_GPIOG_PERIPHID2 (LM_GPIOG_BASE + LM_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM_GPIOG_PERIPHID3 (LM_GPIOG_BASE + LM_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM_GPIOG_PCELLID0 (LM_GPIOG_BASE + LM_GPIO_PCELLID0_OFFSET)
|
||||
#define LM_GPIOG_PCELLID1 (LM_GPIOG_BASE + LM_GPIO_PCELLID1_OFFSET)
|
||||
#define LM_GPIOG_PCELLID2 (LM_GPIOG_BASE + LM_GPIO_PCELLID2_OFFSET)
|
||||
#define LM_GPIOG_PCELLID3 (LM_GPIOG_BASE + LM_GPIO_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_GPIOH_DATA (LM3S_GPIOH_BASE + LM3S_GPIO_DATA_OFFSET)
|
||||
#define LM3S_GPIOH_DIR (LM3S_GPIOH_BASE + LM3S_GPIO_DIR_OFFSET)
|
||||
#define LM3S_GPIOH_IS (LM3S_GPIOH_BASE + LM3S_GPIO_IS_OFFSET)
|
||||
#define LM3S_GPIOH_IBE (LM3S_GPIOH_BASE + LM3S_GPIO_IBE_OFFSET)
|
||||
#define LM3S_GPIOH_IEV (LM3S_GPIOH_BASE + LM3S_GPIO_IEV_OFFSET)
|
||||
#define LM3S_GPIOH_IM (LM3S_GPIOH_BASE + LM3S_GPIO_IM_OFFSET)
|
||||
#define LM3S_GPIOH_RIS (LM3S_GPIOH_BASE + LM3S_GPIO_RIS_OFFSET)
|
||||
#define LM3S_GPIOH_MIS (LM3S_GPIOH_BASE + LM3S_GPIO_MIS_OFFSET)
|
||||
#define LM3S_GPIOH_ICR (LM3S_GPIOH_BASE + LM3S_GPIO_ICR_OFFSET)
|
||||
#define LM3S_GPIOH_AFSEL (LM3S_GPIOH_BASE + LM3S_GPIO_AFSEL_OFFSET)
|
||||
#define LM3S_GPIOH_DR2R (LM3S_GPIOH_BASE + LM3S_GPIO_DR2R_OFFSET)
|
||||
#define LM3S_GPIOH_DR4R (LM3S_GPIOH_BASE + LM3S_GPIO_DR4R_OFFSET)
|
||||
#define LM3S_GPIOH_DR8R (LM3S_GPIOH_BASE + LM3S_GPIO_DR8R_OFFSET)
|
||||
#define LM3S_GPIOH_ODR (LM3S_GPIOH_BASE + LM3S_GPIO_ODR_OFFSET)
|
||||
#define LM3S_GPIOH_PUR (LM3S_GPIOH_BASE + LM3S_GPIO_PUR_OFFSET)
|
||||
#define LM3S_GPIOH_PDR (LM3S_GPIOH_BASE + LM3S_GPIO_PDR_OFFSET)
|
||||
#define LM3S_GPIOH_SLR (LM3S_GPIOH_BASE + LM3S_GPIO_SLR_OFFSET)
|
||||
#define LM3S_GPIOH_DEN (LM3S_GPIOH_BASE + LM3S_GPIO_DEN_OFFSET)
|
||||
#define LM3S_GPIOH_LOCK (LM3S_GPIOH_BASE + LM3S_GPIO_LOCK_OFFSET)
|
||||
#define LM3S_GPIOH_CR (LM3S_GPIOH_BASE + LM3S_GPIO_CR_OFFSET)
|
||||
#define LM3S_GPIOH_PERIPHID4 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM3S_GPIOH_PERIPHID5 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM3S_GPIOH_PERIPHID6 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM3S_GPIOH_PERIPHID7 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM3S_GPIOH_PERIPHID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM3S_GPIOH_PERIPHID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM3S_GPIOH_PERIPHID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM3S_GPIOH_PERIPHID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM3S_GPIOH_PCELLID0 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID0_OFFSET)
|
||||
#define LM3S_GPIOH_PCELLID1 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID1_OFFSET)
|
||||
#define LM3S_GPIOH_PCELLID2 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID2_OFFSET)
|
||||
#define LM3S_GPIOH_PCELLID3 (LM3S_GPIOH_BASE + LM3S_GPIO_PCELLID3_OFFSET)
|
||||
#define LM_GPIOH_DATA (LM_GPIOH_BASE + LM_GPIO_DATA_OFFSET)
|
||||
#define LM_GPIOH_DIR (LM_GPIOH_BASE + LM_GPIO_DIR_OFFSET)
|
||||
#define LM_GPIOH_IS (LM_GPIOH_BASE + LM_GPIO_IS_OFFSET)
|
||||
#define LM_GPIOH_IBE (LM_GPIOH_BASE + LM_GPIO_IBE_OFFSET)
|
||||
#define LM_GPIOH_IEV (LM_GPIOH_BASE + LM_GPIO_IEV_OFFSET)
|
||||
#define LM_GPIOH_IM (LM_GPIOH_BASE + LM_GPIO_IM_OFFSET)
|
||||
#define LM_GPIOH_RIS (LM_GPIOH_BASE + LM_GPIO_RIS_OFFSET)
|
||||
#define LM_GPIOH_MIS (LM_GPIOH_BASE + LM_GPIO_MIS_OFFSET)
|
||||
#define LM_GPIOH_ICR (LM_GPIOH_BASE + LM_GPIO_ICR_OFFSET)
|
||||
#define LM_GPIOH_AFSEL (LM_GPIOH_BASE + LM_GPIO_AFSEL_OFFSET)
|
||||
#define LM_GPIOH_DR2R (LM_GPIOH_BASE + LM_GPIO_DR2R_OFFSET)
|
||||
#define LM_GPIOH_DR4R (LM_GPIOH_BASE + LM_GPIO_DR4R_OFFSET)
|
||||
#define LM_GPIOH_DR8R (LM_GPIOH_BASE + LM_GPIO_DR8R_OFFSET)
|
||||
#define LM_GPIOH_ODR (LM_GPIOH_BASE + LM_GPIO_ODR_OFFSET)
|
||||
#define LM_GPIOH_PUR (LM_GPIOH_BASE + LM_GPIO_PUR_OFFSET)
|
||||
#define LM_GPIOH_PDR (LM_GPIOH_BASE + LM_GPIO_PDR_OFFSET)
|
||||
#define LM_GPIOH_SLR (LM_GPIOH_BASE + LM_GPIO_SLR_OFFSET)
|
||||
#define LM_GPIOH_DEN (LM_GPIOH_BASE + LM_GPIO_DEN_OFFSET)
|
||||
#define LM_GPIOH_LOCK (LM_GPIOH_BASE + LM_GPIO_LOCK_OFFSET)
|
||||
#define LM_GPIOH_CR (LM_GPIOH_BASE + LM_GPIO_CR_OFFSET)
|
||||
#define LM_GPIOH_PERIPHID4 (LM_GPIOH_BASE + LM_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM_GPIOH_PERIPHID5 (LM_GPIOH_BASE + LM_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM_GPIOH_PERIPHID6 (LM_GPIOH_BASE + LM_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM_GPIOH_PERIPHID7 (LM_GPIOH_BASE + LM_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM_GPIOH_PERIPHID0 (LM_GPIOH_BASE + LM_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM_GPIOH_PERIPHID1 (LM_GPIOH_BASE + LM_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM_GPIOH_PERIPHID2 (LM_GPIOH_BASE + LM_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM_GPIOH_PERIPHID3 (LM_GPIOH_BASE + LM_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM_GPIOH_PCELLID0 (LM_GPIOH_BASE + LM_GPIO_PCELLID0_OFFSET)
|
||||
#define LM_GPIOH_PCELLID1 (LM_GPIOH_BASE + LM_GPIO_PCELLID1_OFFSET)
|
||||
#define LM_GPIOH_PCELLID2 (LM_GPIOH_BASE + LM_GPIO_PCELLID2_OFFSET)
|
||||
#define LM_GPIOH_PCELLID3 (LM_GPIOH_BASE + LM_GPIO_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_GPIOJ_DATA (LM3S_GPIOJ_BASE + LM3S_GPIO_DATA_OFFSET)
|
||||
#define LM3S_GPIOJ_DIR (LM3S_GPIOJ_BASE + LM3S_GPIO_DIR_OFFSET)
|
||||
#define LM3S_GPIOJ_IS (LM3S_GPIOJ_BASE + LM3S_GPIO_IS_OFFSET)
|
||||
#define LM3S_GPIOJ_IBE (LM3S_GPIOJ_BASE + LM3S_GPIO_IBE_OFFSET)
|
||||
#define LM3S_GPIOJ_IEV (LM3S_GPIOJ_BASE + LM3S_GPIO_IEV_OFFSET)
|
||||
#define LM3S_GPIOJ_IM (LM3S_GPIOJ_BASE + LM3S_GPIO_IM_OFFSET)
|
||||
#define LM3S_GPIOJ_RIS (LM3S_GPIOJ_BASE + LM3S_GPIO_RIS_OFFSET)
|
||||
#define LM3S_GPIOJ_MIS (LM3S_GPIOJ_BASE + LM3S_GPIO_MIS_OFFSET)
|
||||
#define LM3S_GPIOJ_ICR (LM3S_GPIOJ_BASE + LM3S_GPIO_ICR_OFFSET)
|
||||
#define LM3S_GPIOJ_AFSEL (LM3S_GPIOJ_BASE + LM3S_GPIO_AFSEL_OFFSET)
|
||||
#define LM3S_GPIOJ_DR2R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR2R_OFFSET)
|
||||
#define LM3S_GPIOJ_DR4R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR4R_OFFSET)
|
||||
#define LM3S_GPIOJ_DR8R (LM3S_GPIOJ_BASE + LM3S_GPIO_DR8R_OFFSET)
|
||||
#define LM3S_GPIOJ_ODR (LM3S_GPIOJ_BASE + LM3S_GPIO_ODR_OFFSET)
|
||||
#define LM3S_GPIOJ_PUR (LM3S_GPIOJ_BASE + LM3S_GPIO_PUR_OFFSET)
|
||||
#define LM3S_GPIOJ_PDR (LM3S_GPIOJ_BASE + LM3S_GPIO_PDR_OFFSET)
|
||||
#define LM3S_GPIOJ_SLR (LM3S_GPIOJ_BASE + LM3S_GPIO_SLR_OFFSET)
|
||||
#define LM3S_GPIOJ_DEN (LM3S_GPIOJ_BASE + LM3S_GPIO_DEN_OFFSET)
|
||||
#define LM3S_GPIOJ_LOCK (LM3S_GPIOJ_BASE + LM3S_GPIO_LOCK_OFFSET)
|
||||
#define LM3S_GPIOJ_CR (LM3S_GPIOJ_BASE + LM3S_GPIO_CR_OFFSET)
|
||||
#define LM3S_GPIOJ_PERIPHID4 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM3S_GPIOJ_PERIPHID5 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM3S_GPIOJ_PERIPHID6 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM3S_GPIOJ_PERIPHID7 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM3S_GPIOJ_PERIPHID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM3S_GPIOJ_PERIPHID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM3S_GPIOJ_PERIPHID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM3S_GPIOJ_PERIPHID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM3S_GPIOJ_PCELLID0 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID0_OFFSET)
|
||||
#define LM3S_GPIOJ_PCELLID1 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID1_OFFSET)
|
||||
#define LM3S_GPIOJ_PCELLID2 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID2_OFFSET)
|
||||
#define LM3S_GPIOJ_PCELLID3 (LM3S_GPIOJ_BASE + LM3S_GPIO_PCELLID3_OFFSET)
|
||||
#define LM_GPIOJ_DATA (LM_GPIOJ_BASE + LM_GPIO_DATA_OFFSET)
|
||||
#define LM_GPIOJ_DIR (LM_GPIOJ_BASE + LM_GPIO_DIR_OFFSET)
|
||||
#define LM_GPIOJ_IS (LM_GPIOJ_BASE + LM_GPIO_IS_OFFSET)
|
||||
#define LM_GPIOJ_IBE (LM_GPIOJ_BASE + LM_GPIO_IBE_OFFSET)
|
||||
#define LM_GPIOJ_IEV (LM_GPIOJ_BASE + LM_GPIO_IEV_OFFSET)
|
||||
#define LM_GPIOJ_IM (LM_GPIOJ_BASE + LM_GPIO_IM_OFFSET)
|
||||
#define LM_GPIOJ_RIS (LM_GPIOJ_BASE + LM_GPIO_RIS_OFFSET)
|
||||
#define LM_GPIOJ_MIS (LM_GPIOJ_BASE + LM_GPIO_MIS_OFFSET)
|
||||
#define LM_GPIOJ_ICR (LM_GPIOJ_BASE + LM_GPIO_ICR_OFFSET)
|
||||
#define LM_GPIOJ_AFSEL (LM_GPIOJ_BASE + LM_GPIO_AFSEL_OFFSET)
|
||||
#define LM_GPIOJ_DR2R (LM_GPIOJ_BASE + LM_GPIO_DR2R_OFFSET)
|
||||
#define LM_GPIOJ_DR4R (LM_GPIOJ_BASE + LM_GPIO_DR4R_OFFSET)
|
||||
#define LM_GPIOJ_DR8R (LM_GPIOJ_BASE + LM_GPIO_DR8R_OFFSET)
|
||||
#define LM_GPIOJ_ODR (LM_GPIOJ_BASE + LM_GPIO_ODR_OFFSET)
|
||||
#define LM_GPIOJ_PUR (LM_GPIOJ_BASE + LM_GPIO_PUR_OFFSET)
|
||||
#define LM_GPIOJ_PDR (LM_GPIOJ_BASE + LM_GPIO_PDR_OFFSET)
|
||||
#define LM_GPIOJ_SLR (LM_GPIOJ_BASE + LM_GPIO_SLR_OFFSET)
|
||||
#define LM_GPIOJ_DEN (LM_GPIOJ_BASE + LM_GPIO_DEN_OFFSET)
|
||||
#define LM_GPIOJ_LOCK (LM_GPIOJ_BASE + LM_GPIO_LOCK_OFFSET)
|
||||
#define LM_GPIOJ_CR (LM_GPIOJ_BASE + LM_GPIO_CR_OFFSET)
|
||||
#define LM_GPIOJ_PERIPHID4 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID4_OFFSET)
|
||||
#define LM_GPIOJ_PERIPHID5 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID5_OFFSET)
|
||||
#define LM_GPIOJ_PERIPHID6 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID6_OFFSET)
|
||||
#define LM_GPIOJ_PERIPHID7 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID7_OFFSET)
|
||||
#define LM_GPIOJ_PERIPHID0 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID0_OFFSET)
|
||||
#define LM_GPIOJ_PERIPHID1 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID1_OFFSET)
|
||||
#define LM_GPIOJ_PERIPHID2 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID2_OFFSET)
|
||||
#define LM_GPIOJ_PERIPHID3 (LM_GPIOJ_BASE + LM_GPIO_PERIPHID3_OFFSET)
|
||||
#define LM_GPIOJ_PCELLID0 (LM_GPIOJ_BASE + LM_GPIO_PCELLID0_OFFSET)
|
||||
#define LM_GPIOJ_PCELLID1 (LM_GPIOJ_BASE + LM_GPIO_PCELLID1_OFFSET)
|
||||
#define LM_GPIOJ_PCELLID2 (LM_GPIOJ_BASE + LM_GPIO_PCELLID2_OFFSET)
|
||||
#define LM_GPIOJ_PCELLID3 (LM_GPIOJ_BASE + LM_GPIO_PCELLID3_OFFSET)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
@@ -392,4 +392,4 @@
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_GPIO_H */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_GPIO_H */
|
||||
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -50,99 +50,99 @@
|
||||
|
||||
/* I2C Master */
|
||||
|
||||
#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */
|
||||
#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */
|
||||
#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */
|
||||
#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
|
||||
#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
|
||||
#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
|
||||
#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
|
||||
#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
|
||||
#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */
|
||||
#define LM_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */
|
||||
#define LM_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */
|
||||
#define LM_I2CM_DR_OFFSET 0x008 /* I2C Master Data */
|
||||
#define LM_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
|
||||
#define LM_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
|
||||
#define LM_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
|
||||
#define LM_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
|
||||
#define LM_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
|
||||
#define LM_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */
|
||||
|
||||
/* I2C Slave */
|
||||
|
||||
#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
|
||||
#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
|
||||
#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */
|
||||
#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
|
||||
#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
|
||||
#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
|
||||
#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
|
||||
#define LM_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
|
||||
#define LM_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
|
||||
#define LM_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */
|
||||
#define LM_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
|
||||
#define LM_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
|
||||
#define LM_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
|
||||
#define LM_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
|
||||
|
||||
/* I2C Register Addresses ***********************************************************/
|
||||
|
||||
#if LM3S_NI2C > 0
|
||||
#if LM_NI2C > 0
|
||||
|
||||
/* I2C Master */
|
||||
|
||||
#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000)
|
||||
#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET)
|
||||
#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET)
|
||||
#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET)
|
||||
#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET)
|
||||
#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET)
|
||||
#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET)
|
||||
#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET)
|
||||
#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET)
|
||||
#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET)
|
||||
#define LM_I2CM_BASE(n) (LM_I2CM0_BASE + (n)*0x1000)
|
||||
#define LM_I2CM_SA(n) (LM_I2CM_BASE(n) + LM_I2CM_SA_OFFSET)
|
||||
#define LM_I2CM_CS(n) (LM_I2CM_BASE(n) + LM_I2CM_CS_OFFSET)
|
||||
#define LM_I2CM_DR(n) (LM_I2CM_BASE(n) + LM_I2CM_DR_OFFSET)
|
||||
#define LM_I2CM_TPR(n) (LM_I2CM_BASE(n) + LM_I2CM_TPR_OFFSET)
|
||||
#define LM_I2CM_IMR(n) (LM_I2CM_BASE(n) + LM_I2CM_IMR_OFFSET)
|
||||
#define LM_I2CM_RIS(n) (LM_I2CM_BASE(n) + LM_I2CM_RIS_OFFSET)
|
||||
#define LM_I2CM_MIS(n) (LM_I2CM_BASE(n) + LM_I2CM_MIS_OFFSET)
|
||||
#define LM_I2CM_ICR(n) (LM_I2CM_BASE(n) + LM_I2CM_ICR_OFFSET)
|
||||
#define LM_I2CM_CR(n) (LM_I2CM_BASE(n) + LM_I2CM_CR_OFFSET)
|
||||
|
||||
/* I2C Slave */
|
||||
|
||||
#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000)
|
||||
#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET)
|
||||
#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET)
|
||||
#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET)
|
||||
#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET)
|
||||
#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET)
|
||||
#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET)
|
||||
#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET)
|
||||
#define LM_I2CS_BASE(n) (LM_I2CS0_BASE + (n)*0x1000)
|
||||
#define LM_I2CS_OAR(n) (LM_I2CS_BASE(n) + LM_I2CS_OAR_OFFSET)
|
||||
#define LM_I2CS_CSR(n) (LM_I2CS_BASE(n) + LM_I2CS_CSR_OFFSET)
|
||||
#define LM_I2CS_DR(n) (LM_I2CS_BASE(n) + LM_I2CS_DR_OFFSET)
|
||||
#define LM_I2CS_IMR(n) (LM_I2CS_BASE(n) + LM_I2CS_IMR_OFFSET)
|
||||
#define LM_I2CS_RIS(n) (LM_I2CS_BASE(n) + LM_I2CS_RIS_OFFSET)
|
||||
#define LM_I2CS_MIS(n) (LM_I2CS_BASE(n) + LM_I2CS_MIS_OFFSET)
|
||||
#define LM_I2CS_ICR(n) (LM_I2CS_BASE(n) + LM_I2CS_ICR_OFFSET)
|
||||
|
||||
/* I2C0 Master */
|
||||
|
||||
#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET)
|
||||
#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET)
|
||||
#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET)
|
||||
#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET)
|
||||
#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET)
|
||||
#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET)
|
||||
#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET)
|
||||
#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET)
|
||||
#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET)
|
||||
#define LM_I2CM0_SA (LM_I2CM0_BASE + LM_I2CM_SA_OFFSET)
|
||||
#define LM_I2CM0_CS (LM_I2CM0_BASE + LM_I2CM_CS_OFFSET)
|
||||
#define LM_I2CM0_DR (LM_I2CM0_BASE + LM_I2CM_DR_OFFSET)
|
||||
#define LM_I2CM0_TPR (LM_I2CM0_BASE + LM_I2CM_TPR_OFFSET)
|
||||
#define LM_I2CM0_IMR (LM_I2CM0_BASE + LM_I2CM_IMR_OFFSET)
|
||||
#define LM_I2CM0_RIS (LM_I2CM0_BASE + LM_I2CM_RIS_OFFSET)
|
||||
#define LM_I2CM0_MIS (LM_I2CM0_BASE + LM_I2CM_MIS_OFFSET)
|
||||
#define LM_I2CM0_ICR (LM_I2CM0_BASE + LM_I2CM_ICR_OFFSET)
|
||||
#define LM_I2CM0_CR (LM_I2CM0_BASE + LM_I2CM_CR_OFFSET)
|
||||
|
||||
/* I2C0 Slave */
|
||||
|
||||
#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET)
|
||||
#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET)
|
||||
#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET)
|
||||
#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET)
|
||||
#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET)
|
||||
#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET)
|
||||
#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET)
|
||||
#define LM_I2CS0_OAR (LM_I2CS0_BASE + LM_I2CS_OAR_OFFSET)
|
||||
#define LM_I2CS0_CSR (LM_I2CS0_BASE + LM_I2CS_CSR_OFFSET)
|
||||
#define LM_I2CS0_DR (LM_I2CS0_BASE + LM_I2CS_DR_OFFSET)
|
||||
#define LM_I2CS0_IMR (LM_I2CS0_BASE + LM_I2CS_IMR_OFFSET)
|
||||
#define LM_I2CS0_RIS (LM_I2CS0_BASE + LM_I2CS_RIS_OFFSET)
|
||||
#define LM_I2CS0_MIS (LM_I2CS0_BASE + LM_I2CS_MIS_OFFSET)
|
||||
#define LM_I2CS0_ICR (LM_I2CS0_BASE + LM_I2CS_ICR_OFFSET)
|
||||
|
||||
#if LM3S_NI2C > 1
|
||||
#if LM_NI2C > 1
|
||||
|
||||
/* I2C1 Master */
|
||||
|
||||
#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET)
|
||||
#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET)
|
||||
#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET)
|
||||
#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET)
|
||||
#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET)
|
||||
#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET)
|
||||
#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET)
|
||||
#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET)
|
||||
#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET)
|
||||
#define LM_I2CM1_SA (LM_I2CM1_BASE + LM_I2CM_SA_OFFSET)
|
||||
#define LM_I2CM1_CS (LM_I2CM1_BASE + LM_I2CM_CS_OFFSET)
|
||||
#define LM_I2CM1_DR (LM_I2CM1_BASE + LM_I2CM_DR_OFFSET)
|
||||
#define LM_I2CM1_TPR (LM_I2CM1_BASE + LM_I2CM_TPR_OFFSET)
|
||||
#define LM_I2CM1_IMR (LM_I2CM1_BASE + LM_I2CM_IMR_OFFSET)
|
||||
#define LM_I2CM1_RIS (LM_I2CM1_BASE + LM_I2CM_RIS_OFFSET)
|
||||
#define LM_I2CM1_MIS (LM_I2CM1_BASE + LM_I2CM_MIS_OFFSET)
|
||||
#define LM_I2CM1_ICR (LM_I2CM1_BASE + LM_I2CM_ICR_OFFSET)
|
||||
#define LM_I2CM1_CR (LM_I2CM1_BASE + LM_I2CM_CR_OFFSET)
|
||||
|
||||
/* I2C1 Slave */
|
||||
|
||||
#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET)
|
||||
#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET)
|
||||
#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET)
|
||||
#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET)
|
||||
#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET)
|
||||
#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET)
|
||||
#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET)
|
||||
#define LM_I2CS1_OAR (LM_I2CS1_BASE + LM_I2CS_OAR_OFFSET)
|
||||
#define LM_I2CS1_CSR (LM_I2CS1_BASE + LM_I2CS_CSR_OFFSET)
|
||||
#define LM_I2CS1_DR (LM_I2CS1_BASE + LM_I2CS_DR_OFFSET)
|
||||
#define LM_I2CS1_IMR (LM_I2CS1_BASE + LM_I2CS_IMR_OFFSET)
|
||||
#define LM_I2CS1_RIS (LM_I2CS1_BASE + LM_I2CS_RIS_OFFSET)
|
||||
#define LM_I2CS1_MIS (LM_I2CS1_BASE + LM_I2CS_MIS_OFFSET)
|
||||
#define LM_I2CS1_ICR (LM_I2CS1_BASE + LM_I2CS_ICR_OFFSET)
|
||||
|
||||
#endif
|
||||
#endif
|
||||
@@ -244,4 +244,4 @@
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H */
|
||||
|
||||
@@ -42,7 +42,7 @@
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* Include the memory map file for the specific Stellaris chip */
|
||||
/* Include the pin mapping file for the specific Stellaris chip */
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_LM3S
|
||||
# include "chip/lm3s_pinmap.h"
|
||||
|
||||
+131
-131
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -43,7 +43,7 @@
|
||||
#include <nuttx/config.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#if LM3S_NSSI > 0
|
||||
#if LM_NSSI > 0
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
@@ -51,173 +51,173 @@
|
||||
|
||||
/* SSI register offsets *************************************************************/
|
||||
|
||||
#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */
|
||||
#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */
|
||||
#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */
|
||||
#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */
|
||||
#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */
|
||||
#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */
|
||||
#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */
|
||||
#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */
|
||||
#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */
|
||||
#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
|
||||
#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
|
||||
#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
|
||||
#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
|
||||
#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
|
||||
#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
|
||||
#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
|
||||
#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
|
||||
#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */
|
||||
#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */
|
||||
#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */
|
||||
#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */
|
||||
#define LM_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */
|
||||
#define LM_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */
|
||||
#define LM_SSI_DR_OFFSET 0x008 /* SSI Data */
|
||||
#define LM_SSI_SR_OFFSET 0x00c /* SSI Status */
|
||||
#define LM_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */
|
||||
#define LM_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */
|
||||
#define LM_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */
|
||||
#define LM_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */
|
||||
#define LM_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */
|
||||
#define LM_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
|
||||
#define LM_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
|
||||
#define LM_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
|
||||
#define LM_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
|
||||
#define LM_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
|
||||
#define LM_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
|
||||
#define LM_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
|
||||
#define LM_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
|
||||
#define LM_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */
|
||||
#define LM_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */
|
||||
#define LM_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */
|
||||
#define LM_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */
|
||||
|
||||
/* SSI register addresses ***********************************************************/
|
||||
|
||||
#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET)
|
||||
#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET)
|
||||
#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET)
|
||||
#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET)
|
||||
#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET)
|
||||
#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET)
|
||||
#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET)
|
||||
#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET)
|
||||
#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET)
|
||||
#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET)
|
||||
#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET)
|
||||
#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET)
|
||||
#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET)
|
||||
#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET)
|
||||
#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET)
|
||||
#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET)
|
||||
#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET)
|
||||
#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET)
|
||||
#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET)
|
||||
#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET)
|
||||
#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET)
|
||||
#define LM_SSI0_CR0 (LM_SSI0_BASE + LM_SSI_CR0_OFFSET)
|
||||
#define LM_SSI0_CR1 (LM_SSI0_BASE + LM_SSI_CR1_OFFSET)
|
||||
#define LM_SSI0_DR (LM_SSI0_BASE + LM_SSI_DR_OFFSET)
|
||||
#define LM_SSI0_SR (LM_SSI0_BASE + LM_SSI_SR_OFFSET)
|
||||
#define LM_SSI0_CPSR (LM_SSI0_BASE + LM_SSI_CPSR_OFFSET)
|
||||
#define LM_SSI0_IM (LM_SSI0_BASE + LM_SSI_IM_OFFSET)
|
||||
#define LM_SSI0_RIS (LM_SSI0_BASE + LM_SSI_RIS_OFFSET)
|
||||
#define LM_SSI0_MIS (LM_SSI0_BASE + LM_SSI_MIS_OFFSET)
|
||||
#define LM_SSI0_ICR (LM_SSI0_BASE + LM_SSI_ICR_OFFSET)
|
||||
#define LM_SSI0_PERIPHID4 (LM_SSI0_BASE + LM_SSI_PERIPHID4_OFFSET)
|
||||
#define LM_SSI0_PERIPHID5 (LM_SSI0_BASE + LM_SSI_PERIPHID5_OFFSET)
|
||||
#define LM_SSI0_PERIPHID6 (LM_SSI0_BASE + LM_SSI_PERIPHID6_OFFSET)
|
||||
#define LM_SSI0_PERIPHID7 (LM_SSI0_BASE + LM_SSI_PERIPHID7_OFFSET)
|
||||
#define LM_SSI0_PERIPHID0 (LM_SSI0_BASE + LM_SSI_PERIPHID0_OFFSET)
|
||||
#define LM_SSI0_PERIPHID1 (LM_SSI0_BASE + LM_SSI_PERIPHID1_OFFSET)
|
||||
#define LM_SSI0_PERIPHID2 (LM_SSI0_BASE + LM_SSI_PERIPHID2_OFFSET)
|
||||
#define LM_SSI0_PERIPHID3 (LM_SSI0_BASE + LM_SSI_PERIPHID3_OFFSET)
|
||||
#define LM_SSI0_PCELLID0 (LM_SSI0_BASE + LM_SSI_PCELLID0_OFFSET)
|
||||
#define LM_SSI0_PCELLID1 (LM_SSI0_BASE + LM_SSI_PCELLID1_OFFSET)
|
||||
#define LM_SSI0_PCELLID2 (LM_SSI0_BASE + LM_SSI_PCELLID2_OFFSET)
|
||||
#define LM_SSI0_PCELLID3 (LM_SSI0_BASE + LM_SSI_PCELLID3_OFFSET)
|
||||
|
||||
#if LM3S_NSSI > 1
|
||||
#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET)
|
||||
#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET)
|
||||
#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET)
|
||||
#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET)
|
||||
#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET)
|
||||
#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET)
|
||||
#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET)
|
||||
#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET)
|
||||
#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET)
|
||||
#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET)
|
||||
#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET)
|
||||
#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET)
|
||||
#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET)
|
||||
#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET)
|
||||
#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET)
|
||||
#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET)
|
||||
#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET)
|
||||
#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET)
|
||||
#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET)
|
||||
#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET)
|
||||
#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET)
|
||||
#if LM_NSSI > 1
|
||||
#define LM_SSI1_CR0 (LM_SSI1_BASE + LM_SSI_CR0_OFFSET)
|
||||
#define LM_SSI1_CR1 (LM_SSI1_BASE + LM_SSI_CR1_OFFSET)
|
||||
#define LM_SSI1_DR (LM_SSI1_BASE + LM_SSI_DR_OFFSET)
|
||||
#define LM_SSI1_SR (LM_SSI1_BASE + LM_SSI_SR_OFFSET)
|
||||
#define LM_SSI1_CPSR (LM_SSI1_BASE + LM_SSI_CPSR_OFFSET)
|
||||
#define LM_SSI1_IM (LM_SSI1_BASE + LM_SSI_IM_OFFSET)
|
||||
#define LM_SSI1_RIS (LM_SSI1_BASE + LM_SSI_RIS_OFFSET)
|
||||
#define LM_SSI1_MIS (LM_SSI1_BASE + LM_SSI_MIS_OFFSET)
|
||||
#define LM_SSI1_ICR (LM_SSI1_BASE + LM_SSI_ICR_OFFSET)
|
||||
#define LM_SSI1_PERIPHID4 (LM_SSI1_BASE + LM_SSI_PERIPHID4_OFFSET)
|
||||
#define LM_SSI1_PERIPHID5 (LM_SSI1_BASE + LM_SSI_PERIPHID5_OFFSET)
|
||||
#define LM_SSI1_PERIPHID6 (LM_SSI1_BASE + LM_SSI_PERIPHID6_OFFSET)
|
||||
#define LM_SSI1_PERIPHID7 (LM_SSI1_BASE + LM_SSI_PERIPHID7_OFFSET)
|
||||
#define LM_SSI1_PERIPHID0 (LM_SSI1_BASE + LM_SSI_PERIPHID0_OFFSET)
|
||||
#define LM_SSI1_PERIPHID1 (LM_SSI1_BASE + LM_SSI_PERIPHID1_OFFSET)
|
||||
#define LM_SSI1_PERIPHID2 (LM_SSI1_BASE + LM_SSI_PERIPHID2_OFFSET)
|
||||
#define LM_SSI1_PERIPHID3 (LM_SSI1_BASE + LM_SSI_PERIPHID3_OFFSET)
|
||||
#define LM_SSI1_PCELLID0 (LM_SSI1_BASE + LM_SSI_PCELLID0_OFFSET)
|
||||
#define LM_SSI1_PCELLID1 (LM_SSI1_BASE + LM_SSI_PCELLID1_OFFSET)
|
||||
#define LM_SSI1_PCELLID2 (LM_SSI1_BASE + LM_SSI_PCELLID2_OFFSET)
|
||||
#define LM_SSI1_PCELLID3 (LM_SSI1_BASE + LM_SSI_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000)
|
||||
#define LM_SSI_BASE(n) (LM_SSI0_BASE + (n)*0x01000)
|
||||
|
||||
#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET)
|
||||
#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET)
|
||||
#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET)
|
||||
#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET)
|
||||
#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET)
|
||||
#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET)
|
||||
#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET)
|
||||
#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET)
|
||||
#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET)
|
||||
#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET)
|
||||
#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET)
|
||||
#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET)
|
||||
#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET)
|
||||
#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET)
|
||||
#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET)
|
||||
#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET)
|
||||
#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET)
|
||||
#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET)
|
||||
#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET)
|
||||
#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET)
|
||||
#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET)
|
||||
#endif /* LM3S_NSSI > 1 */
|
||||
#define LM_SSI_CR0(n) (LM_SSI_BASE(n) + LM_SSI_CR0_OFFSET)
|
||||
#define LM_SSI_CR1(n) (LM_SSI_BASE(n) + LM_SSI_CR1_OFFSET)
|
||||
#define LM_SSI_DR(n) (LM_SSI_BASE(n) + LM_SSI_DR_OFFSET)
|
||||
#define LM_SSI_SR(n) (LM_SSI_BASE(n) + LM_SSI_SR_OFFSET)
|
||||
#define LM_SSI_CPSR(n) (LM_SSI_BASE(n) + LM_SSI_CPSR_OFFSET)
|
||||
#define LM_SSI_IM(n) (LM_SSI_BASE(n) + LM_SSI_IM_OFFSET)
|
||||
#define LM_SSI_RIS(n) (LM_SSI_BASE(n) + LM_SSI_RIS_OFFSET)
|
||||
#define LM_SSI_MIS(n) (LM_SSI_BASE(n) + LM_SSI_MIS_OFFSET)
|
||||
#define LM_SSI_ICR(n) (LM_SSI_BASE(n) + LM_SSI_ICR_OFFSET)
|
||||
#define LM_SSI_PERIPHID4(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID4_OFFSET)
|
||||
#define LM_SSI_PERIPHID5(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID5_OFFSET)
|
||||
#define LM_SSI_PERIPHID6(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID6_OFFSET)
|
||||
#define LM_SSI_PERIPHID7(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID7_OFFSET)
|
||||
#define LM_SSI_PERIPHID0(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID0_OFFSET)
|
||||
#define LM_SSI_PERIPHID1(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID1_OFFSET)
|
||||
#define LM_SSI_PERIPHID2(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID2_OFFSET)
|
||||
#define LM_SSI_PERIPHID3(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID3_OFFSET)
|
||||
#define LM_SSI_PCELLID0(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID0_OFFSET)
|
||||
#define LM_SSI_PCELLID1(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID1_OFFSET)
|
||||
#define LM_SSI_PCELLID2(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID2_OFFSET)
|
||||
#define LM_SSI_PCELLID3(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID3_OFFSET)
|
||||
#endif /* LM_NSSI > 1 */
|
||||
|
||||
/* SSI register bit defitiions ******************************************************/
|
||||
|
||||
/* SSI Control 0 (SSICR0), offset 0x000 */
|
||||
|
||||
#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */
|
||||
#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT)
|
||||
#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
|
||||
#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */
|
||||
#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT)
|
||||
#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */
|
||||
#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */
|
||||
#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */
|
||||
#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */
|
||||
#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */
|
||||
#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */
|
||||
#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT)
|
||||
#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */
|
||||
#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT)
|
||||
#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
|
||||
#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */
|
||||
#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT)
|
||||
#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */
|
||||
#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */
|
||||
#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */
|
||||
#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */
|
||||
#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */
|
||||
#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */
|
||||
#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT)
|
||||
|
||||
/* SSI Control 1 (SSICR1), offset 0x004 */
|
||||
|
||||
#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */
|
||||
#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */
|
||||
#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */
|
||||
#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */
|
||||
#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */
|
||||
#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */
|
||||
#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */
|
||||
#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */
|
||||
|
||||
/* SSI Data (SSIDR), offset 0x008 */
|
||||
|
||||
#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */
|
||||
#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */
|
||||
|
||||
/* SSI Status (SSISR), offset 0x00c */
|
||||
|
||||
#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */
|
||||
#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */
|
||||
#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */
|
||||
#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */
|
||||
#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */
|
||||
#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */
|
||||
#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */
|
||||
#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */
|
||||
#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */
|
||||
#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */
|
||||
|
||||
/* SSI Clock Prescale (SSICPSR), offset 0x010 */
|
||||
|
||||
#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */
|
||||
#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */
|
||||
|
||||
/* SSI Interrupt Mask (SSIIM), offset 0x014 */
|
||||
|
||||
#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */
|
||||
#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */
|
||||
#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */
|
||||
#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */
|
||||
#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */
|
||||
#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */
|
||||
#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */
|
||||
#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */
|
||||
|
||||
/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
|
||||
|
||||
#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */
|
||||
#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */
|
||||
#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */
|
||||
#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */
|
||||
#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */
|
||||
#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */
|
||||
#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */
|
||||
#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */
|
||||
|
||||
/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
|
||||
|
||||
#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */
|
||||
#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */
|
||||
#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */
|
||||
#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */
|
||||
#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */
|
||||
#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */
|
||||
#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */
|
||||
#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */
|
||||
|
||||
/* SSI Interrupt Clear (SSIICR), offset 0x020 */
|
||||
|
||||
#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */
|
||||
#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */
|
||||
#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */
|
||||
#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */
|
||||
|
||||
/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
|
||||
|
||||
#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */
|
||||
#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */
|
||||
|
||||
/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
|
||||
|
||||
#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */
|
||||
#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
@@ -231,5 +231,5 @@
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* LM3S_NSSI > 0 */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */
|
||||
#endif /* LM_NSSI > 0 */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H */
|
||||
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -48,67 +48,67 @@
|
||||
|
||||
/* System Control Register Offsets **************************************************/
|
||||
|
||||
#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
|
||||
#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
|
||||
#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
|
||||
#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
|
||||
#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
|
||||
#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
|
||||
#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
|
||||
#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
|
||||
#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */
|
||||
#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
|
||||
#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
|
||||
#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/
|
||||
#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
|
||||
#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
|
||||
#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
|
||||
#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
|
||||
#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
|
||||
#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */
|
||||
#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
|
||||
#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
|
||||
#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
|
||||
#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
|
||||
#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
|
||||
#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
|
||||
#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
|
||||
#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
|
||||
#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
|
||||
#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
|
||||
#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
|
||||
#define LM_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
|
||||
#define LM_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
|
||||
#define LM_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
|
||||
#define LM_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
|
||||
#define LM_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
|
||||
#define LM_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
|
||||
#define LM_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
|
||||
#define LM_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
|
||||
#define LM_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */
|
||||
#define LM_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
|
||||
#define LM_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
|
||||
#define LM_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/
|
||||
#define LM_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
|
||||
#define LM_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
|
||||
#define LM_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
|
||||
#define LM_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
|
||||
#define LM_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
|
||||
#define LM_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */
|
||||
#define LM_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
|
||||
#define LM_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
|
||||
#define LM_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
|
||||
#define LM_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
|
||||
#define LM_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
|
||||
#define LM_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
|
||||
#define LM_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
|
||||
#define LM_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
|
||||
#define LM_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
|
||||
#define LM_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
|
||||
#define LM_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
|
||||
|
||||
/* System Control Register Addresses ************************************************/
|
||||
|
||||
#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET)
|
||||
#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET)
|
||||
#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET)
|
||||
#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET)
|
||||
#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET)
|
||||
#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET)
|
||||
#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET)
|
||||
#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET)
|
||||
#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET)
|
||||
#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET)
|
||||
#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET)
|
||||
#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET)
|
||||
#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET)
|
||||
#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET)
|
||||
#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET)
|
||||
#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET)
|
||||
#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET)
|
||||
#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET)
|
||||
#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET)
|
||||
#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET)
|
||||
#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET)
|
||||
#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET)
|
||||
#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET)
|
||||
#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET)
|
||||
#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET)
|
||||
#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET)
|
||||
#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET)
|
||||
#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET)
|
||||
#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET)
|
||||
#define LM_SYSCON_DID0 (LM_SYSCON_BASE + LM_SYSCON_DID0_OFFSET)
|
||||
#define LM_SYSCON_DID1 (LM_SYSCON_BASE + LM_SYSCON_DID1_OFFSET)
|
||||
#define LM_SYSCON_DC0 (LM_SYSCON_BASE + LM_SYSCON_DC0_OFFSET)
|
||||
#define LM_SYSCON_DC1 (LM_SYSCON_BASE + LM_SYSCON_DC1_OFFSET)
|
||||
#define LM_SYSCON_DC2 (LM_SYSCON_BASE + LM_SYSCON_DC2_OFFSET)
|
||||
#define LM_SYSCON_DC3 (LM_SYSCON_BASE + LM_SYSCON_DC3_OFFSET)
|
||||
#define LM_SYSCON_DC4 (LM_SYSCON_BASE + LM_SYSCON_DC4_OFFSET)
|
||||
#define LM_SYSCON_PBORCTL (LM_SYSCON_BASE + LM_SYSCON_PBORCTL_OFFSET)
|
||||
#define LM_SYSCON_LDOPCTL (LM_SYSCON_BASE + LM_SYSCON_LDOPCTL_OFFSET)
|
||||
#define LM_SYSCON_SRCR0 (LM_SYSCON_BASE + LM_SYSCON_SRCR0_OFFSET)
|
||||
#define LM_SYSCON_SRCR1 (LM_SYSCON_BASE + LM_SYSCON_SRCR1_OFFSET)
|
||||
#define LM_SYSCON_SRCR2 (LM_SYSCON_BASE + LM_SYSCON_SRCR2_OFFSET)
|
||||
#define LM_SYSCON_RIS (LM_SYSCON_BASE + LM_SYSCON_RIS_OFFSET)
|
||||
#define LM_SYSCON_IMC (LM_SYSCON_BASE + LM_SYSCON_IMC_OFFSET)
|
||||
#define LM_SYSCON_MISC (LM_SYSCON_BASE + LM_SYSCON_MISC_OFFSET)
|
||||
#define LM_SYSCON_RESC (LM_SYSCON_BASE + LM_SYSCON_RESC_OFFSET)
|
||||
#define LM_SYSCON_RCC (LM_SYSCON_BASE + LM_SYSCON_RCC_OFFSET)
|
||||
#define LM_SYSCON_PLLCFG (LM_SYSCON_BASE + LM_SYSCON_PLLCFG_OFFSET)
|
||||
#define LM_SYSCON_RCC2 (LM_SYSCON_BASE + LM_SYSCON_RCC2_OFFSET)
|
||||
#define LM_SYSCON_RCGC0 (LM_SYSCON_BASE + LM_SYSCON_RCGC0_OFFSET)
|
||||
#define LM_SYSCON_RCGC1 (LM_SYSCON_BASE + LM_SYSCON_RCGC1_OFFSET)
|
||||
#define LM_SYSCON_RCGC2 (LM_SYSCON_BASE + LM_SYSCON_RCGC2_OFFSET)
|
||||
#define LM_SYSCON_SCGC0 (LM_SYSCON_BASE + LM_SYSCON_SCGC0_OFFSET)
|
||||
#define LM_SYSCON_SCGC1 (LM_SYSCON_BASE + LM_SYSCON_SCGC1_OFFSET)
|
||||
#define LM_SYSCON_SCGC2 (LM_SYSCON_BASE + LM_SYSCON_SCGC2_OFFSET)
|
||||
#define LM_SYSCON_DCGC0 (LM_SYSCON_BASE + LM_SYSCON_DCGC0_OFFSET)
|
||||
#define LM_SYSCON_DCGC1 (LM_SYSCON_BASE + LM_SYSCON_DCGC1_OFFSET)
|
||||
#define LM_SYSCON_DCGC2 (LM_SYSCON_BASE + LM_SYSCON_DCGC2_OFFSET)
|
||||
#define LM_SYSCON_DSLPCLKCFG (LM_SYSCON_BASE + LM_SYSCON_DSLPCLKCFG_OFFSET)
|
||||
|
||||
/* System Control Register Bit Definitions ******************************************/
|
||||
|
||||
@@ -492,4 +492,4 @@
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H */
|
||||
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -46,27 +46,27 @@
|
||||
|
||||
/* Timer register offsets ***********************************************************/
|
||||
|
||||
#define TIMER_GPTMCFG_OFFSET 0x000
|
||||
#define TIMER_GPTMTAMR_OFFSET 0x004
|
||||
#define TIMER_GPTMCTL_OFFSET 0x00C
|
||||
#define TIMER_GPTMIMR_OFFSET 0x018
|
||||
#define TIMER_GPTMRIS_OFFSET 0x01C
|
||||
#define TIMER_GPTMICR_OFFSET 0x024
|
||||
#define TIMER_GPTMTAILR_OFFSET 0x028
|
||||
#define TIMER_GPTMTAR_OFFSET 0x048
|
||||
#define LM_TIMER_GPTMCFG_OFFSET 0x000
|
||||
#define LM_TIMER_GPTMTAMR_OFFSET 0x004
|
||||
#define LM_TIMER_GPTMCTL_OFFSET 0x00c
|
||||
#define LM_TIMER_GPTMIMR_OFFSET 0x018
|
||||
#define LM_TIMER_GPTMRIS_OFFSET 0x01c
|
||||
#define LM_TIMER_GPTMICR_OFFSET 0x024
|
||||
#define LM_TIMER_GPTMTAILR_OFFSET 0x028
|
||||
#define LM_TIMER_GPTMTAR_OFFSET 0x048
|
||||
|
||||
/* SSI register addresses ***********************************************************/
|
||||
|
||||
#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000)
|
||||
#define LM_TIMER_BASE(n) (LM_TIMER0_BASE + (n)*0x01000)
|
||||
|
||||
#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
|
||||
#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
|
||||
#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
|
||||
#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
|
||||
#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
|
||||
#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
|
||||
#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
|
||||
#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
|
||||
#define LM_TIMER_GPTMCFG(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCFG_OFFSET)
|
||||
#define LM_TIMER_GPTMTAMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAMR_OFFSET)
|
||||
#define LM_TIMER_GPTMCTL(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCTL_OFFSET)
|
||||
#define LM_TIMER_GPTMIMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMIMR_OFFSET)
|
||||
#define LM_TIMER_GPTMRIS(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMRIS_OFFSET)
|
||||
#define LM_TIMER_GPTMICR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMICR_OFFSET)
|
||||
#define LM_TIMER_GPTMTAILR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAILR_OFFSET)
|
||||
#define LM_TIMER_GPTMTAR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAR_OFFSET)
|
||||
|
||||
/* SSI register bit defitiions ******************************************************/
|
||||
|
||||
@@ -122,4 +122,4 @@
|
||||
#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/
|
||||
#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H */
|
||||
|
||||
@@ -33,8 +33,8 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
|
||||
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_UART_H
|
||||
#define __ARCH_ARM_SRC_LM_CHIP_LM_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
@@ -48,117 +48,117 @@
|
||||
|
||||
/* UART register offsets ************************************************************/
|
||||
|
||||
#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */
|
||||
#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */
|
||||
#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */
|
||||
#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */
|
||||
#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */
|
||||
#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/
|
||||
#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */
|
||||
#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */
|
||||
#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */
|
||||
#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */
|
||||
#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */
|
||||
#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */
|
||||
#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */
|
||||
#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */
|
||||
#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
|
||||
#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
|
||||
#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
|
||||
#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
|
||||
#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
|
||||
#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
|
||||
#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
|
||||
#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
|
||||
#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */
|
||||
#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */
|
||||
#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */
|
||||
#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */
|
||||
#define LM_UART_DR_OFFSET 0x000 /* UART Data */
|
||||
#define LM_UART_RSR_OFFSET 0x004 /* UART Receive Status */
|
||||
#define LM_UART_ECR_OFFSET 0x004 /* UART Error Clear */
|
||||
#define LM_UART_FR_OFFSET 0x018 /* UART Flag */
|
||||
#define LM_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */
|
||||
#define LM_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/
|
||||
#define LM_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */
|
||||
#define LM_UART_LCRH_OFFSET 0x02c /* UART Line Control */
|
||||
#define LM_UART_CTL_OFFSET 0x030 /* UART Control */
|
||||
#define LM_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */
|
||||
#define LM_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */
|
||||
#define LM_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */
|
||||
#define LM_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */
|
||||
#define LM_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */
|
||||
#define LM_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
|
||||
#define LM_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
|
||||
#define LM_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
|
||||
#define LM_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
|
||||
#define LM_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
|
||||
#define LM_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
|
||||
#define LM_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
|
||||
#define LM_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
|
||||
#define LM_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */
|
||||
#define LM_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */
|
||||
#define LM_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */
|
||||
#define LM_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */
|
||||
|
||||
/* UART register addresses **********************************************************/
|
||||
|
||||
#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000)
|
||||
#define LM_UART_BASE(n) (LM_UART0_BASE + (n)*0x01000)
|
||||
|
||||
#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET)
|
||||
#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET)
|
||||
#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET)
|
||||
#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET)
|
||||
#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET)
|
||||
#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET)
|
||||
#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET)
|
||||
#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET)
|
||||
#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET)
|
||||
#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET)
|
||||
#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET)
|
||||
#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET)
|
||||
#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET)
|
||||
#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET)
|
||||
#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET)
|
||||
#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET)
|
||||
#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET)
|
||||
#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET)
|
||||
#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET)
|
||||
#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET)
|
||||
#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET)
|
||||
#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET)
|
||||
#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET)
|
||||
#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET)
|
||||
#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET)
|
||||
#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET)
|
||||
#define LM_UART_DR(n) (LM_UART_BASE(n) + LM_UART_DR_OFFSET)
|
||||
#define LM_UART_RSR(n) (LM_UART_BASE(n) + LM_UART_RSR_OFFSET)
|
||||
#define LM_UART_ECR(n) (LM_UART_BASE(n) + LM_UART_ECR_OFFSET)
|
||||
#define LM_UART_FR(n) (LM_UART_BASE(n) + LM_UART_FR_OFFSET)
|
||||
#define LM_UART_ILPR(n) (LM_UART_BASE(n) + LM_UART_ILPR_OFFSET)
|
||||
#define LM_UART_IBRD(n) (LM_UART_BASE(n) + LM_UART_IBRD_OFFSET)
|
||||
#define LM_UART_FBRD(n) (LM_UART_BASE(n) + LM_UART_FBRD_OFFSET)
|
||||
#define LM_UART_LCRH(n) (LM_UART_BASE(n) + LM_UART_LCRH_OFFSET)
|
||||
#define LM_UART_CTL(n) (LM_UART_BASE(n) + LM_UART_CTL_OFFSET)
|
||||
#define LM_UART_IFLS(n) (LM_UART_BASE(n) + LM_UART_IFLS_OFFSET)
|
||||
#define LM_UART_IM(n) (LM_UART_BASE(n) + LM_UART_IM_OFFSET)
|
||||
#define LM_UART_RIS(n) (LM_UART_BASE(n) + LM_UART_RIS_OFFSET)
|
||||
#define LM_UART_MIS(n) (LM_UART_BASE(n) + LM_UART_MIS_OFFSET)
|
||||
#define LM_UART_ICR(n) (LM_UART_BASE(n) + LM_UART_ICR_OFFSET)
|
||||
#define LM_UART_PERIPHID4(n) (LM_UART_BASE(n) + LM_UART_PERIPHID4_OFFSET)
|
||||
#define LM_UART_PERIPHID5(n) (LM_UART_BASE(n) + LM_UART_PERIPHID5_OFFSET)
|
||||
#define LM_UART_PERIPHID6(n) (LM_UART_BASE(n) + LM_UART_PERIPHID6_OFFSET)
|
||||
#define LM_UART_PERIPHID7(n) (LM_UART_BASE(n) + LM_UART_PERIPHID7_OFFSET)
|
||||
#define LM_UART_PERIPHID0(n) (LM_UART_BASE(n) + LM_UART_PERIPHID0_OFFSET)
|
||||
#define LM_UART_PERIPHID1(n) (LM_UART_BASE(n) + LM_UART_PERIPHID1_OFFSET)
|
||||
#define LM_UART_PERIPHID2(n) (LM_UART_BASE(n) + LM_UART_PERIPHID2_OFFSET)
|
||||
#define LM_UART_PERIPHID3(n) (LM_UART_BASE(n) + LM_UART_PERIPHID3_OFFSET)
|
||||
#define LM_UART_PCELLID0(n) (LM_UART_BASE(n) + LM_UART_PCELLID0_OFFSET)
|
||||
#define LM_UART_PCELLID1(n) (LM_UART_BASE(n) + LM_UART_PCELLID1_OFFSET)
|
||||
#define LM_UART_PCELLID2(n) (LM_UART_BASE(n) + LM_UART_PCELLID2_OFFSET)
|
||||
#define LM_UART_PCELLID3(n) (LM_UART_BASE(n) + LM_UART_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET)
|
||||
#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET)
|
||||
#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET)
|
||||
#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET)
|
||||
#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET)
|
||||
#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET)
|
||||
#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET)
|
||||
#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET)
|
||||
#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET)
|
||||
#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET)
|
||||
#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET)
|
||||
#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET)
|
||||
#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET)
|
||||
#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET)
|
||||
#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET)
|
||||
#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET)
|
||||
#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET)
|
||||
#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET)
|
||||
#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET)
|
||||
#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET)
|
||||
#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET)
|
||||
#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET)
|
||||
#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET)
|
||||
#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET)
|
||||
#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET)
|
||||
#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET)
|
||||
#define LM_UART0_DR (LM_UART0_BASE + LM_UART_TDR_OFFSET)
|
||||
#define LM_UART0_RSR (LM_UART0_BASE + LM_UART_RSR_OFFSET)
|
||||
#define LM_UART0_ECR (LM_UART0_BASE + LM_UART_ECR_OFFSET)
|
||||
#define LM_UART0_FR (LM_UART0_BASE + LM_UART_FR_OFFSET)
|
||||
#define LM_UART0_ILPR (LM_UART0_BASE + LM_UART_ILPR_OFFSET)
|
||||
#define LM_UART0_IBRD (LM_UART0_BASE + LM_UART_IBRD_OFFSET)
|
||||
#define LM_UART0_FBRD (LM_UART0_BASE + LM_UART_FBRD_OFFSET)
|
||||
#define LM_UART0_LCRH (LM_UART0_BASE + LM_UART_LCRH_OFFSET)
|
||||
#define LM_UART0_CTL (LM_UART0_BASE + LM_UART_CTL_OFFSET)
|
||||
#define LM_UART0_IFLS (LM_UART0_BASE + LM_UART_IFLS_OFFSET)
|
||||
#define LM_UART0_IM (LM_UART0_BASE + LM_UART_IM_OFFSET)
|
||||
#define LM_UART0_RIS (LM_UART0_BASE + LM_UART_RIS_OFFSET)
|
||||
#define LM_UART0_MIS (LM_UART0_BASE + LM_UART_MIS_OFFSET)
|
||||
#define LM_UART0_ICR (LM_UART0_BASE + LM_UART_ICR_OFFSET)
|
||||
#define LM_UART0_PERIPHID4 (LM_UART0_BASE + LM_UART_PERIPHID4_OFFSET)
|
||||
#define LM_UART0_PERIPHID5 (LM_UART0_BASE + LM_UART_PERIPHID5_OFFSET)
|
||||
#define LM_UART0_PERIPHID6 (LM_UART0_BASE + LM_UART_PERIPHID6_OFFSET)
|
||||
#define LM_UART0_PERIPHID7 (LM_UART0_BASE + LM_UART_PERIPHID7_OFFSET)
|
||||
#define LM_UART0_PERIPHID0 (LM_UART0_BASE + LM_UART_PERIPHID0_OFFSET)
|
||||
#define LM_UART0_PERIPHID1 (LM_UART0_BASE + LM_UART_PERIPHID1_OFFSET)
|
||||
#define LM_UART0_PERIPHID2 (LM_UART0_BASE + LM_UART_PERIPHID2_OFFSET)
|
||||
#define LM_UART0_PERIPHID3 (LM_UART0_BASE + LM_UART_PERIPHID3_OFFSET)
|
||||
#define LM_UART0_PCELLID0 (LM_UART0_BASE + LM_UART_PCELLID0_OFFSET)
|
||||
#define LM_UART0_PCELLID1 (LM_UART0_BASE + LM_UART_PCELLID1_OFFSET)
|
||||
#define LM_UART0_PCELLID2 (LM_UART0_BASE + LM_UART_PCELLID2_OFFSET)
|
||||
#define LM_UART0_PCELLID3 (LM_UART0_BASE + LM_UART_PCELLID3_OFFSET)
|
||||
|
||||
#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET)
|
||||
#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET)
|
||||
#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET)
|
||||
#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET)
|
||||
#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET)
|
||||
#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET)
|
||||
#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET)
|
||||
#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET)
|
||||
#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET)
|
||||
#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET)
|
||||
#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET)
|
||||
#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET)
|
||||
#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET)
|
||||
#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET)
|
||||
#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET)
|
||||
#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET)
|
||||
#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET)
|
||||
#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET)
|
||||
#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET)
|
||||
#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET)
|
||||
#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET)
|
||||
#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET)
|
||||
#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET)
|
||||
#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET)
|
||||
#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET)
|
||||
#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET)
|
||||
#define LM_UART1_DR (LM_UART1_BASE + LM_UART_DR_OFFSET)
|
||||
#define LM_UART1_RSR (LM_UART1_BASE + LM_UART_RSR_OFFSET)
|
||||
#define LM_UART1_ECR (LM_UART1_BASE + LM_UART_ECR_OFFSET)
|
||||
#define LM_UART1_FR (LM_UART1_BASE + LM_UART_FR_OFFSET)
|
||||
#define LM_UART1_ILPR (LM_UART1_BASE + LM_UART_ILPR_OFFSET)
|
||||
#define LM_UART1_IBRD (LM_UART1_BASE + LM_UART_IBRD_OFFSET)
|
||||
#define LM_UART1_FBRD (LM_UART1_BASE + LM_UART_FBRD_OFFSET)
|
||||
#define LM_UART1_LCRH (LM_UART1_BASE + LM_UART_LCRH_OFFSET)
|
||||
#define LM_UART1_CTL (LM_UART1_BASE + LM_UART_CTL_OFFSET)
|
||||
#define LM_UART1_IFLS (LM_UART1_BASE + LM_UART_IFLS_OFFSET)
|
||||
#define LM_UART1_IM (LM_UART1_BASE + LM_UART_IM_OFFSET)
|
||||
#define LM_UART1_RIS (LM_UART1_BASE + LM_UART_RIS_OFFSET)
|
||||
#define LM_UART1_MIS (LM_UART1_BASE + LM_UART_MIS_OFFSET)
|
||||
#define LM_UART1_ICR (LM_UART1_BASE + LM_UART_ICR_OFFSET)
|
||||
#define LM_UART1_PERIPHID4 (LM_UART1_BASE + LM_UART_PERIPHID4_OFFSET)
|
||||
#define LM_UART1_PERIPHID5 (LM_UART1_BASE + LM_UART_PERIPHID5_OFFSET)
|
||||
#define LM_UART1_PERIPHID6 (LM_UART1_BASE + LM_UART_PERIPHID6_OFFSET)
|
||||
#define LM_UART1_PERIPHID7 (LM_UART1_BASE + LM_UART_PERIPHID7_OFFSET)
|
||||
#define LM_UART1_PERIPHID0 (LM_UART1_BASE + LM_UART_PERIPHID0_OFFSET)
|
||||
#define LM_UART1_PERIPHID1 (LM_UART1_BASE + LM_UART_PERIPHID1_OFFSET)
|
||||
#define LM_UART1_PERIPHID2 (LM_UART1_BASE + LM_UART_PERIPHID2_OFFSET)
|
||||
#define LM_UART1_PERIPHID3 (LM_UART1_BASE + LM_UART_PERIPHID3_OFFSET)
|
||||
#define LM_UART1_PCELLID0 (LM_UART1_BASE + LM_UART_PCELLID0_OFFSET)
|
||||
#define LM_UART1_PCELLID1 (LM_UART1_BASE + LM_UART_PCELLID1_OFFSET)
|
||||
#define LM_UART1_PCELLID2 (LM_UART1_BASE + LM_UART_PCELLID2_OFFSET)
|
||||
#define LM_UART1_PCELLID3 (LM_UART1_BASE + LM_UART_PCELLID3_OFFSET)
|
||||
|
||||
/* UART register bit settings *******************************************************/
|
||||
|
||||
@@ -275,62 +275,62 @@
|
||||
|
||||
/* UART Interrupt Clear (ICR), offset 0x044 */
|
||||
|
||||
#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */
|
||||
#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */
|
||||
#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */
|
||||
#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */
|
||||
#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */
|
||||
#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */
|
||||
#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
|
||||
#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */
|
||||
#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */
|
||||
#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */
|
||||
#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */
|
||||
#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */
|
||||
#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */
|
||||
#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
|
||||
*/
|
||||
|
||||
/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */
|
||||
|
||||
#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */
|
||||
#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */
|
||||
|
||||
/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */
|
||||
|
||||
#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */
|
||||
#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */
|
||||
|
||||
/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */
|
||||
|
||||
#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */
|
||||
#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */
|
||||
|
||||
/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */
|
||||
|
||||
#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */
|
||||
#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */
|
||||
|
||||
/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */
|
||||
|
||||
#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */
|
||||
#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */
|
||||
|
||||
/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */
|
||||
|
||||
#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */
|
||||
#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */
|
||||
|
||||
/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */
|
||||
|
||||
#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */
|
||||
#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */
|
||||
|
||||
/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */
|
||||
|
||||
#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */
|
||||
#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */
|
||||
|
||||
/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */
|
||||
|
||||
#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */
|
||||
#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */
|
||||
|
||||
/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */
|
||||
|
||||
#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */
|
||||
#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */
|
||||
|
||||
/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */
|
||||
|
||||
#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */
|
||||
#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */
|
||||
|
||||
/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */
|
||||
|
||||
#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */
|
||||
#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
@@ -344,4 +344,4 @@
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */
|
||||
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_UART_H */
|
||||
|
||||
@@ -60,19 +60,19 @@
|
||||
|
||||
/* NOTE: this is duplicated in lm_gpio.c */
|
||||
|
||||
#ifdef LM3S_GPIOH_BASE
|
||||
#ifdef LM_GPIOH_BASE
|
||||
static const uint32_t g_gpiobase[8] =
|
||||
{
|
||||
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
|
||||
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE,
|
||||
LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
|
||||
LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, LM_GPIOH_BASE,
|
||||
};
|
||||
|
||||
static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
|
||||
#else
|
||||
static const uint32_t g_gpiobase[8] =
|
||||
{
|
||||
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
|
||||
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0,
|
||||
LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
|
||||
LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, 0,
|
||||
};
|
||||
|
||||
static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
|
||||
@@ -138,7 +138,7 @@ int lm_dumpgpio(uint32_t pinset, const char *msg)
|
||||
/* The following requires exclusive access to the GPIO registers */
|
||||
|
||||
flags = irqsave();
|
||||
rcgc2 = getreg32(LM3S_SYSCON_RCGC2);
|
||||
rcgc2 = getreg32(LM_SYSCON_RCGC2);
|
||||
enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
|
||||
|
||||
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
|
||||
@@ -151,16 +151,16 @@ int lm_dumpgpio(uint32_t pinset, const char *msg)
|
||||
if (enabled)
|
||||
{
|
||||
lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
|
||||
getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET),
|
||||
getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc));
|
||||
getreg32(base + LM_GPIO_AFSEL_OFFSET), getreg32(base + LM_GPIO_DEN_OFFSET),
|
||||
getreg32(base + LM_GPIO_DIR_OFFSET), getreg32(base + LM_GPIO_DATA_OFFSET + 0x3fc));
|
||||
lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n",
|
||||
getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET),
|
||||
getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET));
|
||||
getreg32(base + LM_GPIO_IEV_OFFSET), getreg32(base + LM_GPIO_IM_OFFSET),
|
||||
getreg32(base + LM_GPIO_RIS_OFFSET), getreg32(base + LM_GPIO_MIS_OFFSET));
|
||||
lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
|
||||
getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET),
|
||||
getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET),
|
||||
getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET),
|
||||
getreg32(base + LM3S_GPIO_SLR_OFFSET));
|
||||
getreg32(base + LM_GPIO_DR2R_OFFSET), getreg32(base + LM_GPIO_DR4R_OFFSET),
|
||||
getreg32(base + LM_GPIO_DR8R_OFFSET), getreg32(base + LM_GPIO_ODR_OFFSET),
|
||||
getreg32(base + LM_GPIO_PUR_OFFSET), getreg32(base + LM_GPIO_PDR_OFFSET),
|
||||
getreg32(base + LM_GPIO_SLR_OFFSET));
|
||||
}
|
||||
irqrestore(flags);
|
||||
return OK;
|
||||
|
||||
+126
-126
@@ -69,68 +69,68 @@
|
||||
/* Half duplex can be forced if CONFIG_LM_ETHHDUPLEX is defined. */
|
||||
|
||||
#ifdef CONFIG_LM_ETHHDUPLEX
|
||||
# define LM3S_DUPLEX_SETBITS 0
|
||||
# define LM3S_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
|
||||
# define LM_DUPLEX_SETBITS 0
|
||||
# define LM_DUPLEX_CLRBITS MAC_TCTL_DUPLEX
|
||||
#else
|
||||
# define LM3S_DUPLEX_SETBITS MAC_TCTL_DUPLEX
|
||||
# define LM3S_DUPLEX_CLRBITS 0
|
||||
# define LM_DUPLEX_SETBITS MAC_TCTL_DUPLEX
|
||||
# define LM_DUPLEX_CLRBITS 0
|
||||
#endif
|
||||
|
||||
/* Auto CRC generation can be suppressed if CONFIG_LM_ETHNOAUTOCRC is definde */
|
||||
|
||||
#ifdef CONFIG_LM_ETHNOAUTOCRC
|
||||
# define LM3S_CRC_SETBITS 0
|
||||
# define LM3S_CRC_CLRBITS MAC_TCTL_CRC
|
||||
# define LM_CRC_SETBITS 0
|
||||
# define LM_CRC_CLRBITS MAC_TCTL_CRC
|
||||
#else
|
||||
# define LM3S_CRC_SETBITS MAC_TCTL_CRC
|
||||
# define LM3S_CRC_CLRBITS 0
|
||||
# define LM_CRC_SETBITS MAC_TCTL_CRC
|
||||
# define LM_CRC_CLRBITS 0
|
||||
#endif
|
||||
|
||||
/* Tx padding can be suppressed if CONFIG_LM_ETHNOPAD is defined */
|
||||
|
||||
#ifdef CONFIG_LM_ETHNOPAD
|
||||
# define LM3S_PADEN_SETBITS 0
|
||||
# define LM3S_PADEN_CLRBITS MAC_TCTL_PADEN
|
||||
# define LM_PADEN_SETBITS 0
|
||||
# define LM_PADEN_CLRBITS MAC_TCTL_PADEN
|
||||
#else
|
||||
# define LM3S_PADEN_SETBITS MAC_TCTL_PADEN
|
||||
# define LM3S_PADEN_CLRBITS 0
|
||||
# define LM_PADEN_SETBITS MAC_TCTL_PADEN
|
||||
# define LM_PADEN_CLRBITS 0
|
||||
#endif
|
||||
|
||||
#define LM3S_TCTCL_SETBITS (LM3S_DUPLEX_SETBITS|LM3S_CRC_SETBITS|LM3S_PADEN_SETBITS)
|
||||
#define LM3S_TCTCL_CLRBITS (LM3S_DUPLEX_CLRBITS|LM3S_CRC_CLRBITS|LM3S_PADEN_CLRBITS)
|
||||
#define LM_TCTCL_SETBITS (LM_DUPLEX_SETBITS|LM_CRC_SETBITS|LM_PADEN_SETBITS)
|
||||
#define LM_TCTCL_CLRBITS (LM_DUPLEX_CLRBITS|LM_CRC_CLRBITS|LM_PADEN_CLRBITS)
|
||||
|
||||
/* Multicast frames can be enabled by defining CONFIG_LM_MULTICAST */
|
||||
|
||||
#ifdef CONFIG_LM_MULTICAST
|
||||
# define LM3S_AMUL_SETBITS MAC_RCTL_AMUL
|
||||
# define LM3S_AMUL_CLRBITS 0
|
||||
# define LM_AMUL_SETBITS MAC_RCTL_AMUL
|
||||
# define LM_AMUL_CLRBITS 0
|
||||
#else
|
||||
# define LM3S_AMUL_SETBITS 0
|
||||
# define LM3S_AMUL_CLRBITS MAC_RCTL_AMUL
|
||||
# define LM_AMUL_SETBITS 0
|
||||
# define LM_AMUL_CLRBITS MAC_RCTL_AMUL
|
||||
#endif
|
||||
|
||||
/* Promiscuous mode can be enabled by defining CONFIG_LM_PROMISCUOUS */
|
||||
|
||||
#ifdef CONFIG_LM_PROMISCUOUS
|
||||
# define LM3S_PRMS_SETBITS MAC_RCTL_PRMS
|
||||
# define LM3S_PRMS_CLRBITS 0
|
||||
# define LM_PRMS_SETBITS MAC_RCTL_PRMS
|
||||
# define LM_PRMS_CLRBITS 0
|
||||
#else
|
||||
# define LM3S_PRMS_SETBITS 0
|
||||
# define LM3S_PRMS_CLRBITS MAC_RCTL_PRMS
|
||||
# define LM_PRMS_SETBITS 0
|
||||
# define LM_PRMS_CLRBITS MAC_RCTL_PRMS
|
||||
#endif
|
||||
|
||||
/* Bad CRC rejection can be enabled by define CONFIG_LM_BADCRC */
|
||||
|
||||
#ifdef CONFIG_LM_BADCRC
|
||||
# define LM3S_BADCRC_SETBITS MAC_RCTL_BADCRC
|
||||
# define LM3S_BADCRC_CLRBITS 0
|
||||
# define LM_BADCRC_SETBITS MAC_RCTL_BADCRC
|
||||
# define LM_BADCRC_CLRBITS 0
|
||||
#else
|
||||
# define LM3S_BADCRC_SETBITS 0
|
||||
# define LM3S_BADCRC_CLRBITS MAC_RCTL_BADCRC
|
||||
# define LM_BADCRC_SETBITS 0
|
||||
# define LM_BADCRC_CLRBITS MAC_RCTL_BADCRC
|
||||
#endif
|
||||
|
||||
#define LM3S_RCTCL_SETBITS (LM3S_AMUL_SETBITS|LM3S_PRMS_SETBITS|LM3S_BADCRC_SETBITS)
|
||||
#define LM3S_RCTCL_CLRBITS (LM3S_AMUL_CLRBITS|LM3S_PRMS_CLRBITS|LM3S_BADCRC_CLRBITS)
|
||||
#define LM_RCTCL_SETBITS (LM_AMUL_SETBITS|LM_PRMS_SETBITS|LM_BADCRC_SETBITS)
|
||||
#define LM_RCTCL_CLRBITS (LM_AMUL_CLRBITS|LM_PRMS_CLRBITS|LM_BADCRC_CLRBITS)
|
||||
|
||||
/* CONFIG_LM_DUMPPACKET will dump the contents of each packet to the console. */
|
||||
|
||||
@@ -142,12 +142,12 @@
|
||||
|
||||
/* TX poll deley = 1 seconds. CLK_TCK is the number of clock ticks per second */
|
||||
|
||||
#define LM3S_WDDELAY (1*CLK_TCK)
|
||||
#define LM3S_POLLHSEC (1*2)
|
||||
#define LM_WDDELAY (1*CLK_TCK)
|
||||
#define LM_POLLHSEC (1*2)
|
||||
|
||||
/* TX timeout = 1 minute */
|
||||
|
||||
#define LM3S_TXTIMEOUT (60*CLK_TCK)
|
||||
#define LM_TXTIMEOUT (60*CLK_TCK)
|
||||
|
||||
/* This is a helper pointer for accessing the contents of the Ethernet header */
|
||||
|
||||
@@ -192,7 +192,7 @@ struct lm_driver_s
|
||||
* multiple Ethernet controllers.
|
||||
*/
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
uint32_t ld_base; /* Ethernet controller base address */
|
||||
int ld_irq; /* Ethernet controller IRQ */
|
||||
#endif
|
||||
@@ -214,7 +214,7 @@ struct lm_driver_s
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static struct lm_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS];
|
||||
static struct lm_driver_s g_lm3sdev[LM_NETHCONTROLLERS];
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
@@ -222,7 +222,7 @@ static struct lm_driver_s g_lm3sdev[LM3S_NETHCONTROLLERS];
|
||||
|
||||
/* Miscellaneous low level helpers */
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
static uint32_t lm_ethin(struct lm_driver_s *priv, int offset);
|
||||
static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value);
|
||||
#else
|
||||
@@ -280,7 +280,7 @@ static int lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac);
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
static uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
|
||||
{
|
||||
return getreg32(priv->ld_base + offset);
|
||||
@@ -288,7 +288,7 @@ static uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
|
||||
#else
|
||||
static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
|
||||
{
|
||||
return getreg32(LM3S_ETHCON_BASE + offset);
|
||||
return getreg32(LM_ETHCON_BASE + offset);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -308,7 +308,7 @@ static inline uint32_t lm_ethin(struct lm_driver_s *priv, int offset)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value)
|
||||
{
|
||||
putreg32(value, priv->ld_base + offset);
|
||||
@@ -316,7 +316,7 @@ static void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value)
|
||||
#else
|
||||
static inline void lm_ethout(struct lm_driver_s *priv, int offset, uint32_t value)
|
||||
{
|
||||
putreg32(value, LM3S_ETHCON_BASE + offset);
|
||||
putreg32(value, LM_ETHCON_BASE + offset);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -341,23 +341,23 @@ static void lm_ethreset(struct lm_driver_s *priv)
|
||||
irqstate_t flags;
|
||||
uint32_t regval;
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
# error "If multiple interfaces are supported, this function would have to be redesigned"
|
||||
#endif
|
||||
|
||||
/* Make sure that clocking is enabled for the Ethernet (and PHY) peripherals */
|
||||
|
||||
flags = irqsave();
|
||||
regval = getreg32(LM3S_SYSCON_RCGC2);
|
||||
regval = getreg32(LM_SYSCON_RCGC2);
|
||||
regval |= (SYSCON_RCGC2_EMAC0|SYSCON_RCGC2_EPHY0);
|
||||
putreg32(regval, LM3S_SYSCON_RCGC2);
|
||||
putreg32(regval, LM_SYSCON_RCGC2);
|
||||
nllvdbg("RCGC2: %08x\n", regval);
|
||||
|
||||
/* Put the Ethernet controller into the reset state */
|
||||
|
||||
regval = getreg32(LM3S_SYSCON_SRCR2);
|
||||
regval = getreg32(LM_SYSCON_SRCR2);
|
||||
regval |= (SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
|
||||
putreg32(regval, LM3S_SYSCON_SRCR2);
|
||||
putreg32(regval, LM_SYSCON_SRCR2);
|
||||
|
||||
/* Wait just a bit. This is a much longer delay than necessary */
|
||||
|
||||
@@ -366,7 +366,7 @@ static void lm_ethreset(struct lm_driver_s *priv)
|
||||
/* Then take the Ethernet controller out of the reset state */
|
||||
|
||||
regval &= ~(SYSCON_SRCR2_EMAC0|SYSCON_SRCR2_EPHY0);
|
||||
putreg32(regval, LM3S_SYSCON_SRCR2);
|
||||
putreg32(regval, LM_SYSCON_SRCR2);
|
||||
nllvdbg("SRCR2: %08x\n", regval);
|
||||
|
||||
/* Wait just a bit, again. If we touch the ethernet too soon, we may busfault. */
|
||||
@@ -384,14 +384,14 @@ static void lm_ethreset(struct lm_driver_s *priv)
|
||||
|
||||
/* Disable all Ethernet controller interrupts */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_IM_OFFSET);
|
||||
regval &= ~MAC_IM_ALLINTS;
|
||||
lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_IM_OFFSET, regval);
|
||||
|
||||
/* Clear any pending interrupts (shouldn't be any) */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET);
|
||||
lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
|
||||
regval = lm_ethin(priv, LM_MAC_RIS_OFFSET);
|
||||
lm_ethout(priv, LM_MAC_IACK_OFFSET, regval);
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
@@ -416,22 +416,22 @@ static void lm_phywrite(struct lm_driver_s *priv, int regaddr, uint16_t value)
|
||||
{
|
||||
/* Wait for any MII transactions in progress to complete */
|
||||
|
||||
while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
|
||||
while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
|
||||
|
||||
/* Set up the data to be written */
|
||||
|
||||
DEBUGASSERT(value < MAC_MTXD_MASK);
|
||||
lm_ethout(priv, LM3S_MAC_MTXD_OFFSET, value);
|
||||
lm_ethout(priv, LM_MAC_MTXD_OFFSET, value);
|
||||
|
||||
/* Set up the PHY register address and start the write operation */
|
||||
|
||||
regaddr <<= MAC_MCTL_REGADR_SHIFT;
|
||||
DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
|
||||
lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
|
||||
lm_ethout(priv, LM_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_WRITE | MAC_MCTL_START);
|
||||
|
||||
/* Wait for the write transaction to complete */
|
||||
|
||||
while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
|
||||
while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -455,21 +455,21 @@ static uint16_t lm_phyread(struct lm_driver_s *priv, int regaddr)
|
||||
{
|
||||
/* Wait for any MII transactions in progress to complete */
|
||||
|
||||
while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
|
||||
while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
|
||||
|
||||
/* Set up the PHY register address and start the read operation */
|
||||
|
||||
regaddr <<= MAC_MCTL_REGADR_SHIFT;
|
||||
DEBUGASSERT((regaddr & MAC_MTXD_MASK) == regaddr);
|
||||
lm_ethout(priv, LM3S_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
|
||||
lm_ethout(priv, LM_MAC_MCTL_OFFSET, regaddr | MAC_MCTL_START);
|
||||
|
||||
/* Wait for the write transaction to complete */
|
||||
|
||||
while ((lm_ethin(priv, LM3S_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
|
||||
while ((lm_ethin(priv, LM_MAC_MCTL_OFFSET) & MAC_MCTL_START) != 0);
|
||||
|
||||
/* Read and return the PHY data */
|
||||
|
||||
return (uint16_t)(lm_ethin(priv, LM3S_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
|
||||
return (uint16_t)(lm_ethin(priv, LM_MAC_MRXD_OFFSET) & MAC_MTRD_MASK);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -499,7 +499,7 @@ static int lm_transmit(struct lm_driver_s *priv)
|
||||
/* Verify that the hardware is ready to send another packet */
|
||||
|
||||
flags = irqsave();
|
||||
if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
if ((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
{
|
||||
/* Increment statistics */
|
||||
|
||||
@@ -520,7 +520,7 @@ static int lm_transmit(struct lm_driver_s *priv)
|
||||
regval = (uint32_t)(pktlen - 14);
|
||||
regval |= ((uint32_t)(*dbuf++) << 16);
|
||||
regval |= ((uint32_t)(*dbuf++) << 24);
|
||||
lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_DATA_OFFSET, regval);
|
||||
|
||||
/* Write all of the whole, 32-bit values in the middle of the packet */
|
||||
|
||||
@@ -530,7 +530,7 @@ static int lm_transmit(struct lm_driver_s *priv)
|
||||
* buffer may be un-aligned.
|
||||
*/
|
||||
|
||||
lm_ethout(priv, LM3S_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
|
||||
lm_ethout(priv, LM_MAC_DATA_OFFSET, *(uint32_t*)dbuf);
|
||||
}
|
||||
|
||||
/* Write the last, partial word in the FIFO */
|
||||
@@ -554,16 +554,16 @@ static int lm_transmit(struct lm_driver_s *priv)
|
||||
regval |= (uint32_t)dbuf[0];
|
||||
break;
|
||||
}
|
||||
lm_ethout(priv, LM3S_MAC_DATA_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_DATA_OFFSET, regval);
|
||||
}
|
||||
|
||||
/* Activate the transmitter */
|
||||
|
||||
lm_ethout(priv, LM3S_MAC_TR_OFFSET, MAC_TR_NEWTX);
|
||||
lm_ethout(priv, LM_MAC_TR_OFFSET, MAC_TR_NEWTX);
|
||||
|
||||
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
|
||||
|
||||
(void)wd_start(priv->ld_txtimeout, LM3S_TXTIMEOUT, lm_txtimeout, 1, (uint32_t)priv);
|
||||
(void)wd_start(priv->ld_txtimeout, LM_TXTIMEOUT, lm_txtimeout, 1, (uint32_t)priv);
|
||||
ret = OK;
|
||||
}
|
||||
|
||||
@@ -608,7 +608,7 @@ static int lm_uiptxpoll(struct uip_driver_s *dev)
|
||||
* packet was successfully handled.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
DEBUGASSERT((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
uip_arp_out(&priv->ld_dev);
|
||||
ret = lm_transmit(priv);
|
||||
}
|
||||
@@ -645,7 +645,7 @@ static void lm_receive(struct lm_driver_s *priv)
|
||||
|
||||
/* Loop while there are incoming packets to be processed */
|
||||
|
||||
while ((lm_ethin(priv, LM3S_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
|
||||
while ((lm_ethin(priv, LM_MAC_NP_OFFSET) & MAC_NP_MASK) != 0)
|
||||
{
|
||||
/* Update statistics */
|
||||
|
||||
@@ -665,7 +665,7 @@ static void lm_receive(struct lm_driver_s *priv)
|
||||
* includes the len/type field (size 2) and the FCS (size 4).
|
||||
*/
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_DATA_OFFSET);
|
||||
pktlen = (int)(regval & 0x0000ffff);
|
||||
nllvdbg("Receiving packet, pktlen: %d\n", pktlen);
|
||||
|
||||
@@ -694,7 +694,7 @@ static void lm_receive(struct lm_driver_s *priv)
|
||||
|
||||
while (wordlen--)
|
||||
{
|
||||
(void)lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
|
||||
(void)lm_ethin(priv, LM_MAC_DATA_OFFSET);
|
||||
}
|
||||
|
||||
/* Check for another packet */
|
||||
@@ -718,7 +718,7 @@ static void lm_receive(struct lm_driver_s *priv)
|
||||
* buffer may be un-aligned.
|
||||
*/
|
||||
|
||||
*(uint32_t*)dbuf = lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
|
||||
*(uint32_t*)dbuf = lm_ethin(priv, LM_MAC_DATA_OFFSET);
|
||||
}
|
||||
|
||||
/* Handle the last, partial word in the FIFO (0-3 bytes) and discard
|
||||
@@ -731,7 +731,7 @@ static void lm_receive(struct lm_driver_s *priv)
|
||||
* bytes of the FCS into the user buffer.
|
||||
*/
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_DATA_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_DATA_OFFSET);
|
||||
switch (bytesleft)
|
||||
{
|
||||
default:
|
||||
@@ -834,7 +834,7 @@ static void lm_txdone(struct lm_driver_s *priv)
|
||||
* at this point.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
DEBUGASSERT((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
|
||||
/* Then poll uIP for new XMIT data */
|
||||
|
||||
@@ -863,7 +863,7 @@ static int lm_interrupt(int irq, FAR void *context)
|
||||
register struct lm_driver_s *priv;
|
||||
uint32_t ris;
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
# error "A mechanism to associate and interface with an IRQ is needed"
|
||||
#else
|
||||
priv = &g_lm3sdev[0];
|
||||
@@ -871,11 +871,11 @@ static int lm_interrupt(int irq, FAR void *context)
|
||||
|
||||
/* Read the raw interrupt status register */
|
||||
|
||||
ris = lm_ethin(priv, LM3S_MAC_RIS_OFFSET);
|
||||
ris = lm_ethin(priv, LM_MAC_RIS_OFFSET);
|
||||
|
||||
/* Clear all pending interrupts */
|
||||
|
||||
lm_ethout(priv, LM3S_MAC_IACK_OFFSET, ris);
|
||||
lm_ethout(priv, LM_MAC_IACK_OFFSET, ris);
|
||||
|
||||
/* Check for errors */
|
||||
|
||||
@@ -898,7 +898,7 @@ static int lm_interrupt(int irq, FAR void *context)
|
||||
|
||||
/* Handle (unmasked) interrupts according to status bit settings */
|
||||
|
||||
ris &= lm_ethin(priv, LM3S_MAC_IM_OFFSET);
|
||||
ris &= lm_ethin(priv, LM_MAC_IM_OFFSET);
|
||||
|
||||
/* Is this an Rx interrupt (meaning that a packet has been received)? */
|
||||
|
||||
@@ -994,15 +994,15 @@ static void lm_polltimer(int argc, uint32_t arg, ...)
|
||||
* inaccuracies.
|
||||
*/
|
||||
|
||||
if ((lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
if ((lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
{
|
||||
/* If so, update TCP timing states and poll uIP for new XMIT data */
|
||||
|
||||
(void)uip_timer(&priv->ld_dev, lm_uiptxpoll, LM3S_POLLHSEC);
|
||||
(void)uip_timer(&priv->ld_dev, lm_uiptxpoll, LM_POLLHSEC);
|
||||
|
||||
/* Setup the watchdog poll timer again */
|
||||
|
||||
(void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, arg);
|
||||
(void)wd_start(priv->ld_txpoll, LM_WDDELAY, lm_polltimer, 1, arg);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1051,7 +1051,7 @@ static int lm_ifup(struct uip_driver_s *dev)
|
||||
*/
|
||||
|
||||
div = SYSCLK_FREQUENCY / 2 / LM32S_MAX_MDCCLK;
|
||||
lm_ethout(priv, LM3S_MAC_MDV_OFFSET, div);
|
||||
lm_ethout(priv, LM_MAC_MDV_OFFSET, div);
|
||||
nllvdbg("MDV: %08x\n", div);
|
||||
|
||||
/* Then configure the Ethernet Controller for normal operation
|
||||
@@ -1060,32 +1060,32 @@ static int lm_ifup(struct uip_driver_s *dev)
|
||||
* TX Padding Enabled).
|
||||
*/
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET);
|
||||
regval &= ~LM3S_TCTCL_CLRBITS;
|
||||
regval |= LM3S_TCTCL_SETBITS;
|
||||
lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
|
||||
regval = lm_ethin(priv, LM_MAC_TCTL_OFFSET);
|
||||
regval &= ~LM_TCTCL_CLRBITS;
|
||||
regval |= LM_TCTCL_SETBITS;
|
||||
lm_ethout(priv, LM_MAC_TCTL_OFFSET, regval);
|
||||
nllvdbg("TCTL: %08x\n", regval);
|
||||
|
||||
/* Setup the receive control register (Disable multicast frames, disable
|
||||
* promiscuous mode, disable bad CRC rejection).
|
||||
*/
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
|
||||
regval &= ~LM3S_RCTCL_CLRBITS;
|
||||
regval |= LM3S_RCTCL_SETBITS;
|
||||
lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
|
||||
regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
|
||||
regval &= ~LM_RCTCL_CLRBITS;
|
||||
regval |= LM_RCTCL_SETBITS;
|
||||
lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
|
||||
nllvdbg("RCTL: %08x\n", regval);
|
||||
|
||||
/* Setup the time stamp configuration register */
|
||||
|
||||
#ifdef LM3S_ETHTS
|
||||
regval = lm_ethin(priv, LM3S_MAC_TS_OFFSET);
|
||||
#ifdef LM_ETHTS
|
||||
regval = lm_ethin(priv, LM_MAC_TS_OFFSET);
|
||||
#ifdef CONFIG_LM_TIMESTAMP
|
||||
regval |= MAC_TS_EN;
|
||||
#else
|
||||
regval &= ~(MAC_TS_EN);
|
||||
#endif
|
||||
lm_ethout(priv, LM3S_MAC_TS_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_TS_OFFSET, regval);
|
||||
nllvdbg("TS: %08x\n", regval);
|
||||
#endif
|
||||
|
||||
@@ -1105,41 +1105,41 @@ static int lm_ifup(struct uip_driver_s *dev)
|
||||
|
||||
/* Reset the receive FIFO */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
|
||||
regval |= MAC_RCTL_RSTFIFO;
|
||||
lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
|
||||
|
||||
/* Enable the Ethernet receiver */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
|
||||
regval |= MAC_RCTL_RXEN;
|
||||
lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
|
||||
|
||||
/* Enable the Ethernet transmitter */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_TCTL_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_TCTL_OFFSET);
|
||||
regval |= MAC_TCTL_TXEN;
|
||||
lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_TCTL_OFFSET, regval);
|
||||
|
||||
/* Reset the receive FIFO (again) */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
|
||||
regval |= MAC_RCTL_RSTFIFO;
|
||||
lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
|
||||
|
||||
/* Enable the Ethernet interrupt */
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
up_enable_irq(priv->irq);
|
||||
#else
|
||||
up_enable_irq(LM3S_IRQ_ETHCON);
|
||||
up_enable_irq(LM_IRQ_ETHCON);
|
||||
#endif
|
||||
|
||||
/* Enable the Ethernet RX packet receipt interrupt */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_IM_OFFSET);
|
||||
regval |= MAC_IM_RXINTM;
|
||||
lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_IM_OFFSET, regval);
|
||||
|
||||
/* Program the hardware with it's MAC address (for filtering) */
|
||||
|
||||
@@ -1147,15 +1147,15 @@ static int lm_ifup(struct uip_driver_s *dev)
|
||||
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[2] << 16 |
|
||||
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[1] << 8 |
|
||||
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[0];
|
||||
lm_ethout(priv, LM3S_MAC_IA0_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_IA0_OFFSET, regval);
|
||||
|
||||
regval = (uint32_t)priv->ld_dev.d_mac.ether_addr_octet[5] << 8 |
|
||||
(uint32_t)priv->ld_dev.d_mac.ether_addr_octet[4];
|
||||
lm_ethout(priv, LM3S_MAC_IA1_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_IA1_OFFSET, regval);
|
||||
|
||||
/* Set and activate a timer process */
|
||||
|
||||
(void)wd_start(priv->ld_txpoll, LM3S_WDDELAY, lm_polltimer, 1, (uint32_t)priv);
|
||||
(void)wd_start(priv->ld_txpoll, LM_WDDELAY, lm_polltimer, 1, (uint32_t)priv);
|
||||
|
||||
priv->ld_bifup = true;
|
||||
irqrestore(flags);
|
||||
@@ -1197,46 +1197,46 @@ static int lm_ifdown(struct uip_driver_s *dev)
|
||||
|
||||
/* Disable the Ethernet interrupt */
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
up_disable_irq(priv->irq);
|
||||
#else
|
||||
up_disable_irq(LM3S_IRQ_ETHCON);
|
||||
up_disable_irq(LM_IRQ_ETHCON);
|
||||
#endif
|
||||
|
||||
/* Disable all Ethernet controller interrupt sources */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_IM_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_IM_OFFSET);
|
||||
regval &= ~MAC_IM_ALLINTS;
|
||||
lm_ethout(priv, LM3S_MAC_IM_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_IM_OFFSET, regval);
|
||||
|
||||
/* Reset the receive FIFO */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
|
||||
regval |= MAC_RCTL_RSTFIFO;
|
||||
lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
|
||||
|
||||
/* Disable the Ethernet receiver */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
|
||||
regval &= ~MAC_RCTL_RXEN;
|
||||
lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
|
||||
|
||||
/* Disable the Ethernet transmitter */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
|
||||
regval &= ~MAC_TCTL_TXEN;
|
||||
lm_ethout(priv, LM3S_MAC_TCTL_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_TCTL_OFFSET, regval);
|
||||
|
||||
/* Reset the receive FIFO (again) */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RCTL_OFFSET);
|
||||
regval = lm_ethin(priv, LM_MAC_RCTL_OFFSET);
|
||||
regval |= MAC_RCTL_RSTFIFO;
|
||||
lm_ethout(priv, LM3S_MAC_RCTL_OFFSET, regval);
|
||||
lm_ethout(priv, LM_MAC_RCTL_OFFSET, regval);
|
||||
|
||||
/* Clear any pending interrupts */
|
||||
|
||||
regval = lm_ethin(priv, LM3S_MAC_RIS_OFFSET);
|
||||
lm_ethout(priv, LM3S_MAC_IACK_OFFSET, regval);
|
||||
regval = lm_ethin(priv, LM_MAC_RIS_OFFSET);
|
||||
lm_ethout(priv, LM_MAC_IACK_OFFSET, regval);
|
||||
|
||||
/* The interface is now DOWN */
|
||||
|
||||
@@ -1278,7 +1278,7 @@ static int lm_txavail(struct uip_driver_s *dev)
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
if (priv->ld_bifup && (lm_ethin(priv, LM3S_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
if (priv->ld_bifup && (lm_ethin(priv, LM_MAC_TR_OFFSET) & MAC_TR_NEWTX) == 0)
|
||||
{
|
||||
/* If the interface is up and we can use the Tx FIFO, then poll uIP
|
||||
* for new Tx data
|
||||
@@ -1371,7 +1371,7 @@ static int lm_rmmac(struct uip_driver_s *dev, FAR const uint8_t *mac)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
int lm_ethinitialize(int intf)
|
||||
#else
|
||||
static inline int lm_ethinitialize(int intf)
|
||||
@@ -1384,12 +1384,12 @@ static inline int lm_ethinitialize(int intf)
|
||||
|
||||
ndbg("Setting up eth%d\n", intf);
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
# error "This debug check only works with one interface"
|
||||
#else
|
||||
DEBUGASSERT((getreg32(LM3S_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
|
||||
DEBUGASSERT((getreg32(LM_SYSCON_DC4) & (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0)) == (SYSCON_DC4_EMAC0|SYSCON_DC4_EPHY0));
|
||||
#endif
|
||||
DEBUGASSERT((unsigned)intf < LM3S_NETHCONTROLLERS);
|
||||
DEBUGASSERT((unsigned)intf < LM_NETHCONTROLLERS);
|
||||
|
||||
/* Initialize the driver structure */
|
||||
|
||||
@@ -1405,7 +1405,7 @@ static inline int lm_ethinitialize(int intf)
|
||||
|
||||
/* Create a watchdog for timing polling for and timing of transmisstions */
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
# error "A mechanism to associate base address an IRQ with an interface is needed"
|
||||
priv->ld_base = ??; /* Ethernet controller base address */
|
||||
priv->ld_irq = ??; /* Ethernet controller IRQ number */
|
||||
@@ -1432,10 +1432,10 @@ static inline int lm_ethinitialize(int intf)
|
||||
|
||||
/* Attach the IRQ to the driver */
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
ret = irq_attach(priv->irq, lm_interrupt);
|
||||
#else
|
||||
ret = irq_attach(LM3S_IRQ_ETHCON, lm_interrupt);
|
||||
ret = irq_attach(LM_IRQ_ETHCON, lm_interrupt);
|
||||
#endif
|
||||
if (ret != 0)
|
||||
{
|
||||
@@ -1461,7 +1461,7 @@ static inline int lm_ethinitialize(int intf)
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if LM3S_NETHCONTROLLERS == 1
|
||||
#if LM_NETHCONTROLLERS == 1
|
||||
void up_netinitialize(void)
|
||||
{
|
||||
(void)lm_ethinitialize(0);
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if LM3S_NETHCONTROLLERS > 1
|
||||
#if LM_NETHCONTROLLERS > 1
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
@@ -77,7 +77,7 @@ extern "C"
|
||||
* Function: lm_ethinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the Ethernet driver for one interface. If the LM3S chip
|
||||
* Initialize the Ethernet driver for one interface. If the Stellaris chip
|
||||
* supports multiple Ethernet controllers, then bould specific logic
|
||||
* must implement up_netinitialize() and call this function to initialize
|
||||
* the desiresed interfaces.
|
||||
@@ -99,5 +99,5 @@ int lm_ethinitialize(int intf);
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* LM3S_NETHCONTROLLERS > 1 */
|
||||
#endif /* LM_NETHCONTROLLERS > 1 */
|
||||
#endif /* __ARCH_ARM_SRC_LM_LM_ETHERNET_H */
|
||||
|
||||
@@ -140,23 +140,23 @@ static const struct gpio_func_s g_funcbits[] =
|
||||
{GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */
|
||||
};
|
||||
|
||||
static const uint32_t g_gpiobase[LM3S_NPORTS] =
|
||||
static const uint32_t g_gpiobase[LM_NPORTS] =
|
||||
{
|
||||
/* All support LM3S parts have at least 7 ports, GPIOA-G */
|
||||
/* All support Stellaris parts have at least 7 ports, GPIOA-G */
|
||||
|
||||
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
|
||||
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE,
|
||||
LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
|
||||
LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE,
|
||||
|
||||
/* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/
|
||||
|
||||
#if LM3S_NPORTS > 7
|
||||
LM3S_GPIOH_BASE,
|
||||
#if LM_NPORTS > 7
|
||||
LM_GPIOH_BASE,
|
||||
#endif
|
||||
|
||||
/* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/
|
||||
|
||||
#if LM3S_NPORTS > 8
|
||||
LM3S_GPIOJ_BASE,
|
||||
#if LM_NPORTS > 8
|
||||
LM_GPIOJ_BASE,
|
||||
#endif
|
||||
};
|
||||
|
||||
@@ -180,7 +180,7 @@ static const uint32_t g_gpiobase[LM3S_NPORTS] =
|
||||
static uint32_t lm_gpiobaseaddress(unsigned int port)
|
||||
{
|
||||
uint32_t gpiobase = 0;
|
||||
if (port < LM3S_NPORTS)
|
||||
if (port < LM_NPORTS)
|
||||
{
|
||||
gpiobase = g_gpiobase[port];
|
||||
}
|
||||
@@ -215,10 +215,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
|
||||
setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno;
|
||||
clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno;
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_ODR_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_ODR_OFFSET);
|
||||
|
||||
/* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
|
||||
* register. When a bit is set to 1, it enables a weak pull-up resistor on the
|
||||
@@ -231,10 +231,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
|
||||
|
||||
if (setbit || clrbit)
|
||||
{
|
||||
regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_PUR_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_PUR_OFFSET);
|
||||
}
|
||||
|
||||
/* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
|
||||
@@ -248,10 +248,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
|
||||
|
||||
if (setbit || clrbit)
|
||||
{
|
||||
regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_PDR_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_PDR_OFFSET);
|
||||
}
|
||||
|
||||
/* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
|
||||
@@ -266,10 +266,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
|
||||
setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno;
|
||||
clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno;
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_DEN_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_DEN_OFFSET);
|
||||
|
||||
/* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data
|
||||
* direction register. Bits set to 1 in the GPIODIR register configure
|
||||
@@ -281,10 +281,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
|
||||
setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno;
|
||||
clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno;
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_DIR_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_DIR_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM3S_GPIO_DIR_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_DIR_OFFSET);
|
||||
|
||||
/* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode
|
||||
* control select register. Writing a 1 to any bit in this register selects
|
||||
@@ -298,10 +298,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
|
||||
setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno;
|
||||
clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno;
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_AFSEL_OFFSET);
|
||||
regval &= ~clrbit;
|
||||
regval |= setbit;
|
||||
putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_AFSEL_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -336,7 +336,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
|
||||
* DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
|
||||
*/
|
||||
|
||||
regoffset = LM3S_GPIO_DR2R_OFFSET;
|
||||
regoffset = LM_GPIO_DR2R_OFFSET;
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -349,7 +349,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
|
||||
* in the GPIO DR8R register are automatically cleared by hardware."
|
||||
*/
|
||||
|
||||
regoffset = LM3S_GPIO_DR4R_OFFSET;
|
||||
regoffset = LM_GPIO_DR4R_OFFSET;
|
||||
}
|
||||
break;
|
||||
|
||||
@@ -374,7 +374,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
|
||||
* DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
|
||||
*/
|
||||
|
||||
regoffset = LM3S_GPIO_DR8R_OFFSET;
|
||||
regoffset = LM_GPIO_DR8R_OFFSET;
|
||||
}
|
||||
break;
|
||||
}
|
||||
@@ -385,10 +385,10 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
|
||||
regval |= pin;
|
||||
putreg32(regval, base + regoffset);
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_SLR_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_SLR_OFFSET);
|
||||
regval &= slrclr;
|
||||
regval |= slrset;
|
||||
putreg32(regval, base + LM3S_GPIO_SLR_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_SLR_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -503,10 +503,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
*/
|
||||
|
||||
#if 0 /* always overwritten by lm_gpiofunc */
|
||||
regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_ODR_OFFSET);
|
||||
regval &= ~odrclr;
|
||||
regval |= odrset;
|
||||
putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_ODR_OFFSET);
|
||||
#endif
|
||||
|
||||
/* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
|
||||
@@ -515,10 +515,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_PUR_OFFSET);
|
||||
regval &= ~purclr;
|
||||
regval |= purset;
|
||||
putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_PUR_OFFSET);
|
||||
|
||||
/* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
|
||||
* register. When a bit is set to 1, it enables a weak pull-down resistor on the
|
||||
@@ -526,10 +526,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_PDR_OFFSET);
|
||||
regval &= ~pdrclr;
|
||||
regval |= pdrset;
|
||||
putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_PDR_OFFSET);
|
||||
|
||||
/* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
|
||||
* register. By default, with the exception of the GPIO signals used for JTAG/SWD
|
||||
@@ -541,10 +541,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
*/
|
||||
|
||||
#if 0 /* always overwritten by lm_gpiofunc */
|
||||
regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_DEN_OFFSET);
|
||||
regval &= ~denclr;
|
||||
regval |= denset;
|
||||
putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_DEN_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -589,18 +589,18 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* on that pin. All bits are cleared by a reset."
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_IM_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_IM_OFFSET);
|
||||
regval &= ~pin;
|
||||
putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_IM_OFFSET);
|
||||
|
||||
/* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
|
||||
* in this register clears the corresponding interrupt edge detection logic
|
||||
* register. Writing a 0 has no effect."
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_ICR_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_ICR_OFFSET);
|
||||
regval |= pin;
|
||||
putreg32(regval, base + LM3S_GPIO_ICR_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_ICR_OFFSET);
|
||||
|
||||
/* Assume rising edge */
|
||||
|
||||
@@ -656,10 +656,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* by a reset.
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_IS_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_IS_OFFSET);
|
||||
regval &= isclr;
|
||||
regval |= isset;
|
||||
putreg32(regval, base + LM3S_GPIO_IS_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_IS_OFFSET);
|
||||
|
||||
/* "The GPIO IBE register is the interrupt both-edges register. When the
|
||||
* corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
|
||||
@@ -670,10 +670,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* are cleared by a reset.
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_IBE_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_IBE_OFFSET);
|
||||
regval &= ibeclr;
|
||||
regval |= ibeset;
|
||||
putreg32(regval, base + LM3S_GPIO_IBE_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_IBE_OFFSET);
|
||||
|
||||
/* "The GPIOIEV register is the interrupt event register. Bits set to
|
||||
* High in GPIO IEV configure the corresponding pin to detect rising edges
|
||||
@@ -683,10 +683,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
|
||||
* value in GPIOIS. All bits are cleared by a reset.
|
||||
*/
|
||||
|
||||
regval = getreg32(base + LM3S_GPIO_IEV_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_IEV_OFFSET);
|
||||
regval &= iveclr;
|
||||
regval |= iveset;
|
||||
putreg32(regval, base + LM3S_GPIO_IEV_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_IEV_OFFSET);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -734,9 +734,9 @@ int lm_configgpio(uint32_t cfgset)
|
||||
* in the RCGC2 register."
|
||||
*/
|
||||
|
||||
regval = getreg32(LM3S_SYSCON_RCGC2);
|
||||
regval = getreg32(LM_SYSCON_RCGC2);
|
||||
regval |= SYSCON_RCGC2_GPIO(port);
|
||||
putreg32(regval, LM3S_SYSCON_RCGC2);
|
||||
putreg32(regval, LM_SYSCON_RCGC2);
|
||||
|
||||
/* First, set the port to digital input. This is the safest state in which
|
||||
* to perform reconfiguration.
|
||||
@@ -810,7 +810,7 @@ void lm_gpiowrite(uint32_t pinset, bool value)
|
||||
* "... All bits are cleared by a reset."
|
||||
*/
|
||||
|
||||
putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
|
||||
putreg32((uint32_t)value << pinno, base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -849,6 +849,6 @@ bool lm_gpioread(uint32_t pinset, bool value)
|
||||
* are cleared by a reset."
|
||||
*/
|
||||
|
||||
return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
|
||||
return (getreg32(base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
|
||||
}
|
||||
|
||||
|
||||
@@ -73,38 +73,38 @@ static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
|
||||
static const uint32_t g_gpiobase[] =
|
||||
{
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
|
||||
LM3S_GPIOA_BASE,
|
||||
LM_GPIOA_BASE,
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
|
||||
LM3S_GPIOB_BASE,
|
||||
LM_GPIOB_BASE,
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
|
||||
LM3S_GPIOC_BASE,
|
||||
LM_GPIOC_BASE,
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
|
||||
LM3S_GPIOD_BASE,
|
||||
LM_GPIOD_BASE,
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
|
||||
LM3S_GPIOE_BASE,
|
||||
LM_GPIOE_BASE,
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
|
||||
LM3S_GPIOF_BASE,
|
||||
LM_GPIOF_BASE,
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
|
||||
LM3S_GPIOG_BASE,
|
||||
LM_GPIOG_BASE,
|
||||
#endif
|
||||
|
||||
/* NOTE: Not all LM3S architectures support GPIOs above GPIOG. If the chip
|
||||
* does not support these higher ports, then they must be disabled in the
|
||||
* configuration. Otherwise, the following will likely cause compilation
|
||||
/* NOTE: Not all Stellaris architectures support GPIOs above GPIOG. If the
|
||||
* chip does not support these higher ports, then they must be disabled in
|
||||
* the configuration. Otherwise, the following will likely cause compilation
|
||||
* errors!
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
|
||||
LM3S_GPIOH_BASE,
|
||||
LM_GPIOH_BASE,
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
|
||||
LM3S_GPIOJ_BASE,
|
||||
LM_GPIOJ_BASE,
|
||||
#endif
|
||||
};
|
||||
|
||||
@@ -161,7 +161,7 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
|
||||
* either no interrupt has been generated, or the interrupt is masked."
|
||||
*/
|
||||
|
||||
mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff;
|
||||
mis = getreg32(regbase + LM_GPIO_MIS_OFFSET) & 0xff;
|
||||
|
||||
/* Clear all GPIO interrupts that we are going to process. "The GPIO ICR
|
||||
* register is the interrupt clear register. Writing a 1 to a bit in this
|
||||
@@ -169,7 +169,7 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
|
||||
* Writing a 0 has no effect."
|
||||
*/
|
||||
|
||||
putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET);
|
||||
putreg32(mis, regbase + LM_GPIO_ICR_OFFSET);
|
||||
|
||||
/* Now process each IRQ pending in the MIS */
|
||||
|
||||
@@ -187,63 +187,63 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
|
||||
static int lm_gpioahandler(int irq, FAR void *context)
|
||||
{
|
||||
return lm_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context);
|
||||
return lm_gpiohandler(LM_GPIOA_BASE, LM_IRQ_GPIOA_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
|
||||
static int lm_gpiobhandler(int irq, FAR void *context)
|
||||
{
|
||||
return lm_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context);
|
||||
return lm_gpiohandler(LM_GPIOB_BASE, LM_IRQ_GPIOB_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
|
||||
static int lm_gpiochandler(int irq, FAR void *context)
|
||||
{
|
||||
return lm_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context);
|
||||
return lm_gpiohandler(LM_GPIOC_BASE, LM_IRQ_GPIOC_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
|
||||
static int lm_gpiodhandler(int irq, FAR void *context)
|
||||
{
|
||||
return lm_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context);
|
||||
return lm_gpiohandler(LM_GPIOD_BASE, LM_IRQ_GPIOD_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
|
||||
static int lm_gpioehandler(int irq, FAR void *context)
|
||||
{
|
||||
return lm_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context);
|
||||
return lm_gpiohandler(LM_GPIOE_BASE, LM_IRQ_GPIOE_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
|
||||
static int lm_gpiofhandler(int irq, FAR void *context)
|
||||
{
|
||||
return lm_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context);
|
||||
return lm_gpiohandler(LM_GPIOF_BASE, LM_IRQ_GPIOF_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
|
||||
static int lm_gpioghandler(int irq, FAR void *context)
|
||||
{
|
||||
return lm_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context);
|
||||
return lm_gpiohandler(LM_GPIOG_BASE, LM_IRQ_GPIOG_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
|
||||
static int lm_gpiohhandler(int irq, FAR void *context)
|
||||
{
|
||||
return lm_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context);
|
||||
return lm_gpiohandler(LM_GPIOH_BASE, LM_IRQ_GPIOH_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
|
||||
static int lm_gpiojhandler(int irq, FAR void *context)
|
||||
{
|
||||
return lm_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context);
|
||||
return lm_gpiohandler(LM_GPIOJ_BASE, LM_IRQ_GPIOJ_0, context);
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -275,40 +275,40 @@ int gpio_irqinitialize(void)
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOA, lm_gpioahandler);
|
||||
up_enable_irq(LM3S_IRQ_GPIOA);
|
||||
irq_attach(LM_IRQ_GPIOA, lm_gpioahandler);
|
||||
up_enable_irq(LM_IRQ_GPIOA);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOB, lm_gpiobhandler);
|
||||
up_enable_irq(LM3S_IRQ_GPIOB);
|
||||
irq_attach(LM_IRQ_GPIOB, lm_gpiobhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOB);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOC, lm_gpiochandler);
|
||||
up_enable_irq(LM3S_IRQ_GPIOC);
|
||||
irq_attach(LM_IRQ_GPIOC, lm_gpiochandler);
|
||||
up_enable_irq(LM_IRQ_GPIOC);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOD, lm_gpiodhandler);
|
||||
up_enable_irq(LM3S_IRQ_GPIOD);
|
||||
irq_attach(LM_IRQ_GPIOD, lm_gpiodhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOD);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOE, lm_gpioehandler);
|
||||
up_enable_irq(LM3S_IRQ_GPIOE);
|
||||
irq_attach(LM_IRQ_GPIOE, lm_gpioehandler);
|
||||
up_enable_irq(LM_IRQ_GPIOE);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOF, lm_gpiofhandler);
|
||||
up_enable_irq(LM3S_IRQ_GPIOF);
|
||||
irq_attach(LM_IRQ_GPIOF, lm_gpiofhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOF);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOG, lm_gpioghandler);
|
||||
up_enable_irq(LM3S_IRQ_GPIOG);
|
||||
irq_attach(LM_IRQ_GPIOG, lm_gpioghandler);
|
||||
up_enable_irq(LM_IRQ_GPIOG);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOH, lm_gpiohhandler);
|
||||
up_enable_irq(LM3S_IRQ_GPIOH);
|
||||
irq_attach(LM_IRQ_GPIOH, lm_gpiohhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOH);
|
||||
#endif
|
||||
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
|
||||
irq_attach(LM3S_IRQ_GPIOJ, lm_gpiojhandler);
|
||||
up_enable_irq(LM3S_IRQ_GPIOJ);
|
||||
irq_attach(LM_IRQ_GPIOJ, lm_gpiojhandler);
|
||||
up_enable_irq(LM_IRQ_GPIOJ);
|
||||
#endif
|
||||
|
||||
return OK;
|
||||
@@ -386,9 +386,9 @@ void gpio_irqenable(int irq)
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
regval = getreg32(base + LM3S_GPIO_IM_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_IM_OFFSET);
|
||||
regval |= pin;
|
||||
putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_IM_OFFSET);
|
||||
irqrestore(flags);
|
||||
}
|
||||
}
|
||||
@@ -425,10 +425,9 @@ void gpio_irqdisable(int irq)
|
||||
*/
|
||||
|
||||
flags = irqsave();
|
||||
regval = getreg32(base + LM3S_GPIO_IM_OFFSET);
|
||||
regval = getreg32(base + LM_GPIO_IM_OFFSET);
|
||||
regval &= ~pin;
|
||||
putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
|
||||
putreg32(regval, base + LM_GPIO_IM_OFFSET);
|
||||
irqrestore(flags);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -63,7 +63,7 @@
|
||||
* bringup
|
||||
*/
|
||||
|
||||
#undef LM3S_IRQ_DEBUG
|
||||
#undef LM_IRQ_DEBUG
|
||||
|
||||
/* Get a 32-bit version of the default priority */
|
||||
|
||||
@@ -95,7 +95,7 @@ volatile uint32_t *current_regs;
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG)
|
||||
#if defined(LM_IRQ_DEBUG) && defined (CONFIG_DEBUG)
|
||||
static void lm_dumpnvic(const char *msg, int irq)
|
||||
{
|
||||
irqstate_t flags;
|
||||
@@ -201,21 +201,21 @@ static int lm_reserved(int irq, FAR void *context)
|
||||
|
||||
static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
|
||||
{
|
||||
DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS);
|
||||
DEBUGASSERT(irq >= LM_IRQ_NMI && irq < NR_IRQS);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= LM3S_IRQ_INTERRUPTS)
|
||||
if (irq >= LM_IRQ_INTERRUPTS)
|
||||
{
|
||||
if (irq < LM3S_IRQ_INTERRUPTS + 32)
|
||||
if (irq < LM_IRQ_INTERRUPTS + 32)
|
||||
{
|
||||
*regaddr = NVIC_IRQ0_31_ENABLE;
|
||||
*bit = 1 << (irq - LM3S_IRQ_INTERRUPTS);
|
||||
*bit = 1 << (irq - LM_IRQ_INTERRUPTS);
|
||||
}
|
||||
else if (irq < NR_IRQS)
|
||||
{
|
||||
*regaddr = NVIC_IRQ32_63_ENABLE;
|
||||
*bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32);
|
||||
*bit = 1 << (irq - LM_IRQ_INTERRUPTS - 32);
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -228,19 +228,19 @@ static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
|
||||
else
|
||||
{
|
||||
*regaddr = NVIC_SYSHCON;
|
||||
if (irq == LM3S_IRQ_MEMFAULT)
|
||||
if (irq == LM_IRQ_MEMFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_MEMFAULTENA;
|
||||
}
|
||||
else if (irq == LM3S_IRQ_BUSFAULT)
|
||||
else if (irq == LM_IRQ_BUSFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_BUSFAULTENA;
|
||||
}
|
||||
else if (irq == LM3S_IRQ_USAGEFAULT)
|
||||
else if (irq == LM_IRQ_USAGEFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_USGFAULTENA;
|
||||
}
|
||||
else if (irq == LM3S_IRQ_SYSTICK)
|
||||
else if (irq == LM_IRQ_SYSTICK)
|
||||
{
|
||||
*regaddr = NVIC_SYSTICK_CTRL;
|
||||
*bit = NVIC_SYSTICK_CTRL_ENABLE;
|
||||
@@ -309,13 +309,13 @@ void up_irqinitialize(void)
|
||||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(LM3S_IRQ_SVCALL, up_svcall);
|
||||
irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault);
|
||||
irq_attach(LM_IRQ_SVCALL, up_svcall);
|
||||
irq_attach(LM_IRQ_HARDFAULT, up_hardfault);
|
||||
|
||||
/* Set the priority of the SVCall interrupt */
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
/* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
#endif
|
||||
|
||||
/* If the MPU is enabled, then attach and enable the Memory Management
|
||||
@@ -323,22 +323,22 @@ void up_irqinitialize(void)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARMV7M_MPU
|
||||
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
|
||||
up_enable_irq(LM3S_IRQ_MEMFAULT);
|
||||
irq_attach(LM_IRQ_MEMFAULT, up_memfault);
|
||||
up_enable_irq(LM_IRQ_MEMFAULT);
|
||||
#endif
|
||||
|
||||
/* Attach all other processor exceptions (except reset and sys tick) */
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
irq_attach(LM3S_IRQ_NMI, lm_nmi);
|
||||
irq_attach(LM_IRQ_NMI, lm_nmi);
|
||||
#ifndef CONFIG_ARMV7M_MPU
|
||||
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
|
||||
irq_attach(LM_IRQ_MEMFAULT, up_memfault);
|
||||
#endif
|
||||
irq_attach(LM3S_IRQ_BUSFAULT, lm_busfault);
|
||||
irq_attach(LM3S_IRQ_USAGEFAULT, lm_usagefault);
|
||||
irq_attach(LM3S_IRQ_PENDSV, lm_pendsv);
|
||||
irq_attach(LM3S_IRQ_DBGMONITOR, lm_dbgmonitor);
|
||||
irq_attach(LM3S_IRQ_RESERVED, lm_reserved);
|
||||
irq_attach(LM_IRQ_BUSFAULT, lm_busfault);
|
||||
irq_attach(LM_IRQ_USAGEFAULT, lm_usagefault);
|
||||
irq_attach(LM_IRQ_PENDSV, lm_pendsv);
|
||||
irq_attach(LM_IRQ_DBGMONITOR, lm_dbgmonitor);
|
||||
irq_attach(LM_IRQ_RESERVED, lm_reserved);
|
||||
#endif
|
||||
|
||||
lm_dumpnvic("initial", NR_IRQS);
|
||||
@@ -433,16 +433,16 @@ int up_prioritize_irq(int irq, int priority)
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
|
||||
if (irq < LM3S_IRQ_INTERRUPTS)
|
||||
if (irq < LM_IRQ_INTERRUPTS)
|
||||
{
|
||||
irq -= 4;
|
||||
regaddr = NVIC_SYSH_PRIORITY(irq);
|
||||
}
|
||||
else
|
||||
{
|
||||
irq -= LM3S_IRQ_INTERRUPTS;
|
||||
irq -= LM_IRQ_INTERRUPTS;
|
||||
regaddr = NVIC_IRQ_PRIORITY(irq);
|
||||
}
|
||||
|
||||
|
||||
@@ -57,12 +57,12 @@
|
||||
|
||||
/* Configuration **********************************************************/
|
||||
|
||||
#if LM3S_NUARTS < 2
|
||||
#if LM_NUARTS < 2
|
||||
# undef CONFIG_LM_UART1
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
#endif
|
||||
|
||||
#if LM3S_NUARTS < 3
|
||||
#if LM_NUARTS < 3
|
||||
# undef CONFIG_LM_UART2
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
#endif
|
||||
@@ -92,52 +92,52 @@
|
||||
/* Select UART parameters for the selected console */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
# define LM3S_CONSOLE_BASE LM3S_UART0_BASE
|
||||
# define LM3S_CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
# define LM3S_CONSOLE_BITS CONFIG_UART0_BITS
|
||||
# define LM3S_CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
# define LM3S_CONSOLE_2STOP CONFIG_UART0_2STOP
|
||||
# define LM_CONSOLE_BASE LM_UART0_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART0_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART0_2STOP
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
# define LM3S_CONSOLE_BASE LM3S_UART1_BASE
|
||||
# define LM3S_CONSOLE_BAUD CONFIG_UART1_BAUD
|
||||
# define LM3S_CONSOLE_BITS CONFIG_UART1_BITS
|
||||
# define LM3S_CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
# define LM3S_CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
# define LM_CONSOLE_BASE LM_UART1_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART1_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART1_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART1_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART1_2STOP
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||
# define LM3S_CONSOLE_BASE LM3S_UART2_BASE
|
||||
# define LM3S_CONSOLE_BAUD CONFIG_UART2_BAUD
|
||||
# define LM3S_CONSOLE_BITS CONFIG_UART2_BITS
|
||||
# define LM3S_CONSOLE_PARITY CONFIG_UART2_PARITY
|
||||
# define LM3S_CONSOLE_2STOP CONFIG_UART2_2STOP
|
||||
# define LM_CONSOLE_BASE LM_UART2_BASE
|
||||
# define LM_CONSOLE_BAUD CONFIG_UART2_BAUD
|
||||
# define LM_CONSOLE_BITS CONFIG_UART2_BITS
|
||||
# define LM_CONSOLE_PARITY CONFIG_UART2_PARITY
|
||||
# define LM_CONSOLE_2STOP CONFIG_UART2_2STOP
|
||||
#else
|
||||
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
|
||||
#endif
|
||||
|
||||
/* Get LCRH settings */
|
||||
|
||||
#if LM3S_CONSOLE_BITS == 5
|
||||
#if LM_CONSOLE_BITS == 5
|
||||
# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
|
||||
#elif LM3S_CONSOLE_BITS == 6
|
||||
#elif LM_CONSOLE_BITS == 6
|
||||
# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
|
||||
#elif LM3S_CONSOLE_BITS == 7
|
||||
#elif LM_CONSOLE_BITS == 7
|
||||
# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
|
||||
#elif LM3S_CONSOLE_BITS == 8
|
||||
#elif LM_CONSOLE_BITS == 8
|
||||
# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
|
||||
#else
|
||||
# error "Number of bits not supported"
|
||||
#endif
|
||||
|
||||
#if LM3S_CONSOLE_PARITY == 0
|
||||
#if LM_CONSOLE_PARITY == 0
|
||||
# define UART_LCRH_PARITY (0)
|
||||
#elif LM3S_CONSOLE_PARITY == 1
|
||||
#elif LM_CONSOLE_PARITY == 1
|
||||
# define UART_LCRH_PARITY UART_LCRH_PEN
|
||||
#elif LM3S_CONSOLE_PARITY == 2
|
||||
#elif LM_CONSOLE_PARITY == 2
|
||||
# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
|
||||
#else
|
||||
# error "Invalid parity selection"
|
||||
#endif
|
||||
|
||||
#if LM3S_CONSOLE_2STOP != 0
|
||||
#if LM_CONSOLE_2STOP != 0
|
||||
# define UART_LCRH_NSTOP UART_LCRH_STP2
|
||||
#else
|
||||
# define UART_LCRH_NSTOP (0)
|
||||
@@ -177,17 +177,17 @@
|
||||
* divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
|
||||
*/
|
||||
|
||||
#define LM3S_BRDDEN (16 * LM3S_CONSOLE_BAUD)
|
||||
#define LM3S_BRDI (SYSCLK_FREQUENCY / LM3S_BRDDEN)
|
||||
#define LM3S_REMAINDER (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI)
|
||||
#define LM3S_DIVFRAC ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN)
|
||||
#define LM_BRDDEN (16 * LM_CONSOLE_BAUD)
|
||||
#define LM_BRDI (SYSCLK_FREQUENCY / LM_BRDDEN)
|
||||
#define LM_REMAINDER (SYSCLK_FREQUENCY - LM_BRDDEN * LM_BRDI)
|
||||
#define LM_DIVFRAC ((LM_REMAINDER * 64 + (LM_BRDDEN/2)) / LM_BRDDEN)
|
||||
|
||||
/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
|
||||
/* For example: LM_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
|
||||
*
|
||||
* LM3S_BRDDEN = (16 * 115,200) = 1,843,200
|
||||
* LM3S_BRDI = 50,000,000 / 1,843,200 = 27
|
||||
* LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600
|
||||
* LM3S_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8
|
||||
* LM_BRDDEN = (16 * 115,200) = 1,843,200
|
||||
* LM_BRDI = 50,000,000 / 1,843,200 = 27
|
||||
* LM_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600
|
||||
* LM_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8
|
||||
*
|
||||
* Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
|
||||
*/
|
||||
@@ -229,11 +229,11 @@ void up_lowputc(char ch)
|
||||
#ifdef HAVE_CONSOLE
|
||||
/* Wait until the TX FIFO is not full */
|
||||
|
||||
while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
|
||||
while ((getreg32(LM_CONSOLE_BASE+LM_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
|
||||
|
||||
/* Then send the character */
|
||||
|
||||
putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET);
|
||||
putreg32((uint32_t)ch, LM_CONSOLE_BASE+LM_UART_DR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -260,18 +260,18 @@ void up_lowsetup(void)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LM_UART0
|
||||
regval = getreg32(LM3S_SYSCON_RCGC1);
|
||||
regval = getreg32(LM_SYSCON_RCGC1);
|
||||
regval |= SYSCON_RCGC1_UART0;
|
||||
putreg32(regval, LM3S_SYSCON_RCGC1);
|
||||
putreg32(regval, LM_SYSCON_RCGC1);
|
||||
|
||||
lm_configgpio(GPIO_UART0_RX);
|
||||
lm_configgpio(GPIO_UART0_TX);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LM_UART1
|
||||
regval = getreg32(LM3S_SYSCON_RCGC1);
|
||||
regval = getreg32(LM_SYSCON_RCGC1);
|
||||
regval |= SYSCON_RCGC1_UART1;
|
||||
putreg32(regval, LM3S_SYSCON_RCGC1);
|
||||
putreg32(regval, LM_SYSCON_RCGC1);
|
||||
|
||||
lm_configgpio(GPIO_UART1_RX);
|
||||
lm_configgpio(GPIO_UART1_TX);
|
||||
@@ -282,26 +282,26 @@ void up_lowsetup(void)
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
|
||||
|
||||
ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
|
||||
ctl = getreg32(LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
|
||||
ctl &= ~UART_CTL_UARTEN;
|
||||
putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
|
||||
putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
|
||||
|
||||
/* Write the integer portion of the BRD to the UART IBRD register */
|
||||
|
||||
putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
|
||||
putreg32(LM_BRDI, LM_CONSOLE_BASE+LM_UART_IBRD_OFFSET);
|
||||
|
||||
/* Write the fractional portion of the BRD to the UART FBRD register */
|
||||
|
||||
putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
|
||||
putreg32(LM_DIVFRAC, LM_CONSOLE_BASE+LM_UART_FBRD_OFFSET);
|
||||
|
||||
/* Write the desired serial parameters to the UART LCRH register */
|
||||
|
||||
putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
|
||||
putreg32(UART_LCRH_VALUE, LM_CONSOLE_BASE+LM_UART_LCRH_OFFSET);
|
||||
|
||||
/* Enable the UART by setting the UARTEN bit in the UART CTL register */
|
||||
|
||||
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
|
||||
putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
|
||||
putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
@@ -66,12 +66,12 @@
|
||||
|
||||
/* Some sanity checks *******************************************************/
|
||||
|
||||
#if LM3S_NUARTS < 2
|
||||
#if LM_NUARTS < 2
|
||||
# undef CONFIG_LM_UART1
|
||||
# undef CONFIG_UART1_SERIAL_CONSOLE
|
||||
#endif
|
||||
|
||||
#if LM3S_NUARTS < 3
|
||||
#if LM_NUARTS < 3
|
||||
# undef CONFIG_LM_UART2
|
||||
# undef CONFIG_UART2_SERIAL_CONSOLE
|
||||
#endif
|
||||
@@ -274,14 +274,14 @@ static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
|
||||
static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
|
||||
#endif
|
||||
|
||||
/* This describes the state of the LM3S uart0 port. */
|
||||
/* This describes the state of the Stellaris uart0 port. */
|
||||
|
||||
#ifdef CONFIG_LM_UART0
|
||||
static struct up_dev_s g_uart0priv =
|
||||
{
|
||||
.uartbase = LM3S_UART0_BASE,
|
||||
.uartbase = LM_UART0_BASE,
|
||||
.baud = CONFIG_UART0_BAUD,
|
||||
.irq = LM3S_IRQ_UART0,
|
||||
.irq = LM_IRQ_UART0,
|
||||
.parity = CONFIG_UART0_PARITY,
|
||||
.bits = CONFIG_UART0_BITS,
|
||||
.stopbits2 = CONFIG_UART0_2STOP,
|
||||
@@ -304,14 +304,14 @@ static uart_dev_t g_uart0port =
|
||||
};
|
||||
#endif
|
||||
|
||||
/* This describes the state of the LM3S uart1 port. */
|
||||
/* This describes the state of the Stellaris uart1 port. */
|
||||
|
||||
#ifdef CONFIG_LM_UART1
|
||||
static struct up_dev_s g_uart1priv =
|
||||
{
|
||||
.uartbase = LM3S_UART1_BASE,
|
||||
.uartbase = LM_UART1_BASE,
|
||||
.baud = CONFIG_UART1_BAUD,
|
||||
.irq = LM3S_IRQ_UART1,
|
||||
.irq = LM_IRQ_UART1,
|
||||
.parity = CONFIG_UART1_PARITY,
|
||||
.bits = CONFIG_UART1_BITS,
|
||||
.stopbits2 = CONFIG_UART1_2STOP,
|
||||
@@ -334,14 +334,14 @@ static uart_dev_t g_uart1port =
|
||||
};
|
||||
#endif
|
||||
|
||||
/* This describes the state of the LM3S uart1 port. */
|
||||
/* This describes the state of the Stellaris uart1 port. */
|
||||
|
||||
#ifdef CONFIG_LM_UART2
|
||||
static struct up_dev_s g_uart2priv =
|
||||
{
|
||||
.uartbase = LM3S_UART2_BASE,
|
||||
.uartbase = LM_UART2_BASE,
|
||||
.baud = CONFIG_UART2_BAUD,
|
||||
.irq = LM3S_IRQ_UART2,
|
||||
.irq = LM_IRQ_UART2,
|
||||
.parity = CONFIG_UART2_PARITY,
|
||||
.bits = CONFIG_UART2_BITS,
|
||||
.stopbits2 = CONFIG_UART2_2STOP,
|
||||
@@ -402,7 +402,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
|
||||
/* Disable all interrupts */
|
||||
|
||||
priv->im = 0;
|
||||
up_serialout(priv, LM3S_UART_IM_OFFSET, 0);
|
||||
up_serialout(priv, LM_UART_IM_OFFSET, 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -412,7 +412,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
|
||||
static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
|
||||
{
|
||||
priv->im = im;
|
||||
up_serialout(priv, LM3S_UART_IM_OFFSET, im);
|
||||
up_serialout(priv, LM_UART_IM_OFFSET, im);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -430,7 +430,7 @@ static inline void up_waittxnotfull(struct up_dev_s *priv)
|
||||
{
|
||||
/* Check Tx FIFO is full */
|
||||
|
||||
if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
|
||||
if ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
|
||||
{
|
||||
/* The Tx FIFO is not full... return */
|
||||
|
||||
@@ -471,9 +471,9 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
|
||||
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
|
||||
|
||||
ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
|
||||
ctl = up_serialin(priv, LM_UART_CTL_OFFSET);
|
||||
ctl &= ~UART_CTL_UARTEN;
|
||||
up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
|
||||
up_serialout(priv, LM_UART_CTL_OFFSET, ctl);
|
||||
|
||||
/* Calculate BAUD rate from the SYS clock:
|
||||
*
|
||||
@@ -517,8 +517,8 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
remainder = SYSCLK_FREQUENCY - den * brdi;
|
||||
divfrac = ((remainder << 6) + (den >> 1)) / den;
|
||||
|
||||
up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi);
|
||||
up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac);
|
||||
up_serialout(priv, LM_UART_IBRD_OFFSET, brdi);
|
||||
up_serialout(priv, LM_UART_FBRD_OFFSET, divfrac);
|
||||
|
||||
/* Set up the LCRH register */
|
||||
|
||||
@@ -558,14 +558,14 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
lcrh |= UART_LCRH_STP2;
|
||||
}
|
||||
|
||||
up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
|
||||
up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh);
|
||||
#endif
|
||||
|
||||
/* Set the UART to interrupt whenever the TX FIFO is almost empty or when
|
||||
* any character is received.
|
||||
*/
|
||||
|
||||
up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
|
||||
up_serialout(priv, LM_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
|
||||
|
||||
/* Flush the Rx and Tx FIFOs -- How do you do that?*/
|
||||
|
||||
@@ -575,27 +575,27 @@ static int up_setup(struct uart_dev_s *dev)
|
||||
* yet because the interrupt is still disabled at the interrupt controller.
|
||||
*/
|
||||
|
||||
up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
|
||||
up_serialout(priv, LM_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
|
||||
|
||||
/* Enable the FIFOs */
|
||||
|
||||
#ifdef CONFIG_SUPPRESS_UART_CONFIG
|
||||
lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET);
|
||||
lcrh = up_serialin(priv, LM_UART_LCRH_OFFSET);
|
||||
#endif
|
||||
lcrh |= UART_LCRH_FEN;
|
||||
up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
|
||||
up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh);
|
||||
|
||||
/* Enable Rx, Tx, and the UART */
|
||||
|
||||
#ifdef CONFIG_SUPPRESS_UART_CONFIG
|
||||
ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
|
||||
ctl = up_serialin(priv, LM_UART_CTL_OFFSET);
|
||||
#endif
|
||||
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
|
||||
up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
|
||||
up_serialout(priv, LM_UART_CTL_OFFSET, ctl);
|
||||
|
||||
/* Set up the cache IM value */
|
||||
|
||||
priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET);
|
||||
priv->im = up_serialin(priv, LM_UART_IM_OFFSET);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@@ -716,8 +716,8 @@ static int up_interrupt(int irq, void *context)
|
||||
|
||||
/* Get the masked UART status and clear the pending interrupts. */
|
||||
|
||||
mis = up_serialin(priv, LM3S_UART_MIS_OFFSET);
|
||||
up_serialout(priv, LM3S_UART_ICR_OFFSET, mis);
|
||||
mis = up_serialin(priv, LM_UART_MIS_OFFSET);
|
||||
up_serialout(priv, LM_UART_ICR_OFFSET, mis);
|
||||
|
||||
/* Handle incoming, receive bytes (with or without timeout) */
|
||||
|
||||
@@ -797,7 +797,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
|
||||
|
||||
/* Get the Rx byte + 4 bits of error information. Return those in status */
|
||||
|
||||
rxd = up_serialin(priv, LM3S_UART_DR_OFFSET);
|
||||
rxd = up_serialin(priv, LM_UART_DR_OFFSET);
|
||||
*status = rxd;
|
||||
|
||||
/* The lower 8bits of the Rx data is the actual recevied byte */
|
||||
@@ -830,7 +830,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
|
||||
{
|
||||
priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
|
||||
}
|
||||
up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
|
||||
up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -844,7 +844,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
|
||||
static bool up_rxavailable(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
|
||||
return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -858,7 +858,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
|
||||
static void up_send(struct uart_dev_s *dev, int ch)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
|
||||
up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -881,11 +881,11 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
|
||||
priv->im |= UART_IM_TXIM;
|
||||
up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
|
||||
up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
|
||||
|
||||
/* The serial driver wants an interrupt here, but will not get get
|
||||
* one unless we "prime the pump." I believe that this is because
|
||||
* behave like a level interrupt and the LM3S interrupts behave
|
||||
* behave like a level interrupt and the Stellaris interrupts behave
|
||||
* (at least by default) like edge interrupts.
|
||||
*
|
||||
* In any event, faking a TX interrupt here solves the problem;
|
||||
@@ -901,7 +901,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
||||
/* Disable the TX interrupt */
|
||||
|
||||
priv->im &= ~UART_IM_TXIM;
|
||||
up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
|
||||
up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
|
||||
}
|
||||
irqrestore(flags);
|
||||
}
|
||||
@@ -917,7 +917,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
|
||||
static bool up_txready(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
|
||||
return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -931,7 +931,7 @@ static bool up_txready(struct uart_dev_s *dev)
|
||||
static bool up_txempty(struct uart_dev_s *dev)
|
||||
{
|
||||
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
|
||||
return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
|
||||
return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -1016,7 +1016,7 @@ int up_putc(int ch)
|
||||
|
||||
up_disableuartint(priv, &im);
|
||||
up_waittxnotfull(priv);
|
||||
up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
|
||||
up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch);
|
||||
|
||||
/* Check for LF */
|
||||
|
||||
@@ -1025,7 +1025,7 @@ int up_putc(int ch)
|
||||
/* Add CR */
|
||||
|
||||
up_waittxnotfull(priv);
|
||||
up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r');
|
||||
up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)'\r');
|
||||
}
|
||||
|
||||
up_waittxnotfull(priv);
|
||||
|
||||
@@ -83,12 +83,12 @@
|
||||
* such case, the following must be expanded).
|
||||
*/
|
||||
|
||||
#if LM3S_NSSI == 0
|
||||
#if LM_NSSI == 0
|
||||
# undef CONFIG_SSI0_DISABLE
|
||||
# define CONFIG_SSI0_DISABLE 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#elif LM3S_NSSI == 1
|
||||
#elif LM_NSSI == 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#endif
|
||||
@@ -102,15 +102,15 @@
|
||||
# define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */
|
||||
# else
|
||||
# define NSSI_ENABLED 1 /* One SSI interface: SSI0 */
|
||||
# define SSI_BASE LM3S_SSI0_BASE
|
||||
# define SSI_IRQ LM3S_IRQ_SSI0
|
||||
# define SSI_BASE LM_SSI0_BASE
|
||||
# define SSI_IRQ LM_IRQ_SSI0
|
||||
# endif
|
||||
#else
|
||||
# ifndef CONFIG_SSI1_DISABLE
|
||||
# define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */
|
||||
# define NSSI_ENABLED 1 /* One SSI interface: SSI1 */
|
||||
# define SSI_BASE LM3S_SSI1_BASE
|
||||
# define SSI_IRQ LM3S_IRQ_SSI1
|
||||
# define SSI_BASE LM_SSI1_BASE
|
||||
# define SSI_IRQ LM_IRQ_SSI1
|
||||
# else
|
||||
# define NSSI_ENABLED 0 /* No SSI interfaces */
|
||||
# endif
|
||||
@@ -124,19 +124,19 @@
|
||||
|
||||
/* The number of (16-bit) words that will fit in the Tx FIFO */
|
||||
|
||||
#define LM3S_TXFIFO_WORDS 8
|
||||
#define LM_TXFIFO_WORDS 8
|
||||
|
||||
/* Configuration settings */
|
||||
|
||||
#ifndef CONFIG_SSI_TXLIMIT
|
||||
# define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2)
|
||||
# define CONFIG_SSI_TXLIMIT (LM_TXFIFO_WORDS/2)
|
||||
#endif
|
||||
|
||||
#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS
|
||||
#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM_TXFIFO_WORDS
|
||||
# error "Invalid range for CONFIG_SSI_TXLIMIT"
|
||||
#endif
|
||||
|
||||
#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2)
|
||||
#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM_TXFIFO_WORDS/2)
|
||||
# error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size"
|
||||
#endif
|
||||
|
||||
@@ -304,10 +304,10 @@ static struct lm_ssidev_s g_ssidev[] =
|
||||
{
|
||||
.ops = &g_spiops,
|
||||
#if NSSI_ENABLED > 1
|
||||
.base = LM3S_SSI0_BASE,
|
||||
.base = LM_SSI0_BASE,
|
||||
#endif
|
||||
#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
|
||||
.irq = LM3S_IRQ_SSI0,
|
||||
.irq = LM_IRQ_SSI0,
|
||||
#endif
|
||||
},
|
||||
#endif
|
||||
@@ -315,10 +315,10 @@ static struct lm_ssidev_s g_ssidev[] =
|
||||
{
|
||||
.ops = &g_spiops,
|
||||
#if NSSI_ENABLED > 1
|
||||
.base = LM3S_SSI1_BASE,
|
||||
.base = LM_SSI1_BASE,
|
||||
#endif
|
||||
#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
|
||||
.irq = LM3S_IRQ_SSI1,
|
||||
.irq = LM_IRQ_SSI1,
|
||||
#endif
|
||||
},
|
||||
#endif
|
||||
@@ -404,9 +404,9 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv)
|
||||
uint32_t retval;
|
||||
uint32_t regval;
|
||||
|
||||
retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
|
||||
retval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
|
||||
regval = (retval & ~SSI_CR1_SSE);
|
||||
ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
|
||||
ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
|
||||
ssivdbg("CR1: %08x\n", regval);
|
||||
return retval;
|
||||
}
|
||||
@@ -430,10 +430,10 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv)
|
||||
|
||||
static void ssi_enable(struct lm_ssidev_s *priv, uint32_t enable)
|
||||
{
|
||||
uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
|
||||
uint32_t regval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
|
||||
regval &= ~SSI_CR1_SSE;
|
||||
regval |= (enable & SSI_CR1_SSE);
|
||||
ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
|
||||
ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
|
||||
ssivdbg("CR1: %08x\n", regval);
|
||||
}
|
||||
|
||||
@@ -484,14 +484,14 @@ static void ssi_semtake(sem_t *sem)
|
||||
static void ssi_txnull(struct lm_ssidev_s *priv)
|
||||
{
|
||||
ssivdbg("TX: ->0xffff\n");
|
||||
ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff);
|
||||
ssi_putreg(priv, LM_SSI_DR_OFFSET, 0xffff);
|
||||
}
|
||||
|
||||
static void ssi_txuint16(struct lm_ssidev_s *priv)
|
||||
{
|
||||
uint16_t *ptr = (uint16_t*)priv->txbuffer;
|
||||
ssivdbg("TX: %p->%04x\n", ptr, *ptr);
|
||||
ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
|
||||
ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
|
||||
priv->txbuffer = (void*)ptr;
|
||||
}
|
||||
|
||||
@@ -499,7 +499,7 @@ static void ssi_txuint8(struct lm_ssidev_s *priv)
|
||||
{
|
||||
uint8_t *ptr = (uint8_t*)priv->txbuffer;
|
||||
ssivdbg("TX: %p->%02x\n", ptr, *ptr);
|
||||
ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
|
||||
ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
|
||||
priv->txbuffer = (void*)ptr;
|
||||
}
|
||||
|
||||
@@ -523,17 +523,17 @@ static void ssi_txuint8(struct lm_ssidev_s *priv)
|
||||
static void ssi_rxnull(struct lm_ssidev_s *priv)
|
||||
{
|
||||
#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE)
|
||||
uint32_t regval = ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
|
||||
uint32_t regval = ssi_getreg(priv, LM_SSI_DR_OFFSET);
|
||||
ssivdbg("RX: discard %04x\n", regval);
|
||||
#else
|
||||
(void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
|
||||
(void)ssi_getreg(priv, LM_SSI_DR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void ssi_rxuint16(struct lm_ssidev_s *priv)
|
||||
{
|
||||
uint16_t *ptr = (uint16_t*)priv->rxbuffer;
|
||||
*ptr = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
|
||||
*ptr = (uint16_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
|
||||
ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
|
||||
priv->rxbuffer = (void*)(++ptr);
|
||||
}
|
||||
@@ -541,7 +541,7 @@ static void ssi_rxuint16(struct lm_ssidev_s *priv)
|
||||
static void ssi_rxuint8(struct lm_ssidev_s *priv)
|
||||
{
|
||||
uint8_t *ptr = (uint8_t*)priv->rxbuffer;
|
||||
*ptr = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
|
||||
*ptr = (uint8_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
|
||||
ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
|
||||
priv->rxbuffer = (void*)(++ptr);
|
||||
}
|
||||
@@ -562,7 +562,7 @@ static void ssi_rxuint8(struct lm_ssidev_s *priv)
|
||||
|
||||
static inline bool ssi_txfifofull(struct lm_ssidev_s *priv)
|
||||
{
|
||||
return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
|
||||
return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -581,7 +581,7 @@ static inline bool ssi_txfifofull(struct lm_ssidev_s *priv)
|
||||
|
||||
static inline bool ssi_rxfifoempty(struct lm_ssidev_s *priv)
|
||||
{
|
||||
return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
|
||||
return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
@@ -657,7 +657,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv)
|
||||
/* Check again... Now have all of the Tx words been sent? */
|
||||
|
||||
#ifndef CONFIG_SSI_POLLWAIT
|
||||
regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
|
||||
regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
|
||||
if (priv->ntxwords > 0)
|
||||
{
|
||||
/* No.. Enable the Tx FIFO interrupt. This interrupt occurs
|
||||
@@ -678,7 +678,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv)
|
||||
|
||||
regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
|
||||
}
|
||||
ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
|
||||
ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
|
||||
#endif /* CONFIG_SSI_POLLWAIT */
|
||||
}
|
||||
return ntxd;
|
||||
@@ -728,7 +728,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv)
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_SSI_POLLWAIT
|
||||
regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
|
||||
regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
|
||||
if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords)
|
||||
{
|
||||
/* There are no more outgoing words to send, but there are
|
||||
@@ -751,7 +751,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv)
|
||||
|
||||
regval &= ~(SSI_IM_RX|SSI_IM_RT);
|
||||
}
|
||||
ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
|
||||
ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
|
||||
#endif /* CONFIG_SSI_POLLWAIT */
|
||||
}
|
||||
|
||||
@@ -829,7 +829,7 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer,
|
||||
flags = irqsave();
|
||||
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
|
||||
priv->ntxwords, priv->nrxwords, priv->nwords,
|
||||
ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
|
||||
ssi_getreg(priv, LM_SSI_SR_OFFSET));
|
||||
|
||||
ntxd = ssi_performtx(priv);
|
||||
|
||||
@@ -842,8 +842,8 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer,
|
||||
|
||||
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
|
||||
priv->ntxwords, priv->nrxwords, priv->nwords,
|
||||
ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
|
||||
ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
|
||||
ssi_getreg(priv, LM_SSI_SR_OFFSET),
|
||||
ssi_getreg(priv, LM_SSI_IM_OFFSET));
|
||||
|
||||
/* Wait for the transfer to complete. Since there is no handshake
|
||||
* with SPI, the following should complete even if there are problems
|
||||
@@ -908,11 +908,11 @@ static inline struct lm_ssidev_s *ssi_mapirq(int irq)
|
||||
switch (irq)
|
||||
{
|
||||
#ifndef CONFIG_SSI0_DISABLE
|
||||
case LM3S_IRQ_SSI0:
|
||||
case LM_IRQ_SSI0:
|
||||
return &g_ssidev[SSI0_NDX];
|
||||
#endif
|
||||
#ifndef CONFIG_SSI1_DISABLE
|
||||
case LM3S_IRQ_SSI1:
|
||||
case LM_IRQ_SSI1:
|
||||
return &g_ssidev[SSI1_NDX];
|
||||
#endif
|
||||
default:
|
||||
@@ -952,8 +952,8 @@ static int ssi_interrupt(int irq, void *context)
|
||||
|
||||
/* Clear pending interrupts */
|
||||
|
||||
regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET);
|
||||
ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval);
|
||||
regval = ssi_getreg(priv, LM_SSI_RIS_OFFSET);
|
||||
ssi_putreg(priv, LM_SSI_ICR_OFFSET, regval);
|
||||
|
||||
/* Check for Rx FIFO overruns */
|
||||
|
||||
@@ -966,7 +966,7 @@ static int ssi_interrupt(int irq, void *context)
|
||||
|
||||
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
|
||||
priv->ntxwords, priv->nrxwords, priv->nwords,
|
||||
ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
|
||||
ssi_getreg(priv, LM_SSI_SR_OFFSET));
|
||||
|
||||
/* Handle outgoing Tx FIFO transfers */
|
||||
|
||||
@@ -978,8 +978,8 @@ static int ssi_interrupt(int irq, void *context)
|
||||
|
||||
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
|
||||
priv->ntxwords, priv->nrxwords, priv->nwords,
|
||||
ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
|
||||
ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
|
||||
ssi_getreg(priv, LM_SSI_SR_OFFSET),
|
||||
ssi_getreg(priv, LM_SSI_IM_OFFSET));
|
||||
|
||||
/* Check if the transfer is complete */
|
||||
|
||||
@@ -987,7 +987,7 @@ static int ssi_interrupt(int irq, void *context)
|
||||
{
|
||||
/* Yes.. Disable all SSI interrupt sources */
|
||||
|
||||
ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
|
||||
ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
|
||||
|
||||
/* Wake up the waiting thread */
|
||||
|
||||
@@ -1135,14 +1135,14 @@ static uint32_t ssi_setfrequencyinternal(struct lm_ssidev_s *priv, uint32_t freq
|
||||
/* Set CPDVSR */
|
||||
|
||||
DEBUGASSERT(cpsdvsr < 255);
|
||||
ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr);
|
||||
ssi_putreg(priv, LM_SSI_CPSR_OFFSET, cpsdvsr);
|
||||
|
||||
/* Set SCR */
|
||||
|
||||
regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
|
||||
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
|
||||
regval &= ~SSI_CR0_SCR_MASK;
|
||||
regval |= (scr << SSI_CR0_SCR_SHIFT);
|
||||
ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
|
||||
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
|
||||
ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
|
||||
|
||||
/* Calcluate the actual frequency */
|
||||
@@ -1235,10 +1235,10 @@ static void ssi_setmodeinternal(struct lm_ssidev_s *priv, enum spi_mode_e mode)
|
||||
|
||||
/* Then set the selected mode: Freescale SPI format, mode0-3 */
|
||||
|
||||
regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
|
||||
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
|
||||
regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
|
||||
regval |= modebits;
|
||||
ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
|
||||
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
|
||||
ssivdbg("CR0: %08x\n", regval);
|
||||
|
||||
/* Save the mode so that subsequent re-configuratins will be faster */
|
||||
@@ -1287,10 +1287,10 @@ static void ssi_setbitsinternal(struct lm_ssidev_s *priv, int nbits)
|
||||
DEBUGASSERT(priv);
|
||||
if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
|
||||
{
|
||||
regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
|
||||
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
|
||||
regval &= ~SSI_CR0_DSS_MASK;
|
||||
regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
|
||||
ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
|
||||
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
|
||||
ssivdbg("CR0: %08x\n", regval);
|
||||
|
||||
priv->nbits = nbits;
|
||||
@@ -1464,9 +1464,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
/* Enable the SSI0 peripheral */
|
||||
|
||||
regval = getreg32(LM3S_SYSCON_RCGC1);
|
||||
regval = getreg32(LM_SYSCON_RCGC1);
|
||||
regval |= SYSCON_RCGC1_SSI0;
|
||||
putreg32(regval, LM3S_SYSCON_RCGC1);
|
||||
putreg32(regval, LM_SYSCON_RCGC1);
|
||||
ssivdbg("RCGC1: %08x\n", regval);
|
||||
|
||||
/* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
|
||||
@@ -1488,9 +1488,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
/* Enable the SSI1 peripheral */
|
||||
|
||||
regval = getreg32(LM3S_SYSCON_RCGC1);
|
||||
regval = getreg32(LM_SYSCON_RCGC1);
|
||||
regval |= SYSCON_RCGC1_SSI1;
|
||||
putreg32(regval, LM3S_SYSCON_RCGC1);
|
||||
putreg32(regval, LM_SYSCON_RCGC1);
|
||||
ssivdbg("RCGC1: %08x\n", regval);
|
||||
|
||||
/* Configure SSI1 GPIOs */
|
||||
@@ -1518,11 +1518,11 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
|
||||
/* Set all CR1 fields to reset state. This will be master mode. */
|
||||
|
||||
ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0);
|
||||
ssi_putreg(priv, LM_SSI_CR1_OFFSET, 0);
|
||||
|
||||
/* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */
|
||||
|
||||
ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0);
|
||||
ssi_putreg(priv, LM_SSI_CR0_OFFSET, 0);
|
||||
|
||||
/* Set the initial mode to mode 0. The application may override
|
||||
* this initial setting using the setmode() method.
|
||||
@@ -1547,7 +1547,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
|
||||
* while there is an SSI transfer in progress.
|
||||
*/
|
||||
|
||||
ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
|
||||
ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
|
||||
|
||||
/* Attach the interrupt */
|
||||
|
||||
|
||||
@@ -159,7 +159,7 @@ static inline void lm_plllock(void)
|
||||
{
|
||||
/* Check if the PLL is locked on */
|
||||
|
||||
if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
|
||||
if ((getreg32(LM_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
|
||||
{
|
||||
/* Yes.. return now */
|
||||
|
||||
@@ -191,17 +191,17 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
|
||||
/* Get the current values of the RCC and RCC2 registers */
|
||||
|
||||
rcc = getreg32(LM3S_SYSCON_RCC);
|
||||
rcc2 = getreg32(LM3S_SYSCON_RCC2);
|
||||
rcc = getreg32(LM_SYSCON_RCC);
|
||||
rcc2 = getreg32(LM_SYSCON_RCC2);
|
||||
|
||||
/* Temporarily bypass the PLL and system clock dividers */
|
||||
|
||||
rcc |= SYSCON_RCC_BYPASS;
|
||||
rcc &= ~(SYSCON_RCC_USESYSDIV);
|
||||
putreg32(rcc, LM3S_SYSCON_RCC);
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
|
||||
rcc2 |= SYSCON_RCC2_BYPASS2;
|
||||
putreg32(rcc2, LM3S_SYSCON_RCC2);
|
||||
putreg32(rcc2, LM_SYSCON_RCC2);
|
||||
|
||||
/* We are probably using the main oscillator. The main oscillator is disabled on
|
||||
* reset and so probably must be enabled here. The internal oscillator is enabled
|
||||
@@ -214,7 +214,7 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
/* Enable any selected osciallators (but don't disable any yet) */
|
||||
|
||||
rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
|
||||
putreg32(rcc, LM3S_SYSCON_RCC);
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
|
||||
/* Wait for the newly selected oscillator(s) to settle. This is tricky because
|
||||
* the time that we wait can be significant and is determined by the previous
|
||||
@@ -234,7 +234,7 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
|
||||
/* Clear the PLL lock interrupt */
|
||||
|
||||
putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC);
|
||||
putreg32(SYSCON_MISC_PLLLMIS, LM_SYSCON_MISC);
|
||||
|
||||
/* Write the new RCC/RCC2 values. Order depends upon whether RCC2 or RCC
|
||||
* is currently enabled.
|
||||
@@ -242,13 +242,13 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
|
||||
if (rcc2 & SYSCON_RCC2_USERCC2)
|
||||
{
|
||||
putreg32(rcc2, LM3S_SYSCON_RCC2);
|
||||
putreg32(rcc, LM3S_SYSCON_RCC);
|
||||
putreg32(rcc2, LM_SYSCON_RCC2);
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
}
|
||||
else
|
||||
{
|
||||
putreg32(rcc, LM3S_SYSCON_RCC);
|
||||
putreg32(rcc2, LM3S_SYSCON_RCC2);
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
putreg32(rcc2, LM_SYSCON_RCC2);
|
||||
}
|
||||
|
||||
/* Wait for the new crystal value and oscillator source to take effect */
|
||||
@@ -279,8 +279,8 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
|
||||
|
||||
/* Now we can set the final RCC/RCC2 values */
|
||||
|
||||
putreg32(rcc, LM3S_SYSCON_RCC);
|
||||
putreg32(rcc2, LM3S_SYSCON_RCC2);
|
||||
putreg32(rcc, LM_SYSCON_RCC);
|
||||
putreg32(rcc2, LM_SYSCON_RCC2);
|
||||
|
||||
/* Wait for the system divider to be effective */
|
||||
|
||||
@@ -303,13 +303,13 @@ void up_clockconfig(void)
|
||||
* around a PLL bug
|
||||
*/
|
||||
|
||||
putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL);
|
||||
putreg32(SYSCON_LPDOPCTL_2750MV, LM_SYSCON_LDOPCTL);
|
||||
#endif
|
||||
|
||||
/* Set the clocking to run with the default settings provided in the board.h
|
||||
* header file
|
||||
*/
|
||||
|
||||
lm_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE);
|
||||
lm_clockconfig(LM_RCC_VALUE, LM_RCC2_VALUE);
|
||||
}
|
||||
|
||||
|
||||
@@ -130,7 +130,7 @@ void up_timerinit(void)
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
(void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr);
|
||||
(void)irq_attach(LM_IRQ_SYSTICK, (xcpt_t)up_timerisr);
|
||||
|
||||
/* Enable SysTick interrupts */
|
||||
|
||||
@@ -138,5 +138,5 @@ void up_timerinit(void)
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(LM3S_IRQ_SYSTICK);
|
||||
up_enable_irq(LM_IRQ_SYSTICK);
|
||||
}
|
||||
|
||||
+201
-201
@@ -421,214 +421,214 @@ lm_vectors:
|
||||
.type handlers, function
|
||||
.thumb_func
|
||||
handlers:
|
||||
HANDLER lm_reserved, LM3S_IRQ_RESERVED /* Unexpected/reserved vector */
|
||||
HANDLER lm_nmi, LM3S_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
HANDLER lm_hardfault, LM3S_IRQ_HARDFAULT /* Vector 3: Hard fault */
|
||||
HANDLER lm_mpu, LM3S_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
|
||||
HANDLER lm_busfault, LM3S_IRQ_BUSFAULT /* Vector 5: Bus fault */
|
||||
HANDLER lm_usagefault, LM3S_IRQ_USAGEFAULT /* Vector 6: Usage fault */
|
||||
HANDLER lm_svcall, LM3S_IRQ_SVCALL /* Vector 11: SVC call */
|
||||
HANDLER lm_dbgmonitor, LM3S_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
|
||||
HANDLER lm_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */
|
||||
HANDLER lm_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */
|
||||
HANDLER lm_reserved, LM_IRQ_RESERVED /* Unexpected/reserved vector */
|
||||
HANDLER lm_nmi, LM_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
|
||||
HANDLER lm_hardfault, LM_IRQ_HARDFAULT /* Vector 3: Hard fault */
|
||||
HANDLER lm_mpu, LM_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
|
||||
HANDLER lm_busfault, LM_IRQ_BUSFAULT /* Vector 5: Bus fault */
|
||||
HANDLER lm_usagefault, LM_IRQ_USAGEFAULT /* Vector 6: Usage fault */
|
||||
HANDLER lm_svcall, LM_IRQ_SVCALL /* Vector 11: SVC call */
|
||||
HANDLER lm_dbgmonitor, LM_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
|
||||
HANDLER lm_pendsv, LM_IRQ_PENDSV /* Vector 14: Penable system service request */
|
||||
HANDLER lm_systick, LM_IRQ_SYSTICK /* Vector 15: System tick */
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
|
||||
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */
|
||||
HANDLER lm_ssi1, LM3S_IRQ_SSI1 /* Vector 50: SSI 1 */
|
||||
HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */
|
||||
HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: SSI 1 */
|
||||
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
|
||||
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
|
||||
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */
|
||||
HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
|
||||
HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
|
||||
HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */
|
||||
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */
|
||||
HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
|
||||
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */
|
||||
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
|
||||
HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
|
||||
HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */
|
||||
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
|
||||
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */
|
||||
HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
|
||||
HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
|
||||
HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */
|
||||
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */
|
||||
HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
|
||||
HANDLER lm_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */
|
||||
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */
|
||||
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
|
||||
HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
|
||||
HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */
|
||||
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */
|
||||
HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
|
||||
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
|
||||
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */
|
||||
HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
|
||||
HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
|
||||
HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */
|
||||
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_cmp2, LM3S_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */
|
||||
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */
|
||||
HANDLER lm_uart2, LM3S_IRQ_UART2 /* Vector 49: UART 2 */
|
||||
HANDLER lm_ssi1, LM3S_IRQ_SSI1 /* Vector 50: GPIO Port H */
|
||||
HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
|
||||
HANDLER lm_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */
|
||||
HANDLER lm_can1, LM3S_IRQ_CAN1 /* Vector 56: CAN 1 */
|
||||
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_usb, LM3S_IRQ_USB /* Vector 60: USB */
|
||||
HANDLER lm_pwm3, LM3S_IRQ_PWM3 /* Vector 61: PWM 3 */
|
||||
HANDLER lm_udmasoft, LM3S_IRQ_UDMASOFT /* Vector 62: uDMA Software */
|
||||
HANDLER lm_udmaerror, LM3S_IRQ_UDMAERROR /* Vector 63: uDMA Error */
|
||||
HANDLER lm_adc1_0, LM3S_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */
|
||||
HANDLER lm_adc1_1, LM3S_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */
|
||||
HANDLER lm_adc1_2, LM3S_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */
|
||||
HANDLER lm_adc1_3, LM3S_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */
|
||||
HANDLER lm_i2s0, LM3S_IRQ_I2S0 /* Vector 68: I2S 0 */
|
||||
HANDLER lm_epi, LM3S_IRQ_EPI /* Vector 69: EPI */
|
||||
HANDLER lm_gpioj, LM3S_IRQ_GPIOJ /* Vector 70: GPIO Port J */
|
||||
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
|
||||
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
|
||||
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
|
||||
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
|
||||
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
|
||||
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
|
||||
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
|
||||
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
|
||||
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
|
||||
HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */
|
||||
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
|
||||
HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
|
||||
HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
|
||||
HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */
|
||||
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
|
||||
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
|
||||
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
|
||||
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
|
||||
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
|
||||
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
|
||||
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
|
||||
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
|
||||
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
|
||||
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
|
||||
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
|
||||
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
|
||||
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
|
||||
HANDLER lm_cmp2, LM_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */
|
||||
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
|
||||
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
|
||||
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
|
||||
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
|
||||
HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */
|
||||
HANDLER lm_uart2, LM_IRQ_UART2 /* Vector 49: UART 2 */
|
||||
HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: GPIO Port H */
|
||||
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
|
||||
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
|
||||
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
|
||||
HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */
|
||||
HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */
|
||||
HANDLER lm_can1, LM_IRQ_CAN1 /* Vector 56: CAN 1 */
|
||||
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
|
||||
HANDLER lm_usb, LM_IRQ_USB /* Vector 60: USB */
|
||||
HANDLER lm_pwm3, LM_IRQ_PWM3 /* Vector 61: PWM 3 */
|
||||
HANDLER lm_udmasoft, LM_IRQ_UDMASOFT /* Vector 62: uDMA Software */
|
||||
HANDLER lm_udmaerror, LM_IRQ_UDMAERROR /* Vector 63: uDMA Error */
|
||||
HANDLER lm_adc1_0, LM_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */
|
||||
HANDLER lm_adc1_1, LM_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */
|
||||
HANDLER lm_adc1_2, LM_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */
|
||||
HANDLER lm_adc1_3, LM_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */
|
||||
HANDLER lm_i2s0, LM_IRQ_I2S0 /* Vector 68: I2S 0 */
|
||||
HANDLER lm_epi, LM_IRQ_EPI /* Vector 69: EPI */
|
||||
HANDLER lm_gpioj, LM_IRQ_GPIOJ /* Vector 70: GPIO Port J */
|
||||
#else
|
||||
# error "Vectors not specified for this LM3S chip"
|
||||
# error "Vectors not specified for this Stellaris chip"
|
||||
#endif
|
||||
|
||||
/* Common IRQ handling logic. On entry here, the return stack is on either
|
||||
|
||||
@@ -431,14 +431,16 @@ AVR32DEV1 Configuration Options
|
||||
Configurations
|
||||
^^^^^^^^^^^^^^
|
||||
|
||||
Each Stellaris LM3S6965 Evaluation Kit configuration is maintained in a
|
||||
sudirectory and can be selected as follow:
|
||||
Each Atmel AVR32DEV configuration is maintained in a sudirectory and
|
||||
can be selected as follow:
|
||||
|
||||
cd tools
|
||||
./configure.sh avr32dev1/<subdir>
|
||||
cd -
|
||||
. ./setenv.sh
|
||||
|
||||
(Or configure.bat in a native Windows environment).
|
||||
|
||||
Where <subdir> is one of the following:
|
||||
|
||||
nsh:
|
||||
|
||||
@@ -344,7 +344,7 @@ Eagle100-specific Configuration Options
|
||||
CONFIG_LM_DISABLE_GPIOH_IRQS=y
|
||||
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
|
||||
|
||||
LM3S6818 specific device driver settings
|
||||
LM3S6918 specific device driver settings
|
||||
|
||||
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
|
||||
console and ttys0 (default is the UART0).
|
||||
@@ -368,7 +368,7 @@ Eagle100-specific Configuration Options
|
||||
Rx FIFO overrun errors. Default: half of the Tx FIFO size (4).
|
||||
|
||||
CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
|
||||
to build the LM3S Ethernet driver
|
||||
to build the Stellaris Ethernet driver
|
||||
CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
|
||||
CONFIG_LM_BOARDMAC - If the board-specific logic can provide
|
||||
a MAC address (via lm_ethernetmac()), then this should be selected.
|
||||
|
||||
@@ -63,7 +63,7 @@
|
||||
* of (400 / 2) / 4 = 50MHz
|
||||
*/
|
||||
|
||||
#define LM3S_SYSDIV 4
|
||||
#define LM_SYSDIV 4
|
||||
#define SYSCLK_FREQUENCY 50000000 /* 50MHz */
|
||||
|
||||
/* Other RCC settings:
|
||||
@@ -74,7 +74,7 @@
|
||||
* - No auto-clock gating reset
|
||||
*/
|
||||
|
||||
#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* RCC2 settings -- RCC2 not used. Other RCC2 settings
|
||||
*
|
||||
@@ -83,7 +83,7 @@
|
||||
* - Not using RCC2
|
||||
*/
|
||||
|
||||
#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
|
||||
@@ -115,9 +115,9 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
@@ -56,12 +56,12 @@
|
||||
* expanded).
|
||||
*/
|
||||
|
||||
#if LM3S_NSSI == 0
|
||||
#if LM_NSSI == 0
|
||||
# undef CONFIG_SSI0_DISABLE
|
||||
# define CONFIG_SSI0_DISABLE 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#elif LM3S_NSSI == 1
|
||||
#elif LM_NSSI == 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#endif
|
||||
|
||||
@@ -63,9 +63,10 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lm_boardinitialize(void)
|
||||
|
||||
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
|
||||
|
||||
/* Get the current value of the user registers */
|
||||
|
||||
user0 = getreg32(LM3S_FLASH_USERREG0);
|
||||
user1 = getreg32(LM3S_FLASH_USERREG1);
|
||||
user0 = getreg32(LM_FLASH_USERREG0);
|
||||
user1 = getreg32(LM_FLASH_USERREG1);
|
||||
|
||||
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
|
||||
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
|
||||
|
||||
@@ -324,7 +324,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
|
||||
|
||||
CONFIG_DRAM_START=0x20000000
|
||||
|
||||
CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
|
||||
CONFIG_ARCH_IRQPRIO - The LM3S9B96 supports interrupt prioritization
|
||||
|
||||
CONFIG_ARCH_IRQPRIO=y
|
||||
|
||||
@@ -348,7 +348,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
|
||||
the delay actually is 100 seconds.
|
||||
|
||||
There are configurations for disabling support for interrupts GPIO ports.
|
||||
GPIOJ must be disabled because it does not exist on the LM3S6918.
|
||||
GPIOJ must be disabled because it does not exist on the LM3S9B96.
|
||||
Additional interrupt support can be disabled if desired to reduce memory
|
||||
footprint.
|
||||
|
||||
@@ -362,7 +362,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
|
||||
CONFIG_LM_DISABLE_GPIOH_IRQS=n
|
||||
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
|
||||
|
||||
LM3S6818 specific device driver settings
|
||||
LM3S9B96 specific device driver settings
|
||||
|
||||
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
|
||||
console and ttys0 (default is the UART0).
|
||||
@@ -386,7 +386,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
|
||||
Rx FIFO overrun errors. Default: half of the Tx FIFO size (4).
|
||||
|
||||
CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
|
||||
to build the LM3S Ethernet driver
|
||||
to build the Stellaris Ethernet driver
|
||||
CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
|
||||
CONFIG_LM_BOARDMAC - If the board-specific logic can provide
|
||||
a MAC address (via lm_ethernetmac()), then this should be selected.
|
||||
|
||||
@@ -64,7 +64,7 @@
|
||||
* of (400 / 2) / 4 = 50MHz
|
||||
*/
|
||||
|
||||
#define LM3S_SYSDIV 4
|
||||
#define LM_SYSDIV 4
|
||||
#define SYSCLK_FREQUENCY 50000000 /* 50MHz */
|
||||
|
||||
/* Other RCC settings:
|
||||
@@ -75,7 +75,7 @@
|
||||
* - No auto-clock gating reset
|
||||
*/
|
||||
|
||||
#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* RCC2 settings -- RCC2 not used. Other RCC2 settings
|
||||
*
|
||||
@@ -84,7 +84,7 @@
|
||||
* - Not using RCC2
|
||||
*/
|
||||
|
||||
#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
|
||||
@@ -116,9 +116,9 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
@@ -57,12 +57,12 @@
|
||||
* expanded).
|
||||
*/
|
||||
|
||||
#if LM3S_NSSI == 0
|
||||
#if LM_NSSI == 0
|
||||
# undef CONFIG_SSI0_DISABLE
|
||||
# define CONFIG_SSI0_DISABLE 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#elif LM3S_NSSI == 1
|
||||
#elif LM_NSSI == 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#endif
|
||||
|
||||
@@ -65,9 +65,10 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lm_boardinitialize(void)
|
||||
|
||||
@@ -81,8 +81,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
|
||||
|
||||
/* Get the current value of the user registers */
|
||||
|
||||
user0 = getreg32(LM3S_FLASH_USERREG0);
|
||||
user1 = getreg32(LM3S_FLASH_USERREG1);
|
||||
user0 = getreg32(LM_FLASH_USERREG0);
|
||||
user1 = getreg32(LM_FLASH_USERREG1);
|
||||
|
||||
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
|
||||
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
|
||||
|
||||
@@ -318,7 +318,7 @@ Stellaris MDL-S2E Reference Design Configuration Options
|
||||
|
||||
CONFIG_DRAM_START=0x20000000
|
||||
|
||||
CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
|
||||
CONFIG_ARCH_IRQPRIO - The LM3S6432 supports interrupt prioritization
|
||||
|
||||
CONFIG_ARCH_IRQPRIO=y
|
||||
|
||||
@@ -389,7 +389,7 @@ Stellaris MDL-S2E Reference Design Configuration Options
|
||||
Rx FIFO overrun errors. Default: half of the Tx FIFO size (4).
|
||||
|
||||
CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
|
||||
to build the LM3S Ethernet driver
|
||||
to build the Stellaris Ethernet driver
|
||||
CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
|
||||
CONFIG_LM_BOARDMAC - This should be set in order to use the
|
||||
MAC address configured in the flash USER registers.
|
||||
|
||||
@@ -63,7 +63,7 @@
|
||||
* of (400 / 2) / 4 = 50MHz
|
||||
*/
|
||||
|
||||
#define LM3S_SYSDIV 4
|
||||
#define LM_SYSDIV 4
|
||||
#define SYSCLK_FREQUENCY 50000000 /* 50MHz */
|
||||
|
||||
/* Other RCC settings:
|
||||
@@ -74,7 +74,7 @@
|
||||
* - No auto-clock gating reset
|
||||
*/
|
||||
|
||||
#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* RCC2 settings -- RCC2 not used. Other RCC2 settings
|
||||
*
|
||||
@@ -83,7 +83,7 @@
|
||||
* - Not using RCC2
|
||||
*/
|
||||
|
||||
#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
|
||||
@@ -117,9 +117,9 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
@@ -55,7 +55,7 @@
|
||||
* expanded).
|
||||
*/
|
||||
|
||||
#if LM3S_NSSI == 0
|
||||
#if LM_NSSI == 0
|
||||
# undef CONFIG_SSI0_DISABLE
|
||||
# define CONFIG_SSI0_DISABLE 1
|
||||
#endif
|
||||
|
||||
@@ -70,9 +70,10 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lm_boardinitialize(void)
|
||||
|
||||
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
|
||||
|
||||
/* Get the current value of the user registers */
|
||||
|
||||
user0 = getreg32(LM3S_FLASH_USERREG0);
|
||||
user1 = getreg32(LM3S_FLASH_USERREG1);
|
||||
user0 = getreg32(LM_FLASH_USERREG0);
|
||||
user1 = getreg32(LM_FLASH_USERREG1);
|
||||
|
||||
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
|
||||
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
|
||||
|
||||
@@ -387,7 +387,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
|
||||
|
||||
CONFIG_DRAM_START=0x20000000
|
||||
|
||||
CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
|
||||
CONFIG_ARCH_IRQPRIO - The LM3S6965 supports interrupt prioritization
|
||||
|
||||
CONFIG_ARCH_IRQPRIO=y
|
||||
|
||||
@@ -411,7 +411,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
|
||||
the delay actually is 100 seconds.
|
||||
|
||||
There are configurations for disabling support for interrupts GPIO ports.
|
||||
GPIOJ must be disabled because it does not exist on the LM3S6918.
|
||||
GPIOJ must be disabled because it does not exist on the LM3S6965.
|
||||
Additional interrupt support can be disabled if desired to reduce memory
|
||||
footprint.
|
||||
|
||||
@@ -425,7 +425,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
|
||||
CONFIG_LM_DISABLE_GPIOH_IRQS=n
|
||||
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
|
||||
|
||||
LM3S6818 specific device driver settings
|
||||
LM3S6965 specific device driver settings
|
||||
|
||||
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
|
||||
console and ttys0 (default is the UART0).
|
||||
@@ -449,7 +449,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
|
||||
Rx FIFO overrun errors. Default: half of the Tx FIFO size (4).
|
||||
|
||||
CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
|
||||
to build the LM3S Ethernet driver
|
||||
to build the Stellaris Ethernet driver
|
||||
CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
|
||||
CONFIG_LM_BOARDMAC - If the board-specific logic can provide
|
||||
a MAC address (via lm_ethernetmac()), then this should be selected.
|
||||
|
||||
@@ -63,7 +63,7 @@
|
||||
* of (400 / 2) / 4 = 50MHz
|
||||
*/
|
||||
|
||||
#define LM3S_SYSDIV 4
|
||||
#define LM_SYSDIV 4
|
||||
#define SYSCLK_FREQUENCY 50000000 /* 50MHz */
|
||||
|
||||
/* Other RCC settings:
|
||||
@@ -74,7 +74,7 @@
|
||||
* - No auto-clock gating reset
|
||||
*/
|
||||
|
||||
#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* RCC2 settings -- RCC2 not used. Other RCC2 settings
|
||||
*
|
||||
@@ -83,7 +83,7 @@
|
||||
* - Not using RCC2
|
||||
*/
|
||||
|
||||
#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
|
||||
@@ -115,9 +115,9 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
@@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
|
||||
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
|
||||
|
||||
#
|
||||
# LM3S Configuration Options
|
||||
# Stellaris Configuration Options
|
||||
#
|
||||
# CONFIG_ARCH_CHIP_LM3S6918 is not set
|
||||
# CONFIG_ARCH_CHIP_LM3S9B96 is not set
|
||||
@@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y
|
||||
CONFIG_LM_DFU=y
|
||||
|
||||
#
|
||||
# Select LM3S Peripheral Support
|
||||
# Select Stellaris Peripheral Support
|
||||
#
|
||||
CONFIG_LM_UART0=y
|
||||
# CONFIG_LM_UART1 is not set
|
||||
@@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y
|
||||
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
|
||||
|
||||
#
|
||||
# LM3S Ethernet Configuration
|
||||
# Stellaris Ethernet Configuration
|
||||
#
|
||||
# CONFIG_LM_ETHLEDS is not set
|
||||
# CONFIG_LM_BOARDMAC is not set
|
||||
@@ -141,7 +141,7 @@ CONFIG_LM_DISABLE_GPIOJ_IRQS=y
|
||||
# CONFIG_M3S_DUMPPACKET is not set
|
||||
|
||||
#
|
||||
# LM3S SSI Configuration
|
||||
# Stellaris SSI Configuration
|
||||
#
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
@@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
|
||||
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
|
||||
|
||||
#
|
||||
# LM3S Configuration Options
|
||||
# Stellaris Configuration Options
|
||||
#
|
||||
# CONFIG_ARCH_CHIP_LM3S6918 is not set
|
||||
# CONFIG_ARCH_CHIP_LM3S9B96 is not set
|
||||
@@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y
|
||||
CONFIG_LM_DFU=y
|
||||
|
||||
#
|
||||
# Select LM3S Peripheral Support
|
||||
# Select Stellaris Peripheral Support
|
||||
#
|
||||
CONFIG_LM_UART0=y
|
||||
# CONFIG_LM_UART1 is not set
|
||||
@@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y
|
||||
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
|
||||
|
||||
#
|
||||
# LM3S SSI Configuration
|
||||
# Stellaris SSI Configuration
|
||||
#
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
@@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
|
||||
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
|
||||
|
||||
#
|
||||
# LM3S Configuration Options
|
||||
# Stellaris Configuration Options
|
||||
#
|
||||
# CONFIG_ARCH_CHIP_LM3S6918 is not set
|
||||
# CONFIG_ARCH_CHIP_LM3S9B96 is not set
|
||||
@@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y
|
||||
CONFIG_LM_DFU=y
|
||||
|
||||
#
|
||||
# Select LM3S Peripheral Support
|
||||
# Select Stellaris Peripheral Support
|
||||
#
|
||||
CONFIG_LM_UART0=y
|
||||
# CONFIG_LM_UART1 is not set
|
||||
@@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y
|
||||
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
|
||||
|
||||
#
|
||||
# LM3S SSI Configuration
|
||||
# Stellaris SSI Configuration
|
||||
#
|
||||
CONFIG_SSI_POLLWAIT=y
|
||||
CONFIG_SSI_TXLIMIT=4
|
||||
|
||||
@@ -56,12 +56,12 @@
|
||||
* expanded).
|
||||
*/
|
||||
|
||||
#if LM3S_NSSI == 0
|
||||
#if LM_NSSI == 0
|
||||
# undef CONFIG_SSI0_DISABLE
|
||||
# define CONFIG_SSI0_DISABLE 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#elif LM3S_NSSI == 1
|
||||
#elif LM_NSSI == 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#endif
|
||||
|
||||
@@ -64,9 +64,10 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lm_boardinitialize(void)
|
||||
|
||||
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
|
||||
|
||||
/* Get the current value of the user registers */
|
||||
|
||||
user0 = getreg32(LM3S_FLASH_USERREG0);
|
||||
user1 = getreg32(LM3S_FLASH_USERREG1);
|
||||
user0 = getreg32(LM_FLASH_USERREG0);
|
||||
user1 = getreg32(LM_FLASH_USERREG1);
|
||||
|
||||
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
|
||||
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
|
||||
|
||||
@@ -371,7 +371,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
|
||||
|
||||
CONFIG_DRAM_START=0x20000000
|
||||
|
||||
CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
|
||||
CONFIG_ARCH_IRQPRIO - The LM3S8962 supports interrupt prioritization
|
||||
|
||||
CONFIG_ARCH_IRQPRIO=y
|
||||
|
||||
@@ -395,7 +395,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
|
||||
the delay actually is 100 seconds.
|
||||
|
||||
There are configurations for disabling support for interrupts GPIO ports.
|
||||
GPIOJ must be disabled because it does not exist on the LM3S6918.
|
||||
GPIOJ must be disabled because it does not exist on the LM3S8962.
|
||||
Additional interrupt support can be disabled if desired to reduce memory
|
||||
footprint.
|
||||
|
||||
@@ -409,7 +409,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
|
||||
CONFIG_LM_DISABLE_GPIOH_IRQS=n
|
||||
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
|
||||
|
||||
LM3S6818 specific device driver settings
|
||||
LM3S8962 specific device driver settings
|
||||
|
||||
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
|
||||
console and ttys0 (default is the UART0).
|
||||
@@ -433,7 +433,7 @@ Stellaris LM3S8962 Evaluation Kit Configuration Options
|
||||
Rx FIFO overrun errors. Default: half of the Tx FIFO size (4).
|
||||
|
||||
CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
|
||||
to build the LM3S Ethernet driver
|
||||
to build the Stellaris Ethernet driver
|
||||
CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
|
||||
CONFIG_LM_BOARDMAC - If the board-specific logic can provide
|
||||
a MAC address (via lm_ethernetmac()), then this should be selected.
|
||||
|
||||
@@ -63,7 +63,7 @@
|
||||
* of (400 / 2) / 4 = 50MHz
|
||||
*/
|
||||
|
||||
#define LM3S_SYSDIV 4
|
||||
#define LM_SYSDIV 4
|
||||
#define SYSCLK_FREQUENCY 50000000 /* 50MHz */
|
||||
|
||||
/* Other RCC settings:
|
||||
@@ -74,7 +74,7 @@
|
||||
* - No auto-clock gating reset
|
||||
*/
|
||||
|
||||
#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* RCC2 settings -- RCC2 not used. Other RCC2 settings
|
||||
*
|
||||
@@ -83,7 +83,7 @@
|
||||
* - Not using RCC2
|
||||
*/
|
||||
|
||||
#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
|
||||
#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
|
||||
|
||||
/* LED definitions ******************************************************************/
|
||||
|
||||
@@ -115,9 +115,9 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
@@ -56,12 +56,12 @@
|
||||
* expanded).
|
||||
*/
|
||||
|
||||
#if LM3S_NSSI == 0
|
||||
#if LM_NSSI == 0
|
||||
# undef CONFIG_SSI0_DISABLE
|
||||
# define CONFIG_SSI0_DISABLE 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#elif LM3S_NSSI == 1
|
||||
#elif LM_NSSI == 1
|
||||
# undef CONFIG_SSI1_DISABLE
|
||||
# define CONFIG_SSI1_DISABLE 1
|
||||
#endif
|
||||
|
||||
@@ -64,9 +64,10 @@
|
||||
* Name: lm_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All LM3S architectures must provide the following entry point. This entry point
|
||||
* is called early in the intitialization -- after all memory has been configured
|
||||
* and mapped but before any devices have been initialized.
|
||||
* All Stellaris architectures must provide the following entry point. This entry
|
||||
* point is called early in the intitialization -- after all memory has been
|
||||
* configured and mapped but before any devices have been initialized.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lm_boardinitialize(void)
|
||||
|
||||
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
|
||||
|
||||
/* Get the current value of the user registers */
|
||||
|
||||
user0 = getreg32(LM3S_FLASH_USERREG0);
|
||||
user1 = getreg32(LM3S_FLASH_USERREG1);
|
||||
user0 = getreg32(LM_FLASH_USERREG0);
|
||||
user1 = getreg32(LM_FLASH_USERREG1);
|
||||
|
||||
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
|
||||
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
|
||||
|
||||
@@ -361,7 +361,7 @@ Code Red IDE
|
||||
crt_emu_cm3_nxp (for LPC17xx parts)
|
||||
crt_emu_a7_nxp (for LPC21/22/23/24 parts)
|
||||
crt_emu_a9_nxp (for LPC31/32 and LPC29xx parts)
|
||||
crt_emu_cm3_lmi (for TI Stellaris LM3S parts
|
||||
crt_emu_cm3_lmi (for TI Stellaris parts)
|
||||
|
||||
wire is one of:
|
||||
|
||||
|
||||
@@ -52,8 +52,6 @@
|
||||
#include "lpc17_internal.h"
|
||||
#include "lpcxpresso_internal.h"
|
||||
|
||||
/* The LM3S6965 Eval Kit microSD CS is on SSI0 */
|
||||
|
||||
#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1)
|
||||
|
||||
/************************************************************************************
|
||||
@@ -98,7 +96,7 @@
|
||||
* Name: lpc17_sspinitialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit.
|
||||
* Called to configure SPI chip select GPIO pins for the LPCXpresso.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
@@ -52,8 +52,6 @@
|
||||
#include "lpc17_internal.h"
|
||||
#include "nucleus2g_internal.h"
|
||||
|
||||
/* The LM3S6965 Eval Kit microSD CS is on SSI0 */
|
||||
|
||||
#if defined(CONFIG_LPC17_SSP0) || defined(CONFIG_LPC17_SSP1)
|
||||
|
||||
/************************************************************************************
|
||||
@@ -98,7 +96,7 @@
|
||||
* Name: lpc17_sspinitialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the LM3S6965 Eval Kit.
|
||||
* Called to configure SPI chip select GPIO pins for the Nucleus 2G.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
|
||||
@@ -112,12 +112,12 @@
|
||||
|
||||
/* Luminary LM3S6918 built-in PHY: 0x07-0x0f, 0x14-0x16, 0x19-0x1f reserved */
|
||||
|
||||
#define MII_LM3S_VSPECIFIC 0x10 /* Vendor-Specific */
|
||||
#define MII_LM3S_INTCS 0x11 /* Interrupt control/status */
|
||||
#define MII_LM3S_DIAGNOSTIC 0x12 /* Diagnostic */
|
||||
#define MII_LM3S_XCVRCONTROL 0x13 /* Transceiver Control */
|
||||
#define MII_LM3S_LEDCONFIG 0x17 /* LED Configuration */
|
||||
#define MII_LM3S_MDICONTROL 0x18 /* Ethernet PHY Management MDI/MDIX Control */
|
||||
#define MII_LM_VSPECIFIC 0x10 /* Vendor-Specific */
|
||||
#define MII_LM_INTCS 0x11 /* Interrupt control/status */
|
||||
#define MII_LM_DIAGNOSTIC 0x12 /* Diagnostic */
|
||||
#define MII_LM_XCVRCONTROL 0x13 /* Transceiver Control */
|
||||
#define MII_LM_LEDCONFIG 0x17 /* LED Configuration */
|
||||
#define MII_LM_MDICONTROL 0x18 /* Ethernet PHY Management MDI/MDIX Control */
|
||||
|
||||
/* Micrel KS8721: 0x15, 0x1b, and 0x1f */
|
||||
|
||||
@@ -323,79 +323,79 @@
|
||||
/* LM3S6918-specific register bit settings **********************************/
|
||||
/* LM3S6918 Vendor-Specific, address 0x10 */
|
||||
|
||||
#define LM3S_VSPECIFIC_RXCC (1 << 0) /* Bit 0: Receive Clock Control*/
|
||||
#define LM3S_VSPECIFIC_PCSBP (1 << 1) /* Bit 1: PCS Bypass */
|
||||
#define LM3S_VSPECIFIC_RVSPOL (1 << 4) /* Bit 4: Receive Data Polarity */
|
||||
#define LM3S_VSPECIFIC_APOL (1 << 5) /* Bit 5: Auto-Polarity Disable */
|
||||
#define LM3S_VSPECIFIC_NL10 (1 << 10) /* Bit 10: Natural Loopback Mode */
|
||||
#define LM3S_VSPECIFIC_SQEI (1 << 11) /* Bit 11: SQE Inhibit Testing */
|
||||
#define LM3S_VSPECIFIC_TXHIM (1 << 12) /* Bit 12: Transmit High Impedance Mode */
|
||||
#define LM3S_VSPECIFIC_INPOL (1 << 14) /* Bit 14: Interrupt Polarity Value*/
|
||||
#define LM3S_VSPECIFIC_RPTR (1 << 15) /* Bit 15: Repeater mode*/
|
||||
#define LM_VSPECIFIC_RXCC (1 << 0) /* Bit 0: Receive Clock Control*/
|
||||
#define LM_VSPECIFIC_PCSBP (1 << 1) /* Bit 1: PCS Bypass */
|
||||
#define LM_VSPECIFIC_RVSPOL (1 << 4) /* Bit 4: Receive Data Polarity */
|
||||
#define LM_VSPECIFIC_APOL (1 << 5) /* Bit 5: Auto-Polarity Disable */
|
||||
#define LM_VSPECIFIC_NL10 (1 << 10) /* Bit 10: Natural Loopback Mode */
|
||||
#define LM_VSPECIFIC_SQEI (1 << 11) /* Bit 11: SQE Inhibit Testing */
|
||||
#define LM_VSPECIFIC_TXHIM (1 << 12) /* Bit 12: Transmit High Impedance Mode */
|
||||
#define LM_VSPECIFIC_INPOL (1 << 14) /* Bit 14: Interrupt Polarity Value*/
|
||||
#define LM_VSPECIFIC_RPTR (1 << 15) /* Bit 15: Repeater mode*/
|
||||
|
||||
/* LM3S6918 Interrupt Control/Status, address 0x11 */
|
||||
|
||||
#define LM3S_INTCS_ANEGCOMPINT (1 << 0) /* Bit 0: Auto-Negotiation Complete Interrupt */
|
||||
#define LM3S_INTCS_RFAULTINT (1 << 1) /* Bit 1: Remote Fault Interrupt */
|
||||
#define LM3S_INTCS_LSCHGINT (1 << 2) /* Bit 2: Link Status Change Interrupt */
|
||||
#define LM3S_INTCS_LPACKINT (1 << 3) /* Bit 3: LP Acknowledge Interrupt */
|
||||
#define LM3S_INTCS_PDFINT (1 << 4) /* Bit 4: Parallel Detection Fault Interrupt */
|
||||
#define LM3S_INTCS_PRXINT (1 << 5) /* Bit 5: Page Receive Interrupt */
|
||||
#define LM3S_INTCS_RXERINT (1 << 6) /* Bit 6: Receive Error Interrupt */
|
||||
#define LM3S_INTCS_JABBERINT (1 << 7) /* Bit 7: Jabber Event Interrupt */
|
||||
#define LM3S_INTCS_ANEGCOMPIE (1 << 8) /* Bit 8: Auto-Negotiation Complete Interrupt Enable */
|
||||
#define LM3S_INTCS_RFAULTIE (1 << 9) /* Bit 9: Remote Fault Interrupt Enable */
|
||||
#define LM3S_INTCS_LSCHGIE (1 << 10) /* Bit 10: Link Status Change Interrupt Enable */
|
||||
#define LM3S_INTCS_LPACKIE (1 << 11) /* Bit 11: LP Acknowledge Interrupt Enable */
|
||||
#define LM3S_INTCS_PDFIE (1 << 12) /* Bit 12: Parallel Detection Fault Interrupt Enable */
|
||||
#define LM3S_INTCS_PRXIE (1 << 13) /* Bit 13: Page Received Interrupt Enable */
|
||||
#define LM3S_INTCS_RXERIE (1 << 14) /* Bit 14: Receive Error Interrupt Enable */
|
||||
#define LM3S_INTCS_JABBERIE (1 << 15) /* Bit 15: Jabber Interrupt Enable */
|
||||
#define LM_INTCS_ANEGCOMPINT (1 << 0) /* Bit 0: Auto-Negotiation Complete Interrupt */
|
||||
#define LM_INTCS_RFAULTINT (1 << 1) /* Bit 1: Remote Fault Interrupt */
|
||||
#define LM_INTCS_LSCHGINT (1 << 2) /* Bit 2: Link Status Change Interrupt */
|
||||
#define LM_INTCS_LPACKINT (1 << 3) /* Bit 3: LP Acknowledge Interrupt */
|
||||
#define LM_INTCS_PDFINT (1 << 4) /* Bit 4: Parallel Detection Fault Interrupt */
|
||||
#define LM_INTCS_PRXINT (1 << 5) /* Bit 5: Page Receive Interrupt */
|
||||
#define LM_INTCS_RXERINT (1 << 6) /* Bit 6: Receive Error Interrupt */
|
||||
#define LM_INTCS_JABBERINT (1 << 7) /* Bit 7: Jabber Event Interrupt */
|
||||
#define LM_INTCS_ANEGCOMPIE (1 << 8) /* Bit 8: Auto-Negotiation Complete Interrupt Enable */
|
||||
#define LM_INTCS_RFAULTIE (1 << 9) /* Bit 9: Remote Fault Interrupt Enable */
|
||||
#define LM_INTCS_LSCHGIE (1 << 10) /* Bit 10: Link Status Change Interrupt Enable */
|
||||
#define LM_INTCS_LPACKIE (1 << 11) /* Bit 11: LP Acknowledge Interrupt Enable */
|
||||
#define LM_INTCS_PDFIE (1 << 12) /* Bit 12: Parallel Detection Fault Interrupt Enable */
|
||||
#define LM_INTCS_PRXIE (1 << 13) /* Bit 13: Page Received Interrupt Enable */
|
||||
#define LM_INTCS_RXERIE (1 << 14) /* Bit 14: Receive Error Interrupt Enable */
|
||||
#define LM_INTCS_JABBERIE (1 << 15) /* Bit 15: Jabber Interrupt Enable */
|
||||
|
||||
/* LM3S6918 Diagnostic, address 0x12 */
|
||||
|
||||
#define LM3S_DIAGNOSTIC_RX_LOCK (1 << 8) /* Bit 8: Receive PLL Lock */
|
||||
#define LM3S_DIAGNOSTIC_RXSD (1 << 9) /* Bit 9: Receive Detection */
|
||||
#define LM3S_DIAGNOSTIC_RATE (1 << 10) /* Bit 10: Rate */
|
||||
#define LM3S_DIAGNOSTIC_DPLX (1 << 11) /* Bit 11: Duplex Mode */
|
||||
#define LM3S_DIAGNOSTIC_ANEGF (1 << 12) /* Bit 12: Auto-Negotiation Failure */
|
||||
#define LM_DIAGNOSTIC_RX_LOCK (1 << 8) /* Bit 8: Receive PLL Lock */
|
||||
#define LM_DIAGNOSTIC_RXSD (1 << 9) /* Bit 9: Receive Detection */
|
||||
#define LM_DIAGNOSTIC_RATE (1 << 10) /* Bit 10: Rate */
|
||||
#define LM_DIAGNOSTIC_DPLX (1 << 11) /* Bit 11: Duplex Mode */
|
||||
#define LM_DIAGNOSTIC_ANEGF (1 << 12) /* Bit 12: Auto-Negotiation Failure */
|
||||
|
||||
/* LM3S6918 Transceiver Control, address 0x13 */
|
||||
|
||||
#define LM3S_XCVRCONTROL_TXO_SHIFT 14 /* Bits 15-14: Transmit Amplitude Selection */
|
||||
#define LM3S_XCVRCONTROL_TXO_MASK (3 << LM3S_XCVRCONTROL_TXO_SHIFT)
|
||||
#define LM3S_XCVRCONTROL_TXO_00DB (0 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.0dB of insertion loss */
|
||||
#define LM3S_XCVRCONTROL_TXO_04DB (1 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.4dB of insertion loss */
|
||||
#define LM3S_XCVRCONTROL_TXO_08DB (2 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 0.8dB of insertion loss */
|
||||
#define LM3S_XCVRCONTROL_TXO_12DB (3 << LM3S_XCVRCONTROL_TXO_SHIFT) /* Gain 1.2dB of insertion loss */
|
||||
#define LM_XCVRCONTROL_TXO_SHIFT 14 /* Bits 15-14: Transmit Amplitude Selection */
|
||||
#define LM_XCVRCONTROL_TXO_MASK (3 << LM_XCVRCONTROL_TXO_SHIFT)
|
||||
#define LM_XCVRCONTROL_TXO_00DB (0 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 0.0dB of insertion loss */
|
||||
#define LM_XCVRCONTROL_TXO_04DB (1 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 0.4dB of insertion loss */
|
||||
#define LM_XCVRCONTROL_TXO_08DB (2 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 0.8dB of insertion loss */
|
||||
#define LM_XCVRCONTROL_TXO_12DB (3 << LM_XCVRCONTROL_TXO_SHIFT) /* Gain 1.2dB of insertion loss */
|
||||
|
||||
/* LM3S6918 LED Configuration, address 0x17 */
|
||||
|
||||
#define LM3S_LEDCONFIG_LED0_SHIFT (0) /* Bits 3-0: LED0 Source */
|
||||
#define LM3S_LEDCONFIG_LED0_MASK (0x0f << LM3S_LEDCONFIG_LED0_SHIFT)
|
||||
#define LM3S_LEDCONFIG_LED0_LINKOK (0 << LM3S_LEDCONFIG_LED0_SHIFT) /* Link OK */
|
||||
#define LM3S_LEDCONFIG_LED0_RXTX (1 << LM3S_LEDCONFIG_LED0_SHIFT) /* RX or TX activity */
|
||||
#define LM3S_LEDCONFIG_LED0_100BASET (5 << LM3S_LEDCONFIG_LED0_SHIFT) /* 100BASE-TX mode */
|
||||
#define LM3S_LEDCONFIG_LED0_10BASET (6 << LM3S_LEDCONFIG_LED0_SHIFT) /* 10BASE-T mode */
|
||||
#define LM3S_LEDCONFIG_LED0_FDUPLEX (7 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */
|
||||
#define LM3S_LEDCONFIG_LED0_OKRXTX (8 << LM3S_LEDCONFIG_LED0_SHIFT) /* Full duplex */
|
||||
#define LM3S_LEDCONFIG_LED1_SHIFT (4) /* Bits 7-4: LED1 Source */
|
||||
#define LM3S_LEDCONFIG_LED1_MASK (0x0f << LM3S_LEDCONFIG_LED1_SHIFT)
|
||||
#define LM3S_LEDCONFIG_LED1_LINKOK (0 << LM3S_LEDCONFIG_LED1_SHIFT) /* Link OK */
|
||||
#define LM3S_LEDCONFIG_LED1_RXTX (1 << LM3S_LEDCONFIG_LED1_SHIFT) /* RX or TX activity */
|
||||
#define LM3S_LEDCONFIG_LED1_100BASET (5 << LM3S_LEDCONFIG_LED1_SHIFT) /* 100BASE-TX mode */
|
||||
#define LM3S_LEDCONFIG_LED1_10BASET (6 << LM3S_LEDCONFIG_LED1_SHIFT) /* 10BASE-T mode */
|
||||
#define LM3S_LEDCONFIG_LED1_FDUPLEX (7 << LM3S_LEDCONFIG_LED1_SHIFT) /* Full duplex */
|
||||
#define LM3S_LEDCONFIG_LED1_OKRXTX (8 << LM3S_LEDCONFIG_LED1_SHIFT) /* Full duplex */
|
||||
#define LM_LEDCONFIG_LED0_SHIFT (0) /* Bits 3-0: LED0 Source */
|
||||
#define LM_LEDCONFIG_LED0_MASK (0x0f << LM_LEDCONFIG_LED0_SHIFT)
|
||||
#define LM_LEDCONFIG_LED0_LINKOK (0 << LM_LEDCONFIG_LED0_SHIFT) /* Link OK */
|
||||
#define LM_LEDCONFIG_LED0_RXTX (1 << LM_LEDCONFIG_LED0_SHIFT) /* RX or TX activity */
|
||||
#define LM_LEDCONFIG_LED0_100BASET (5 << LM_LEDCONFIG_LED0_SHIFT) /* 100BASE-TX mode */
|
||||
#define LM_LEDCONFIG_LED0_10BASET (6 << LM_LEDCONFIG_LED0_SHIFT) /* 10BASE-T mode */
|
||||
#define LM_LEDCONFIG_LED0_FDUPLEX (7 << LM_LEDCONFIG_LED0_SHIFT) /* Full duplex */
|
||||
#define LM_LEDCONFIG_LED0_OKRXTX (8 << LM_LEDCONFIG_LED0_SHIFT) /* Full duplex */
|
||||
#define LM_LEDCONFIG_LED1_SHIFT (4) /* Bits 7-4: LED1 Source */
|
||||
#define LM_LEDCONFIG_LED1_MASK (0x0f << LM_LEDCONFIG_LED1_SHIFT)
|
||||
#define LM_LEDCONFIG_LED1_LINKOK (0 << LM_LEDCONFIG_LED1_SHIFT) /* Link OK */
|
||||
#define LM_LEDCONFIG_LED1_RXTX (1 << LM_LEDCONFIG_LED1_SHIFT) /* RX or TX activity */
|
||||
#define LM_LEDCONFIG_LED1_100BASET (5 << LM_LEDCONFIG_LED1_SHIFT) /* 100BASE-TX mode */
|
||||
#define LM_LEDCONFIG_LED1_10BASET (6 << LM_LEDCONFIG_LED1_SHIFT) /* 10BASE-T mode */
|
||||
#define LM_LEDCONFIG_LED1_FDUPLEX (7 << LM_LEDCONFIG_LED1_SHIFT) /* Full duplex */
|
||||
#define LM_LEDCONFIG_LED1_OKRXTX (8 << LM_LEDCONFIG_LED1_SHIFT) /* Full duplex */
|
||||
|
||||
/* LM3S6918 MDI/MDIX Control, address 0x18 */
|
||||
|
||||
#define LM3S_MDICONTROL_MDIXSD_SHIFT (0) /* Bits 3-0: Auto-Switching Seed */
|
||||
#define LM3S_MDICONTROL_MDIXSD_MASK (0x0f << LM3S_MDICONTROL_MDIXSD_SHIFT)
|
||||
#define LM3S_MDICONTROL_MDIXCM (1 << 4) /* Bit 4: Auto-Switching Complete */
|
||||
#define LM3S_MDICONTROL_MDIX (1 << 5) /* Bit 5: Auto-Switching Configuration */
|
||||
#define LM3S_MDICONTROL_AUTOSW (1 << 6) /* Bit 6: Auto-Switching Enable */
|
||||
#define LM3S_MDICONTROL_PDMODE (1 << 7) /* Bit 7: Parallel Detection Mode */
|
||||
#define LM_MDICONTROL_MDIXSD_SHIFT (0) /* Bits 3-0: Auto-Switching Seed */
|
||||
#define LM_MDICONTROL_MDIXSD_MASK (0x0f << LM_MDICONTROL_MDIXSD_SHIFT)
|
||||
#define LM_MDICONTROL_MDIXCM (1 << 4) /* Bit 4: Auto-Switching Complete */
|
||||
#define LM_MDICONTROL_MDIX (1 << 5) /* Bit 5: Auto-Switching Configuration */
|
||||
#define LM_MDICONTROL_AUTOSW (1 << 6) /* Bit 6: Auto-Switching Enable */
|
||||
#define LM_MDICONTROL_PDMODE (1 << 7) /* Bit 7: Parallel Detection Mode */
|
||||
|
||||
/* KS8921-specific register bit settings ************************************/
|
||||
/* KS8921 MII Control register bit definitions (not in 802.3) */
|
||||
@@ -430,26 +430,26 @@
|
||||
|
||||
/* KS8921 10BASE-TX PHY control register */
|
||||
|
||||
#define KS8721_10BTCR_BIT0 (1 << 0) /* Bit 0: xxx */
|
||||
#define KS8721_10BTCR_BIT1 (1 << 1) /* Bit 1: xxx */
|
||||
#define KS8721_10BTCR_MODE_SHIFT (2) /* Bits 2-4: Operation Mode Indication */
|
||||
#define KS8721_10BTCR_MODE_MASK (7 << KS8721_10BTCR_MODE_SHIFT)
|
||||
# define KS8721_10BTCR_MODE_ANEG (0 << KS8721_10BTCR_MODE_SHIFT) /* Still in auto-negotiation */
|
||||
# define KS8721_10BTCR_MODE_10BTHD (1 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T half-duplex */
|
||||
# define KS8721_10BTCR_MODE_100BTHD (2 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE_t half-duplex */
|
||||
# define KS8721_10BTCR_MODE_DEFAULT (3 << KS8721_10BTCR_MODE_SHIFT) /* Default */
|
||||
# define KS8721_10BTCR_MODE_10BTFD (5 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T full duplex */
|
||||
# define KS8721_10BTCR_MODE_100BTFD (6 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE-T full duplex */
|
||||
# define KS8721_10BTCR_MODE_ISOLATE (7 << KS8721_10BTCR_MODE_SHIFT) /* PHY/MII isolate */
|
||||
#define KS8721_10BTCR_ISOLATE (1 << 5) /* Bit 5: PHY isolate */
|
||||
#define KS8721_10BTCR_PAUSE (1 << 6) /* Bit 6: Enable pause */
|
||||
#define KS8721_10BTCR_ANEGCOMP (1 << 7) /* Bit 7: Auto-negotiation complete */
|
||||
#define KS8721_10BTCR_JABBERE (1 << 8) /* Bit 8: Enable Jabber */
|
||||
#define KS8721_10BTCR_INTLVL (1 << 9) /* Bit 9: Interrupt level */
|
||||
#define KS8721_10BTCR_POWER (1 << 10) /* Bit 10: Power saving */
|
||||
#define KS8721_10BTCR_FORCE (1 << 11) /* Bit 11: Force link */
|
||||
#define KS8721_10BTCR_ENERGY (1 << 12) /* Bit 12: Energy detect */
|
||||
#define KS8721_10BTCR_PAIRSWAPD (1 << 13) /* Bit 13: Pairswap disable */
|
||||
#define KS8721_10BTCR_BIT0 (1 << 0) /* Bit 0: xxx */
|
||||
#define KS8721_10BTCR_BIT1 (1 << 1) /* Bit 1: xxx */
|
||||
#define KS8721_10BTCR_MODE_SHIFT (2) /* Bits 2-4: Operation Mode Indication */
|
||||
#define KS8721_10BTCR_MODE_MASK (7 << KS8721_10BTCR_MODE_SHIFT)
|
||||
# define KS8721_10BTCR_MODE_ANEG (0 << KS8721_10BTCR_MODE_SHIFT) /* Still in auto-negotiation */
|
||||
# define KS8721_10BTCR_MODE_10BTHD (1 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T half-duplex */
|
||||
# define KS8721_10BTCR_MODE_100BTHD (2 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE_t half-duplex */
|
||||
# define KS8721_10BTCR_MODE_DEFAULT (3 << KS8721_10BTCR_MODE_SHIFT) /* Default */
|
||||
# define KS8721_10BTCR_MODE_10BTFD (5 << KS8721_10BTCR_MODE_SHIFT) /* 10BASE-T full duplex */
|
||||
# define KS8721_10BTCR_MODE_100BTFD (6 << KS8721_10BTCR_MODE_SHIFT) /* 100BASE-T full duplex */
|
||||
# define KS8721_10BTCR_MODE_ISOLATE (7 << KS8721_10BTCR_MODE_SHIFT) /* PHY/MII isolate */
|
||||
#define KS8721_10BTCR_ISOLATE (1 << 5) /* Bit 5: PHY isolate */
|
||||
#define KS8721_10BTCR_PAUSE (1 << 6) /* Bit 6: Enable pause */
|
||||
#define KS8721_10BTCR_ANEGCOMP (1 << 7) /* Bit 7: Auto-negotiation complete */
|
||||
#define KS8721_10BTCR_JABBERE (1 << 8) /* Bit 8: Enable Jabber */
|
||||
#define KS8721_10BTCR_INTLVL (1 << 9) /* Bit 9: Interrupt level */
|
||||
#define KS8721_10BTCR_POWER (1 << 10) /* Bit 10: Power saving */
|
||||
#define KS8721_10BTCR_FORCE (1 << 11) /* Bit 11: Force link */
|
||||
#define KS8721_10BTCR_ENERGY (1 << 12) /* Bit 12: Energy detect */
|
||||
#define KS8721_10BTCR_PAIRSWAPD (1 << 13) /* Bit 13: Pairswap disable */
|
||||
|
||||
/****************************************************************************
|
||||
* Type Definitions
|
||||
|
||||
Reference in New Issue
Block a user