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drivers/imu/bosch/bmi088: add more time between configure and FIFO_READ
- new FIFO_RESET state used to give the sensor more time after successful configuration before sampling begins Co-authored-by: Mathieu Bresciani <brescianimathieu@gmail.com>
This commit is contained in:
co-authored by
Mathieu Bresciani
parent
1134d5338f
commit
a18e07e525
@@ -73,6 +73,7 @@ protected:
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RESET,
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WAIT_FOR_RESET,
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CONFIGURE,
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FIFO_RESET,
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FIFO_READ,
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} _state{STATE::RESET};
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@@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (c) 2020-2021 PX4 Development Team. All rights reserved.
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* Copyright (c) 2020-2023 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -120,6 +120,7 @@ void BMI088_Accelerometer::RunImpl()
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case STATE::RESET:
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// ACC_SOFTRESET: Writing a value of 0xB6 to this register resets the sensor
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RegisterWrite(Register::ACC_SOFTRESET, 0xB6);
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DataReadyInterruptDisable();
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_reset_timestamp = now;
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_failure_count = 0;
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_state = STATE::WAIT_FOR_RESET;
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@@ -152,21 +153,9 @@ void BMI088_Accelerometer::RunImpl()
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case STATE::CONFIGURE:
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if (Configure()) {
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// if configure succeeded then start reading from FIFO
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_state = STATE::FIFO_READ;
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if (DataReadyInterruptConfigure()) {
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_data_ready_interrupt_enabled = true;
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// backup schedule as a watchdog timeout
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ScheduleDelayed(100_ms);
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} else {
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_data_ready_interrupt_enabled = false;
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ScheduleOnInterval(_fifo_empty_interval_us, _fifo_empty_interval_us);
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}
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FIFOReset();
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// if configure succeeded then reset the FIFO
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_state = STATE::FIFO_RESET;
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ScheduleDelayed(10_ms);
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} else {
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// CONFIGURE not complete
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@@ -183,6 +172,25 @@ void BMI088_Accelerometer::RunImpl()
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break;
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case STATE::FIFO_RESET:
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// if configure succeeded then start reading from FIFO
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_state = STATE::FIFO_READ;
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FIFOReset();
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if (DataReadyInterruptConfigure()) {
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_data_ready_interrupt_enabled = true;
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// backup schedule as a watchdog timeout
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ScheduleDelayed(100_ms);
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} else {
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_data_ready_interrupt_enabled = false;
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ScheduleOnInterval(_fifo_empty_interval_us, _fifo_empty_interval_us);
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}
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break;
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case STATE::FIFO_READ: {
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hrt_abstime timestamp_sample = now;
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uint8_t samples = 0;
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@@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (c) 2020-2021 PX4 Development Team. All rights reserved.
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* Copyright (c) 2020-2023 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -102,6 +102,7 @@ void BMI088_Gyroscope::RunImpl()
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// GYRO_SOFTRESET: Writing a value of 0xB6 to this register resets the sensor.
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// Following a delay of 30 ms, all configuration settings are overwritten with their reset value.
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RegisterWrite(Register::GYRO_SOFTRESET, 0xB6);
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DataReadyInterruptDisable();
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_reset_timestamp = now;
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_failure_count = 0;
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_state = STATE::WAIT_FOR_RESET;
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@@ -112,7 +113,7 @@ void BMI088_Gyroscope::RunImpl()
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if ((RegisterRead(Register::GYRO_CHIP_ID) == ID)) {
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// if reset succeeded then configure
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_state = STATE::CONFIGURE;
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ScheduleDelayed(1_ms);
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ScheduleDelayed(10_ms);
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} else {
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// RESET not complete
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@@ -131,21 +132,9 @@ void BMI088_Gyroscope::RunImpl()
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case STATE::CONFIGURE:
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if (Configure()) {
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// if configure succeeded then start reading from FIFO
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_state = STATE::FIFO_READ;
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if (DataReadyInterruptConfigure()) {
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_data_ready_interrupt_enabled = true;
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// backup schedule as a watchdog timeout
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ScheduleDelayed(100_ms);
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} else {
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_data_ready_interrupt_enabled = false;
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ScheduleOnInterval(_fifo_empty_interval_us, _fifo_empty_interval_us);
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}
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FIFOReset();
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// if configure succeeded then reset the FIFO
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_state = STATE::FIFO_RESET;
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ScheduleDelayed(10_ms);
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} else {
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// CONFIGURE not complete
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@@ -162,6 +151,25 @@ void BMI088_Gyroscope::RunImpl()
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break;
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case STATE::FIFO_RESET:
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// if configure succeeded then start reading from FIFO
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_state = STATE::FIFO_READ;
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FIFOReset();
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if (DataReadyInterruptConfigure()) {
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_data_ready_interrupt_enabled = true;
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// backup schedule as a watchdog timeout
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ScheduleDelayed(100_ms);
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} else {
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_data_ready_interrupt_enabled = false;
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ScheduleOnInterval(_fifo_empty_interval_us, _fifo_empty_interval_us);
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}
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break;
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case STATE::FIFO_READ: {
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hrt_abstime timestamp_sample = 0;
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