mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-11-08 17:21:36 +08:00
imxrt:ADC & LPADC bifurcation and restructuring
This commit is contained in:
David Sidrane
@@ -32,4 +32,14 @@
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****************************************************************************/
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#pragma once
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#include "../../../imxrt/include/px4_arch/adc.h"
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#include <board_config.h>
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#if !defined(HW_REV_VER_ADC_BASE)
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# define HW_REV_VER_ADC_BASE IMXRT_ADC1_BASE
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#endif
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#if !defined(SYSTEM_ADC_BASE)
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# define SYSTEM_ADC_BASE IMXRT_ADC1_BASE
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#endif
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#include <px4_platform/adc.h>
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@@ -58,30 +58,59 @@ typedef uint32_t adc_chan_t;
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#define REG(base_address, _reg) _REG((base_address) + (_reg))
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#define rHC0(base_address) REG(base_address, IMXRT_ADC_HC0_OFFSET) /* Control register for hardware triggers */
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#define rHC1(base_address) REG(base_address, IMXRT_ADC_HC1_OFFSET) /* Control register for hardware triggers */
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#define rHC2(base_address) REG(base_address, IMXRT_ADC_HC2_OFFSET) /* Control register for hardware triggers */
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#define rHC3(base_address) REG(base_address, IMXRT_ADC_HC3_OFFSET) /* Control register for hardware triggers */
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#define rHC4(base_address) REG(base_address, IMXRT_ADC_HC4_OFFSET) /* Control register for hardware triggers */
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#define rHC5(base_address) REG(base_address, IMXRT_ADC_HC5_OFFSET) /* Control register for hardware triggers */
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#define rHC6(base_address) REG(base_address, IMXRT_ADC_HC6_OFFSET) /* Control register for hardware triggers */
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#define rHC7(base_address) REG(base_address, IMXRT_ADC_HC7_OFFSET) /* Control register for hardware triggers */
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#define rHS(base_address) REG(base_address, IMXRT_ADC_HS_OFFSET) /* Status register for HW triggers */
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#define rR0(base_address) REG(base_address, IMXRT_ADC_R0_OFFSET) /* Data result register for HW triggers */
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#define rR1(base_address) REG(base_address, IMXRT_ADC_R1_OFFSET) /* Data result register for HW triggers */
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#define rR2(base_address) REG(base_address, IMXRT_ADC_R2_OFFSET) /* Data result register for HW triggers */
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#define rR3(base_address) REG(base_address, IMXRT_ADC_R3_OFFSET) /* Data result register for HW triggers */
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#define rR4(base_address) REG(base_address, IMXRT_ADC_R4_OFFSET) /* Data result register for HW triggers */
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#define rR5(base_address) REG(base_address, IMXRT_ADC_R5_OFFSET) /* Data result register for HW triggers */
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#define rR6(base_address) REG(base_address, IMXRT_ADC_R6_OFFSET) /* Data result register for HW triggers */
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#define rR7(base_address) REG(base_address, IMXRT_ADC_R7_OFFSET) /* Data result register for HW triggers */
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#define rCFG(base_address) REG(base_address, IMXRT_ADC_CFG_OFFSET) /* Configuration register */
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#define rGC(base_address) REG(base_address, IMXRT_ADC_GC_OFFSET) /* General control register */
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#define rGS(base_address) REG(base_address, IMXRT_ADC_GS_OFFSET) /* General status register */
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#define rCV(base_address) REG(base_address, IMXRT_ADC_CV_OFFSET) /* Compare value register */
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#define rOFS(base_address) REG(base_address, IMXRT_ADC_OFS_OFFSET) /* Offset correction value register */
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#define rCAL(base_address) REG(base_address, IMXRT_ADC_CAL_OFFSET) /* Calibration value register */
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#define rVERID(base_address) REG(base_address, IMXRT_LPADC_VERID_OFFSET) /* Version ID Register */
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#define rPARAM(base_address) REG(base_address, IMXRT_LPADC_PARAM_OFFSET) /* Parameter Register */
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#define rCTRL(base_address) REG(base_address, IMXRT_LPADC_CTRL_OFFSET) /* LPADC Control Register */
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#define rSTAT(base_address) REG(base_address, IMXRT_LPADC_STAT_OFFSET) /* LPADC Status Register */
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#define rIE(base_address) REG(base_address, IMXRT_LPADC_IE_OFFSET) /* Interrupt Enable Register */
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#define rDE(base_address) REG(base_address, IMXRT_LPADC_DE_OFFSET) /* DMA Enable Register */
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#define rCFG(base_address) REG(base_address, IMXRT_LPADC_CFG_OFFSET) /* LPADC Configuration Register */
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#define rPAUSE(base_address) REG(base_address, IMXRT_LPADC_PAUSE_OFFSET) /* LPADC Pause Register */
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#define rFCTRL(base_address) REG(base_address, IMXRT_LPADC_FCTRL_OFFSET) /* LPADC FIFO Control Register */
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#define rSWTRIG(base_address) REG(base_address, IMXRT_LPADC_SWTRIG_OFFSET) /* Software Trigger Register */
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#define rCMDL1(base_address) REG(base_address, IMXRT_LPADC_CMDL1_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH1(base_address) REG(base_address, IMXRT_LPADC_CMDH1_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL2(base_address) REG(base_address, IMXRT_LPADC_CMDL2_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH2(base_address) REG(base_address, IMXRT_LPADC_CMDH2_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL3(base_address) REG(base_address, IMXRT_LPADC_CMDL3_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH3(base_address) REG(base_address, IMXRT_LPADC_CMDH3_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL4(base_address) REG(base_address, IMXRT_LPADC_CMDL4_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH4(base_address) REG(base_address, IMXRT_LPADC_CMDH4_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL5(base_address) REG(base_address, IMXRT_LPADC_CMDL5_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH5(base_address) REG(base_address, IMXRT_LPADC_CMDH5_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL6(base_address) REG(base_address, IMXRT_LPADC_CMDL6_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH6(base_address) REG(base_address, IMXRT_LPADC_CMDH6_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL7(base_address) REG(base_address, IMXRT_LPADC_CMDL7_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH7(base_address) REG(base_address, IMXRT_LPADC_CMDH7_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL8(base_address) REG(base_address, IMXRT_LPADC_CMDL8_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH8(base_address) REG(base_address, IMXRT_LPADC_CMDH8_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL9(base_address) REG(base_address, IMXRT_LPADC_CMDL9_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH9(base_address) REG(base_address, IMXRT_LPADC_CMDH9_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL10(base_address) REG(base_address, IMXRT_LPADC_CMDL10_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH10(base_address) REG(base_address, IMXRT_LPADC_CMDH10_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL11(base_address) REG(base_address, IMXRT_LPADC_CMDL11_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH11(base_address) REG(base_address, IMXRT_LPADC_CMDH11_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL12(base_address) REG(base_address, IMXRT_LPADC_CMDL12_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH12(base_address) REG(base_address, IMXRT_LPADC_CMDH12_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL13(base_address) REG(base_address, IMXRT_LPADC_CMDL13_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH13(base_address) REG(base_address, IMXRT_LPADC_CMDH13_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL14(base_address) REG(base_address, IMXRT_LPADC_CMDL14_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH14(base_address) REG(base_address, IMXRT_LPADC_CMDH14_OFFSET) /* LPADC Command High Buffer Register */
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#define rCMDL15(base_address) REG(base_address, IMXRT_LPADC_CMDL15_OFFSET) /* LPADC Command Low Buffer Register */
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#define rCMDH15(base_address) REG(base_address, IMXRT_LPADC_CMDH15_OFFSET) /* LPADC Command High Buffer Register */
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#define rRESFIFO(base_address) REG(base_address, IMXRT_LPADC_RESFIFO_OFFSET) /* LPADC Data Result FIFO Register */
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#define rTCTRL0(base_address) REG(base_address, IMXRT_LPADC_TCTRL0_OFFSET) /* Trigger Control Register */
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#define rTCTRL1(base_address) REG(base_address, IMXRT_LPADC_TCTRL1_OFFSET) /* Trigger Control Register */
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#define rTCTRL2(base_address) REG(base_address, IMXRT_LPADC_TCTRL2_OFFSET) /* Trigger Control Register */
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#define rTCTRL3(base_address) REG(base_address, IMXRT_LPADC_TCTRL3_OFFSET) /* Trigger Control Register */
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#define rTCTRL4(base_address) REG(base_address, IMXRT_LPADC_TCTRL4_OFFSET) /* Trigger Control Register */
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#define rTCTRL5(base_address) REG(base_address, IMXRT_LPADC_TCTRL5_OFFSET) /* Trigger Control Register */
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#define rTCTRL6(base_address) REG(base_address, IMXRT_LPADC_TCTRL6_OFFSET) /* Trigger Control Register */
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#define rTCTRL7(base_address) REG(base_address, IMXRT_LPADC_TCTRL7_OFFSET) /* Trigger Control Register */
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#define rCV1(base_address) REG(base_address, IMXRT_LPADC_CV1_OFFSET) /* Compare Value Register */
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#define rCV2(base_address) REG(base_address, IMXRT_LPADC_CV2_OFFSET) /* Compare Value Register */
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#define rCV3(base_address) REG(base_address, IMXRT_LPADC_CV3_OFFSET) /* Compare Value Register */
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#define rCV4(base_address) REG(base_address, IMXRT_LPADC_CV4_OFFSET) /* Compare Value Register */
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int px4_arch_adc_init(uint32_t base_address)
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{
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@@ -91,67 +120,57 @@ int px4_arch_adc_init(uint32_t base_address)
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once = true;
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/* Input is Buss Clock 144 Mhz We will use /4 for 36 Mhz */
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/* Input is ADCx_CLK_ROOT_SYS_PLL2_CLK with devide by 6.
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* 528 Mhz / 6 = 88 Mhz.
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*/
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if (base_address == IMXRT_LPADC1_BASE) {
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imxrt_clockall_adc1();
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} else if (base_address == IMXRT_LPADC2_BASE) {
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imxrt_clockall_adc2();
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}
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irqstate_t flags = px4_enter_critical_section();
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rCTRL(base_address) |= IMXRT_LPADC_CTRL_RST;
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rCTRL(base_address) &= ~IMXRT_LPADC_CTRL_RST;
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rCTRL(base_address) |= IMXRT_LPADC_CTRL_RSTFIFO;
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rCFG(base_address) = IMXRT_LPADC_CFG_REFSEL_REFSEL_0 | IMXRT_LPADC_CFG_PWREN | IMXRT_LPADC_CFG_PWRSEL_PWRSEL_3 |
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IMXRT_LPADC_CFG_PUDLY(128);
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rCTRL(base_address) = IMXRT_LPADC_CTRL_ADCEN;
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// imxrt_clockall_adc1();
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rCFG(base_address) = ADC_CFG_ADICLK_IPG | ADC_CFG_MODE_12BIT | \
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ADC_CFG_ADIV_DIV4 | ADC_CFG_ADLSMP | ADC_CFG_ADSTS_7_21 | \
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ADC_CFG_AVGS_4SMPL | ADC_CFG_OVWREN;
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px4_leave_critical_section(flags);
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/* Clear the CALF and begin the calibration */
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/* Read ADC1 vtemp_sensor_plus */
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rGS(base_address) = ADC_GS_CALF;
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rGC(base_address) = ADC_GC_CAL;
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uint32_t guard = 100;
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rCMDL1(base_address) = IMXRT_LPADC_CMDL1_ADCH_ADCH_7;
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while (guard != 0 && (rGS(base_address) & ADC_GC_CAL) == 0) {
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guard--;
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usleep(1);
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}
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while ((rGS(base_address) & ADC_GC_CAL) == ADC_GC_CAL) {
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usleep(100);
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if (rGS(base_address) & ADC_GS_CALF) {
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return -1;
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}
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}
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if ((rHS(base_address) & ADC_HS_COCO0) == 0) {
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return -2;
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}
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if (rGS(base_address) & ADC_GS_CALF) {
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return -3;
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}
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/* dummy read to clear COCO of calibration */
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int32_t r = rR0(base_address);
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UNUSED(r);
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rCMDH1(base_address) = IMXRT_LPADC_CMDH1_STS_STS_5 | IMXRT_LPADC_CMDH1_AVGS_AVGS_2;
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rTCTRL0(base_address) = IMXRT_LPADC_TCTRL0_TCMD_TCMD_1;
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rSTAT(base_address) = IMXRT_LPADC_STAT_FOF;
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/* kick off a sample and wait for it to complete */
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hrt_abstime now = hrt_absolute_time();
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rGC(base_address) = ADC_GC_AVGE;
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rHC0(base_address) = 0xd; // VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
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while (!(rHS(base_address) & ADC_HS_COCO0)) {
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rSWTRIG(base_address) = IMXRT_LPADC_SWTRIG_SWT0;
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while (!(rSTAT(base_address) & IMXRT_LPADC_STAT_RDY)) {
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/* don't wait for more than 500us, since that means something broke -
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* should reset here if we see this
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*/
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if ((hrt_absolute_time() - now) > 500) {
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rCTRL(base_address) &= ~IMXRT_LPADC_CTRL_ADCEN;
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return -4;
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}
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}
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r = rR0(base_address);
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int32_t r = rRESFIFO(base_address) & IMXRT_LPADC_RESFIFO_D_MASK;
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UNUSED(r);
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rCTRL(base_address) &= ~IMXRT_LPADC_CTRL_ADCEN;
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} // once
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return 0;
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@@ -159,7 +178,14 @@ int px4_arch_adc_init(uint32_t base_address)
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void px4_arch_adc_uninit(uint32_t base_address)
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{
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//imxrt_clockoff_adc1();
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rCTRL(base_address) &= ~IMXRT_LPADC_CTRL_ADCEN;
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if (base_address == IMXRT_LPADC1_BASE) {
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imxrt_clockoff_adc1();
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} else if (base_address == IMXRT_LPADC2_BASE) {
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imxrt_clockoff_adc2();
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}
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}
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uint32_t px4_arch_adc_sample(uint32_t base_address, unsigned channel)
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@@ -167,27 +193,36 @@ uint32_t px4_arch_adc_sample(uint32_t base_address, unsigned channel)
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irqstate_t flags = px4_enter_critical_section();
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/* clear any previous COCO0 */
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/* clear any previous results */
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uint16_t result = rR0(base_address);
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rCTRL(base_address) |= IMXRT_LPADC_CTRL_RSTFIFO;
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rHC0(base_address) = channel;
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rCMDL1(base_address) = channel & IMXRT_LPADC_CMDL1_ADCH_MASK;
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rCMDH1(base_address) = IMXRT_LPADC_CMDH1_STS_STS_5 | IMXRT_LPADC_CMDH1_AVGS_AVGS_2;
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rTCTRL0(base_address) = IMXRT_LPADC_TCTRL0_TCMD_TCMD_1;
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rSTAT(base_address) = IMXRT_LPADC_STAT_FOF;
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rCTRL(base_address) = IMXRT_LPADC_CTRL_ADCEN;
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up_udelay(1);
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rSWTRIG(base_address) = IMXRT_LPADC_SWTRIG_SWT0;
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/* wait for the conversion to complete */
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hrt_abstime now = hrt_absolute_time();
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while (!(rHS(base_address) & ADC_HS_COCO0)) {
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while (!(rSTAT(base_address) & IMXRT_LPADC_STAT_RDY)) {
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/* don't wait for more than 10us, since that means something broke
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* should reset here if we see this
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*/
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if ((hrt_absolute_time() - now) > 30) {
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rCTRL(base_address) &= ~IMXRT_LPADC_CTRL_ADCEN;
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px4_leave_critical_section(flags);
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return UINT32_MAX;
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}
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}
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/* read the result and clear COCO0 */
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result = rR0(base_address);
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uint32_t result = rRESFIFO(base_address) & IMXRT_LPADC_RESFIFO_D_MASK;
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rCTRL(base_address) &= ~IMXRT_LPADC_CTRL_ADCEN;
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px4_leave_critical_section(flags);
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return result;
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@@ -32,4 +32,14 @@
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****************************************************************************/
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#pragma once
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#include "../../../imxrt/include/px4_arch/adc.h"
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#include <board_config.h>
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#if !defined(HW_REV_VER_ADC_BASE)
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# define HW_REV_VER_ADC_BASE IMXRT_LPADC1_BASE
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#endif
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#if !defined(SYSTEM_ADC_BASE)
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# define SYSTEM_ADC_BASE IMXRT_LPADC1_BASE
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#endif
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#include <px4_platform/adc.h>
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