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nxphlite-v3:V3.5 HW changes
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@@ -62,24 +62,22 @@
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#include "chip/kinetis_sim.h"
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#include "chip/kinetis_ftm.h"
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/* The FTM prescalers are limited to Divide by 2^n where n={1-7}
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* Therefore we use the FTM2 CH0 on PTA10 drive FTM_CLKIN0 (PCT12)
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* and use this at a 4Mhz clock for FTM0 and FTM3.
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/* The FTM pre-scalers are limited to Divide by 2^n where n={1-7}
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* Therefore we use Y1 at 16 Mhz to drive FTM_CLKIN0 (PCT12)
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* and use this at a 16Mhz clock for FTM0, FTM2 and FTM3.
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*
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* The input frequencies avaialble from FTM2 are 56,28,14,7,3.5
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* So a onshot mode at 8Mhz is not possible. We will use 4Mhz
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*
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* FTM0 will drive FMU_CH1-6, FTM3 will drive IO_CH1-8
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* FTM0 will drive FMU_CH1-4, FTM3 will drive FMU_CH5,6, and
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* U_TRI. FTM2 will be used as input capture on U_ECH
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*/
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#if !defined(BOARD_PWM_FREQ)
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#define BOARD_PWM_FREQ 1000000
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#endif
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#if !defined(BOARD_ONESHOT_FREQ)
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#define BOARD_ONESHOT_FREQ 4000000
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#define BOARD_ONESHOT_FREQ 8000000
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#endif
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#define FTM_SRC_CLOCK_FREQ 4000000
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#define FTM_SRC_CLOCK_FREQ 16000000
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#define MAX_CHANNELS_PER_TIMER 8
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