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Add a driver for SST 25 FLASH

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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4868 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
2012-06-25 21:21:08 +00:00
parent c8f02e00cd
commit 7ec3df6877
9 changed files with 1096 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files
nuttx/ChangeLog
+6 -1
View File
@@ -2926,5 +2926,10 @@
* arch/mips/src/pic32mx/pic32mx-gpio.c: All digital inputs were being
configured as outputs. This is a *critical* bug fix and needs to be
incorporated by any PIC32 users.
* drivers/mtd/sst25.c: Added a driver for the SST 25 SPI-based FLASH
parts.
* configs/mirtoo/src/up_nsh.c: The Mirtoo NSH configuration can now
mount the SST 25 devices so that it can be used for a FAT file system.
There are are, however, some NSH memory usage issues if this configuration
enabled now. Some tuning is still needed.
nuttx/configs/mirtoo/nsh/defconfig
+10
View File
@@ -163,6 +163,14 @@ CONFIG_PIC32MX_IOPORTA=y
CONFIG_PIC32MX_IOPORTB=y
CONFIG_PIC32MX_IOPORTC=y
#
# Mirtoo Board Settings
#
CONFIG_MTD_SST25=n
#CONFIG_SST25_SPIMODE
#CONFIG_SST25_SPIFREQUENCY
CONFIG_SST25_SECTOR512=n
#
# PIC32MX Configuration Settings
#
@@ -346,6 +354,8 @@ CONFIG_DEBUG=n
CONFIG_DEBUG_VERBOSE=n
CONFIG_DEBUG_SYMBOLS=n
CONFIG_DEBUG_SCHED=n
CONFIG_DEBUG_FS=n
CONFIG_DEBUG_SPI=n
CONFIG_HAVE_CXX=n
CONFIG_HAVE_CXXINITIALIZE=n
nuttx/configs/mirtoo/src/Makefile
+6 -2
View File
@@ -44,6 +44,10 @@ ifeq ($(CONFIG_PIC32MX_SPI2),y)
CSRCS += up_spi2.c
endif
ifeq ($(CONFIG_NSH_ARCHINIT),y)
CSRCS += up_nsh.c
endif
AOBJS = $(ASRCS:.S=$(OBJEXT))
COBJS = $(CSRCS:.c=$(OBJEXT))
@@ -53,8 +57,8 @@ OBJS = $(AOBJS) $(COBJS)
ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
ifeq ($(WINTOOL),y)
CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/mips32}"
-I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-I "${shell cygpath -w $(ARCH_SRCDIR)/mips32}"
else
CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/mips32
endif
nuttx/configs/mirtoo/src/up_nsh.c
+126
View File
@@ -0,0 +1,126 @@
/****************************************************************************
* config/mirtoo/src/up_nsh.c
* arch/arm/src/board/up_nsh.c
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdio.h>
#include <errno.h>
#include <debug.h>
#ifdef CONFIG_PIC32MX_SPI2
# include <nuttx/spi.h>
# include <nuttx/mtd.h>
#endif
#include "pic32mx-internal.h"
/****************************************************************************
* Pre-Processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Can't support the SST25 device if it SPI2 or SST25 support is not enabled */
#define HAVE_SST25 1
#if !defined(CONFIG_PIC32MX_SPI2) || !defined(CONFIG_MTD_SST25)
# undef HAVE_SST25
#endif
/* Can't support SST25 features if mountpoints are disabled */
#if defined(CONFIG_DISABLE_MOUNTPOINT)
# undef HAVE_SST25
#endif
/* Use minor device number 0 is not is provided */
#ifndef CONFIG_NSH_SST25MINOR
# define CONFIG_NSH_SST25MINOR 0
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: nsh_archinitialize
*
* Description:
* Perform architecture specific initialization
*
****************************************************************************/
int nsh_archinitialize(void)
{
#ifdef HAVE_SST25
FAR struct spi_dev_s *spi;
FAR struct mtd_dev_s *mtd;
int ret;
/* Get the SPI port */
spi = up_spiinitialize(2);
if (!spi)
{
fdbg("ERROR: Failed to initialize SPI port 2\n");
return -ENODEV;
}
/* Now bind the SPI interface to the SST 25 SPI FLASH driver */
mtd = sst25_initialize(spi);
if (!mtd)
{
fdbg("ERROR: Failed to bind SPI port 2 to the SST 25 FLASH driver\n");
return -ENODEV;
}
/* And finally, use the FTL layer to wrap the MTD driver as a block driver */
ret = ftl_initialize(CONFIG_NSH_SST25MINOR, mtd);
if (ret < 0)
{
fdbg("ERROR: Initialize the FTL layer\n");
return -ENODEV;
}
#endif
return OK;
}
nuttx/configs/mirtoo/src/up_spi2.c
+4 -6
View File
@@ -51,7 +51,7 @@
#include "chip.h"
#include "pic32mx-internal.h"
#include "pic32mx-pps.h"
#include "mirtoo_internal.h"
#include "mirtoo-internal.h"
#ifdef CONFIG_PIC32MX_SPI2
@@ -119,8 +119,6 @@
void weak_function pic32mx_spi2initialize(void)
{
uint32_t regval;
/* Make sure that TRIS pins are set correctly. Configure the SPI pins as digital
* inputs and outputs first.
*/
@@ -171,7 +169,7 @@ void weak_function pic32mx_spi2initialize(void)
struct spi_dev_s;
enum spi_dev_e;
void pic31mx_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
void pic32mx_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
{
spidbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
@@ -185,13 +183,13 @@ void pic31mx_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool s
}
}
uint8_t pic31mx_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
uint8_t pic32mx_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
{
return 0;
}
#ifdef CONFIG_SPI_CMDDATA
int pic31mx_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
int pic32mx_spi2cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd)
{
return 0;
}
nuttx/drivers/mtd/Make.defs
+6 -2
View File
@@ -2,8 +2,8 @@
# drivers/mtd/Make.defs
# This driver supports a block of RAM as a NuttX MTD device
#
# Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <spudmonkey@racsa.co.cr>
# Copyright (C) 2009-2012 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gnutt@nuttx.org>
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
@@ -42,6 +42,10 @@ ifeq ($(CONFIG_MTD_AT24XX),y)
CSRCS += at24xx.c
endif
ifeq ($(CONFIG_MTD_SST25),y)
CSRCS += sst25.c
endif
# Include MTD driver support
DEPPATH += --dep-path mtd
nuttx/drivers/mtd/m25px.c
+26 -2
View File
@@ -1,6 +1,7 @@
/************************************************************************************
* drivers/mtd/m25px.c
* Driver for SPI-based M25P1 (128Kbit), M25P64 (64Mbit), and M25P128 (128Mbit) FLASH
* Driver for SPI-based M25P1 (128Kbit), M25P64 (32Mbit), M25P64 (64Mbit), and
* M25P128 (128Mbit) FLASH (and compatible).
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
@@ -83,6 +84,7 @@
#define M25P_MANUFACTURER CONFIG_MP25P_MANUFACTURER
#define M25P_MEMORY_TYPE 0x20
#define M25P_M25P1_CAPACITY 0x11 /* 1 M-bit */
#define M25P_M25P32_CAPACITY 0x16 /* 32 M-bit */
#define M25P_M25P64_CAPACITY 0x17 /* 64 M-bit */
#define M25P_M25P128_CAPACITY 0x18 /* 128 M-bit */
@@ -96,6 +98,16 @@
#define M25P_M25P1_PAGE_SHIFT 8 /* Page size 1 << 8 = 256 */
#define M25P_M25P1_NPAGES 512
/* M25P32 capacity is 4,194,304 bytes:
* (64 sectors) * (65,536 bytes per sector)
* (16384 pages) * (256 bytes per page)
*/
#define M25P_M25P32_SECTOR_SHIFT 16 /* Sector size 1 << 16 = 65,536 */
#define M25P_M25P32_NSECTORS 64
#define M25P_M25P32_PAGE_SHIFT 8 /* Page size 1 << 8 = 256 */
#define M25P_M25P32_NPAGES 16384
/* M25P64 capacity is 8,338,608 bytes:
* (128 sectors) * (65,536 bytes per sector)
* (32768 pages) * (256 bytes per page)
@@ -128,9 +140,10 @@
#define M25P_PP 0x02 /* 1 Page Program 3 0 1-256 */
#define M25P_SE 0xd8 /* 1 Sector Erase 3 0 0 */
#define M25P_BE 0xc7 /* 1 Bulk Erase 0 0 0 */
#define M25P_DP 0xb9 /* 2 Deep power down 0 0 0 */
#define M25P_RES 0xab /* 2 Read Electronic Signature 0 3 >=1 */
/* NOTE 1: Both parts, NOTE 2: M25P64 only */
/* NOTE 1: All parts, NOTE 2: M25P632/M25P64 */
/* Status register bit definitions */
@@ -146,6 +159,7 @@
# define M25P_SR_BP_UPPERQTR (5 << M25P_SR_BP_SHIFT) /* Upper quarter */
# define M25P_SR_BP_UPPERHALF (6 << M25P_SR_BP_SHIFT) /* Upper half */
# define M25P_SR_BP_ALL (7 << M25P_SR_BP_SHIFT) /* All sectors */
/* Bits 5-6: Unused, read zero */
#define M25P_SR_SRWD (1 << 7) /* Bit 7: Status register write protect */
#define M25P_DUMMY 0xa5
@@ -288,6 +302,16 @@ static inline int m25p_readid(struct m25p_dev_s *priv)
priv->npages = M25P_M25P1_NPAGES;
return OK;
}
else if (capacity == M25P_M25P32_CAPACITY)
{
/* Save the FLASH geometry */
priv->sectorshift = M25P_M25P32_SECTOR_SHIFT;
priv->nsectors = M25P_M25P32_NSECTORS;
priv->pageshift = M25P_M25P32_PAGE_SHIFT;
priv->npages = M25P_M25P32_NPAGES;
return OK;
}
else if (capacity == M25P_M25P64_CAPACITY)
{
/* Save the FLASH geometry */
nuttx/drivers/mtd/sst25.c
+895
View File
@@ -0,0 +1,895 @@
/************************************************************************************
* drivers/mtd/m25px.c
* Driver for SPI-based SST25 FLASH.
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stdlib.h>
#include <unistd.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/kmalloc.h>
#include <nuttx/fs/ioctl.h>
#include <nuttx/spi.h>
#include <nuttx/mtd.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Configuration ********************************************************************/
/* Per the data sheet, MP25P10 parts can be driven with either SPI mode 0 (CPOL=0 and
* CPHA=0) or mode 3 (CPOL=1 and CPHA=1). But I have heard that other devices can
* operated in mode 0 or 1. So you may need to specify CONFIG_SST25_SPIMODE to
* select the best mode for your device. If CONFIG_SST25_SPIMODE is not defined,
* mode 0 will be used.
*/
#ifndef CONFIG_SST25_SPIMODE
# define CONFIG_SST25_SPIMODE SPIDEV_MODE0
#endif
/* SPI Frequency. May be up to 25MHz. */
#ifndef CONFIG_SST25_SPIFREQUENCY
# define CONFIG_SST25_SPIFREQUENCY 20000000
#endif
/* SST25 Instructions ***************************************************************/
/* Command Value Description Addr Data */
/* Dummy */
#define SST25_READ 0x03 /* Read data bytes 3 0 >=1 */
#define SST25_FAST_READ 0x0b /* Higher speed read 3 1 >=1 */
#define SST25_SE 0x20 /* 4Kb Sector erase 3 0 0 */
#define SST25_BE32 0x52 /* 32Kbit block Erase 3 0 0 */
#define SST25_BE64 0xd8 /* 64Kbit block Erase 3 0 0 */
#define SST25_CE 0xc7 /* Chip erase 0 0 0 */
#define SST25_CE_ALT 0x60 /* Chip erase (alternate) 0 0 0 */
#define SST25_BP 0x02 /* Byte program 3 0 1 */
#define SST25_AAI 0xad /* Auto address increment 3 0 >=2 */
#define SST25_RDSR 0x05 /* Read status register 0 0 >=1 */
#define SST25_EWSR 0x50 /* Write enable status 0 0 0 */
#define SST25_WRSR 0x01 /* Write Status Register 0 0 1 */
#define SST25_WREN 0x06 /* Write Enable 0 0 0 */
#define SST25_WRDI 0x04 /* Write Disable 0 0 0 */
#define SST25_RDID 0xab /* Read Identification 0 0 >=1 */
#define SST25_RDID_ALT 0x90 /* Read Identification (alt) 0 0 >=1 */
#define SST25_JEDEC_ID 0x9f /* JEDEC ID read 0 0 >=3 */
#define SST25_EBSY 0x70 /* Enable SO RY/BY# status 0 0 0 */
#define SST25_DBSY 0x80 /* Disable SO RY/BY# status 0 0 0 */
/* SST25 Registers ******************************************************************/
/* Read ID (RDID) register values */
#define SST25_MANUFACTURER 0xbf /* SST manufacturer ID */
#define SST25_VF032_DEVID 0x20 /* SSTVF032B device ID */
/* JEDEC Read ID register values */
#define SST25_JEDEC_MANUFACTURER 0xbf /* SST manufacturer ID */
#define SST25_JEDEC_MEMORY_TYPE 0x25 /* SST25 memory type */
#define SST25_JEDEC_MEMORY_CAPACITY 0x4a /* SST25VF032B memory capacity */
/* Status register bit definitions */
#define SST25_SR_BUSY (1 << 0) /* Bit 0: Write in progress */
#define SST25_SR_WEL (1 << 1) /* Bit 1: Write enable latch bit */
#define SST25_SR_BP_SHIFT (2) /* Bits 2-5: Block protect bits */
#define SST25_SR_BP_MASK (15 << SST25_SR_BP_SHIFT)
# define SST25_SR_BP_NONE (0 << SST25_SR_BP_SHIFT) /* Unprotected */
# define SST25_SR_BP_UPPER64th (1 << SST25_SR_BP_SHIFT) /* Upper 64th */
# define SST25_SR_BP_UPPER32nd (2 << SST25_SR_BP_SHIFT) /* Upper 32nd */
# define SST25_SR_BP_UPPER16th (3 << SST25_SR_BP_SHIFT) /* Upper 16th */
# define SST25_SR_BP_UPPER8th (4 << SST25_SR_BP_SHIFT) /* Upper 8th */
# define SST25_SR_BP_UPPERQTR (5 << SST25_SR_BP_SHIFT) /* Upper quarter */
# define SST25_SR_BP_UPPERHALF (6 << SST25_SR_BP_SHIFT) /* Upper half */
# define SST25_SR_BP_ALL (7 << SST25_SR_BP_SHIFT) /* All sectors */
#define SST25_SR_AAI (1 << 6) /* Bit 6: Auto Address increment programming */
#define SST25_SR_SRWD (1 << 7) /* Bit 7: Status register write protect */
#define SST25_DUMMY 0xa5
/* Chip Geometries ******************************************************************/
/* SST25VF512 capacity is 512Kbit (64Kbit x 8) = 64Kb (8Kb x 8)*/
/* SST25VF010 capacity is 1Mbit (128Kbit x 8) = 128Kb (16Kb x 8*/
/* SST25VF520 capacity is 2Mbit (256Kbit x 8) = 256Kb (32Kb x 8) */
/* SST25VF540 capacity is 4Mbit (512Kbit x 8) = 512Kb (64Kb x 8) */
/* SST25VF080 capacity is 8Mbit (1024Kbit x 8) = 1Mb (128Kb x 8) */
/* SST25VF016 capacity is 16Mbit (2048Kbit x 8) = 2Mb (256Kb x 8) */
/* Not yet supported */
/* SST25VF032 capacity is 32Mbit (4096Kbit x 8) = 4Mb (512kb x 8) */
#define SST25_VF032_SECTOR_SHIFT 12 /* Sector size 1 << 12 = 4Kb */
#define SST25_VF032_NSECTORS 1024 /* 1024 sectors x 4096 bytes/sector = 4Mb */
#ifdef CONFIG_SST25_SECTOR512 /* Simulate a 512 byte sector */
# define SST25_SECTOR_SHIFT 9 /* Sector size 1 << 9 = 512 bytes */
# define SST25_SECTOR_SIZE 512 /* Sector size = 512 bytes */
#endif
/************************************************************************************
* Private Types
************************************************************************************/
/* This type represents the state of the MTD device. The struct mtd_dev_s must
* appear at the beginning of the definition so that you can freely cast between
* pointers to struct mtd_dev_s and struct sst25_dev_s.
*/
struct sst25_dev_s
{
struct mtd_dev_s mtd; /* MTD interface */
FAR struct spi_dev_s *dev; /* Saved SPI interface instance */
uint16_t nsectors; /* Number of erase sectors */
uint8_t sectorshift; /* Log2 of erase sector size */
#ifdef CONFIG_SST25_SECTOR512 /* Simulate a 512 byte sector */
bool valid; /* Buffered sector valid */
uint16_t esectno; /* Erase sector number in the cache*/
FAR uint8_t *sector; /* Allocated sector data */
#endif
};
/************************************************************************************
* Private Function Prototypes
************************************************************************************/
/* Helpers */
static void sst25_lock(FAR struct spi_dev_s *dev);
static inline void sst25_unlock(FAR struct spi_dev_s *dev);
static inline int sst25_readid(FAR struct sst25_dev_s *priv);
static void sst25_waitwritecomplete(FAR struct sst25_dev_s *priv);
static inline void sst25_wren(FAR struct sst25_dev_s *priv);
static inline void sst25_wrdi(FAR struct sst25_dev_s *priv);
static inline void sst25_sectorerase(FAR struct sst25_dev_s *priv, off_t offset);
static inline int sst25_chiperase(FAR struct sst25_dev_s *priv);
static void sst25_byteread(FAR struct sst25_dev_s *priv, FAR uint8_t *buffer,
off_t address, size_t nbytes);
static void sst32_wordwrite(FAR struct sst25_dev_s *priv, FAR const uint8_t *buffer,
off_t address, size_t nwords);
#ifdef CONFIG_SST25_SECTOR512 /* Simulate a 512 byte sector */
static FAR uint8_t *sst25_cache(struct sst25_dev_s *priv, off_t address);
#endif
/* MTD driver methods */
static int sst25_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks);
static ssize_t sst25_bread(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR uint8_t *buf);
static ssize_t sst25_bwrite(FAR struct mtd_dev_s *dev, off_t startblock,
size_t nblocks, FAR const uint8_t *buf);
static ssize_t sst25_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
FAR uint8_t *buffer);
static int sst25_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg);
/************************************************************************************
* Private Data
************************************************************************************/
/************************************************************************************
* Private Functions
************************************************************************************/
/************************************************************************************
* Name: sst25_lock
************************************************************************************/
static void sst25_lock(FAR struct spi_dev_s *dev)
{
/* On SPI busses where there are multiple devices, it will be necessary to
* lock SPI to have exclusive access to the busses for a sequence of
* transfers. The bus should be locked before the chip is selected.
*
* This is a blocking call and will not return until we have exclusiv access to
* the SPI buss. We will retain that exclusive access until the bus is unlocked.
*/
SPI_LOCK(dev, true);
/* After locking the SPI bus, the we also need call the setfrequency, setbits, and
* setmode methods to make sure that the SPI is properly configured for the device.
* If the SPI buss is being shared, then it may have been left in an incompatible
* state.
*/
SPI_SETMODE(dev, CONFIG_SST25_SPIMODE);
SPI_SETBITS(dev, 8);
(void)SPI_SETFREQUENCY(dev, CONFIG_SST25_SPIFREQUENCY);
}
/************************************************************************************
* Name: sst25_unlock
************************************************************************************/
static inline void sst25_unlock(FAR struct spi_dev_s *dev)
{
SPI_LOCK(dev, false);
}
/************************************************************************************
* Name: sst25_readid
************************************************************************************/
static inline int sst25_readid(struct sst25_dev_s *priv)
{
uint16_t manufacturer;
uint16_t memory;
uint16_t capacity;
fvdbg("priv: %p\n", priv);
/* Lock the SPI bus, configure the bus, and select this FLASH part. */
sst25_lock(priv->dev);
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send the "Read ID (RDID)" command and read the first three ID bytes */
(void)SPI_SEND(priv->dev, SST25_JEDEC_ID);
manufacturer = SPI_SEND(priv->dev, SST25_DUMMY);
memory = SPI_SEND(priv->dev, SST25_DUMMY);
capacity = SPI_SEND(priv->dev, SST25_DUMMY);
/* Deselect the FLASH and unlock the bus */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
sst25_unlock(priv->dev);
fvdbg("manufacturer: %02x memory: %02x capacity: %02x\n",
manufacturer, memory, capacity);
/* Check for a valid manufacturer and memory type */
if (manufacturer == SST25_JEDEC_MANUFACTURER && memory == SST25_JEDEC_MEMORY_TYPE)
{
/* Okay.. is it a FLASH capacity that we understand? This should be extended
* support other members of the SST25 family.
*/
if (capacity == SST25_JEDEC_MEMORY_CAPACITY)
{
/* Save the FLASH geometry */
priv->sectorshift = SST25_VF032_SECTOR_SHIFT;
priv->nsectors = SST25_VF032_NSECTORS;
return OK;
}
}
return -ENODEV;
}
/************************************************************************************
* Name: sst25_waitwritecomplete
************************************************************************************/
static void sst25_waitwritecomplete(struct sst25_dev_s *priv)
{
uint8_t status;
/* Are we the only device on the bus? */
#ifdef CONFIG_SPI_OWNBUS
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Read Status Register (RDSR)" command */
(void)SPI_SEND(priv->dev, SST25_RDSR);
/* Loop as long as the memory is busy with a write cycle */
do
{
/* Send a dummy byte to generate the clock needed to shift out the status */
status = SPI_SEND(priv->dev, SST25_DUMMY);
}
while ((status & SST25_SR_BUSY) != 0);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
#else
/* Loop as long as the memory is busy with a write cycle */
do
{
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Read Status Register (RDSR)" command */
(void)SPI_SEND(priv->dev, SST25_RDSR);
/* Send a dummy byte to generate the clock needed to shift out the status */
status = SPI_SEND(priv->dev, SST25_DUMMY);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
/* Given that writing could take up to few tens of milliseconds, and erasing
* could take more. The following short delay in the "busy" case will allow
* other peripherals to access the SPI bus.
*/
if ((status & SST25_SR_BUSY) != 0)
{
sst25_unlock(priv->dev);
usleep(1000);
sst25_lock(priv->dev);
}
}
while ((status & SST25_SR_BUSY) != 0);
#endif
fvdbg("Complete\n");
}
/************************************************************************************
* Name: sst25_wren
************************************************************************************/
static inline void sst25_wren(struct sst25_dev_s *priv)
{
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Write Enable (WREN)" command */
(void)SPI_SEND(priv->dev, SST25_WREN);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Enabled\n");
}
/************************************************************************************
* Name: sst25_wrdi
************************************************************************************/
static inline void sst25_wrdi(struct sst25_dev_s *priv)
{
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Write Disable (WRDI)" command */
(void)SPI_SEND(priv->dev, SST25_WRDI);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Enabled\n");
}
/************************************************************************************
* Name: sst25_sectorerase
************************************************************************************/
static inline void sst25_sectorerase(struct sst25_dev_s *priv, off_t sector)
{
off_t address = sector << priv->sectorshift;
fvdbg("sector: %08lx\n", (long)sector);
/* Wait for any preceding write or erase operation to complete. */
sst25_waitwritecomplete(priv);
/* Send write enable instruction */
sst25_wren(priv);
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send the "Sector Erase (SE)" instruction */
(void)SPI_SEND(priv->dev, SST25_SE);
/* Send the sector address high byte first. Only the most significant bits (those
* corresponding to the sector) have any meaning.
*/
(void)SPI_SEND(priv->dev, (address >> 16) & 0xff);
(void)SPI_SEND(priv->dev, (address >> 8) & 0xff);
(void)SPI_SEND(priv->dev, address & 0xff);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Erased\n");
}
/************************************************************************************
* Name: sst25_chiperase
************************************************************************************/
static inline int sst25_chiperase(struct sst25_dev_s *priv)
{
fvdbg("priv: %p\n", priv);
/* Wait for any preceding write or erase operation to complete. */
sst25_waitwritecomplete(priv);
/* Send write enable instruction */
sst25_wren(priv);
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send the "Chip Erase (CE)" instruction */
(void)SPI_SEND(priv->dev, SST25_CE);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
fvdbg("Return: OK\n");
return OK;
}
/************************************************************************************
* Name: sst25_byteread
************************************************************************************/
static void sst25_byteread(FAR struct sst25_dev_s *priv, FAR uint8_t *buffer,
off_t address, size_t nbytes)
{
fvdbg("address: %08lx nbytes: %d\n", (long)address, (int)nbytes);
/* Wait for any preceding write or erase operation to complete. */
sst25_waitwritecomplete(priv);
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Read from Memory " instruction */
(void)SPI_SEND(priv->dev, SST25_FAST_READ);
/* Send the address high byte first. */
(void)SPI_SEND(priv->dev, (address >> 16) & 0xff);
(void)SPI_SEND(priv->dev, (address >> 8) & 0xff);
(void)SPI_SEND(priv->dev, address & 0xff);
/* Send a dummy byte */
(void)SPI_SEND(priv->dev, SST25_DUMMY);
/* Then read all of the requested bytes */
SPI_RECVBLOCK(priv->dev, buffer, nbytes);
/* Deselect the FLASH */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
}
/************************************************************************************
* Name: sst32_wordwrite
************************************************************************************/
static void sst32_wordwrite(struct sst25_dev_s *priv, FAR const uint8_t *buffer,
off_t address, size_t nwords)
{
fvdbg("address: %08lx nwords: %d\n", (long)address, (int)nwords);
DEBUGASSERT(priv && buffer);
/* Wait for any preceding write or erase operation to complete. */
sst25_waitwritecomplete(priv);
/* Enable the write access to the FLASH */
sst25_wren(priv);
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Send "Auto Address Increment (AAI)" command */
(void)SPI_SEND(priv->dev, SST25_AAI);
/* Send the page address high byte first. */
(void)SPI_SEND(priv->dev, (address >> 16) & 0xff);
(void)SPI_SEND(priv->dev, (address >> 8) & 0xff);
(void)SPI_SEND(priv->dev, address & 0xff);
/* Then write one 16-bit word */
SPI_SNDBLOCK(priv->dev, buffer, 2);
/* Deselect the FLASH: Chip Select high */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
buffer += 2;
/* Now loop, writing 16-bits of data on each pass through the loop until all
* of the words have been transferred.
*/
for (nwords--; nwords > 0; nwords--)
{
/* Select this FLASH part */
SPI_SELECT(priv->dev, SPIDEV_FLASH, true);
/* Wait for the preceding write to complete. */
sst25_waitwritecomplete(priv);
/* Send "Auto Address Increment (AAI)" command with no address */
(void)SPI_SEND(priv->dev, SST25_AAI);
/* Then write one 16-bit word */
SPI_SNDBLOCK(priv->dev, buffer, 2);
buffer += 2;
/* Deselect the FLASH: Chip Select high */
SPI_SELECT(priv->dev, SPIDEV_FLASH, false);
}
/* Disable writing */
sst25_wrdi(priv);
fvdbg("Written\n");
}
/************************************************************************************
* Name: sst25_cache
************************************************************************************/
#ifdef CONFIG_SST25_SECTOR512
static FAR uint8_t *sst25_cache(struct sst25_dev_s *priv, off_t sector)
{
off_t esectno;
off_t address;
int shift;
int index;
/* Convert from the 512 byte sector to the erase sector size of the device. For
* exmample, if the actual erase sector size if 4Kb (1 << 12), then we first
* shift to the right by 3 to get the sector number in 4096 increments.
*/
shift = priv->sectorshift - SST25_SECTOR_SHIFT;
esectno = sector >> shift;
fvdbg("sector: %ld esectno: %d shift=%d\n", sector, sectno, shift);
/* Check if this erase block is alread in the cache */
if (!priv->valid || esectno != priv->esectno)
{
/* Read the erase block into the cache */
sst325_byteread(priv, priv->sector, (esectno << priv->sectorshift), 1 << priv->sectorshift);
/* Mark the sector as cached */
priv->valid = true;
priv->esectno = esectno;
}
/* Get the index to the 512 sector in the erase block that holds the argument */
index = sector & ((1 << shift) - 1);
/* Return the address in the cache that holds this sector */
return &priv->sector[index << SST25_SECTOR_SHIFT];
}
#endif
/************************************************************************************
* Name: sst25_erase
************************************************************************************/
static int sst25_erase(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks)
{
FAR struct sst25_dev_s *priv = (FAR struct sst25_dev_s *)dev;
size_t blocksleft = nblocks;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* Lock access to the SPI bus until we complete the erase */
sst25_lock(priv->dev);
while (blocksleft-- > 0)
{
/* Erase each sector */
sst25_sectorerase(priv, startblock);
startblock++;
}
sst25_unlock(priv->dev);
return (int)nblocks;
}
/************************************************************************************
* Name: sst25_bread
************************************************************************************/
static ssize_t sst25_bread(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
FAR uint8_t *buffer)
{
FAR struct sst25_dev_s *priv = (FAR struct sst25_dev_s *)dev;
ssize_t nbytes;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* On this device, we can handle the block read just like the byte-oriented read */
#ifdef CONFIG_SST25_SECTOR512
nbytes = sst25_read(dev, startblock << SST25_SECTOR_SHIFT, nblocks << SST25_SECTOR_SHIFT, buffer);
if (nbytes > 0)
{
return nbytes >> SST25_SECTOR_SHIFT;
}
#else
nbytes = sst25_read(dev, startblock << priv->sectorshift, nblocks << priv->sectorshift, buffer);
if (nbytes > 0)
{
return nbytes >> priv->sectorshift;
}
#endif
return (int)nbytes;
}
/************************************************************************************
* Name: sst25_bwrite
************************************************************************************/
static ssize_t sst25_bwrite(FAR struct mtd_dev_s *dev, off_t startblock, size_t nblocks,
FAR const uint8_t *buffer)
{
FAR struct sst25_dev_s *priv = (FAR struct sst25_dev_s *)dev;
size_t nwords;
fvdbg("startblock: %08lx nblocks: %d\n", (long)startblock, (int)nblocks);
/* Lock the SPI bus and write all of the pages to FLASH */
sst25_lock(priv->dev);
#ifdef CONFIG_SST25_SECTOR512
nwords = (nblocks << (SST25_SECTOR_SHIFT - 1));
sst32_wordwrite(priv, buffer, startblock << SST25_SECTOR_SHIFT, nwords);
#else
nwords = (nblocks << (priv->sectorshift - 1));
sst32_wordwrite(priv, buffer, startblock << priv->sectorshift, nwords);
#endif
sst25_unlock(priv->dev);
return nblocks;
}
/************************************************************************************
* Name: sst25_read
************************************************************************************/
static ssize_t sst25_read(FAR struct mtd_dev_s *dev, off_t offset, size_t nbytes,
FAR uint8_t *buffer)
{
FAR struct sst25_dev_s *priv = (FAR struct sst25_dev_s *)dev;
fvdbg("offset: %08lx nbytes: %d\n", (long)offset, (int)nbytes);
/* Lock the SPI bus and select this FLASH part */
sst25_lock(priv->dev);
sst25_byteread(priv, buffer, offset, nbytes);
sst25_unlock(priv->dev);
fvdbg("return nbytes: %d\n", (int)nbytes);
return nbytes;
}
/************************************************************************************
* Name: sst25_ioctl
************************************************************************************/
static int sst25_ioctl(FAR struct mtd_dev_s *dev, int cmd, unsigned long arg)
{
FAR struct sst25_dev_s *priv = (FAR struct sst25_dev_s *)dev;
int ret = -EINVAL; /* Assume good command with bad parameters */
fvdbg("cmd: %d \n", cmd);
switch (cmd)
{
case MTDIOC_GEOMETRY:
{
FAR struct mtd_geometry_s *geo = (FAR struct mtd_geometry_s *)((uintptr_t)arg);
if (geo)
{
/* Populate the geometry structure with information need to know
* the capacity and how to access the device.
*
* NOTE: that the device is treated as though it where just an array
* of fixed size blocks. That is most likely not true, but the client
* will expect the device logic to do whatever is necessary to make it
* appear so.
*/
#ifdef CONFIG_SST25_SECTOR512
geo->blocksize = (1 << SST25_SECTOR_SHIFT);
#else
geo->blocksize = (1 << priv->sectorshift);
#endif
geo->erasesize = (1 << priv->sectorshift);
geo->neraseblocks = priv->nsectors;
ret = OK;
fvdbg("blocksize: %d erasesize: %d neraseblocks: %d\n",
geo->blocksize, geo->erasesize, geo->neraseblocks);
}
}
break;
case MTDIOC_BULKERASE:
{
/* Erase the entire device */
sst25_lock(priv->dev);
ret = sst25_chiperase(priv);
sst25_unlock(priv->dev);
}
break;
case MTDIOC_XIPBASE:
default:
ret = -ENOTTY; /* Bad command */
break;
}
fvdbg("return %d\n", ret);
return ret;
}
/************************************************************************************
* Public Functions
************************************************************************************/
/************************************************************************************
* Name: sst25_initialize
*
* Description:
* Create an initialize MTD device instance. MTD devices are not registered
* in the file system, but are created as instances that can be bound to
* other functions (such as a block or character driver front end).
*
************************************************************************************/
FAR struct mtd_dev_s *sst25_initialize(FAR struct spi_dev_s *dev)
{
FAR struct sst25_dev_s *priv;
int ret;
fvdbg("dev: %p\n", dev);
/* Allocate a state structure (we allocate the structure instead of using
* a fixed, static allocation so that we can handle multiple FLASH devices.
* The current implementation would handle only one FLASH part per SPI
* device (only because of the SPIDEV_FLASH definition) and so would have
* to be extended to handle multiple FLASH parts on the same SPI bus.
*/
priv = (FAR struct sst25_dev_s *)kzalloc(sizeof(struct sst25_dev_s));
if (priv)
{
/* Initialize the allocated structure */
priv->mtd.erase = sst25_erase;
priv->mtd.bread = sst25_bread;
priv->mtd.bwrite = sst25_bwrite;
priv->mtd.read = sst25_read;
priv->mtd.ioctl = sst25_ioctl;
priv->dev = dev;
/* Deselect the FLASH */
SPI_SELECT(dev, SPIDEV_FLASH, false);
/* Identify the FLASH chip and get its capacity */
ret = sst25_readid(priv);
if (ret != OK)
{
/* Unrecognized! Discard all of that work we just did and return NULL */
fdbg("Unrecognized\n");
kfree(priv);
priv = NULL;
}
#ifdef CONFIG_SST25_SECTOR512 /* Simulate a 512 byte sector */
else
{
/* Allocate a sector buffer */
priv->sector = (FAR uint8_t *)kmalloc(1 << priv->sectorshift);
if (!priv->sector)
{
/* Allocation failed! Discard all of that work we just did and return NULL */
fdbg("Allocation failed\n");
kfree(priv);
priv = NULL;
}
}
#endif
}
/* Return the implementation-specific state structure as the MTD device */
fvdbg("Return %p\n", priv);
return (FAR struct mtd_dev_s *)priv;
}
nuttx/include/nuttx/mtd.h
+17 -5
View File
@@ -2,8 +2,8 @@
* include/nuttx/mtd.h
* Memory Technology Device (MTD) interface
*
* Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
* Copyright (C) 2009-2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -176,7 +176,7 @@ EXTERN FAR struct mtd_dev_s *rammtd_initialize(FAR uint8_t *start, size_t size);
* Name: m25p_initialize
*
* Description:
* Create an initialize MTD device instance. MTD devices are not registered
* Create an initialized MTD device instance. MTD devices are not registered
* in the file system, but are created as instances that can be bound to
* other functions (such as a block or character driver front end).
*
@@ -188,7 +188,7 @@ EXTERN FAR struct mtd_dev_s *m25p_initialize(FAR struct spi_dev_s *dev);
* Name: at45db_initialize
*
* Description:
* Create an initialize MTD device instance. MTD devices are not registered
* Create an initialized MTD device instance. MTD devices are not registered
* in the file system, but are created as instances that can be bound to
* other functions (such as a block or character driver front end).
*
@@ -200,7 +200,7 @@ EXTERN FAR struct mtd_dev_s *at45db_initialize(FAR struct spi_dev_s *dev);
* Name: at24c_initialize
*
* Description:
* Create an initialize MTD device instance. MTD devices are not registered
* Create an initialized MTD device instance. MTD devices are not registered
* in the file system, but are created as instances that can be bound to
* other functions (such as a block or character driver front end).
*
@@ -208,6 +208,18 @@ EXTERN FAR struct mtd_dev_s *at45db_initialize(FAR struct spi_dev_s *dev);
EXTERN FAR struct mtd_dev_s *at24c_initialize(FAR struct i2c_dev_s *dev);
/****************************************************************************
* Name: sst25_initialize
*
* Description:
* Create an initialized MTD device instance. MTD devices are not registered
* in the file system, but are created as instances that can be bound to
* other functions (such as a block or character driver front end).
*
****************************************************************************/
EXTERN FAR struct mtd_dev_s *sst25_initialize(FAR struct spi_dev_s *dev);
#undef EXTERN
#ifdef __cplusplus
}