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smt32 adc:Ensure the the ADC clock is not out of spec

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The data sheet for the F4, F7 indicate a maximum of 36 Mhz
   in the 2.4-3.3 volt Soc operating range. This change sets
   the clock based on the STM32_PCLK2_FREQUENCY.
This commit is contained in:
David Sidrane
2017-09-06 15:30:48 -10:00
committed by Daniel Agar
parent dcf8d82f8c
commit 63ac56aeb0
1 changed files with 23 additions and 2 deletions
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src/drivers/stm32/adc/adc.cpp
+23 -2
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@@ -98,6 +98,22 @@
#ifdef STM32_ADC_CCR
# define rCCR REG(STM32_ADC_CCR_OFFSET)
/* Assuming VDC 2.4 - 3.6 */
#define ADC_MAX_FADC 36000000
# if STM32_PCLK2_FREQUENCY/2 <= ADC_MAX_FADC
# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV2
# elif STM32_PCLK2_FREQUENCY/4 <= ADC_MAX_FADC
# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV4
# elif STM32_PCLK2_FREQUENCY/6 <= ADC_MAX_FADC
# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV6
# elif STM32_PCLK2_FREQUENCY/8 <= ADC_MAX_FADC
# define ADC_CCR_ADCPRE_DIV ADC_CCR_ADCPRE_DIV8
# else
# error "ADC PCLK2 too high - no divisor found "
# endif
#endif
class ADC : public device::CDev
@@ -222,9 +238,14 @@ ADC::init()
#endif
0;
#ifdef ADC_CCR_TSVREFE
/* Soc have CCR */
#ifdef STM32_ADC_CCR
# ifdef ADC_CCR_TSVREFE
/* enable temperature sensor in CCR */
rCCR = ADC_CCR_TSVREFE;
rCCR = ADC_CCR_TSVREFE | ADC_CCR_ADCPRE_DIV;
# else
rCCR = ADC_CCR_ADCPRE_DIV;
# endif
#endif
/* configure for a single-channel sequence */