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LPC11C24: Proper CRT initialization with BSS and constructors. All assembler code was removed.

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This commit is contained in:
Pavel Kirienko
2014-04-14 23:30:06 +04:00
parent af2141daaf
commit 38ca53d7d5
6 changed files with 300 additions and 518 deletions
Download Patch File Download Diff File Expand all files Collapse all files
libuavcan_drivers/lpc11c24/test_olimex_lpc_p11c24/Makefile
+8 -15
View File
@@ -2,12 +2,11 @@
# Pavel Kirienko, 2014 <pavel.kirienko@gmail.com>
#
CPPSRC := $(wildcard src/*.cpp) \
CPPSRC := $(wildcard src/*.cpp) \
$(wildcard src/sys/*.cpp)
CSRC := $(wildcard lpc_chip_11cxx_lib/src/*.c)
ASMSRC := $(wildcard src/sys/*.S)
CSRC := $(wildcard lpc_chip_11cxx_lib/src/*.c) \
$(wildcard src/sys/*.c)
DEF =
@@ -26,9 +25,7 @@ DEF += -DNDEBUG -DCHIP_LPC11CXX -DCORE_M0 -DTHUMB_NO_INTERWORKING
FLAGS = -mthumb -mcpu=cortex-m0 -mno-thumb-interwork
ASMFLAGS = $(FLAGS)
C_CPP_FLAGS = $(FLAGS) -g3 -Os -Wall -Wextra -Werror -ffunction-sections -fdata-sections \
C_CPP_FLAGS = $(FLAGS) -Os -g3 -Wall -Wextra -Werror -ffunction-sections -fdata-sections \
-fno-common -fno-exceptions -fno-unwind-tables -fno-stack-protector -fomit-frame-pointer
# Dependencies
@@ -38,14 +35,14 @@ CFLAGS = $(C_CPP_FLAGS) -std=c99
CPPFLAGS = $(C_CPP_FLAGS) -pedantic -std=c++11 -fno-rtti -fno-threadsafe-statics
LDFLAGS = $(FLAGS) -nodefaultlibs -lc -lgcc -nostartfiles -Tlpc11c24.ld -Xlinker --gc-sections
LDFLAGS = $(FLAGS) -nodefaultlibs -lc -lgcc -nostartfiles -Tlpc11c24.ld -Xlinker --gc-sections \
-Wl,-Map,$(BUILDDIR)/output.map
COBJ = $(addprefix $(OBJDIR)/, $(notdir $(CSRC:.c=.o)))
CPPOBJ = $(addprefix $(OBJDIR)/, $(notdir $(CPPSRC:.cpp=.o)))
ASMOBJ = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.S=.o)))
OBJ = $(COBJ) $(ASMOBJ) $(CPPOBJ)
OBJ = $(COBJ) $(CPPOBJ)
VPATH = $(sort $(dir $(CSRC)) $(dir $(CPPSRC)) $(dir $(ASMSRC)))
VPATH = $(sort $(dir $(CSRC)) $(dir $(CPPSRC)))
ELF = $(BUILDDIR)/firmware.elf
BIN = $(BUILDDIR)/firmware.bin
@@ -87,10 +84,6 @@ $(CPPOBJ): $(OBJDIR)/%.o: %.cpp
@echo
$(CPPC) -c $(DEF) $(INC) $(CPPFLAGS) $< -o $@
$(ASMOBJ): $(OBJDIR)/%.o: %.S
@echo
$(AS) -c $(DEF) $(INC) $(ASMFLAGS) $< -o $@
clean:
rm -rf $(BUILDDIR)
libuavcan_drivers/lpc11c24/test_olimex_lpc_p11c24/lpc11c24.ld
+63 -130
View File
@@ -1,82 +1,47 @@
/*
* Pavel Kirienko, 2014 <pavel.kirienko@gmail.com>
* Originally copied from lpcopen-make by Mark Burton.
* Linker script for LPC11C24
*/
MEMORY
{
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K
/* Notice RAM offset - this is needed for on-chip CCAN */
RAM (rwx) : ORIGIN = 0x100000C0, LENGTH = 0x1F40
/* Specify RAM1 and RAM2 regions as zero length to stop them being used */
RAM1(rwx) : ORIGIN = 0x00000000, LENGTH = 0k
RAM2(rwx) : ORIGIN = 0x00000000, LENGTH = 0k
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
. = 0;
_text = .;
startup :
{
KEEP(*(.isr_vector))
*crti.o(.text*)
*crtbegin.o(.text*)
*crt0.o(.text*)
. = DEFINED(__nxp_crp) ? 0x2fc : .;
KEEP(*(.NXP.CRP))
*(.text*)
KEEP(*(vectors))
} > FLASH
KEEP(*(.init))
KEEP(*(.fini))
constructors : ALIGN(16) SUBALIGN(16)
{
PROVIDE(__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE(__init_array_end = .);
} > FLASH
/* C++ Static constructors/destructors (elf) */
. = ALIGN(4);
_ctor_start = .;
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
_ctor_end = .;
/* NO DESTRUCTORS */
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
.text : ALIGN(16) SUBALIGN(16)
{
*(.text.startup.*)
*(.text)
*(.text.*)
*(.rodata)
*(.rodata.*)
*(.glue_7t)
*(.glue_7)
*(.gcc*)
} > FLASH
.ARM.extab :
@@ -84,88 +49,56 @@ SECTIONS
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
.ARM.exidx : {
PROVIDE(__exidx_start = .);
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
PROVIDE(__exidx_end = .);
} > FLASH
__etext = .;
.data : AT (__etext)
.eh_frame_hdr :
{
__data_start__ = .;
*(vtable)
*(.data*)
*(.eh_frame_hdr)
} > FLASH
.eh_frame : ONLY_IF_RO
{
*(.eh_frame)
} > FLASH
.textalign : ONLY_IF_RO
{
. = ALIGN(8);
} > FLASH
. = ALIGN(4);
_etext = .;
_textdata = _etext;
.data :
{
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
PROVIDE(_data = .);
*(.data)
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
*(.data.*)
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
*(.ramtext)
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
PROVIDE(_edata = .);
} > RAM AT > FLASH
.bss :
{
__bss_start__ = .;
*(.bss*)
. = ALIGN(4);
PROVIDE(_bss = .);
*(.bss)
. = ALIGN(4);
*(.bss.*)
. = ALIGN(4);
*(COMMON)
__bss_end__ = .;
. = ALIGN(4);
PROVIDE(_ebss = .);
} > RAM
.ahb_ram0 (NOLOAD):
{
*.o (AHB_RAM0)
} >RAM1
.ahb_ram1 (NOLOAD):
{
*.o (AHB_RAM1)
} >RAM2
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contain any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy :
{
*(.stack)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "Region RAM overflowed with stack")
PROVIDE(__stack_end = ORIGIN(RAM) + LENGTH(RAM));
}
libuavcan_drivers/lpc11c24/test_olimex_lpc_p11c24/src/main.cpp
+19
View File
@@ -21,8 +21,27 @@ struct A
static A a;
static long long zero_global;
static long long non_zero_global = 123456789123456789;
static long long post_initialized_global;
__attribute__((constructor))
static void foo()
{
post_initialized_global = 987654321987654321;
}
int main()
{
static long long zero_local;
while (zero_global != 0) { } // BSS init check
while (zero_local != 0) { }
while (non_zero_global != 123456789123456789) { } // Data init check
while (post_initialized_global != 987654321987654321) { } // Constructor check
while (true)
{
for (volatile int i = 0; i < 1000000; i++) { __asm volatile ("nop"); }
libuavcan_drivers/lpc11c24/test_olimex_lpc_p11c24/src/sys/board.cpp
+1 -35
View File
@@ -126,46 +126,12 @@ void setErrorLed(bool state)
} // namespace board
/*
* Basic hardware initialization
* C++ runtime initialization
*/
extern "C"
{
extern unsigned long __preinit_array_start;
extern unsigned long __preinit_array_end;
extern unsigned long __init_array_start;
extern unsigned long __init_array_end;
extern unsigned long _ctor_start;
extern unsigned long _ctor_end;
static void call_init_array(unsigned long* start, unsigned long* end)
{
for (unsigned long* i = start; i < end; i++)
{
reinterpret_cast<void (*)()>(*i)();
}
}
// We need to disable pedantic mode to call main()
#pragma GCC diagnostic ignored "-Wpedantic"
__attribute__((noreturn))
extern int main();
__attribute__((noreturn))
void __start()
void __low_init()
{
board::init();
call_init_array(&__preinit_array_start, &__preinit_array_end);
call_init_array(&__init_array_start, &__init_array_end);
call_init_array(&_ctor_start, &_ctor_end);
(void)main();
while (true) { }
}
}
libuavcan_drivers/lpc11c24/test_olimex_lpc_p11c24/src/sys/crt0.c
+209
View File
@@ -0,0 +1,209 @@
/*
* Pavel Kirienko, 2014 <pavel.kirienko@gmail.com>
* ARM Cortex-M0(+)/M1/M3 startup file.
*/
typedef void (*funptr_t)(void);
#define fill32(start, end, filler) { \
unsigned *p1 = start; \
const unsigned * const p2 = end; \
while (p1 < p2) \
*p1++ = filler; \
}
extern const unsigned _etext;
extern unsigned _data;
extern unsigned _edata;
extern unsigned _bss;
extern unsigned _ebss;
extern funptr_t __init_array_start;
extern funptr_t __init_array_end;
__attribute__((noreturn))
extern int main(void);
extern void __low_init(void);
/**
* Firmware entry point
*/
__attribute__((naked, noreturn))
void Reset_Handler(void)
{
// Data section
{
const unsigned* tp = &_etext;
unsigned* dp = &_data;
while (dp < &_edata)
{
*dp++ = *tp++;
}
}
// BSS section
fill32(&_bss, &_ebss, 0);
__low_init();
// Constructors
{
funptr_t* fpp = &__init_array_start;
while (fpp < &__init_array_end)
{
(*fpp)();
fpp++;
}
}
(void)main();
while (1) { }
}
/**
* Default handlers
*/
__attribute__((weak))
void Default_Handler(void)
{
while(1) { }
}
__attribute__((weak))
void NMI_Handler(void)
{
while(1) { }
}
__attribute__((weak))
void HardFault_Handler(void)
{
while(1) { }
}
__attribute__((weak))
void SVC_Handler(void)
{
while(1) { }
}
__attribute__((weak))
void PendSV_Handler(void)
{
while(1) { }
}
__attribute__((weak))
void SysTick_Handler(void)
{
while(1) { }
}
/**
* Default vectors for LPC11C24, to be overriden by the firmware as needed
*/
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
void CAN_IRQHandler(void) ALIAS(Default_Handler);
void SSP1_IRQHandler(void) ALIAS(Default_Handler);
void I2C_IRQHandler(void) ALIAS(Default_Handler);
void TIMER16_0_IRQHandler(void) ALIAS(Default_Handler);
void TIMER16_1_IRQHandler(void) ALIAS(Default_Handler);
void TIMER32_0_IRQHandler(void) ALIAS(Default_Handler);
void TIMER32_1_IRQHandler(void) ALIAS(Default_Handler);
void SSP0_IRQHandler(void) ALIAS(Default_Handler);
void UART_IRQHandler(void) ALIAS(Default_Handler);
void ADC_IRQHandler(void) ALIAS(Default_Handler);
void WDT_IRQHandler(void) ALIAS(Default_Handler);
void BOD_IRQHandler(void) ALIAS(Default_Handler);
void PIOINT3_IRQHandler(void) ALIAS(Default_Handler);
void PIOINT2_IRQHandler(void) ALIAS(Default_Handler);
void PIOINT1_IRQHandler(void) ALIAS(Default_Handler);
void PIOINT0_IRQHandler(void) ALIAS(Default_Handler);
void WAKEUP_IRQHandler(void) ALIAS(Default_Handler);
/**
* Refer to the linker script
*/
extern void __stack_end(void);
/**
* Vector table for LPC11Cxx
*/
__attribute__ ((section("vectors")))
void (* const VectorTable[64])(void) =
{
__stack_end, // The initial stack pointer
Reset_Handler, // The reset handler
NMI_Handler, // The NMI handler
HardFault_Handler, // The hard fault handler
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
0, // Reserved
SVC_Handler, // SVCall handler
0, // Reserved
0, // Reserved
PendSV_Handler, // The PendSV handler
SysTick_Handler, // The SysTick handler
WAKEUP_IRQHandler, // PIO0_0 Wakeup
WAKEUP_IRQHandler, // PIO0_1 Wakeup
WAKEUP_IRQHandler, // PIO0_2 Wakeup
WAKEUP_IRQHandler, // PIO0_3 Wakeup
WAKEUP_IRQHandler, // PIO0_4 Wakeup
WAKEUP_IRQHandler, // PIO0_5 Wakeup
WAKEUP_IRQHandler, // PIO0_6 Wakeup
WAKEUP_IRQHandler, // PIO0_7 Wakeup
WAKEUP_IRQHandler, // PIO0_8 Wakeup
WAKEUP_IRQHandler, // PIO0_9 Wakeup
WAKEUP_IRQHandler, // PIO0_10 Wakeup
WAKEUP_IRQHandler, // PIO0_11 Wakeup
WAKEUP_IRQHandler, // PIO1_0 Wakeup
CAN_IRQHandler, // C_CAN Interrupt
SSP1_IRQHandler, // SPI/SSP1 Interrupt
I2C_IRQHandler, // I2C0
TIMER16_0_IRQHandler, // CT16B0 (16-bit Timer 0)
TIMER16_1_IRQHandler, // CT16B1 (16-bit Timer 1)
TIMER32_0_IRQHandler, // CT32B0 (32-bit Timer 0)
TIMER32_1_IRQHandler, // CT32B1 (32-bit Timer 1)
SSP0_IRQHandler, // SPI/SSP0 Interrupt
UART_IRQHandler, // UART0
0, // Reserved
0, // Reserved
ADC_IRQHandler, // ADC (A/D Converter)
WDT_IRQHandler, // WDT (Watchdog Timer)
BOD_IRQHandler, // BOD (Brownout Detect)
0, // Reserved
PIOINT3_IRQHandler, // PIO INT3
PIOINT2_IRQHandler, // PIO INT2
PIOINT1_IRQHandler, // PIO INT1
PIOINT0_IRQHandler, // PIO INT0
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0
};
libuavcan_drivers/lpc11c24/test_olimex_lpc_p11c24/src/sys/startup_armcm0.S
-338
View File
@@ -1,338 +0,0 @@
/* File: startup_ARMCM0.S
* Purpose: startup file for Cortex-M0 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V1.3
* Date: 08 Feb 2012
*
* Copyright (c) 2012, ARM Limited
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
* Neither the name of the ARM Limited nor the
names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
.syntax unified
.arch armv6-m
#ifdef NXP_CRP
.section .NXP.CRP
.align 2
.globl __nxp_crp
__nxp_crp:
.long NXP_CRP
.size __nxp_crp, . - __nxp_crp
#endif
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x400
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0xC00
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External interrupts */
#if defined(CHIP_LPC11AXX)
#define HAVE_LPC_IRQ_HANDLERS
.long PIN_INT0_IRQHandler // 16+ 0: Pin interrupt
.long PIN_INT1_IRQHandler // 16+ 1: Pin interrupt
.long PIN_INT2_IRQHandler // 16+ 2: Pin interrupt
.long PIN_INT3_IRQHandler // 16+ 3: Pin interrupt
.long PIN_INT4_IRQHandler // 16+ 4: Pin interrupt
.long PIN_INT5_IRQHandler // 16+ 5: Pin interrupt
.long PIN_INT6_IRQHandler // 16+ 6: Pin interrupt
.long PIN_INT7_IRQHandler // 16+ 7: Pin interrupt
.long GINT0_IRQHandler // 16+ 8: Port interrupt
.long GINT1_IRQHandler // 16+ 9: Port interrupt
.long ACMP_IRQHandler // 16+10: Analog Comparator
.long DAC_IRQHandler // 16+11: D/A Converter
.long 0 // 16+12: Reserved
.long 0 // 16+13: Reserved
.long SSP1_IRQHandler // 16+14: SSP1
.long I2C_IRQHandler // 16+15: I2C
.long TIMER_16_0_IRQHandler // 16+16: 16-bit Timer0
.long TIMER_16_1_IRQHandler // 16+17: 16-bit Timer1
.long TIMER_32_0_IRQHandler // 16+18: 32-bit Timer0
.long TIMER_32_1_IRQHandler // 16+19: 32-bit Timer1
.long SSP0_IRQHandler // 16+20: SSP0
.long USART_IRQHandler // 16+21: USART
.long 0 // 16+22: Reserved
.long 0 // 16+23: Reserved
.long ADC_IRQHandler // 16+24: A/D Converter
.long WDT_IRQHandler // 16+25: Watchdog Timer
.long BOD_IRQHandler // 16+26: Brown Out Detect
.long FMC_IRQHandler // 16+27: IP2111 Flash Memory Controller
.long 0 // 16+28: Reserved
.long 0 // 16+29: Reserved
.long 0 // 16+30: Reserved
.long 0 // 16+31: Reserved
#endif
#if defined(CHIP_LPC11CXX)
#define HAVE_LPC_IRQ_HANDLERS
.long WAKEUP_IRQHandler // PIO0_0 Wakeup
.long WAKEUP_IRQHandler // PIO0_1 Wakeup
.long WAKEUP_IRQHandler // PIO0_2 Wakeup
.long WAKEUP_IRQHandler // PIO0_3 Wakeup
.long WAKEUP_IRQHandler // PIO0_4 Wakeup
.long WAKEUP_IRQHandler // PIO0_5 Wakeup
.long WAKEUP_IRQHandler // PIO0_6 Wakeup
.long WAKEUP_IRQHandler // PIO0_7 Wakeup
.long WAKEUP_IRQHandler // PIO0_8 Wakeup
.long WAKEUP_IRQHandler // PIO0_9 Wakeup
.long WAKEUP_IRQHandler // PIO0_10 Wakeup
.long WAKEUP_IRQHandler // PIO0_11 Wakeup
.long WAKEUP_IRQHandler // PIO1_0 Wakeup
.long CAN_IRQHandler // C_CAN Interrupt
.long SSP1_IRQHandler // SPI/SSP1 Interrupt
.long I2C_IRQHandler // I2C0
.long TIMER_16_0_IRQHandler // CT16B0 (16-bit Timer 0)
.long TIMER_16_1_IRQHandler // CT16B1 (16-bit Timer 1)
.long TIMER_32_0_IRQHandler // CT32B0 (32-bit Timer 0)
.long TIMER_32_1_IRQHandler // CT32B1 (32-bit Timer 1)
.long SSP0_IRQHandler // SPI/SSP0 Interrupt
.long UART_IRQHandler // UART0
.long 0 // Reserved
.long 0 // Reserved
.long ADC_IRQHandler // ADC (A/D Converter)
.long WDT_IRQHandler // WDT (Watchdog Timer)
.long BOD_IRQHandler // BOD (Brownout Detect)
.long 0 // Reserved
.long PIOINT3_IRQHandler // PIO INT3
.long PIOINT2_IRQHandler // PIO INT2
.long PIOINT1_IRQHandler // PIO INT1
.long PIOINT0_IRQHandler // PIO INT0
#endif
#if defined(CHIP_LPC11UXX)
#define HAVE_LPC_IRQ_HANDLERS
.long FLEX_INT0_IRQHandler // 0 - GPIO pin interrupt 0
.long FLEX_INT1_IRQHandler // 1 - GPIO pin interrupt 1
.long FLEX_INT2_IRQHandler // 2 - GPIO pin interrupt 2
.long FLEX_INT3_IRQHandler // 3 - GPIO pin interrupt 3
.long FLEX_INT4_IRQHandler // 4 - GPIO pin interrupt 4
.long FLEX_INT5_IRQHandler // 5 - GPIO pin interrupt 5
.long FLEX_INT6_IRQHandler // 6 - GPIO pin interrupt 6
.long FLEX_INT7_IRQHandler // 7 - GPIO pin interrupt 7
.long GINT0_IRQHandler // 8 - GPIO GROUP0 interrupt
.long GINT1_IRQHandler // 9 - GPIO GROUP1 interrupt
.long 0 // 10 - Reserved
.long 0 // 11 - Reserved
.long 0 // 12 - Reserved
.long 0 // 13 - Reserved
.long SSP1_IRQHandler // 14 - SPI/SSP1 Interrupt
.long I2C_IRQHandler // 15 - I2C0
.long TIMER_16_0_IRQHandler // 16 - CT16B0 (16-bit Timer 0)
.long TIMER_16_1_IRQHandler // 17 - CT16B1 (16-bit Timer 1)
.long TIMER_32_0_IRQHandler // 18 - CT32B0 (32-bit Timer 0)
.long TIMER_32_1_IRQHandler // 19 - CT32B1 (32-bit Timer 1)
.long SSP0_IRQHandler // 20 - SPI/SSP0 Interrupt
.long UART_IRQHandler // 21 - UART0
.long USB_IRQHandler // 22 - USB IRQ
.long USB_FIQHandler // 23 - USB FIQ
.long ADC_IRQHandler // 24 - ADC (A/D Converter)
.long WDT_IRQHandler // 25 - WDT (Watchdog Timer)
.long BOD_IRQHandler // 26 - BOD (Brownout Detect)
.long FMC_IRQHandler // 27 - IP2111 Flash Memory Controller
.long 0 // 28 - Reserved
.long 0 // 29 - Reserved
.long USBWakeup_IRQHandler // 30 - USB wake-up interrupt
.long 0 // 31 - Reserved
#endif
#ifndef HAVE_LPC_IRQ_HANDLERS
#error "No LPC IRQ handlers defined for this chip type."
#endif
.size __isr_vector, . - __isr_vector
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .flash_to_ram_loop_end
movs r4, 0
.flash_to_ram_loop:
ldr r0, [r1,r4]
str r0, [r2,r4]
adds r4, 4
cmp r4, r3
blt .flash_to_ram_loop
.flash_to_ram_loop_end:
ldr r0, =__start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_irq_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_irq_handler NMI_Handler
def_irq_handler HardFault_Handler
def_irq_handler SVC_Handler
def_irq_handler PendSV_Handler
def_irq_handler SysTick_Handler
def_irq_handler Default_Handler
#if defined(CHIP_LPC11AXX)
def_irq_handler PIN_INT0_IRQHandler
def_irq_handler PIN_INT1_IRQHandler
def_irq_handler PIN_INT2_IRQHandler
def_irq_handler PIN_INT3_IRQHandler
def_irq_handler PIN_INT4_IRQHandler
def_irq_handler PIN_INT5_IRQHandler
def_irq_handler PIN_INT6_IRQHandler
def_irq_handler PIN_INT7_IRQHandler
def_irq_handler GINT0_IRQHandler
def_irq_handler GINT1_IRQHandler
def_irq_handler ACMP_IRQHandler
def_irq_handler DAC_IRQHandler
def_irq_handler SSP1_IRQHandler
def_irq_handler I2C_IRQHandler
def_irq_handler TIMER_16_0_IRQHandler
def_irq_handler TIMER_16_1_IRQHandler
def_irq_handler TIMER_32_0_IRQHandler
def_irq_handler TIMER_32_1_IRQHandler
def_irq_handler SSP0_IRQHandler
def_irq_handler USART_IRQHandler
def_irq_handler ADC_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler BOD_IRQHandler
def_irq_handler FMC_IRQHandler
#elif defined(CHIP_LPC11CXX)
def_irq_handler WAKEUP_IRQHandler
def_irq_handler CAN_IRQHandler
def_irq_handler SSP1_IRQHandler
def_irq_handler I2C_IRQHandler
def_irq_handler TIMER_16_0_IRQHandler
def_irq_handler TIMER_16_1_IRQHandler
def_irq_handler TIMER_32_0_IRQHandler
def_irq_handler TIMER_32_1_IRQHandler
def_irq_handler SSP0_IRQHandler
def_irq_handler UART_IRQHandler
def_irq_handler ADC_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler BOD_IRQHandler
def_irq_handler PIOINT3_IRQHandler
def_irq_handler PIOINT2_IRQHandler
def_irq_handler PIOINT1_IRQHandler
def_irq_handler PIOINT0_IRQHandler
#elif defined(CHIP_LPC11UXX)
def_irq_handler FLEX_INT0_IRQHandler
def_irq_handler FLEX_INT1_IRQHandler
def_irq_handler FLEX_INT2_IRQHandler
def_irq_handler FLEX_INT3_IRQHandler
def_irq_handler FLEX_INT4_IRQHandler
def_irq_handler FLEX_INT5_IRQHandler
def_irq_handler FLEX_INT6_IRQHandler
def_irq_handler FLEX_INT7_IRQHandler
def_irq_handler GINT0_IRQHandler
def_irq_handler GINT1_IRQHandler
def_irq_handler SSP1_IRQHandler
def_irq_handler I2C_IRQHandler
def_irq_handler TIMER_16_0_IRQHandler
def_irq_handler TIMER_16_1_IRQHandler
def_irq_handler TIMER_32_0_IRQHandler
def_irq_handler TIMER_32_1_IRQHandler
def_irq_handler SSP0_IRQHandler
def_irq_handler UART_IRQHandler
def_irq_handler USB_IRQHandler
def_irq_handler USB_FIQHandler
def_irq_handler ADC_IRQHandler
def_irq_handler WDT_IRQHandler
def_irq_handler BOD_IRQHandler
def_irq_handler FMC_IRQHandler
def_irq_handler USBWakeup_IRQHandler
#endif
.end