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https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-10-29 20:53:33 +08:00
NXP UCANS32K: Add Support for PWM
S32K1XX HRT: Allow any channel of any FTM timer to be used NXP UCANS32K: Enable additional FlexTimers and use FTM5 for HRT NXP UCANS32K - Change FTM clocksource to system oscillator NXP UCANS32K - Only need one FlexTimer and channel for PWM output NXP UCANS32K will have only one PWM header by default S32K1XX support FlexTimers beyond FTM3 S32K1XX io_timer.c - replace references to Kinetis S32K1XX io_timer.c correct register names S32K1XX input_capture.c and pwm_servo.c replace references to Kinetis
This commit is contained in:
Jari van Ewijk
committed by
David Sidrane
David Sidrane
parent
4ed3ecea41
commit
35dce9aff6
@@ -41,6 +41,7 @@ add_library(drivers_board
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init.c
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periphclocks.c
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spi.c
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timer_config.cpp
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userleds.c
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)
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@@ -90,13 +90,32 @@ __BEGIN_DECLS
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/* Count of peripheral clock user configurations */
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#define NUM_OF_PERIPHERAL_CLOCKS_0 14
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#define NUM_OF_PERIPHERAL_CLOCKS_0 18
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/* High-resolution timer */
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#define HRT_TIMER 1 /* FTM timer for the HRT */
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#define HRT_TIMER 5 /* FTM timer for the HRT */
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#define HRT_TIMER_CHANNEL 0 /* Use capture/compare channel 0 */
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#define HRT_PPM_CHANNEL 1 /* Use TPM1 capture/compare channel 1 */
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/* Timer I/O PWM and capture
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*
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* ?? PWM outputs are configured.
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* ?? Timer inputs are configured.
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*
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* Pins:
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* Defined in board.h
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*/
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// todo:Design this!
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#define DIRECT_PWM_OUTPUT_CHANNELS 1
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#define BOARD_HAS_PWM DIRECT_PWM_OUTPUT_CHANNELS
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#define BOARD_HAS_LED_PWM 1
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#define LED_TIM3_CH1OUT /* PTD1 RGB_R */ PIN_FTM3_CH1_1
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#define LED_TIM3_CH5OUT /* PTC9 RGB_G */ PIN_FTM3_CH5_1
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#define LED_TIM3_CH4OUT /* PTC8 RGB_B */ PIN_FTM3_CH4_1
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/****************************************************************************
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* Public Types
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@@ -144,12 +144,32 @@ const struct peripheral_clock_config_s g_peripheral_clockconfig0[] = {
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{
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.clkname = FTM0_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SIRC,
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.clksrc = CLK_SRC_SOSC_DIV1,
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},
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{
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.clkname = FTM1_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SIRC,
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.clksrc = CLK_SRC_SOSC_DIV1,
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},
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{
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.clkname = FTM2_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SOSC_DIV1,
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},
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{
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.clkname = FTM3_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SOSC_DIV1,
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},
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{
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.clkname = FTM4_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SOSC_DIV1,
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},
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{
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.clkname = FTM5_CLK,
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.clkgate = true,
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.clksrc = CLK_SRC_SOSC_DIV1,
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},
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{
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.clkname = PORTA_CLK,
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@@ -0,0 +1,179 @@
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/****************************************************************************
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*
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* Copyright (C) 2016, 2018 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/*
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* @file timer_config.c
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*
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* Configuration data for the S32K1XX pwm_servo, input capture and pwm input driver.
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*
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* Note that these arrays must always be fully-sized.
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*/
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// TODO:Stubbed out for now
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#include <stdint.h>
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#include "hardware/s32k1xx_pcc.h"
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#include "hardware/s32k1xx_ftm.h"
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#include "s32k1xx_pin.h"
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#include <drivers/drv_pwm_output.h>
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#include <px4_arch/io_timer_hw_description.h>
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#include "board_config.h"
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/****************************************************************************
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* Definitions
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****************************************************************************/
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/* Register accessors */
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#define _REG(_addr) (*(volatile uint32_t *)(_addr))
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/* Timer register accessors */
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#define REG(t, _reg) _REG(S32K1XX_FTM##t##_BASE + (_reg))
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#define rSC(t) REG(t,S32K1XX_FTM_SC_OFFSET)
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#define rCNT(t) REG(t,S32K1XX_FTM_CNT_OFFSET)
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#define rMOD(t) REG(t,S32K1XX_FTM_MOD_OFFSET)
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#define rC0SC(t) REG(t,S32K1XX_FTM_C0SC_OFFSET)
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#define rC0V(t) REG(t,S32K1XX_FTM_C0V_OFFSET)
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#define rC1SC(t) REG(t,S32K1XX_FTM_C1SC_OFFSET)
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#define rC1V(t) REG(t,S32K1XX_FTM_C1V_OFFSET)
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#define rC2SC(t) REG(t,S32K1XX_FTM_C2SC_OFFSET)
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#define rC2V(t) REG(t,S32K1XX_FTM_C2V_OFFSET)
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#define rC3SC(t) REG(t,S32K1XX_FTM_C3SC_OFFSET)
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#define rC3V(t) REG(t,S32K1XX_FTM_C3V_OFFSET)
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#define rC4SC(t) REG(t,S32K1XX_FTM_C4SC_OFFSET)
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#define rC4V(t) REG(t,S32K1XX_FTM_C4V_OFFSET)
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#define rC5SC(t) REG(t,S32K1XX_FTM_C5SC_OFFSET)
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#define rC5V(t) REG(t,S32K1XX_FTM_C5V_OFFSET)
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#define rC6SC(t) REG(t,S32K1XX_FTM_C6SC_OFFSET)
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#define rC6V(t) REG(t,S32K1XX_FTM_C6V_OFFSET)
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#define rC7SC(t) REG(t,S32K1XX_FTM_C7SC_OFFSET)
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#define rC7V(t) REG(t,S32K1XX_FTM_C7V_OFFSET)
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#define rCNTIN(t) REG(t,S32K1XX_FTM_CNTIN_OFFSET)
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#define rSTATUS(t) REG(t,S32K1XX_FTM_STATUS_OFFSET)
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#define rMODE(t) REG(t,S32K1XX_FTM_MODE_OFFSET)
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#define rSYNC(t) REG(t,S32K1XX_FTM_SYNC_OFFSET)
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#define rOUTINIT(t) REG(t,S32K1XX_FTM_OUTINIT_OFFSET)
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#define rOUTMASK(t) REG(t,S32K1XX_FTM_OUTMASK_OFFSET)
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#define rCOMBINE(t) REG(t,S32K1XX_FTM_COMBINE_OFFSET)
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#define rDEADTIME(t) REG(t,S32K1XX_FTM_DEADTIME_OFFSET)
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#define rEXTTRIG(t) REG(t,S32K1XX_FTM_EXTTRIG_OFFSET)
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#define rPOL(t) REG(t,S32K1XX_FTM_POL_OFFSET)
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#define rFMS(t) REG(t,S32K1XX_FTM_FMS_OFFSET)
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#define rFILTER(t) REG(t,S32K1XX_FTM_FILTER_OFFSET)
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#define rFLTCTRL(t) REG(t,S32K1XX_FTM_FLTCTRL_OFFSET)
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#define rQDCTRL(t) REG(t,S32K1XX_FTM_QDCTRL_OFFSET)
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#define rCONF(t) REG(t,S32K1XX_FTM_CONF_OFFSET)
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#define rFLTPOL(t) REG(t,S32K1XX_FTM_FLTPOL_OFFSET)
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#define rSYNCONF(t) REG(t,S32K1XX_FTM_SYNCONF_OFFSET)
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#define rINVCTRL(t) REG(t,S32K1XX_FTM_INVCTRL_OFFSET)
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#define rSWOCTRL(t) REG(t,S32K1XX_FTM_SWOCTRL_OFFSET)
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#define rPWMLOAD(t) REG(t,S32K1XX_FTM_PWMLOAD_OFFSET)
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constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
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initIOTimer(Timer::FTM0),
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//initIOTimer(Timer::FTM2),
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};
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constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
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initIOTimerChannel(io_timers, {Timer::FTM0, Timer::Channel7}, {GPIO::PortE, GPIO::Pin9}),
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//initIOTimerChannel(io_timers, {Timer::FTM2, Timer::Channel1}, {GPIO::PortA, GPIO::Pin0}),
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};
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constexpr io_timers_channel_mapping_t io_timers_channel_mapping =
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initIOTimerChannelMapping(io_timers, timer_io_channels);
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const struct io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
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// To Do: Remove or add the right definitions.
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/*
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{
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.base = S32K1XX_FTM0_BASE,
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.clock_register = S32K1XX_PCC_FTM0,
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.clock_bit = PCC_CGC,
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//.vectorno = 0,
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},
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*/
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};
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const struct timer_io_channels_t led_pwm_channels[MAX_TIMER_LED_CHANNELS] = {
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// To Do: Remove or add the right definitions.
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/*
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{
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.gpio_out = LED_TIM3_CH1OUT, // RGB_R
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.gpio_in = 0,
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.timer_index = 0,
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.timer_channel = 2,
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},
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{
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.gpio_out = LED_TIM3_CH5OUT, // RGB_G
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.gpio_in = 0,
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.timer_index = 0,
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.timer_channel = 6,
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},
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{
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.gpio_out = LED_TIM3_CH4OUT, // RGB_B
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.gpio_in = 0,
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.timer_index = 0,
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.timer_channel = 5,
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},
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*/
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};
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void ucans32k_timer_initialize(void)
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{
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/* Select external clock (set to SOSC in periphclocks.c) as source for FTM0, and FTM2 */
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uint32_t regval = _REG(S32K1XX_FTM0_SC);
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regval &= ~(FTM_SC_CLKS_MASK);
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regval |= FTM_SC_CLKS_FTM;
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_REG(S32K1XX_FTM0_SC) = regval;
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regval = _REG(S32K1XX_FTM2_SC);
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regval &= ~(FTM_SC_CLKS_MASK);
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regval |= FTM_SC_CLKS_FTM;
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_REG(S32K1XX_FTM2_SC) = regval;
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/* Enabled System Clock Gating Control for FTM0, and FTM2 */
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regval = _REG(S32K1XX_PCC_FTM0);
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regval |= PCC_CGC;
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_REG(S32K1XX_PCC_FTM0) = regval;
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regval = _REG(S32K1XX_PCC_FTM2);
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regval |= PCC_CGC;
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_REG(S32K1XX_PCC_FTM2) = regval;
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}
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