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MR-CANHUBK344 NXP B3RB Rover support (#23897)

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* s32k3xx: EMIOS allow independent frequencies for each channel

* mr-canhubk3: update config

* mr-canhubk344: Fix adap board detect

* mr-canhubk344: Use LPSPI1 (Port P1A) for SD card

* airframes: Add B3RB Ackermann rover config

See https://nxp.gitbook.io/mr-b3rb for more information about the NXP
B3RB platform. PX4 Support basic control for now
This commit is contained in:
Peter van der Perk
2025-10-09 23:28:43 -08:00
committed by GitHub
parent d6f7519df0
commit 2f48cb4ef2
12 changed files with 170 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files
boards/nxp/mr-canhubk3/fmu.px4board
+8 -2
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@@ -1,6 +1,8 @@
# CONFIG_BOARD_ROMFSROOT is not set
CONFIG_DRIVERS_BAROMETER_BMP388=n
CONFIG_DRIVERS_MAGNETOMETER_BOSCH_BMM150=n
CONFIG_ARCH_CHIP_S32K3XX=y
CONFIG_BOARD_PWM_FREQ=1000000
CONFIG_BOARD_SERIAL_GPS1="/dev/ttyS1"
CONFIG_BOARD_SERIAL_GPS2="/dev/ttyS4"
CONFIG_BOARD_SERIAL_RC="/dev/ttyS5"
@@ -20,6 +22,7 @@ CONFIG_DRIVERS_DISTANCE_SENSOR_LIGHTWARE_SF45_SERIAL=y
CONFIG_DRIVERS_GPS=y
CONFIG_DRIVERS_IRLOCK=y
CONFIG_DRIVERS_RC_INPUT=y
CONFIG_DRIVERS_ROBOCLAW=y
CONFIG_DRIVERS_SAFETY_BUTTON=y
CONFIG_DRIVERS_UAVCAN=y
CONFIG_EXAMPLES_FAKE_GPS=y
@@ -33,9 +36,10 @@ CONFIG_MODULES_EVENTS=y
CONFIG_MODULES_FLIGHT_MODE_MANAGER=y
CONFIG_MODULES_FW_ATT_CONTROL=y
CONFIG_MODULES_FW_AUTOTUNE_ATTITUDE_CONTROL=y
CONFIG_MODULES_FW_MODE_MANAGER=y
CONFIG_MODULES_FW_LATERAL_LONGITUDINAL_CONTROL=y
CONFIG_MODULES_FW_MODE_MANAGER=y
CONFIG_MODULES_FW_RATE_CONTROL=y
CONFIG_MODULES_GIMBAL=y
CONFIG_MODULES_GYRO_CALIBRATION=y
CONFIG_MODULES_GYRO_FFT=y
CONFIG_MODULES_LANDING_TARGET_ESTIMATOR=y
@@ -50,8 +54,10 @@ CONFIG_MODULES_MC_AUTOTUNE_ATTITUDE_CONTROL=y
CONFIG_MODULES_MC_HOVER_THRUST_ESTIMATOR=y
CONFIG_MODULES_MC_POS_CONTROL=y
CONFIG_MODULES_MC_RATE_CONTROL=y
CONFIG_MODULES_NAVIGATOR=y
CONFIG_MODULES_RC_UPDATE=y
CONFIG_MODULES_ROVER_ACKERMANN=y
CONFIG_MODULES_ROVER_DIFFERENTIAL=y
CONFIG_MODULES_ROVER_MECANUM=y
CONFIG_MODULES_TEMPERATURE_COMPENSATION=y
CONFIG_MODULES_UXRCE_DDS_CLIENT=y
CONFIG_MODULES_VTOL_ATT_CONTROL=y
boards/nxp/mr-canhubk3/nuttx-config/nsh/defconfig
+15
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@@ -94,6 +94,7 @@ CONFIG_FAT_LFN_ALIAS_HASH=y
CONFIG_FDCLONE_STDIO=y
CONFIG_FS26_SPI_FREQUENCY=5000000
CONFIG_FSUTILS_IPCFG=y
CONFIG_FS_BINFS=y
CONFIG_FS_CROMFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FATTIME=y
@@ -126,16 +127,24 @@ CONFIG_LPUART0_IFLOWCONTROL=y
CONFIG_LPUART0_OFLOWCONTROL=y
CONFIG_LPUART0_RXBUFSIZE=640
CONFIG_LPUART0_RXDMA=y
CONFIG_LPUART0_TXBUFSIZE=1100
CONFIG_LPUART0_TXDMA=y
CONFIG_LPUART13_RXDMA=y
CONFIG_LPUART13_TXDMA=y
CONFIG_LPUART14_RXDMA=y
CONFIG_LPUART14_TXDMA=y
CONFIG_LPUART1_RXBUFSIZE=600
CONFIG_LPUART1_RXDMA=y
CONFIG_LPUART1_TXBUFSIZE=1100
CONFIG_LPUART1_TXDMA=y
CONFIG_LPUART2_RXDMA=y
CONFIG_LPUART2_SERIAL_CONSOLE=y
CONFIG_LPUART2_TXDMA=y
CONFIG_LPUART4_RXBUFSIZE=600
CONFIG_LPUART4_TXBUFSIZE=600
CONFIG_LPUART7_RXDMA=y
CONFIG_LPUART7_TXBUFSIZE=1500
CONFIG_LPUART7_TXDMA=y
CONFIG_MEMSET_64BIT=y
CONFIG_MEMSET_OPTSPEED=y
CONFIG_MMCSD=y
@@ -197,6 +206,7 @@ CONFIG_NSH_LINELEN=128
CONFIG_NSH_MAXARGUMENTS=15
CONFIG_NSH_MMCSDSPIPORTNO=1
CONFIG_NSH_NESTDEPTH=8
CONFIG_NSH_READLINE=y
CONFIG_NSH_QUOTE=y
CONFIG_NSH_ROMFSETC=y
CONFIG_NSH_ROMFSSECTSIZE=128
@@ -213,6 +223,8 @@ CONFIG_PTHREAD_STACK_MIN=512
CONFIG_RAM_SIZE=272000
CONFIG_RAM_START=0x20400000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_READLINE_TABCOMPLETION=y
CONFIG_S32K3XX_DTCM_HEAP=y
CONFIG_S32K3XX_EDMA=y
CONFIG_S32K3XX_EDMA_EDBG=y
@@ -280,7 +292,10 @@ CONFIG_STACK_COLORATION=y
CONFIG_START_DAY=30
CONFIG_START_MONTH=11
CONFIG_STDIO_BUFFER_SIZE=256
CONFIG_SYSTEM_CLE=y
CONFIG_SYSTEM_DHCPC_RENEW=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_PING=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_TASK_NAME_SIZE=24
CONFIG_USEC_PER_TICK=1000
boards/nxp/mr-canhubk3/src/board_config.h
+1 -1
View File
@@ -112,7 +112,7 @@ __BEGIN_DECLS
/* To detect MR-CANHUBK3-ADAP board */
#define BOARD_HAS_HW_VERSIONING 1
#define CANHUBK3_ADAP_DETECT (PIN_PTA12 | GPIO_INPUT | GPIO_PULLUP)
#define CANHUBK3_ADAP_DETECT (PIN_PTA11 | GPIO_INPUT | GPIO_PULLUP)
/*
boards/nxp/mr-canhubk3/src/init.c
+5 -5
View File
@@ -105,18 +105,18 @@ __EXPORT int board_app_initialize(uintptr_t arg)
/* Configure LPSPI1 peripheral chip select */
s32k3xx_pinconfig(PIN_LPSPI2_PCS);
s32k3xx_pinconfig(PIN_LPSPI1_PCS);
/* Initialize the SPI driver for LPSPI1 */
struct spi_dev_s *g_lpspi2 = s32k3xx_lpspibus_initialize(2);
struct spi_dev_s *g_lpspi1 = s32k3xx_lpspibus_initialize(1);
if (g_lpspi2 == NULL) {
spierr("ERROR: FAILED to initialize LPSPI2\n");
if (g_lpspi1 == NULL) {
spierr("ERROR: FAILED to initialize LPSPI1\n");
return -ENODEV;
}
rv = mmcsd_spislotinitialize(0, 0, g_lpspi2);
rv = mmcsd_spislotinitialize(0, 0, g_lpspi1);
if (rv < 0) {
mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n",
boards/nxp/mr-canhubk3/src/timer_config.cpp
+16 -9
View File
@@ -51,18 +51,25 @@
constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
initIOTimer(Timer::EMIOS0)
initIOTimer(Timer::EMIOS0_Channel0, Timer::Channel0),
initIOTimer(Timer::EMIOS0_Channel1, Timer::Channel1),
initIOTimer(Timer::EMIOS0_Channel2, Timer::Channel2),
initIOTimer(Timer::EMIOS0_Channel3, Timer::Channel3),
initIOTimer(Timer::EMIOS0_Channel4, Timer::Channel4),
initIOTimer(Timer::EMIOS0_Channel5, Timer::Channel5),
initIOTimer(Timer::EMIOS0_Channel6, Timer::Channel6),
initIOTimer(Timer::EMIOS0_Channel7, Timer::Channel7),
};
constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel0}, PIN_EMIOS0_CH0_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel1}, PIN_EMIOS0_CH1_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel2}, PIN_EMIOS0_CH2_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel3}, PIN_EMIOS0_CH3_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel4}, PIN_EMIOS0_CH4_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel5}, PIN_EMIOS0_CH5_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel6}, PIN_EMIOS0_CH6_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel7}, PIN_EMIOS0_CH7_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel0, Timer::Channel0}, PIN_EMIOS0_CH0_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel1, Timer::Channel1}, PIN_EMIOS0_CH1_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel2, Timer::Channel2}, PIN_EMIOS0_CH2_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel3, Timer::Channel3}, PIN_EMIOS0_CH3_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel4, Timer::Channel4}, PIN_EMIOS0_CH4_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel5, Timer::Channel5}, PIN_EMIOS0_CH5_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel6, Timer::Channel6}, PIN_EMIOS0_CH6_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel7, Timer::Channel7}, PIN_EMIOS0_CH7_2),
};
constexpr io_timers_channel_mapping_t io_timers_channel_mapping =