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MR-CANHUBK344 NXP B3RB Rover support (#23897)

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* s32k3xx: EMIOS allow independent frequencies for each channel

* mr-canhubk3: update config

* mr-canhubk344: Fix adap board detect

* mr-canhubk344: Use LPSPI1 (Port P1A) for SD card

* airframes: Add B3RB Ackermann rover config

See https://nxp.gitbook.io/mr-b3rb for more information about the NXP
B3RB platform. PX4 Support basic control for now
This commit is contained in:
Peter van der Perk 2025-10-10 09:28:43 +02:00 committed by GitHub
parent d6f7519df0
commit 2f48cb4ef2
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
12 changed files with 170 additions and 39 deletions
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31
ROMFS/px4fmu_common/init.d/airframes/51002_nxp_b3rb Normal file
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@ -0,0 +1,31 @@
#!/bin/sh
#
# @name NXP B3RB Rover Ackermann
#
# @type Rover
# @class Rover
#
# @board px4_fmu-v2 exclude
# @board bitcraze_crazyflie exclude
#
. ${R}etc/init.d/rc.rover_ackermann_defaults
param set-default BAT1_N_CELLS 3
# Set geometry & output configration
param set-default PWM_MAIN_FUNC1 201
param set-default PWM_MAIN_FUNC2 101
param set-default PWM_MAIN_FUNC3 101
param set-default PWM_MAIN_DIS1 1500
param set-default PWM_MAIN_DIS2 0
param set-default PWM_MAIN_DIS3 1500
param set-default PWM_MAIN_MIN1 1000
param set-default PWM_MAIN_MIN2 2500
param set-default PWM_MAIN_MIN3 0
param set-default PWM_MAIN_MAX1 2000
param set-default PWM_MAIN_MAX2 2500
param set-default PWM_MAIN_MAX3 50
param set-default PWM_MAIN_TIM0 400
param set-default PWM_MAIN_TIM1 400
param set-default PWM_MAIN_TIM2 20000

1
ROMFS/px4fmu_common/init.d/airframes/CMakeLists.txt
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@ -153,6 +153,7 @@ if(CONFIG_MODULES_ROVER_ACKERMANN)
# [51000, 51999] Ackermann rovers
51000_generic_rover_ackermann
51001_axial_scx10_2_trail_honcho
51002_nxp_b3rb
)
endif()

10
boards/nxp/mr-canhubk3/fmu.px4board
View File

@ -1,6 +1,8 @@
# CONFIG_BOARD_ROMFSROOT is not set
CONFIG_DRIVERS_BAROMETER_BMP388=n
CONFIG_DRIVERS_MAGNETOMETER_BOSCH_BMM150=n
CONFIG_ARCH_CHIP_S32K3XX=y
CONFIG_BOARD_PWM_FREQ=1000000
CONFIG_BOARD_SERIAL_GPS1="/dev/ttyS1"
CONFIG_BOARD_SERIAL_GPS2="/dev/ttyS4"
CONFIG_BOARD_SERIAL_RC="/dev/ttyS5"
@ -20,6 +22,7 @@ CONFIG_DRIVERS_DISTANCE_SENSOR_LIGHTWARE_SF45_SERIAL=y
CONFIG_DRIVERS_GPS=y
CONFIG_DRIVERS_IRLOCK=y
CONFIG_DRIVERS_RC_INPUT=y
CONFIG_DRIVERS_ROBOCLAW=y
CONFIG_DRIVERS_SAFETY_BUTTON=y
CONFIG_DRIVERS_UAVCAN=y
CONFIG_EXAMPLES_FAKE_GPS=y
@ -33,9 +36,10 @@ CONFIG_MODULES_EVENTS=y
CONFIG_MODULES_FLIGHT_MODE_MANAGER=y
CONFIG_MODULES_FW_ATT_CONTROL=y
CONFIG_MODULES_FW_AUTOTUNE_ATTITUDE_CONTROL=y
CONFIG_MODULES_FW_MODE_MANAGER=y
CONFIG_MODULES_FW_LATERAL_LONGITUDINAL_CONTROL=y
CONFIG_MODULES_FW_MODE_MANAGER=y
CONFIG_MODULES_FW_RATE_CONTROL=y
CONFIG_MODULES_GIMBAL=y
CONFIG_MODULES_GYRO_CALIBRATION=y
CONFIG_MODULES_GYRO_FFT=y
CONFIG_MODULES_LANDING_TARGET_ESTIMATOR=y
@ -50,8 +54,10 @@ CONFIG_MODULES_MC_AUTOTUNE_ATTITUDE_CONTROL=y
CONFIG_MODULES_MC_HOVER_THRUST_ESTIMATOR=y
CONFIG_MODULES_MC_POS_CONTROL=y
CONFIG_MODULES_MC_RATE_CONTROL=y
CONFIG_MODULES_NAVIGATOR=y
CONFIG_MODULES_RC_UPDATE=y
CONFIG_MODULES_ROVER_ACKERMANN=y
CONFIG_MODULES_ROVER_DIFFERENTIAL=y
CONFIG_MODULES_ROVER_MECANUM=y
CONFIG_MODULES_TEMPERATURE_COMPENSATION=y
CONFIG_MODULES_UXRCE_DDS_CLIENT=y
CONFIG_MODULES_VTOL_ATT_CONTROL=y

15
boards/nxp/mr-canhubk3/nuttx-config/nsh/defconfig
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@ -94,6 +94,7 @@ CONFIG_FAT_LFN_ALIAS_HASH=y
CONFIG_FDCLONE_STDIO=y
CONFIG_FS26_SPI_FREQUENCY=5000000
CONFIG_FSUTILS_IPCFG=y
CONFIG_FS_BINFS=y
CONFIG_FS_CROMFS=y
CONFIG_FS_FAT=y
CONFIG_FS_FATTIME=y
@ -126,16 +127,24 @@ CONFIG_LPUART0_IFLOWCONTROL=y
CONFIG_LPUART0_OFLOWCONTROL=y
CONFIG_LPUART0_RXBUFSIZE=640
CONFIG_LPUART0_RXDMA=y
CONFIG_LPUART0_TXBUFSIZE=1100
CONFIG_LPUART0_TXDMA=y
CONFIG_LPUART13_RXDMA=y
CONFIG_LPUART13_TXDMA=y
CONFIG_LPUART14_RXDMA=y
CONFIG_LPUART14_TXDMA=y
CONFIG_LPUART1_RXBUFSIZE=600
CONFIG_LPUART1_RXDMA=y
CONFIG_LPUART1_TXBUFSIZE=1100
CONFIG_LPUART1_TXDMA=y
CONFIG_LPUART2_RXDMA=y
CONFIG_LPUART2_SERIAL_CONSOLE=y
CONFIG_LPUART2_TXDMA=y
CONFIG_LPUART4_RXBUFSIZE=600
CONFIG_LPUART4_TXBUFSIZE=600
CONFIG_LPUART7_RXDMA=y
CONFIG_LPUART7_TXBUFSIZE=1500
CONFIG_LPUART7_TXDMA=y
CONFIG_MEMSET_64BIT=y
CONFIG_MEMSET_OPTSPEED=y
CONFIG_MMCSD=y
@ -197,6 +206,7 @@ CONFIG_NSH_LINELEN=128
CONFIG_NSH_MAXARGUMENTS=15
CONFIG_NSH_MMCSDSPIPORTNO=1
CONFIG_NSH_NESTDEPTH=8
CONFIG_NSH_READLINE=y
CONFIG_NSH_QUOTE=y
CONFIG_NSH_ROMFSETC=y
CONFIG_NSH_ROMFSSECTSIZE=128
@ -213,6 +223,8 @@ CONFIG_PTHREAD_STACK_MIN=512
CONFIG_RAM_SIZE=272000
CONFIG_RAM_START=0x20400000
CONFIG_RAW_BINARY=y
CONFIG_READLINE_CMD_HISTORY=y
CONFIG_READLINE_TABCOMPLETION=y
CONFIG_S32K3XX_DTCM_HEAP=y
CONFIG_S32K3XX_EDMA=y
CONFIG_S32K3XX_EDMA_EDBG=y
@ -280,7 +292,10 @@ CONFIG_STACK_COLORATION=y
CONFIG_START_DAY=30
CONFIG_START_MONTH=11
CONFIG_STDIO_BUFFER_SIZE=256
CONFIG_SYSTEM_CLE=y
CONFIG_SYSTEM_DHCPC_RENEW=y
CONFIG_SYSTEM_NSH=y
CONFIG_SYSTEM_PING=y
CONFIG_SYSTEM_SYSTEM=y
CONFIG_TASK_NAME_SIZE=24
CONFIG_USEC_PER_TICK=1000

2
boards/nxp/mr-canhubk3/src/board_config.h
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@ -112,7 +112,7 @@ __BEGIN_DECLS
/* To detect MR-CANHUBK3-ADAP board */
#define BOARD_HAS_HW_VERSIONING 1
#define CANHUBK3_ADAP_DETECT (PIN_PTA12 | GPIO_INPUT | GPIO_PULLUP)
#define CANHUBK3_ADAP_DETECT (PIN_PTA11 | GPIO_INPUT | GPIO_PULLUP)
/*

10
boards/nxp/mr-canhubk3/src/init.c
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@ -105,18 +105,18 @@ __EXPORT int board_app_initialize(uintptr_t arg)
/* Configure LPSPI1 peripheral chip select */
s32k3xx_pinconfig(PIN_LPSPI2_PCS);
s32k3xx_pinconfig(PIN_LPSPI1_PCS);
/* Initialize the SPI driver for LPSPI1 */
struct spi_dev_s *g_lpspi2 = s32k3xx_lpspibus_initialize(2);
struct spi_dev_s *g_lpspi1 = s32k3xx_lpspibus_initialize(1);
if (g_lpspi2 == NULL) {
spierr("ERROR: FAILED to initialize LPSPI2\n");
if (g_lpspi1 == NULL) {
spierr("ERROR: FAILED to initialize LPSPI1\n");
return -ENODEV;
}
rv = mmcsd_spislotinitialize(0, 0, g_lpspi2);
rv = mmcsd_spislotinitialize(0, 0, g_lpspi1);
if (rv < 0) {
mcerr("ERROR: Failed to bind SPI port %d to SD slot %d\n",

25
boards/nxp/mr-canhubk3/src/timer_config.cpp
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@ -51,18 +51,25 @@
constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
initIOTimer(Timer::EMIOS0)
initIOTimer(Timer::EMIOS0_Channel0, Timer::Channel0),
initIOTimer(Timer::EMIOS0_Channel1, Timer::Channel1),
initIOTimer(Timer::EMIOS0_Channel2, Timer::Channel2),
initIOTimer(Timer::EMIOS0_Channel3, Timer::Channel3),
initIOTimer(Timer::EMIOS0_Channel4, Timer::Channel4),
initIOTimer(Timer::EMIOS0_Channel5, Timer::Channel5),
initIOTimer(Timer::EMIOS0_Channel6, Timer::Channel6),
initIOTimer(Timer::EMIOS0_Channel7, Timer::Channel7),
};
constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel0}, PIN_EMIOS0_CH0_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel1}, PIN_EMIOS0_CH1_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel2}, PIN_EMIOS0_CH2_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel3}, PIN_EMIOS0_CH3_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel4}, PIN_EMIOS0_CH4_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel5}, PIN_EMIOS0_CH5_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel6}, PIN_EMIOS0_CH6_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0, Timer::Channel7}, PIN_EMIOS0_CH7_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel0, Timer::Channel0}, PIN_EMIOS0_CH0_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel1, Timer::Channel1}, PIN_EMIOS0_CH1_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel2, Timer::Channel2}, PIN_EMIOS0_CH2_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel3, Timer::Channel3}, PIN_EMIOS0_CH3_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel4, Timer::Channel4}, PIN_EMIOS0_CH4_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel5, Timer::Channel5}, PIN_EMIOS0_CH5_2),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel6, Timer::Channel6}, PIN_EMIOS0_CH6_1),
initIOTimerChannel(io_timers, {Timer::EMIOS0_Channel7, Timer::Channel7}, PIN_EMIOS0_CH7_2),
};
constexpr io_timers_channel_mapping_t io_timers_channel_mapping =

62
platforms/nuttx/src/px4/nxp/s32k3xx/include/px4_arch/hw_description.h
View File

@ -46,10 +46,34 @@
namespace Timer
{
// Just to keep def extract_timer(line): happy
enum Timer {
EMIOS0 = 0,
EMIOS1,
EMIOS2,
EMIOS0_Channel0,
EMIOS0_Channel1,
EMIOS0_Channel2,
EMIOS0_Channel3,
EMIOS0_Channel4,
EMIOS0_Channel5,
EMIOS0_Channel6,
EMIOS0_Channel7,
EMIOS1_Channel0,
EMIOS1_Channel1,
EMIOS1_Channel2,
EMIOS1_Channel3,
EMIOS1_Channel4,
EMIOS1_Channel5,
EMIOS1_Channel6,
EMIOS1_Channel7,
EMIOS2_Channel0,
EMIOS2_Channel1,
EMIOS2_Channel2,
EMIOS2_Channel3,
EMIOS2_Channel4,
EMIOS2_Channel5,
EMIOS2_Channel6,
EMIOS2_Channel7,
};
enum Channel {
Channel0 = 0,
@ -70,11 +94,37 @@ struct TimerChannel {
static inline constexpr uint32_t timerBaseRegister(Timer::Timer timer)
{
switch (timer) {
case Timer::EMIOS0: return S32K3XX_EMIOS0_BASE;
case Timer::EMIOS0_Channel0:
case Timer::EMIOS0_Channel1:
case Timer::EMIOS0_Channel2:
case Timer::EMIOS0_Channel3:
case Timer::EMIOS0_Channel4:
case Timer::EMIOS0_Channel5:
case Timer::EMIOS0_Channel6:
case Timer::EMIOS0_Channel7:
return S32K3XX_EMIOS0_BASE;
case Timer::EMIOS1: return S32K3XX_EMIOS1_BASE;
case Timer::EMIOS2: return S32K3XX_EMIOS2_BASE;
case Timer::EMIOS1_Channel0:
case Timer::EMIOS1_Channel1:
case Timer::EMIOS1_Channel2:
case Timer::EMIOS1_Channel3:
case Timer::EMIOS1_Channel4:
case Timer::EMIOS1_Channel5:
case Timer::EMIOS1_Channel6:
case Timer::EMIOS1_Channel7:
return S32K3XX_EMIOS1_BASE;
case Timer::EMIOS2_Channel0:
case Timer::EMIOS2_Channel1:
case Timer::EMIOS2_Channel2:
case Timer::EMIOS2_Channel3:
case Timer::EMIOS2_Channel4:
case Timer::EMIOS2_Channel5:
case Timer::EMIOS2_Channel6:
case Timer::EMIOS2_Channel7:
return S32K3XX_EMIOS2_BASE;
}
return 0;

3
platforms/nuttx/src/px4/nxp/s32k3xx/include/px4_arch/io_timer.h
View File

@ -45,7 +45,7 @@
#pragma once
__BEGIN_DECLS
/* configuration limits */
#define MAX_IO_TIMERS 1
#define MAX_IO_TIMERS 8
#define MAX_TIMER_IO_CHANNELS 8
#define MAX_LED_TIMERS 2
@ -88,6 +88,7 @@ typedef struct io_timers_t {
uint32_t vectorno_12_15; /* IRQ number */
uint32_t vectorno_16_19; /* IRQ number */
uint32_t vectorno_20_23; /* IRQ number */
uint32_t channel;
} io_timers_t;
typedef struct io_timers_channel_mapping_element_t {

41
platforms/nuttx/src/px4/nxp/s32k3xx/include/px4_arch/io_timer_hw_description.h
View File

@ -55,15 +55,7 @@ static inline constexpr timer_io_channels_t initIOTimerChannel(const io_timers_t
ret.timer_channel = (int)timer.channel + 1;
// find timer index
ret.timer_index = 0xff;
const uint32_t timer_base = timerBaseRegister(timer.timer);
for (int i = 0; i < MAX_IO_TIMERS; ++i) {
if (io_timers_conf[i].base == timer_base) {
ret.timer_index = i;
break;
}
}
ret.timer_index = timer.channel;
constexpr_assert(ret.timer_index != 0xff, "Timer not found");
@ -80,13 +72,20 @@ static inline constexpr timer_io_channels_t initIOTimerChannel(const io_timers_t
* Ch20 - Ch23 = vectorno - 5
*/
static inline constexpr io_timers_t initIOTimer(Timer::Timer timer)
static inline constexpr io_timers_t initIOTimer(Timer::Timer timer, Timer::Channel channel)
{
bool nuttx_config_timer_enabled = false;
io_timers_t ret{};
switch (timer) {
case Timer::EMIOS0:
case Timer::EMIOS0_Channel0:
case Timer::EMIOS0_Channel1:
case Timer::EMIOS0_Channel2:
case Timer::EMIOS0_Channel3:
case Timer::EMIOS0_Channel4:
case Timer::EMIOS0_Channel5:
case Timer::EMIOS0_Channel6:
case Timer::EMIOS0_Channel7:
ret.base = S32K3XX_EMIOS0_BASE;
ret.clock_register = 0;
ret.clock_bit = 0;
@ -96,12 +95,20 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer)
ret.vectorno_12_15 = S32K3XX_IRQ_EMIOS0_12_15;
ret.vectorno_16_19 = S32K3XX_IRQ_EMIOS0_16_19;
ret.vectorno_20_23 = S32K3XX_IRQ_EMIOS0_20_23;
ret.channel = channel;
#ifdef CONFIG_S32K3XX_EMIOS0
nuttx_config_timer_enabled = true;
#endif
break;
case Timer::EMIOS1:
case Timer::EMIOS1_Channel0:
case Timer::EMIOS1_Channel1:
case Timer::EMIOS1_Channel2:
case Timer::EMIOS1_Channel3:
case Timer::EMIOS1_Channel4:
case Timer::EMIOS1_Channel5:
case Timer::EMIOS1_Channel6:
case Timer::EMIOS1_Channel7:
ret.base = S32K3XX_EMIOS1_BASE;
ret.clock_register = 0;
ret.clock_bit = 0;
@ -116,7 +123,15 @@ static inline constexpr io_timers_t initIOTimer(Timer::Timer timer)
#endif
break;
case Timer::EMIOS2:
case Timer::EMIOS2_Channel0:
case Timer::EMIOS2_Channel1:
case Timer::EMIOS2_Channel2:
case Timer::EMIOS2_Channel3:
case Timer::EMIOS2_Channel4:
case Timer::EMIOS2_Channel5:
case Timer::EMIOS2_Channel6:
case Timer::EMIOS2_Channel7:
ret.base = S32K3XX_EMIOS2_BASE;
ret.clock_register = 0;
ret.clock_bit = 0;

5
platforms/nuttx/src/px4/nxp/s32k3xx/io_pins/io_timer.c
View File

@ -868,6 +868,11 @@ int io_timer_set_ccr(unsigned channel, uint16_t value)
} else {
//FIXME why multiple by 2
if ((rC(channels_timer(channel), channel) & EMIOS_C_UCPRE_MASK) == 0) {
value = value * 4;
}
/* configure the channel */
irqstate_t flags = px4_enter_critical_section();
rA(channels_timer(channel), timer_io_channels[channel].timer_channel - 1) = EMIOS_A(value * 2);

4
platforms/nuttx/src/px4/nxp/s32k3xx/io_pins/pwm_servo.c
View File

@ -128,13 +128,13 @@ int up_pwm_servo_set_rate_group_update(unsigned channel, unsigned rate)
if (rate != 0) {
/* limit update rate to 1..10000Hz; somewhat arbitrary but safe */
/* limit update rate to 1..20000Hz; somewhat arbitrary but safe */
if (rate < 1) {
return -ERANGE;
}
if (rate > 10000) {
if (rate > 20000) {
return -ERANGE;
}
}