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LPC11C24 clock driver bug fix: SysTick pending bit is checked in SCB.ICSR, which is the only right way according to the Cortex-M0 manual
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@@ -56,15 +56,13 @@ void init()
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}
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}
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// Optimizer breaks this function.
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__attribute__((optimize("0")))
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static uint64_t sampleFromCriticalSection(const volatile uint64_t* const value)
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{
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const uint32_t reload = SysTick->LOAD; // SysTick counts downwards, hence the value subtracted from reload
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const uint32_t reload = SysTick->LOAD + 1; // SysTick counts downwards, hence the value subtracted from reload
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volatile uint64_t time = *value;
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volatile uint32_t cycles = reload - SysTick->VAL;
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if (NVIC_GetPendingIRQ(SysTick_IRQn))
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if ((SCB->ICSR & SCB_ICSR_PENDSTSET_Msk) == SCB_ICSR_PENDSTSET_Msk)
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{
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/*
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* The timer has overflowed either before or after CNT sample was obtained.
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@@ -101,16 +99,13 @@ uavcan::MonotonicTime getMonotonic()
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uavcan::UtcTime getUtc()
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{
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uint64_t usec = 0;
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if (utc_set)
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{
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uint64_t usec = 0;
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{
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CriticalSectionLocker locker;
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usec = sampleFromCriticalSection(&time_utc);
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}
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return uavcan::UtcTime::fromUSec(usec);
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CriticalSectionLocker locker;
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usec = sampleFromCriticalSection(&time_utc);
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}
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return uavcan::UtcTime();
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return uavcan::UtcTime::fromUSec(usec);
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}
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uavcan::UtcDuration getPrevUtcAdjustment()
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@@ -169,7 +164,6 @@ SystemClock& SystemClock::instance()
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extern "C"
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{
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__attribute__((optimize("0")))
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void SysTick_Handler()
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{
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using namespace uavcan_lpc11c24::clock;
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