mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-10-22 01:33:35 +08:00
Andrew Tridgell
9064f8bf09
this fixes the PX4IO state machine to avoid the io errors we were seeing. There are still some open questions with this code, but it now seems to give zero errors, which is an improvement!
342 lines
8.7 KiB
C
342 lines
8.7 KiB
C
/****************************************************************************
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*
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* Copyright (C) 2012,2013 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/**
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* @file i2c.c
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*
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* I2C communication for the PX4IO module.
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*/
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#include <stdint.h>
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#include <nuttx/arch.h>
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#include <arch/board/board.h>
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#include <stm32_i2c.h>
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#include <stm32_dma.h>
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//#define DEBUG
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#include "px4io.h"
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/*
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* I2C register definitions.
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*/
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#define I2C_BASE STM32_I2C1_BASE
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#define REG(_reg) (*(volatile uint32_t *)(I2C_BASE + _reg))
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#define rCR1 REG(STM32_I2C_CR1_OFFSET)
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#define rCR2 REG(STM32_I2C_CR2_OFFSET)
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#define rOAR1 REG(STM32_I2C_OAR1_OFFSET)
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#define rOAR2 REG(STM32_I2C_OAR2_OFFSET)
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#define rDR REG(STM32_I2C_DR_OFFSET)
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#define rSR1 REG(STM32_I2C_SR1_OFFSET)
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#define rSR2 REG(STM32_I2C_SR2_OFFSET)
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#define rCCR REG(STM32_I2C_CCR_OFFSET)
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#define rTRISE REG(STM32_I2C_TRISE_OFFSET)
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static int i2c_interrupt(int irq, void *context);
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static void i2c_rx_setup(void);
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static void i2c_tx_setup(void);
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static void i2c_rx_complete(void);
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static void i2c_tx_complete(void);
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static void i2c_dump(void);
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static DMA_HANDLE rx_dma;
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static DMA_HANDLE tx_dma;
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static uint8_t rx_buf[68];
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static unsigned rx_len;
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static const uint8_t junk_buf[] = { 0xff, 0xff, 0xff, 0xff };
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static const uint8_t *tx_buf = junk_buf;
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static unsigned tx_len = sizeof(junk_buf);
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unsigned tx_count;
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static uint8_t selected_page;
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static uint8_t selected_offset;
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enum {
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DIR_NONE = 0,
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DIR_TX = 1,
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DIR_RX = 2
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} direction;
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void
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interface_init(void)
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{
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debug("i2c init");
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/* allocate DMA handles and initialise DMA */
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rx_dma = stm32_dmachannel(DMACHAN_I2C1_RX);
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i2c_rx_setup();
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tx_dma = stm32_dmachannel(DMACHAN_I2C1_TX);
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i2c_tx_setup();
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/* enable the i2c block clock and reset it */
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modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C1EN);
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modifyreg32(STM32_RCC_APB1RSTR, 0, RCC_APB1RSTR_I2C1RST);
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modifyreg32(STM32_RCC_APB1RSTR, RCC_APB1RSTR_I2C1RST, 0);
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/* configure the i2c GPIOs */
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stm32_configgpio(GPIO_I2C1_SCL);
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stm32_configgpio(GPIO_I2C1_SDA);
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/* soft-reset the block */
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rCR1 |= I2C_CR1_SWRST;
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rCR1 = 0;
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/* set for DMA operation */
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rCR2 |= I2C_CR2_ITEVFEN |I2C_CR2_ITERREN | I2C_CR2_DMAEN;
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/* set the frequency value in CR2 */
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rCR2 &= ~I2C_CR2_FREQ_MASK;
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rCR2 |= STM32_PCLK1_FREQUENCY / 1000000;
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/* set divisor and risetime for fast mode */
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uint16_t result = STM32_PCLK1_FREQUENCY / (400000 * 25);
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if (result < 1)
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result = 1;
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result = 3;
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rCCR &= ~I2C_CCR_CCR_MASK;
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rCCR |= I2C_CCR_DUTY | I2C_CCR_FS | result;
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rTRISE = (uint16_t)((((STM32_PCLK1_FREQUENCY / 1000000) * 300) / 1000) + 1);
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/* set our device address */
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rOAR1 = 0x1a << 1;
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/* enable event interrupts */
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irq_attach(STM32_IRQ_I2C1EV, i2c_interrupt);
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irq_attach(STM32_IRQ_I2C1ER, i2c_interrupt);
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up_enable_irq(STM32_IRQ_I2C1EV);
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up_enable_irq(STM32_IRQ_I2C1ER);
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/* and enable the I2C port */
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rCR1 |= I2C_CR1_ACK | I2C_CR1_PE;
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#ifdef DEBUG
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i2c_dump();
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#endif
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}
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/*
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reset the I2C bus
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used to recover from lockups
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*/
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void
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i2c_reset(void)
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{
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rCR1 |= I2C_CR1_SWRST;
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rCR1 = 0;
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/* set for DMA operation */
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rCR2 |= I2C_CR2_ITEVFEN |I2C_CR2_ITERREN | I2C_CR2_DMAEN;
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/* set the frequency value in CR2 */
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rCR2 &= ~I2C_CR2_FREQ_MASK;
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rCR2 |= STM32_PCLK1_FREQUENCY / 1000000;
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/* set divisor and risetime for fast mode */
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uint16_t result = STM32_PCLK1_FREQUENCY / (400000 * 25);
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if (result < 1)
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result = 1;
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result = 3;
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rCCR &= ~I2C_CCR_CCR_MASK;
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rCCR |= I2C_CCR_DUTY | I2C_CCR_FS | result;
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rTRISE = (uint16_t)((((STM32_PCLK1_FREQUENCY / 1000000) * 300) / 1000) + 1);
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/* set our device address */
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rOAR1 = 0x1a << 1;
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/* and enable the I2C port */
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rCR1 |= I2C_CR1_ACK | I2C_CR1_PE;
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}
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static int
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i2c_interrupt(int irq, FAR void *context)
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{
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uint16_t sr1 = rSR1;
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if (sr1 & (I2C_SR1_STOPF | I2C_SR1_AF | I2C_SR1_ADDR)) {
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if (sr1 & I2C_SR1_STOPF) {
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/* write to CR1 to clear STOPF */
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(void)rSR1; /* as recommended, re-read SR1 */
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rCR1 |= I2C_CR1_PE;
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}
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/* DMA never stops, so we should do that now */
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switch (direction) {
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case DIR_TX:
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i2c_tx_complete();
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break;
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case DIR_RX:
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i2c_rx_complete();
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break;
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default:
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/* not currently transferring - must be a new txn */
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break;
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}
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direction = DIR_NONE;
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}
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if (sr1 & I2C_SR1_ADDR) {
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/* clear ADDR to ack our selection and get direction */
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(void)rSR1; /* as recommended, re-read SR1 */
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uint16_t sr2 = rSR2;
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if (sr2 & I2C_SR2_TRA) {
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/* we are the transmitter */
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direction = DIR_TX;
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} else {
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/* we are the receiver */
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direction = DIR_RX;
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}
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}
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/* clear any errors that might need it (this handles AF as well */
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if (sr1 & I2C_SR1_ERRORMASK)
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rSR1 = 0;
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return 0;
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}
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static void
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i2c_rx_setup(void)
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{
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/*
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* Note that we configure DMA in circular mode; this means that a too-long
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* transfer will overwrite the buffer, but that avoids us having to deal with
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* bailing out of a transaction while the master is still babbling at us.
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*/
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rx_len = 0;
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stm32_dmasetup(rx_dma, (uintptr_t)&rDR, (uintptr_t)&rx_buf[0], sizeof(rx_buf),
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DMA_CCR_CIRC |
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DMA_CCR_MINC |
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DMA_CCR_PSIZE_32BITS |
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DMA_CCR_MSIZE_8BITS |
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DMA_CCR_PRIMED);
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stm32_dmastart(rx_dma, NULL, NULL, false);
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}
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static void
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i2c_rx_complete(void)
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{
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rx_len = sizeof(rx_buf) - stm32_dmaresidual(rx_dma);
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stm32_dmastop(rx_dma);
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if (rx_len >= 2) {
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selected_page = rx_buf[0];
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selected_offset = rx_buf[1];
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/* work out how many registers are being written */
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unsigned count = (rx_len - 2) / 2;
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if (count > 0) {
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registers_set(selected_page, selected_offset, (const uint16_t *)&rx_buf[2], count);
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} else {
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/* no registers written, must be an address cycle */
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uint16_t *regs;
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unsigned reg_count;
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/* work out which registers are being addressed */
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int ret = registers_get(selected_page, selected_offset, ®s, ®_count);
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if (ret == 0) {
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tx_buf = (uint8_t *)regs;
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tx_len = reg_count * 2;
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} else {
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tx_buf = junk_buf;
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tx_len = sizeof(junk_buf);
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}
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/* disable interrupts while reconfiguring DMA for the selected registers */
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irqstate_t flags = irqsave();
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stm32_dmastop(tx_dma);
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i2c_tx_setup();
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irqrestore(flags);
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}
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}
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/* prepare for the next transaction */
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i2c_rx_setup();
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}
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static void
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i2c_tx_setup(void)
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{
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/*
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* Note that we configure DMA in circular mode; this means that a too-long
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* transfer will copy the buffer more than once, but that avoids us having
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* to deal with bailing out of a transaction while the master is still
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* babbling at us.
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*/
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stm32_dmasetup(tx_dma, (uintptr_t)&rDR, (uintptr_t)&tx_buf[0], tx_len,
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DMA_CCR_DIR |
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DMA_CCR_CIRC |
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DMA_CCR_MINC |
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DMA_CCR_PSIZE_8BITS |
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DMA_CCR_MSIZE_8BITS |
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DMA_CCR_PRIMED);
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stm32_dmastart(tx_dma, NULL, NULL, false);
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}
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static void
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i2c_tx_complete(void)
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{
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tx_count = tx_len - stm32_dmaresidual(tx_dma);
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stm32_dmastop(tx_dma);
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/* for debug purposes, save the length of the last transmit as seen by the DMA */
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/* leave tx_buf/tx_len alone, so that a retry will see the same data */
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/* prepare for the next transaction */
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i2c_tx_setup();
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}
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static void
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i2c_dump(void)
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{
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debug("CR1 0x%08x CR2 0x%08x", rCR1, rCR2);
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debug("OAR1 0x%08x OAR2 0x%08x", rOAR1, rOAR2);
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debug("CCR 0x%08x TRISE 0x%08x", rCCR, rTRISE);
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debug("SR1 0x%08x SR2 0x%08x", rSR1, rSR2);
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}
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