mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-11-09 23:31:35 +08:00
nxp/rt117x:Fix Pin IRQ
nxp/rt117x:Support 4 i2c busses
nxp/rt117x:Add px4io_serial support
nxp/imxrt:Expand ToneAlarmInterface to GPT 3 & 4
nxp_fmurt1170-v1:Using imxrt_flexspi_nor_octal
nxp_fmurt1170-v1:Entry is start
nxp_fmurt1170-v1:Add Proper MTD
nxp_fmurt1170-v1:Set I2C Buses
nxp_fmurt1170-v1:Proper SPI usage
nxpfmurt1170-v1:Adjust memory Map to use the 2 MB
nxp_fmurt1170:Bring in ROMAPI
nxp_fmurt1170-v1:Push FLASH to 200Mhz
nxp_fmurt1170-v1:Use BOARD_I2C_LATEINIT
nxp_fmurt1170-v1:Clock Config remove unused devices
nxp_fmurt1170-v1:Remove EVK SDRAM IO
nxp_fmurt1170-v1:Enable SE550 using HW_VER_REV_DRIVE
nxp_fmurt1170-v1:Use MTD to mount FRAM on Flex SPI
nxp_fmurt1170-v1:Manifest
nxpi_fmurt1170-v1:Restore board_peripheral_reset
nxp_fmurt1170-v1:Set I2C buss Interna/Externa and startup
nxp/rt117x:Set 6 I2C busses
nxp_fmurt1170-v1:Correct Clock Sources and Freqency Settings
nxp_fmurt1170-v1:Correct ADC Settings
Tune FlexSPI config and sync header with debug variant Linker prep for rodata ahb partitioning
FlexSPI prefetch partition split .text and .rodata
Current config
1KB Prefetch .rodata
3KB Prefetch .text
nxp_fmurt1170-v1:Run imxrt_flash_setup_prefetch_partition from ram with barriers
nxp_fmurt1170-v1:Use All OCTL setting from FLASH g_flash_config SANS lookupTable
Octal spi boot/debug problem bypass
nxp_fmurt1170-v1:Add PWM test
Fix clockconfig and USB vbus sense
fmurt1170-v1: Use TCM
nxp_fmurt1170-v1: Ethernet bringup
imxrt: use unique_id register for board_identity
fmurt7: update ITCM mapping, todo proper trap on pc hitting 0x0
fmurt7: correct rotation icm42688p onboard imu
rt117x: Add SSARC HP RAM driver for memory dumps
nxp_fmurt1170-v1: Enable hardfault_log
nxp_fmurt1170-v1: Enable DMA pool
fmurt1170-v1: fix uart mapping
nxp_fmurt1170-v1: enable SocketCAN & DroneCAN
nxp_fmurt1170-v1:Command line history TAB completion
nxp_fmurt1170-v1:Fix pinning duplication
nxp_fmurt1170-v1:Support conditional PHY address based on selected PHY
nxp_fmurt1170-v1:Add Pull Downs on CTS, use GPIO for RTS
nxp_fmurt1170-v1:Set TelemN TX Slew rate and Drive Strenth to max
nxp_fmurt1170-v:Set TELEM Buffers add HW HS
nxp_fmurt1170-v1:Turn off DMA poll
nxp_fmurt1170-v1:RC_SERIAL_PORT needed to be px4io to disable rc_input using TELEM2!
imxrt1170 bootloader (#22228)
* imxrt:Add bootloader support
* bootloader:imxrt clear BOOT_RTC_SIGNATURE
* nxp_fmurt1170-v1:Add bootloader
* nxp_fmurt1170-v1:bootloader removed ADC
* nxp_fmurt1170-v1:bootloader base bootloader script off of script.ld
* nxp_fmurt1170-v1:add _bootdelay_signature & change entry from 0x30000000 to 0x30040000
* fmurt1170-v1:hw_config Bootloader has to have 12 bytes
nxp_fmurt1170-v1:Default to use LAN8742A PHY
75 lines
3.6 KiB
C
75 lines
3.6 KiB
C
/****************************************************************************
|
|
*
|
|
* Copyright (c) 2019 PX4 Development Team. All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions
|
|
* are met:
|
|
*
|
|
* 1. Redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer.
|
|
* 2. Redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in
|
|
* the documentation and/or other materials provided with the
|
|
* distribution.
|
|
* 3. Neither the name PX4 nor the names of its contributors may be
|
|
* used to endorse or promote products derived from this software
|
|
* without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
|
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
|
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
|
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
|
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
|
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
|
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
|
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
|
* POSSIBILITY OF SUCH DAMAGE.
|
|
*
|
|
****************************************************************************/
|
|
#pragma once
|
|
|
|
/* The modern flash controllers manage flash for ECC
|
|
* On the H7 there is a block size (256) bits
|
|
* This code translates between the bootloaders word read/write
|
|
* interface and the H7 need for block based writes.
|
|
*
|
|
* All writes* are buffered until 8 word can be written.
|
|
* Verification is made from the cache. On the verification of the
|
|
* 8th word all the wordfs in the the cache are written to flash.
|
|
* If the write fails the value returned for the last word is negated
|
|
* to ensure an error on verification.
|
|
*
|
|
* *writes to the first 8 words of flash at APP_LOAD_ADDRESS
|
|
* are buffered until the "first word" is written with the real value (not 0xffffffff)
|
|
*
|
|
* On a imxrt the ROM API supports 256 byte writes.
|
|
*/
|
|
|
|
#if defined(CONFIG_ARCH_CHIP_IMXRT)
|
|
#define FC_NUMBER_WORDS 64 // Number of words per page
|
|
#else
|
|
#define FC_NUMBER_WORDS 8 // Number of words per cache line.
|
|
#endif
|
|
#define FC_NUMBER_LINES 2 // Number of cache lines.
|
|
#define FC_LAST_WORD FC_NUMBER_WORDS-1 // The index of the last word in cache line.
|
|
#define FC_ADDRESS_MASK ~(sizeof(flash_cache[0].words)-1) // Cache tag from address
|
|
#define FC_ADDR2INDX(a) (((a) / sizeof(flash_cache[0].words[0])) % FC_NUMBER_WORDS) // index from address
|
|
#define FC_CLEAN ((uint32_t)-1) // Cache clean
|
|
|
|
// Cache line
|
|
typedef struct flash_cache_line_t {
|
|
uint32_t index; // Index of word written
|
|
uintptr_t start_address; // cache tag (address in FLASH this is buffering)
|
|
uint32_t words[FC_NUMBER_WORDS]; // Buffered data
|
|
} flash_cache_line_t;
|
|
|
|
// Resets the cache - all lines flashed and cache_line[0] start_address == APP_LOAD_ADDRESS
|
|
void fc_reset(void);
|
|
// Cache operations
|
|
uint32_t fc_read(uintptr_t address);
|
|
int fc_write(uintptr_t address, uint32_t word);
|