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* ist8310: do reset before WHOAMI call Apparently, the IST8310's WHOAMI register is writeable. Presumably, this can get corrupted by bus noise. It is only reset if powered off for 30s. Therefore, we do a reset before doing the WHOAMI. * ist8310: improve comment Co-authored-by: Beat Küng <beat-kueng@gmx.net> --------- Co-authored-by: Beat Küng <beat-kueng@gmx.net>
308 lines
8.0 KiB
C++
308 lines
8.0 KiB
C++
/****************************************************************************
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*
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* Copyright (c) 2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#include "IST8310.hpp"
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using namespace time_literals;
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static constexpr int16_t combine(uint8_t msb, uint8_t lsb)
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{
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return (msb << 8u) | lsb;
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}
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IST8310::IST8310(const I2CSPIDriverConfig &config) :
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I2C(config),
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I2CSPIDriver(config),
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_px4_mag(get_device_id(), config.rotation)
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{
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}
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IST8310::~IST8310()
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{
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perf_free(_reset_perf);
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perf_free(_bad_register_perf);
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perf_free(_bad_transfer_perf);
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}
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int IST8310::init()
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{
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int ret = I2C::init();
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if (ret != PX4_OK) {
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DEVICE_DEBUG("I2C::init failed (%i)", ret);
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return ret;
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}
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return Reset() ? 0 : -1;
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}
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bool IST8310::Reset()
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{
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_state = STATE::RESET;
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ScheduleClear();
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ScheduleNow();
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return true;
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}
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void IST8310::print_status()
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{
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I2CSPIDriverBase::print_status();
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perf_print_counter(_reset_perf);
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perf_print_counter(_bad_register_perf);
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perf_print_counter(_bad_transfer_perf);
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}
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int IST8310::probe()
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{
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// Apparently, the IST8310's WHOAMI register is writeable. Presumably,
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// this can get corrupted by bus noise. It is only reset if powered off
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// for 30s or by a reset.
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//
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// Therefore, we do a reset before doing the WHOAMI.
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RegisterWrite(Register::CNTL2, CNTL2_BIT::SRST);
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px4_usleep(10000);
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const uint8_t WAI = RegisterRead(Register::WAI);
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if (WAI != Device_ID) {
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DEVICE_DEBUG("unexpected WAI 0x%02x", WAI);
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return PX4_ERROR;
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}
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return PX4_OK;
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}
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void IST8310::RunImpl()
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{
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const hrt_abstime now = hrt_absolute_time();
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switch (_state) {
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case STATE::RESET:
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// CNTL2: Software Reset
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RegisterWrite(Register::CNTL2, CNTL2_BIT::SRST);
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_reset_timestamp = now;
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_failure_count = 0;
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_state = STATE::WAIT_FOR_RESET;
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perf_count(_reset_perf);
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ScheduleDelayed(50_ms); // Power On Reset: max 50ms
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break;
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case STATE::WAIT_FOR_RESET:
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// SRST: This bit is automatically reset to zero after POR routine
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if ((RegisterRead(Register::WAI) == Device_ID)
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&& ((RegisterRead(Register::CNTL2) & CNTL2_BIT::SRST) == 0)) {
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// if reset succeeded then configure
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_state = STATE::CONFIGURE;
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ScheduleDelayed(10_ms);
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} else {
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// RESET not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) {
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PX4_DEBUG("Reset failed, retrying");
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_state = STATE::RESET;
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ScheduleDelayed(100_ms);
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} else {
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PX4_DEBUG("Reset not complete, check again in 10 ms");
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ScheduleDelayed(10_ms);
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}
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}
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break;
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case STATE::CONFIGURE:
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if (Configure()) {
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// if configure succeeded then start measurement cycle
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_state = STATE::MEASURE;
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ScheduleDelayed(20_ms);
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} else {
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// CONFIGURE not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 1000_ms) {
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PX4_DEBUG("Configure failed, resetting");
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_state = STATE::RESET;
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} else {
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PX4_DEBUG("Configure failed, retrying");
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}
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ScheduleDelayed(100_ms);
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}
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break;
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case STATE::MEASURE:
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RegisterWrite(Register::CNTL1, CNTL1_BIT::MODE_SINGLE_MEASUREMENT);
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_state = STATE::READ;
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ScheduleDelayed(20_ms); // Wait at least 6ms. (minimum waiting time for 16 times internal average setup)
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break;
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case STATE::READ: {
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struct TransferBuffer {
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uint8_t STAT1;
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uint8_t DATAXL;
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uint8_t DATAXH;
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uint8_t DATAYL;
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uint8_t DATAYH;
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uint8_t DATAZL;
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uint8_t DATAZH;
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} buffer{};
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bool success = false;
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uint8_t cmd = static_cast<uint8_t>(Register::STAT1);
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if (transfer(&cmd, 1, (uint8_t *)&buffer, sizeof(buffer)) == PX4_OK) {
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if (buffer.STAT1 & STAT1_BIT::DRDY) {
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int16_t x = combine(buffer.DATAXH, buffer.DATAXL);
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int16_t y = combine(buffer.DATAYH, buffer.DATAYL);
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int16_t z = combine(buffer.DATAZH, buffer.DATAZL);
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// sensor's frame is +x forward, +y right, +z up
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z = (z == INT16_MIN) ? INT16_MAX : -z; // flip z
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_px4_mag.set_error_count(perf_event_count(_bad_register_perf) + perf_event_count(_bad_transfer_perf));
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_px4_mag.update(now, x, y, z);
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success = true;
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if (_failure_count > 0) {
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_failure_count--;
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}
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}
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} else {
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perf_count(_bad_transfer_perf);
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}
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if (!success) {
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_failure_count++;
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// full reset if things are failing consistently
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if (_failure_count > 10) {
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Reset();
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return;
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}
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}
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if (!success || hrt_elapsed_time(&_last_config_check_timestamp) > 100_ms) {
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// check configuration registers periodically or immediately following any failure
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if (RegisterCheck(_register_cfg[_checked_register])) {
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_last_config_check_timestamp = now;
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_checked_register = (_checked_register + 1) % size_register_cfg;
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} else {
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// register check failed, force reset
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perf_count(_bad_register_perf);
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Reset();
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return;
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}
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}
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// initiate next measurement
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RegisterWrite(Register::CNTL1, CNTL1_BIT::MODE_SINGLE_MEASUREMENT);
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ScheduleDelayed(20_ms); // Wait at least 6ms. (minimum waiting time for 16 times internal average setup)
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}
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break;
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}
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}
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bool IST8310::Configure()
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{
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// first set and clear all configured register bits
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for (const auto ®_cfg : _register_cfg) {
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RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
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}
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// now check that all are configured
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bool success = true;
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for (const auto ®_cfg : _register_cfg) {
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if (!RegisterCheck(reg_cfg)) {
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success = false;
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}
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}
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_px4_mag.set_scale(1.f / 1320.f); // 1320 LSB/Gauss
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return success;
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}
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bool IST8310::RegisterCheck(const register_config_t ®_cfg)
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{
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bool success = true;
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const uint8_t reg_value = RegisterRead(reg_cfg.reg);
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if (reg_cfg.set_bits && ((reg_value & reg_cfg.set_bits) != reg_cfg.set_bits)) {
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PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not set)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.set_bits);
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success = false;
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}
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if (reg_cfg.clear_bits && ((reg_value & reg_cfg.clear_bits) != 0)) {
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PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not cleared)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.clear_bits);
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success = false;
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}
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return success;
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}
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uint8_t IST8310::RegisterRead(Register reg)
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{
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const uint8_t cmd = static_cast<uint8_t>(reg);
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uint8_t buffer{};
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transfer(&cmd, 1, &buffer, 1);
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return buffer;
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}
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void IST8310::RegisterWrite(Register reg, uint8_t value)
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{
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uint8_t buffer[2] { (uint8_t)reg, value };
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transfer(buffer, sizeof(buffer), nullptr, 0);
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}
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void IST8310::RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t clearbits)
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{
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const uint8_t orig_val = RegisterRead(reg);
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uint8_t val = (orig_val & ~clearbits) | setbits;
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if (orig_val != val) {
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RegisterWrite(reg, val);
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}
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}
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