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https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-07-06 16:40:34 +08:00
Simone Guscetti
279 lines
13 KiB
C
279 lines
13 KiB
C
/****************************************************************************
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*
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* Copyright (c) 2016 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#pragma once
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/*
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* This file is a shim to bridge to nuttx_v3
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*/
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#ifdef __PX4_NUTTX
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__BEGIN_DECLS
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#include <nuttx/spi/spi.h>
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#include <nuttx/i2c/i2c_master.h>
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/* For historical reasons (NuttX STM32 numbering) PX4 bus numbering is 1 based
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* All PX4 code, including, board code is written to assuming 1 based numbering.
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* The following macros are used to allow the board config to define the bus
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* numbers in terms of the NuttX driver numbering. 1,2,3 for one based numbering
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* schemes or 0,1,2 for zero based schemes.
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*/
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#define PX4_BUS_NUMBER_TO_PX4(x) ((x)+PX4_BUS_OFFSET) /* Use to define Zero based to match Nuttx Driver but provide 1 based to PX4 */
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#define PX4_BUS_NUMBER_FROM_PX4(x) ((x)-PX4_BUS_OFFSET) /* Use to map PX4 1 based to NuttX driver 0 based */
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# define px4_enter_critical_section() enter_critical_section()
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# define px4_leave_critical_section(flags) leave_critical_section(flags)
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# if defined(CONFIG_ARCH_CHIP_STM32) || defined(CONFIG_ARCH_CHIP_STM32F7)
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# if defined(CONFIG_ARCH_CHIP_STM32)
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# include <stm32.h>
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# define PX4_FLASH_BASE STM32_FLASH_BASE
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# if defined(CONFIG_STM32_STM32F4XXX)
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# include <stm32_bbsram.h>
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# define PX4_BBSRAM_SIZE STM32_BBSRAM_SIZE
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# define PX4_BBSRAM_GETDESC_IOCTL STM32_BBSRAM_GETDESC_IOCTL
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# endif
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# define PX4_NUMBER_I2C_BUSES STM32_NI2C
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# endif
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# if defined(CONFIG_ARCH_CHIP_STM32F7)
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# include <chip.h>
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# include <up_internal.h> //include up_systemreset() which is included on stm32.h
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# include <stm32_bbsram.h>
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# define PX4_BBSRAM_SIZE STM32F7_BBSRAM_SIZE
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# define PX4_BBSRAM_GETDESC_IOCTL STM32F7_BBSRAM_GETDESC_IOCTL
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# define PX4_FLASH_BASE 0x08000000
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# define PX4_NUMBER_I2C_BUSES STM32F7_NI2C
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# endif
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# include <stm32_tim.h>
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# include <stm32_spi.h>
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# include <stm32_i2c.h>
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/* STM32/32F7 defines the 96 bit UUID as
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* init32_t[3] that can be read as bytes/half-words/words
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* init32_t[0] PX4_CPU_UUID_ADDRESS[0] bits 31:0 (offset 0)
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* init32_t[1] PX4_CPU_UUID_ADDRESS[1] bits 63:32 (offset 4)
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* init32_t[2] PX4_CPU_UUID_ADDRESS[3] bits 96:64 (offset 8)
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*
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* The original PX4 stm32 (legacy) based implementation **displayed** the
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* UUID as: ABCD EFGH IJKL
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* Where:
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* A was bit 31 and D was bit 0
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* E was bit 63 and H was bit 32
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* I was bit 95 and L was bit 64
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*
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* Since the string was used by some manufactures to identify the units
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* it must be preserved.
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*
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* For new targets moving forward we will use
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* IJKL EFGH ABCD
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*/
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# define PX4_CPU_UUID_BYTE_LENGTH 12
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# define PX4_CPU_UUID_WORD32_LENGTH (PX4_CPU_UUID_BYTE_LENGTH/sizeof(uint32_t))
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/* The mfguid will be an array of bytes with
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* MSD @ index 0 - LSD @ index PX4_CPU_MFGUID_BYTE_LENGTH-1
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*
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* It will be converted to a string with the MSD on left and LSD on the right most position.
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*/
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# define PX4_CPU_MFGUID_BYTE_LENGTH PX4_CPU_UUID_BYTE_LENGTH
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/* By not defining PX4_CPU_UUID_CORRECT_CORRELATION the following maintains the legacy incorrect order
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* used for selection of significant digits of the UUID in the PX4 code base.
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* This is done to avoid the ripple effects changing the IDs used on STM32 base platforms
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*/
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# if defined(PX4_CPU_UUID_CORRECT_CORRELATION)
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# define PX4_CPU_UUID_WORD32_UNIQUE_H 0 /* Least significant digits change the most */
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# define PX4_CPU_UUID_WORD32_UNIQUE_M 1 /* Middle significant digits */
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# define PX4_CPU_UUID_WORD32_UNIQUE_L 2 /* Most significant digits change the least */
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# else
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/* Legacy incorrect ordering */
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# define PX4_CPU_UUID_WORD32_UNIQUE_H 2 /* Most significant digits change the least */
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# define PX4_CPU_UUID_WORD32_UNIQUE_M 1 /* Middle significant digits */
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# define PX4_CPU_UUID_WORD32_UNIQUE_L 0 /* Least significant digits change the most */
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# endif
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/* Separator nnn:nnn:nnnn 2 char per byte term */
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# define PX4_CPU_UUID_WORD32_FORMAT_SIZE (PX4_CPU_UUID_WORD32_LENGTH-1+(2*PX4_CPU_UUID_BYTE_LENGTH)+1)
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# define PX4_CPU_MFGUID_FORMAT_SIZE ((2*PX4_CPU_MFGUID_BYTE_LENGTH)+1)
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# define px4_savepanic(fileno, context, length) stm32_bbsram_savepanic(fileno, context, length)
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# define PX4_BUS_OFFSET 0 /* STM buses are 1 based no adjustment needed */
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# define px4_spibus_initialize(bus_num_1based) stm32_spibus_initialize(bus_num_1based)
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# define px4_i2cbus_initialize(bus_num_1based) stm32_i2cbus_initialize(bus_num_1based)
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# define px4_i2cbus_uninitialize(pdev) stm32_i2cbus_uninitialize(pdev)
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# define px4_arch_configgpio(pinset) stm32_configgpio(pinset)
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# define px4_arch_unconfiggpio(pinset) stm32_unconfiggpio(pinset)
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# define px4_arch_gpioread(pinset) stm32_gpioread(pinset)
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# define px4_arch_gpiowrite(pinset, value) stm32_gpiowrite(pinset, value)
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# define px4_arch_gpiosetevent(pinset,r,f,e,fp) stm32_gpiosetevent(pinset,r,f, e,fp)
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#endif // defined(CONFIG_ARCH_CHIP_STM32) || defined(CONFIG_ARCH_CHIP_STM32F7)
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#if defined(CONFIG_ARCH_CHIP_KINETIS)
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# // Fixme: using ??
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# define PX4_BBSRAM_SIZE 2048
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# define PX4_BBSRAM_GETDESC_IOCTL 0
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# define PX4_NUMBER_I2C_BUSES KINETIS_NI2C
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# define GPIO_OUTPUT_SET GPIO_OUTPUT_ONE
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# define GPIO_OUTPUT_CLEAR GPIO_OUTPUT_ZER0
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# include <chip.h>
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# include <kinetis_spi.h>
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# include <kinetis_i2c.h>
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# include <kinetis_uid.h>
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/* Kinetis defines the 128 bit UUID as
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* init32_t[4] that can be read as words
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* init32_t[0] PX4_CPU_UUID_ADDRESS[0] bits 127:96 (offset 0)
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* init32_t[1] PX4_CPU_UUID_ADDRESS[1] bits 95:64 (offset 4)
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* init32_t[2] PX4_CPU_UUID_ADDRESS[1] bits 63:32 (offset 8)
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* init32_t[3] PX4_CPU_UUID_ADDRESS[3] bits 31:0 (offset C)
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*
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* PX4 uses the words in bigendian order MSB to LSB
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* word [0] [1] [2] [3]
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* bits 127:96 95-64 63-32, 31-00,
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*/
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# define PX4_CPU_UUID_BYTE_LENGTH KINETIS_UID_SIZE
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# define PX4_CPU_UUID_WORD32_LENGTH (PX4_CPU_UUID_BYTE_LENGTH/sizeof(uint32_t))
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/* The mfguid will be an array of bytes with
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* MSD @ index 0 - LSD @ index PX4_CPU_MFGUID_BYTE_LENGTH-1
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*
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* It wil be conferted to a string with the MSD on left and LSD on the right most position.
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*/
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# define PX4_CPU_MFGUID_BYTE_LENGTH PX4_CPU_UUID_BYTE_LENGTH
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/* define common formating across all commands */
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# define PX4_CPU_UUID_WORD32_FORMAT "%08x"
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# define PX4_CPU_UUID_WORD32_SEPARATOR ":"
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# define PX4_CPU_UUID_WORD32_UNIQUE_H 3 /* Least significant digits change the most */
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# define PX4_CPU_UUID_WORD32_UNIQUE_M 2 /* Middle High significant digits */
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# define PX4_CPU_UUID_WORD32_UNIQUE_L 1 /* Middle Low significant digits */
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# define PX4_CPU_UUID_WORD32_UNIQUE_N 0 /* Most significant digits change the least */
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/* Separator nnn:nnn:nnnn 2 char per byte term */
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# define PX4_CPU_UUID_WORD32_FORMAT_SIZE (PX4_CPU_UUID_WORD32_LENGTH-1+(2*PX4_CPU_UUID_BYTE_LENGTH)+1)
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# define PX4_CPU_MFGUID_FORMAT_SIZE ((2*PX4_CPU_MFGUID_BYTE_LENGTH)+1)
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# define kinetis_bbsram_savepanic(fileno, context, length) (0) // todo:Not implemented yet
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# define px4_savepanic(fileno, context, length) kinetis_bbsram_savepanic(fileno, context, length)
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/* bus_num is zero based on kinetis and must be translated from the legacy one based */
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# define PX4_BUS_OFFSET 1 /* Kinetis buses are 0 based and adjustment is needed */
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# define px4_spibus_initialize(bus_num_1based) kinetis_spibus_initialize(PX4_BUS_NUMBER_FROM_PX4(bus_num_1based))
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# define px4_i2cbus_initialize(bus_num_1based) kinetis_i2cbus_initialize(PX4_BUS_NUMBER_FROM_PX4(bus_num_1based))
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# define px4_i2cbus_uninitialize(pdev) kinetis_i2cbus_uninitialize(pdev)
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# define px4_arch_configgpio(pinset) kinetis_pinconfig(pinset)
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# define px4_arch_unconfiggpio(pinset)
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# define px4_arch_gpioread(pinset) kinetis_gpioread(pinset)
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# define px4_arch_gpiowrite(pinset, value) kinetis_gpiowrite(pinset, value)
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# define px4_arch_gpiosetevent(pinset,r,f,e,fp) kinetis_gpiosetevent(pinset,r,f, e,fp)
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# endif
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# if defined(CONFIG_ARCH_CHIP_SAMV7)
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# include <sam_spi.h>
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# include <sam_twihs.h>
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# // Fixme: using ??
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# define PX4_BBSRAM_SIZE 2048
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# define PX4_BBSRAM_GETDESC_IOCTL 0
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# define PX4_NUMBER_I2C_BUSES SAMV7_NTWIHS
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//todo:define this for Atmel and add loader.
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/* Atmel defines the 128 bit UUID as
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* init8_t[8] that can be read as bytes using Start Read Unique Identifier
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*
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* PX4 uses the bytes in bigendian order MSB to LSB
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* word [0] [1] [2] [3]
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* bits 127:96 95-64 63-32, 31-00,
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*/
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# define PX4_CPU_UUID_BYTE_LENGTH 16
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# define PX4_CPU_UUID_WORD32_LENGTH (PX4_CPU_UUID_BYTE_LENGTH/sizeof(uint32_t))
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/* The mfguid will be an array of bytes with
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* MSD @ index 0 - LSD @ index PX4_CPU_MFGUID_BYTE_LENGTH-1
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*
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* It will be converted to a string with the MSD on left and LSD on the right most position.
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*/
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# define PX4_CPU_MFGUID_BYTE_LENGTH PX4_CPU_UUID_BYTE_LENGTH
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/* define common formating across all commands */
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# define PX4_CPU_UUID_WORD32_FORMAT "%08x"
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# define PX4_CPU_UUID_WORD32_SEPARATOR ":"
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# define PX4_CPU_UUID_WORD32_UNIQUE_H 3 /* Least significant digits change the most */
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# define PX4_CPU_UUID_WORD32_UNIQUE_M 2 /* Middle High significant digits */
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# define PX4_CPU_UUID_WORD32_UNIQUE_L 1 /* Middle Low significant digits */
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# define PX4_CPU_UUID_WORD32_UNIQUE_N 0 /* Most significant digits change the least */
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/* Separator nnn:nnn:nnnn 2 char per byte term */
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# define PX4_CPU_UUID_WORD32_FORMAT_SIZE (PX4_CPU_UUID_WORD32_LENGTH-1+(2*PX4_CPU_UUID_BYTE_LENGTH)+1)
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# define PX4_CPU_MFGUID_FORMAT_SIZE ((2*PX4_CPU_MFGUID_BYTE_LENGTH)+1)
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# define atmel_bbsram_savepanic(fileno, context, length) (0) // todo:Not implemented yet
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# define px4_savepanic(fileno, context, length) atmel_bbsram_savepanic(fileno, context, length)
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/* bus_num is zero based on same70 and must be translated from the legacy one based */
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# define PX4_BUS_OFFSET 1 /* Same70 buses are 0 based and adjustment is needed */
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# define px4_spibus_initialize(bus_num_1based) sam_spibus_initialize(PX4_BUS_NUMBER_FROM_PX4(bus_num_1based))
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# define px4_i2cbus_initialize(bus_num_1based) sam_i2cbus_initialize(PX4_BUS_NUMBER_FROM_PX4(bus_num_1based))
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# define px4_i2cbus_uninitialize(pdev) sam_i2cbus_uninitialize(pdev)
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# define px4_arch_configgpio(pinset) sam_configgpio(pinset)
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# define px4_arch_unconfiggpio(pinset) sam_unconfiggpio(pinset)
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# define px4_arch_gpioread(pinset) sam_gpioread(pinset)
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# define px4_arch_gpiowrite(pinset, value) sam_gpiowrite(pinset, value)
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# define px4_arch_gpiosetevent(pinset,r,f,e,fp) sam_gpiosetevent(pinset,r,f, e,fp)
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# endif
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#include <arch/board/board.h>
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__END_DECLS
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#endif
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