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533 lines
15 KiB
C
533 lines
15 KiB
C
/****************************************************************************
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*
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* Copyright (C) 2020 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/**
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* @file rcc.c
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*
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* Board-specific clock config functions.
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*/
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include "board_config.h"
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#include "stm32_pwr.h"
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#include "hardware/stm32_axi.h"
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#include "hardware/stm32_syscfg.h"
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* Allow up to 100 milliseconds for the high speed clock to become ready.
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* that is a very long delay, but if the clock does not become ready we are
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* hosed anyway. Normally this is very fast, but I have seen at least one
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* board that required this long, long timeout for the HSE to be ready.
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*/
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#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
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/* Same for HSI */
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#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
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/* HSE divisor to yield ~1MHz RTC clock */
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#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
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/* Voltage output scale (default to Scale 1 mode) */
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#ifndef STM32_PWR_VOS_SCALE
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# define STM32_PWR_VOS_SCALE PWR_D3CR_VOS_SCALE_1
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#endif
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#if !defined(BOARD_FLASH_PROGDELAY)
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# if STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1
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# if STM32_SYSCLK_FREQUENCY <= 70000000 && BOARD_FLASH_WAITSTATES == 0
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# define BOARD_FLASH_PROGDELAY 0
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# elif STM32_SYSCLK_FREQUENCY <= 140000000 && BOARD_FLASH_WAITSTATES == 1
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# define BOARD_FLASH_PROGDELAY 10
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# elif STM32_SYSCLK_FREQUENCY <= 185000000 && BOARD_FLASH_WAITSTATES == 2
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# define BOARD_FLASH_PROGDELAY 1
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# elif STM32_SYSCLK_FREQUENCY <= 210000000 && BOARD_FLASH_WAITSTATES == 2
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# define BOARD_FLASH_PROGDELAY 2
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# elif STM32_SYSCLK_FREQUENCY <= 225000000 && BOARD_FLASH_WAITSTATES == 3
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# define BOARD_FLASH_PROGDELAY 2
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# else
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# define BOARD_FLASH_PROGDELAY 2
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# endif
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# endif
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#endif
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/* PLL are only enabled if the P,Q or R outputs are enabled. */
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#undef USE_PLL1
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#if STM32_PLLCFG_PLL1CFG & (RCC_PLLCFGR_DIVP1EN | RCC_PLLCFGR_DIVQ1EN | \
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RCC_PLLCFGR_DIVR1EN)
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# define USE_PLL1
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#endif
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#undef USE_PLL2
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#if STM32_PLLCFG_PLL2CFG & (RCC_PLLCFGR_DIVP2EN | RCC_PLLCFGR_DIVQ2EN | \
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RCC_PLLCFGR_DIVR2EN)
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# define USE_PLL2
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#endif
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#undef USE_PLL3
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#if STM32_PLLCFG_PLL3CFG & (RCC_PLLCFGR_DIVP3EN | RCC_PLLCFGR_DIVQ3EN | \
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RCC_PLLCFGR_DIVR3EN)
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# define USE_PLL3
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#endif
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/************************************************************************************
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* Private Functions
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG)
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extern uint32_t _start_itcm;
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extern uint32_t _end_itcm;
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extern uint32_t _load_itcm;
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extern uint32_t _start_sram;
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extern uint32_t _end_sram;
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extern uint32_t _load_sram;
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__ramfunc__ void stm32_board_clockconfig(void)
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{
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volatile uint32_t regval = 0;
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volatile int32_t timeout;
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/* This is not the best place for copying code to ITCM and RAM.
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* Since our code work to slow in External Flash, we need to copy it to ITCM and RAM.
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* This currently way to do it inside board specific code.
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*/
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const uint32_t *src;
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uint32_t *dest;
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for (src = &_load_itcm, dest = &_start_itcm; dest < &_end_itcm;) {
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*dest++ = *src++;
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}
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for (src = &_load_sram, dest = &_start_sram; dest < &_end_sram;) {
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*dest++ = *src++;
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}
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#ifdef STM32_BOARD_USEHSI
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/* Enable Internal High-Speed Clock (HSI) */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_HSION; /* Enable HSI */
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSI is ready (or until a timeout elapsed) */
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for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) {
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/* Check if the HSIRDY flag is the set in the CR */
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if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) {
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/* If so, then break-out with timeout > 0 */
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break;
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}
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}
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#else /* if STM32_BOARD_USEHSE */
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/* Enable External High-Speed Clock (HSE) */
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regval = getreg32(STM32_RCC_CR);
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#ifdef STM32_HSEBYP_ENABLE /* May be defined in board.h header file */
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regval |= RCC_CR_HSEBYP; /* Enable HSE clock bypass */
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#else
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regval &= ~RCC_CR_HSEBYP; /* Disable HSE clock bypass */
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#endif
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regval |= RCC_CR_HSEON; /* Enable HSE */
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSE is ready (or until a timeout elapsed) */
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for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--) {
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/* Check if the HSERDY flag is the set in the CR */
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if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0) {
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/* If so, then break-out with timeout > 0 */
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break;
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}
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}
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#endif
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#ifdef CONFIG_STM32H7_HSI48
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/* Enable HSI48 */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_HSI48ON;
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSI48 is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_HSI48RDY) == 0) {
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}
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#endif
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/* Check for a timeout. If this timeout occurs, then we are hosed. We
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* have no real back-up plan, although the following logic makes it look
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* as though we do.
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*/
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if (timeout > 0) {
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/* Set the D1 domain Core prescaler and the HCLK source/divider */
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regval = getreg32(STM32_RCC_D1CFGR);
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regval &= ~(RCC_D1CFGR_HPRE_MASK | RCC_D1CFGR_D1CPRE_MASK);
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regval |= (STM32_RCC_D1CFGR_HPRE | STM32_RCC_D1CFGR_D1CPRE);
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putreg32(regval, STM32_RCC_D1CFGR);
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/* Set PCLK1 */
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regval = getreg32(STM32_RCC_D2CFGR);
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regval &= ~RCC_D2CFGR_D2PPRE2_MASK;
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regval |= STM32_RCC_D2CFGR_D2PPRE1;
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putreg32(regval, STM32_RCC_D2CFGR);
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/* Set PCLK2 */
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regval = getreg32(STM32_RCC_D2CFGR);
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regval &= ~RCC_D2CFGR_D2PPRE2_MASK;
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regval |= STM32_RCC_D2CFGR_D2PPRE2;
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putreg32(regval, STM32_RCC_D2CFGR);
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/* Set PCLK3 */
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regval = getreg32(STM32_RCC_D1CFGR);
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regval &= ~RCC_D1CFGR_D1PPRE_MASK;
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regval |= STM32_RCC_D1CFGR_D1PPRE;
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putreg32(regval, STM32_RCC_D1CFGR);
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/* Set PCLK4 */
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regval = getreg32(STM32_RCC_D3CFGR);
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regval &= ~RCC_D3CFGR_D3PPRE_MASK;
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regval |= STM32_RCC_D3CFGR_D3PPRE;
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putreg32(regval, STM32_RCC_D3CFGR);
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#ifdef CONFIG_STM32H7_RTC_HSECLOCK
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/* Set the RTC clock divisor */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_RTCPRE_MASK;
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regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
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putreg32(regval, STM32_RCC_CFGR);
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#endif
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/* Configure PLL123 clock source and multipiers */
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#ifdef STM32_BOARD_USEHSI
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regval = (RCC_PLLCKSELR_PLLSRC_HSI |
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STM32_PLLCFG_PLL1M |
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STM32_PLLCFG_PLL2M |
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STM32_PLLCFG_PLL3M);
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#else /* if STM32_BOARD_USEHSE */
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regval = (RCC_PLLCKSELR_PLLSRC_HSE |
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STM32_PLLCFG_PLL1M |
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STM32_PLLCFG_PLL2M |
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STM32_PLLCFG_PLL3M);
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#endif
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putreg32(regval, STM32_RCC_PLLCKSELR);
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/* Each PLL offers 3 outputs with post-dividers (PLLxP/PLLxQ/PLLxR) */
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/* Configure PLL1 dividers */
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regval = (STM32_PLLCFG_PLL1N |
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STM32_PLLCFG_PLL1P |
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STM32_PLLCFG_PLL1Q |
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STM32_PLLCFG_PLL1R);
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putreg32(regval, STM32_RCC_PLL1DIVR);
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/* Configure PLL2 dividers */
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regval = (STM32_PLLCFG_PLL2N |
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STM32_PLLCFG_PLL2P |
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STM32_PLLCFG_PLL2Q |
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STM32_PLLCFG_PLL2R);
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putreg32(regval, STM32_RCC_PLL2DIVR);
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/* Configure PLL3 dividers */
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regval = (STM32_PLLCFG_PLL3N |
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STM32_PLLCFG_PLL3P |
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STM32_PLLCFG_PLL3Q |
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STM32_PLLCFG_PLL3R);
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putreg32(regval, STM32_RCC_PLL3DIVR);
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/* Configure PLLs */
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regval = (STM32_PLLCFG_PLL1CFG |
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STM32_PLLCFG_PLL2CFG |
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STM32_PLLCFG_PLL3CFG);
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putreg32(regval, STM32_RCC_PLLCFGR);
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regval = getreg32(STM32_RCC_CR);
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#if defined(USE_PLL1)
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/* Enable the PLL1 */
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regval |= RCC_CR_PLL1ON;
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#endif
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#if defined(USE_PLL2)
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/* Enable the PLL2 */
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regval |= RCC_CR_PLL2ON;
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#endif
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#if defined(USE_PLL3)
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/* Enable the PLL3 */
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regval |= RCC_CR_PLL3ON;
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#endif
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putreg32(regval, STM32_RCC_CR);
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#if defined(USE_PLL1)
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/* Wait until the PLL1 is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL1RDY) == 0) {
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}
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#endif
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#if defined(USE_PLL2)
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/* Wait until the PLL2 is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL2RDY) == 0) {
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}
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#endif
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#if defined(USE_PLL3)
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/* Wait until the PLL3 is ready */
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while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL3RDY) == 0) {
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}
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#endif
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/* Ww must write the lower byte of the PWR_CR3 register is written once
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* after POR and it shall be written before changing VOS level or ck_sys
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* clock frequency. No limitation applies to the upper bytes.
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*
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* Programming data corresponding to an invalid combination of
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* LDOEN and BYPASS bits will be ignored: data will not be written,
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* the written-once mechanism will lock the register and any further
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* write access will be ignored. The default supply configuration will
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* be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1)
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* will go on indicating invalid voltage levels.
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*
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* N.B. The system shall be power cycled before writing a new value.
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*/
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regval = getreg32(STM32_PWR_CR3);
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regval |= STM32_PWR_CR3_LDOEN | STM32_PWR_CR3_SCUEN;
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putreg32(regval, STM32_PWR_CR3);
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/* Set the voltage output scale */
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regval = getreg32(STM32_PWR_D3CR);
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regval &= ~STM32_PWR_D3CR_VOS_MASK;
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regval |= STM32_PWR_VOS_SCALE;
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putreg32(regval, STM32_PWR_D3CR);
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while ((getreg32(STM32_PWR_D3CR) & STM32_PWR_D3CR_VOSRDY) == 0) {
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}
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/* Over-drive is needed if
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* - Voltage output scale 1 mode is selected and SYSCLK frequency is
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* over 400 Mhz.
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*/
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if ((STM32_PWR_VOS_SCALE == PWR_D3CR_VOS_SCALE_1) &&
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STM32_SYSCLK_FREQUENCY > 400000000) {
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/* Enable System configuration controller clock to Enable ODEN */
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regval = getreg32(STM32_RCC_APB4ENR);
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regval |= RCC_APB4ENR_SYSCFGEN;
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putreg32(regval, STM32_RCC_APB4ENR);
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/* Enable Overdrive to extend the clock frequency up to 480 Mhz. */
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regval = getreg32(STM32_SYSCFG_PWRCR);
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regval |= SYSCFG_PWRCR_ODEN;
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putreg32(regval, STM32_SYSCFG_PWRCR);
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while ((getreg32(STM32_PWR_D3CR) & STM32_PWR_D3CR_VOSRDY) == 0) {
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}
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}
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/* Configure FLASH wait states */
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regval = FLASH_ACR_WRHIGHFREQ(BOARD_FLASH_PROGDELAY) |
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FLASH_ACR_LATENCY(BOARD_FLASH_WAITSTATES);
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putreg32(regval, STM32_FLASH_ACR);
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/* Configure new QSPI source clock */
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#if defined(STM32_RCC_D1CCIPR_QSPISEL)
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regval = getreg32(STM32_RCC_D1CCIPR);
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regval &= ~RCC_D1CCIPR_QSPISEL_MASK;
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regval |= STM32_RCC_D1CCIPR_QSPISEL;
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putreg32(regval, STM32_RCC_D1CCIPR);
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#endif
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/* Select the PLL1P as system clock source */
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regval = getreg32(STM32_RCC_CFGR);
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regval &= ~RCC_CFGR_SW_MASK;
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regval |= RCC_CFGR_SW_PLL1;
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putreg32(regval, STM32_RCC_CFGR);
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/* Wait until the PLL source is used as the system clock source */
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while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_PLL1) {
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}
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/* Configure I2C source clock */
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#if (STM32_RCC_D2CCIP2R_I2C123SRC == RCC_D2CCIP2R_I2C123SEL_HSI)
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/* Enable Internal High-Speed Clock (HSI) */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_HSION; /* Enable HSI */
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regval |= RCC_CR_HSIDIV_4; /* Set HSI to 16 MHz */
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSI is ready (or until a timeout elapsed) */
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for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--) {
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/* Check if the HSIRDY flag is the set in the CR */
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if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0) {
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/* If so, then break-out with timeout > 0 */
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break;
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}
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}
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#endif
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#if defined(STM32_RCC_D2CCIP2R_I2C123SRC)
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regval = getreg32(STM32_RCC_D2CCIP2R);
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regval &= ~RCC_D2CCIP2R_I2C123SEL_MASK;
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regval |= STM32_RCC_D2CCIP2R_I2C123SRC;
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putreg32(regval, STM32_RCC_D2CCIP2R);
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#endif
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#if defined(STM32_RCC_D3CCIPR_I2C4SRC)
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regval = getreg32(STM32_RCC_D3CCIPR);
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regval &= ~RCC_D3CCIPR_I2C4SEL_MASK;
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regval |= STM32_RCC_D3CCIPR_I2C4SRC;
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putreg32(regval, STM32_RCC_D3CCIPR);
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#endif
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/* Configure SPI source clock */
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#if defined(STM32_RCC_D2CCIP1R_SPI123SRC)
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regval = getreg32(STM32_RCC_D2CCIP1R);
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regval &= ~RCC_D2CCIP1R_SPI123SEL_MASK;
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regval |= STM32_RCC_D2CCIP1R_SPI123SRC;
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putreg32(regval, STM32_RCC_D2CCIP1R);
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#endif
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#if defined(STM32_RCC_D2CCIP1R_SPI45SRC)
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|
regval = getreg32(STM32_RCC_D2CCIP1R);
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|
regval &= ~RCC_D2CCIP1R_SPI45SEL_MASK;
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|
regval |= STM32_RCC_D2CCIP1R_SPI45SRC;
|
|
putreg32(regval, STM32_RCC_D2CCIP1R);
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|
#endif
|
|
|
|
#if defined(STM32_RCC_D3CCIPR_SPI6SRC)
|
|
regval = getreg32(STM32_RCC_D3CCIPR);
|
|
regval &= ~RCC_D3CCIPR_SPI6SEL_MASK;
|
|
regval |= STM32_RCC_D3CCIPR_SPI6SRC;
|
|
putreg32(regval, STM32_RCC_D3CCIPR);
|
|
#endif
|
|
|
|
/* Configure USB source clock */
|
|
|
|
#if defined(STM32_RCC_D2CCIP2R_USBSRC)
|
|
regval = getreg32(STM32_RCC_D2CCIP2R);
|
|
regval &= ~RCC_D2CCIP2R_USBSEL_MASK;
|
|
regval |= STM32_RCC_D2CCIP2R_USBSRC;
|
|
putreg32(regval, STM32_RCC_D2CCIP2R);
|
|
#endif
|
|
|
|
/* Configure ADC source clock */
|
|
|
|
#if defined(STM32_RCC_D3CCIPR_ADCSRC)
|
|
regval = getreg32(STM32_RCC_D3CCIPR);
|
|
regval &= ~RCC_D3CCIPR_ADCSEL_MASK;
|
|
regval |= STM32_RCC_D3CCIPR_ADCSRC;
|
|
putreg32(regval, STM32_RCC_D3CCIPR);
|
|
#endif
|
|
|
|
#if defined(CONFIG_STM32H7_IWDG) || defined(CONFIG_STM32H7_RTC_LSICLOCK)
|
|
/* Low speed internal clock source LSI */
|
|
|
|
stm32_rcc_enablelsi();
|
|
#endif
|
|
|
|
#if defined(CONFIG_STM32H7_RTC_LSECLOCK)
|
|
/* Low speed external clock source LSE
|
|
*
|
|
* TODO: There is another case where the LSE needs to
|
|
* be enabled: if the MCO1 pin selects LSE as source.
|
|
*/
|
|
|
|
stm32_rcc_enablelse();
|
|
#endif
|
|
}
|
|
|
|
}
|
|
|
|
#endif //#if defined(CONFIG_STM32H7_CUSTOM_CLOCKCONFIG)
|