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Radiolink
2ec0407815
* boards: add Radiolink PIX6 * Fix newlines and format issues * Fix newlines issues * docs:add radiolink_pix6.md document * Subedit, prettier, get images * Add hero image * docs:Add some necessary instructions * Subedit --------- Co-authored-by: Ubuntu <diaohuayuan@radiolink.com.cn> Co-authored-by: Hamish Willee <hamishwillee@gmail.com>
456 lines
17 KiB
C
456 lines
17 KiB
C
/************************************************************************************
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*
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* Copyright (C) 2016-2019 Gregory Nutt. All rights reserved.
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* Authors: David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include "board_dma_map.h"
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include "stm32_rcc.h"
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#include "stm32_sdmmc.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Clocking *************************************************************************/
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/* The radiolink_pix6 board provides the following clock sources:
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*
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* 24 MHz crystal for HSE
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 16 MHz RC factory-trimmed
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* HSE: 24 MHz crystal for HSE
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*/
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#define STM32_BOARD_XTAL 24000000ul
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE = 24,000,000
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*
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* PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 2 <= PLLM <= 63
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* 192 <= PLLN <= 432
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* 192 MHz <= PLL_VCO <= 432MHz
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*
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* SYSCLK = PLL_VCO / PLLP
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* Subject to
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*
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* PLLP = {2, 4, 6, 8}
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* SYSCLK <= 216 MHz
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*
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* USB OTG FS, SDMMC and RNG Clock = PLL_VCO / PLLQ
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* Subject to
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* The USB OTG FS requires a 48 MHz clock to work correctly. The SDMMC
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* and the random number generator need a frequency lower than or equal
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* to 48 MHz to work correctly.
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*
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* 2 <= PLLQ <= 15
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*/
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/* Highest SYSCLK with USB OTG FS clock = 48 MHz
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*
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* PLL_VCO = (24,000,000 / 24) * 432 = 432 MHz
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* SYSCLK = 432 MHz / 2 = 216 MHz
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* USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
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*/
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#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(24)
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#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(432)
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#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
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#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
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#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 24) * 432)
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#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
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#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
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/* Configure factors for PLLSAI clock */
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#define CONFIG_STM32F7_PLLSAI 1
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#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
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#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
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#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
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#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
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/* Configure Dedicated Clock Configuration Register */
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#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
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#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
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#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
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#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
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#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
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#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
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#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
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/* Configure factors for PLLI2S clock */
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#define CONFIG_STM32F7_PLLI2S 1
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#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
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#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
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/* Configure Dedicated Clock Configuration Register 2 */
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#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
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#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
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#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
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#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
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#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
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#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
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#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
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#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
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#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
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#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
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#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
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#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
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#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
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#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
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#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
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/* Several prescalers allow the configuration of the two AHB buses, the
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* high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
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* frequency of the two AHB buses is 216 MHz while the maximum frequency of
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* the high-speed APB domains is 108 MHz. The maximum allowed frequency of
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* the low-speed APB domain is 54 MHz.
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*/
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/* AHB clock (HCLK) is SYSCLK (216 MHz) */
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#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
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#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
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#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
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/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
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#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
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#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* SDMMC dividers. Note that slower clocking is required when DMA is disabled
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* in order to avoid RX overrun/TX underrun errors due to delayed responses
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* to service FIFOs in interrupt driven mode. These values have not been
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* tuned!!!
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*
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* SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(118+2)=400 KHz
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*/
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/* Use the Falling edge of the SDIO_CLK clock to change the edge the
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* data and commands are change on
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*/
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#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
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#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
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* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
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*/
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#ifdef CONFIG_STM32F7_SDMMC_DMA
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# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
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* DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
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*/
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//TODO #warning "Check Freq for 24mHz"
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#ifdef CONFIG_STM32F7_SDMMC_DMA
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# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#else
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# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#endif
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/* FLASH wait states
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*
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* --------- ---------- -----------
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* VDD MAX SYSCLK WAIT STATES
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* --------- ---------- -----------
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* 1.7-2.1 V 180 MHz 8
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* 2.1-2.4 V 216 MHz 9
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* 2.4-2.7 V 216 MHz 8
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* 2.7-3.6 V 216 MHz 7
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* --------- ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 7
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/* LED definitions ******************************************************************/
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/* The radiolink_pix6 board has numerous LEDs but only three, LED_GREEN a Green LED, LED_BLUE
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* a Blue LED and LED_RED a Red LED, that can be controlled by software.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
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* The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_NLEDS 3
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#define BOARD_LED_RED BOARD_LED1
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#define BOARD_LED_GREEN BOARD_LED2
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#define BOARD_LED_BLUE BOARD_LED3
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related
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* events as follows:
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*
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*
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* SYMBOL Meaning LED state
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* Red Green Blue
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* ---------------------- -------------------------- ------ ------ ----*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
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#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
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/* Thus if the Green LED is statically on, NuttX has successfully booted and
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* is, apparently, running normally. If the Red LED is flashing at
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* approximately 2Hz, then a fatal error has been detected and the system
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* has halted.
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*/
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/* Alternate function pin selections ************************************************/
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#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
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#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
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#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
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#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
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#define GPIO_USART2_RTS GPIO_USART2_RTS_2 /* PD4 */
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#define GPIO_USART2_CTS GPIO_USART2_CTS_2 /* PD3 */
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#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
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#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
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#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */
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#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */
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#define GPIO_UART4_RX GPIO_UART4_RX_1 /* PA1 */
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#define GPIO_UART4_TX GPIO_UART4_TX_1 /* PA0 */
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#define GPIO_UART7_RX GPIO_UART7_RX_1 /* PE7 */
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#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE8 */
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/* UART8: has no remap
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*
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* GPIO_UART8_RX PE0
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* GPIO_UART8_TX PE1
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*/
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/* CAN
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*
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* CAN1 is routed to transceiver.
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* CAN2 is routed to transceiver.
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*/
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#define GPIO_CAN1_RX GPIO_CAN1_RX_3 /* PD0 */
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#define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */
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#define GPIO_CAN2_RX GPIO_CAN2_RX_2 /* PB13 */
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#define GPIO_CAN2_TX GPIO_CAN2_TX_1 /* PB5 */
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/* SPI
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* SPI1 is sensors
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* SPI2 is OSD & RAMTRON
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* SPI4 is EXTERNAL1
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*
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*/
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#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
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#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_3 /* PD7 */
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#define GPIO_SPI1_SCK GPIO_SPI1_SCK_2 /* PB3 */
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#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
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#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
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#define GPIO_SPI2_SCK GPIO_SPI2_SCK_1 /* PA9 */
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#define GPIO_SPI4_MISO GPIO_SPI4_MISO_2 /* PE13 */
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#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE6 */
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#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1 /* PE2 */
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/* I2C
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*
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* The optional _GPIO configurations allow the I2C driver to manually
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* reset the bus to clear stuck slaves. They match the pin configuration,
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* but are normally-high GPIOs.
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*
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*/
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#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2 /* PB8 */
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#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2 /* PB9 */
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#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1 /* PB10 */
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#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1 /* PB11 */
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/* SDMMC1
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*
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* VDD 3.3
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* GND
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* SDMMC1_CK PC12
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* SDMMC1_CMD PD2
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* SDMMC1_D0 PC8
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* SDMMC1_D1 PC9
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* SDMMC1_D2 PC10
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* SDMMC1_D3 PC11
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*/
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// #define GPIO_SDMMC1_D0 GPIO_SDMMC1_D0
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// #define GPIO_SDMMC1_D1 GPIO_SDMMC1_D1
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// #define GPIO_SDMMC1_D2 GPIO_SDMMC1_D2
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// #define GPIO_SDMMC1_D3 GPIO_SDMMC1_D3
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/* The STM32 F7 connects to a TI DP83848TSQ/NOPB
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* using RMII
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*
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* STM32 F7 BOARD DP83848TSQ/NOPB
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* GPIO SIGNAL PIN NAME
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* -------- ------------ -------------
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* PA7 ETH_CRS_DV CRS_DV
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* PC1 ETH_MDC MDC
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* PA2 ETH_MDIO MDIO
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* PA1 ETH_REF_CL X1
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* PC4 ETH_RXD0 RX_D0
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* PC5 ETH_RXD1 RX_D1
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* PB11 ETH_TX_EN TX_EN
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* PG13 ETH_TXD0 TX_D0
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* PB13 ETH_TXD1 TX_D1
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*
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* The PHY address is 1, since COL/PHYAD0 features a pull up.
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*/
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// #define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1
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// #define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2
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// #define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1
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/* USB
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*
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* OTG_FS_DM PA11
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* OTG_FS_DP PA12
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* VBUS PA9
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*/
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/* Board provides GPIO or other Hardware for signaling to timing analyzer */
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#if defined(CONFIG_BOARD_USE_PROBES)
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# include "stm32_gpio.h"
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# define PROBE_N(n) (1<<((n)-1))
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# define PROBE_1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN14) /* PE14 AUX1 */
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# define PROBE_2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN10) /* PA10 AUX2 */
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# define PROBE_3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN11) /* PE11 AUX3 */
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# define PROBE_4 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTE|GPIO_PIN9) /* PE9 AUX4 */
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# define PROBE_5 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN15) /* PA15 AUX5 */
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# define PROBE_6 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7) /* PA7 AUX6 */
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# define PROBE_7 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN6) /* PC6 AUX7 */
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# define PROBE_8 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN3) /* PA3 AUX8 */
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# //define PROBE_9 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTI|GPIO_PIN0) /* PI0 CAP1 */
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# define PROBE_INIT(mask) \
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do { \
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if ((mask)& PROBE_N(1)) { stm32_configgpio(PROBE_1); } \
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if ((mask)& PROBE_N(2)) { stm32_configgpio(PROBE_2); } \
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if ((mask)& PROBE_N(3)) { stm32_configgpio(PROBE_3); } \
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if ((mask)& PROBE_N(4)) { stm32_configgpio(PROBE_4); } \
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if ((mask)& PROBE_N(5)) { stm32_configgpio(PROBE_5); } \
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if ((mask)& PROBE_N(6)) { stm32_configgpio(PROBE_6); } \
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if ((mask)& PROBE_N(7)) { stm32_configgpio(PROBE_7); } \
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if ((mask)& PROBE_N(8)) { stm32_configgpio(PROBE_8); } \
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/*if ((mask)& PROBE_N(9)) { stm32_configgpio(PROBE_9); } \*/
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} while (0)
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# define PROBE(n,s) do {stm32_gpiowrite(PROBE_##n,(s));}while(0)
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# define PROBE_MARK(n) PROBE(n,false);PROBE(n,true)
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#else
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# define PROBE_INIT(mask)
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# define PROBE(n,s)
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# define PROBE_MARK(n)
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#endif
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