mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-10-26 02:43:33 +08:00
Julian Oes
3c39095271
* hrt: Fix PPM input on channel 2 The CCMR1_PPM define for PPM input on channel 2 was incorrectly set to 2, which was setting bits for channel 1 instead of channel 2. This prevented PPM input from functioning properly on channel 2. Changed CCMR1_PPM for channel 2 from 2 to (1 << 8), which correctly configures the CC2S bits for input capture mode on TI2. This fixes an issue noted in the existing code comment: "FIXME! There is an interaction in the CCMR registers that prevents using Chan 1 as the timer and chan 2 as the PPM" Tested on STM32H743 with PPM input on PC7 (TIM8_CH2). * rc_input: enable sharing serial and PPM pin By setting RC_SERIAL_PORT_SHARED_PPM_PIN_GPIO_RX it is now possible to use the same pin on the STM32 for PPM input as well as serial input. * boards: Add support for Holybro KakuteH7-Wing
82 lines
3.7 KiB
C
82 lines
3.7 KiB
C
/****************************************************************************
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*
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* Copyright (c) 2025 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#pragma once
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// DMAMUX1 Using at most 8 Channels on DMA1 -------- Assigned
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// V
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#define DMAMAP_SPI1_RX DMAMAP_DMA12_SPI1RX_0 /* 1 DMA1:37 */
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#define DMAMAP_SPI1_TX DMAMAP_DMA12_SPI1TX_0 /* 2 DMA1:38 */
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#define DMAMAP_SPI3_RX DMAMAP_DMA12_SPI3RX_0 /* 3 DMA1:39 FRAM */
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#define DMAMAP_SPI3_TX DMAMAP_DMA12_SPI3TX_0 /* 4 DMA1:40 FRAM */
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// TODO
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//#define DMAMAP_USART1_RX DMAMAP_DMA12_USART1RX_0 /* DMA1:41 GPS1 */
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//#define DMAMAP_USART1_TX DMAMAP_DMA12_USART1TX_0 /* DMA1:42 GPS1 */
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//#define DMAMAP_USART2_RX DMAMAP_DMA12_USART2RX_0 /* DMA1:43 Telem3 */
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//#define DMAMAP_USART2_TX DMAMAP_DMA12_USART2TX_0 /* DMA1:44 Telem3 */
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//#define DMAMAP_USART3_RX DMAMAP_DMA12_USART3RX_0 /* DMA1:45 DEBUG */
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//#define DMAMAP_USART3_TX DMAMAP_DMA12_USART3TX_0 /* DMA1:46 DEBUG */
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//#define DMAMAP_UART4_RX DMAMAP_DMA12_UART4RX_0 /* DMA1:63 EXT2 */
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//#define DMAMAP_UART4_TX DMAMAP_DMA12_UART4TX_0 /* DMA1:64 EXT2 */
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//#define DMAMAP_USART6_RX DMAMAP_DMA12_USART6RX_0 /* 5 DMA1:71 PX4IO */
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//#define DMAMAP_USART6_TX DMAMAP_DMA12_USART6TX_0 /* 6 DMA1:72 PX4IO */
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// Assigned in timer_config.cpp
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// TODO
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// Timer 4 /* 7 DMA1:32 TIM4UP */
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// Timer 5 /* 8 DMA1:50 TIM5UP */
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// DMAMUX2 Using at most 8 Channels on DMA2 -------- Assigned
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// V
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// TODO
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#define DMAMAP_USART3_RX DMAMAP_DMA12_USART3RX_1 /* 1 DMA2:45 */
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#define DMAMAP_USART3_TX DMAMAP_DMA12_USART3TX_1 /* 2 DMA2:46 */
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#define DMAMAP_UART5_RX DMAMAP_DMA12_UART5RX_1 /* 3 DMA2:65 */
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#define DMAMAP_UART5_TX DMAMAP_DMA12_UART5TX_1 /* 4 DMA2:66 */
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//#define DMAMAP_USART6_RX DMAMAP_DMA12_USART6RX_1 /* 5 DMA2:71 */
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//#define DMAMAP_USART6_TX DMAMAP_DMA12_USART6TX_1 /* 6 DMA2:72 */
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#define DMAMAP_UART7_RX DMAMAP_DMA12_UART7RX_1 /* 7 DMA1:79 */
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#define DMAMAP_UART7_TX DMAMAP_DMA12_UART7TX_1 /* 8 DMA1:80 */
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