mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-07-04 09:50:35 +08:00
henrykotze
8b58c01cd7
nsh console running on USB param module running working with i2c and common drivers provided implementation for drv_pwm_output.h i2cdetect working as expected with no device mavlink started succesfully mounts sd card and logger runs logger to file succesfully pwm_servo implemented without using Nuttx lib pwm_out outputs expected waveforms - however currently if the frequency is higher than what the pwm_out driver runs, there will be aliasing, based on how the registers gets resets wifi softap working - Seeing wifi hotspot - cant connect due to wrong password - problems with adjusting ssid and password wifi ssid and password being set accordinglu connected to wifi hotspot with dhpcd - made some changes to nuttx to only build for SoftAP mode, however this was effectivelyy removing the ifdef for STATION mode. Should investigate the coexist option again added ifdef to not use timer 0 when wifi enabled - reverted esp32 rt_timer to make use of timer 0 by default fix setting incorrect bit in hrt timer register - hrt running as expected, but on startup the pwm_out driver starts up at about 200Hz and then rises over a minute or so 250Hz. Not sure if this was present previously, and could be due to Wifi running at time priority on timer 0 pull xtensa compilers in setup.ubuntu.sh revert logger stacksize and cmake argument esp32 chip revision and PX4 UUID implemented spi board reset implemented, formatting checked devkit acts on startup as a wifi bridge for comms - the most usefull setting for the general developer when buying a esp32 devkit - testing Mavlink shell using ./Tools/mavlink_shell.py - todo: Test mavlink messages being forward improve wifi telemetry by increasing prio - Remove power save mode on wifi - increased daemon thread schedule priority to 50 compiles without Nuttx changes - updated compiler settings to match those of nuttx on px4 side add espressif_esp32 to excluded boards ci: allow docker to find xtensa compilers
79 lines
3.6 KiB
Plaintext
79 lines
3.6 KiB
Plaintext
/****************************************************************************
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* boards/xtensa/esp32/common/scripts/esp32.ld
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Default entry point: */
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MEMORY
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{
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/* Below values assume the flash cache is on, and have the blocks this
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* uses subtracted from the length of the various regions. The 'data access
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* port' dram/drom regions map to the same iram/irom regions but are
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* connected to the data port of the CPU and e.g. allow bytewise access.
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*/
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Flash mapped instruction data. */
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/* The 0x20 offset is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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irom0_0_seg (RX) : org = 0x400d0020, len = 0x330000 - 0x20
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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* Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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* the amount of RAM available.
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*
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* Note: The length of this section should be 0x50000, and this extra
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* DRAM is available in heap at runtime. However due to static ROM memory
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* usage at this 176KB mark, the additional static memory temporarily cannot
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* be used.
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*/
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dram0_0_seg (RW) : org = 0x3ffb0000 + 0,
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len = 0x2c200 - 0 - 0
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/* Flash mapped constant data */
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/* The 0x20 offset is a convenience for the app binary image generation.
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* Flash cache has 64KB pages. The .bin file which is flashed to the chip
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* has a 0x18 byte file header, and each segment has a 0x08 byte segment
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* header. Setting this offset makes it simple to meet the flash cache MMU's
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* constraint that (paddr % 64KB == vaddr % 64KB).
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*/
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drom0_0_seg (R) : org = 0x3f400020, len = 0x400000 - 0x20
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/* RTC fast memory (executable). Persists over deep sleep. */
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rtc_iram_seg (RWX) : org = 0x400c0000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep.
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* Start of RTC slow memory is reserved for ULP co-processor code + data,
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* if enabled.
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*/
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rtc_slow_seg (RW) : org = 0x50000000 + 0,
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len = 0x1000 - 0
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/* External memory, including data and text */
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extmem_seg (RWX) : org = 0x3f800000, len = 0x400000
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}
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REGION_ALIAS("default_rodata_seg", drom0_0_seg);
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REGION_ALIAS("default_code_seg", irom0_0_seg);
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/* Heap ends at top of dram0_0_seg */
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_eheap = 0x40000000 - 0;
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/* IRAM heap ends at top of dram0_0_seg */
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_eiramheap = 0x400a0000;
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/* Mark the end of the RTC heap (top of the RTC region) */
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_ertcheap = 0x50001fff;
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