Showcase clang-format google style

.clang-format

@@ -0,0 +1,13 @@
+# Google C++ style as base
+Language: Cpp
+BasedOnStyle: Google
+
+# Indentation using tabs
+UseTab: ForContinuationAndIndentation
+TabWidth: 8
+IndentWidth: 8
+ContinuationIndentWidth: 8
+ConstructorInitializerIndentWidth: 8
+AccessModifierOffset: -8
+
+ColumnLimit: 120 # Allow more collumns

.clang-tidy

@@ -1,17 +1,11 @@
 ---
 Checks:          '*,
-                  -*-avoid-c-arrays,
-                  -*-uppercase-literal-suffix,
-                  -*-magic-numbers,
-                  -altera-id-dependent-backward-branch,
-                  -altera-unroll-loops,
                   -android*,
                   -bugprone-integer-division,
                   -cert-dcl50-cpp,
                   -cert-env33-c,
                   -cert-err34-c,
                   -cert-err58-cpp,
-                  -cert-flp30-c,
                   -cert-msc30-c,
                   -cert-msc50-cpp,
                   -clang-analyzer-core.CallAndMessage,
@@ -24,7 +18,6 @@ Checks:          '*,
                   -clang-analyzer-deadcode.DeadStores,
                   -clang-analyzer-optin.cplusplus.VirtualCall,
                   -clang-analyzer-optin.performance.Padding,
-                  -clang-analyzer-security.FloatLoopCounter,
                   -clang-analyzer-security.insecureAPI.strcpy,
                   -clang-analyzer-unix.API,
                   -clang-analyzer-unix.cstring.BadSizeArg,
@@ -44,7 +37,8 @@ Checks:          '*,
                   -cppcoreguidelines-pro-type-union-access,
                   -cppcoreguidelines-pro-type-vararg,
                   -cppcoreguidelines-special-member-functions,
-                  -fuchsia-*,
+                  -fuchsia-default-arguments,
+                  -fuchsia-overloaded-operator,
                   -google-build-using-namespace,
                   -google-explicit-constructor,
                   -google-global-names-in-headers,
@@ -68,7 +62,6 @@ Checks:          '*,
                   -hicpp-use-equals-delete,
                   -hicpp-use-override,
                   -hicpp-vararg,
-                  -llvmlibc-*,
                   -llvm-header-guard,
                   -llvm-include-order,
                   -llvm-namespace-comment,
@@ -91,7 +84,6 @@ Checks:          '*,
                   -modernize-use-override,
                   -modernize-use-trailing-return-type,
                   -modernize-use-using,
-                  -modernize-use-trailing-return-type,
                   -performance-inefficient-string-concatenation,
                   -readability-avoid-const-params-in-decls,
                   -readability-container-size-empty,

CMakeLists.txt

@@ -175,12 +175,6 @@ include(kconfig)
 message(STATUS "PX4 config: ${PX4_CONFIG}")
 message(STATUS "PX4 platform: ${PX4_PLATFORM}")
 
-if($ENV{CLION_IDE})
-	# CLion automatically executes some compiler commands after configuring the
-	# project. This would fail on NuttX, as visibility.h tries to (indirectly)
-	# include nuttx/config.h, which at that point does not exist yet
-	add_definitions(-DPX4_DISABLE_GCC_POISON)
-endif()
 
 if(${PX4_PLATFORM} STREQUAL "posix")
 	if(ENABLE_LOCKSTEP_SCHEDULER)

Makefile

@@ -375,6 +375,10 @@ format:
 	$(call colorecho,'Formatting with astyle')
 	@"$(SRC_DIR)"/Tools/astyle/check_code_style_all.sh --fix
 
+format_clang:
+	$(call colorecho,'Formatting with clang-format')
+	@"$(SRC_DIR)"/Tools/astyle/files_to_check_code_style.sh | xargs clang-format -i -style=file
+
 # Testing
 # --------------------------------------------------------------------
 .PHONY: tests tests_coverage tests_mission tests_mission_coverage tests_offboard tests_avoidance

README.md

@@ -6,38 +6,38 @@
 
 [![Slack](/.github/slack.svg)](https://join.slack.com/t/px4/shared_invite/zt-si4xo5qs-R4baYFmMjlrT4rQK5yUnaA)
 
-This repository holds the [PX4](http://px4.io) flight control solution for drones, with the main applications located in the [src/modules](https://github.com/PX4/PX4-Autopilot/tree/main/src/modules) directory. It also contains the PX4 Drone Middleware Platform, which provides drivers and middleware to run drones.
+This repository holds the [PX4](http://px4.io) flight control solution for drones, with the main applications located in the [src/modules](https://github.com/PX4/PX4-Autopilot/tree/master/src/modules) directory. It also contains the PX4 Drone Middleware Platform, which provides drivers and middleware to run drones.
 
 PX4 is highly portable, OS-independent and supports Linux, NuttX and MacOS out of the box.
 
 * Official Website: http://px4.io (License: BSD 3-clause, [LICENSE](https://github.com/PX4/PX4-Autopilot/blob/master/LICENSE))
-* [Supported airframes](https://docs.px4.io/main/en/airframes/airframe_reference.html) ([portfolio](http://px4.io/#airframes)):
-  * [Multicopters](https://docs.px4.io/main/en/frames_multicopter/)
-  * [Fixed wing](https://docs.px4.io/main/en/frames_plane/)
-  * [VTOL](https://docs.px4.io/main/en/frames_vtol/)
-  * [Autogyro](https://docs.px4.io/main/en/frames_autogyro/)
-  * [Rover](https://docs.px4.io/main/en/frames_rover/)
+* [Supported airframes](https://docs.px4.io/master/en/airframes/airframe_reference.html) ([portfolio](http://px4.io/#airframes)):
+  * [Multicopters](https://docs.px4.io/master/en/frames_multicopter/)
+  * [Fixed wing](https://docs.px4.io/master/en/frames_plane/)
+  * [VTOL](https://docs.px4.io/master/en/frames_vtol/)
+  * [Autogyro](https://docs.px4.io/master/en/frames_autogyro/)
+  * [Rover](https://docs.px4.io/master/en/frames_rover/)
   * many more experimental types (Blimps, Boats, Submarines, High altitude balloons, etc)
 * Releases: [Downloads](https://github.com/PX4/PX4-Autopilot/releases)
 
 
 ## Building a PX4 based drone, rover, boat or robot
 
-The [PX4 User Guide](https://docs.px4.io/main/en/) explains how to assemble [supported vehicles](https://docs.px4.io/main/en/airframes/airframe_reference.html) and fly drones with PX4.
-See the [forum and chat](https://docs.px4.io/main/en/#getting-help) if you need help!
+The [PX4 User Guide](https://docs.px4.io/master/en/) explains how to assemble [supported vehicles](https://docs.px4.io/master/en/airframes/airframe_reference.html) and fly drones with PX4.
+See the [forum and chat](https://docs.px4.io/master/en/#support) if you need help!
 
 
 ## Changing code and contributing
 
-This [Developer Guide](https://docs.px4.io/main/en/development/development.html) is for software developers who want to modify the flight stack and middleware (e.g. to add new flight modes), hardware integrators who want to support new flight controller boards and peripherals, and anyone who wants to get PX4 working on a new (unsupported) airframe/vehicle.
+This [Developer Guide](https://docs.px4.io/master/en/development/development.html) is for software developers who want to modify the flight stack and middleware (e.g. to add new flight modes), hardware integrators who want to support new flight controller boards and peripherals, and anyone who wants to get PX4 working on a new (unsupported) airframe/vehicle.
 
-Developers should read the [Guide for Contributions](https://docs.px4.io/main/en/contribute/).
-See the [forum and chat](https://docs.px4.io/main/en/#getting-help) if you need help!
+Developers should read the [Guide for Contributions](https://docs.px4.io/master/en/contribute/).
+See the [forum and chat](https://dev.px4.io/master/en/#support) if you need help!
 
 
 ### Weekly Dev Call
 
-The PX4 Dev Team syncs up on a [weekly dev call](https://docs.px4.io/main/en/contribute/).
+The PX4 Dev Team syncs up on a [weekly dev call](https://dev.px4.io/master/en/contribute/#dev_call).
 
 > **Note** The dev call is open to all interested developers (not just the core dev team). This is a great opportunity to meet the team and contribute to the ongoing development of the platform. It includes a QA session for newcomers. All regular calls are listed in the [Dronecode calendar](https://www.dronecode.org/calendar/).
 
@@ -88,43 +88,35 @@ This repository contains code supporting Pixhawk standard boards (best supported
   * FMUv6X and FMUv6U (STM32H7, 2021)
     * Various vendors will provide FMUv6X and FMUv6U based designs Q3/2021
   * FMUv5 and FMUv5X (STM32F7, 2019/20)
-    * [Pixhawk 4 (FMUv5)](https://docs.px4.io/main/en/flight_controller/pixhawk4.html)
-    * [Pixhawk 4 mini (FMUv5)](https://docs.px4.io/main/en/flight_controller/pixhawk4_mini.html)
-    * [CUAV V5+ (FMUv5)](https://docs.px4.io/main/en/flight_controller/cuav_v5_plus.html)
-    * [CUAV V5 nano (FMUv5)](https://docs.px4.io/main/en/flight_controller/cuav_v5_nano.html)
-    * [Auterion Skynode (FMUv5X)](https://docs.auterion.com/skynode)
+    * [Pixhawk 4 (FMUv5)](https://docs.px4.io/master/en/flight_controller/pixhawk4.html)
+    * [Pixhawk 4 mini (FMUv5)](https://docs.px4.io/master/en/flight_controller/pixhawk4_mini.html)
+    * [CUAV V5+ (FMUv5)](https://docs.px4.io/master/en/flight_controller/cuav_v5_plus.html)
+    * [CUAV V5 nano (FMUv5)](https://docs.px4.io/master/en/flight_controller/cuav_v5_nano.html)
+    * [Auterion Skynode (FMUv5X)](https://docs.px4.io/master/en/flight_controller/auterion_skynode.html)
   * FMUv4 (STM32F4, 2015)
-    * [Pixracer](https://docs.px4.io/main/en/flight_controller/pixracer.html)
-    * [Pixhawk 3 Pro](https://docs.px4.io/main/en/flight_controller/pixhawk3_pro.html)
+    * [Pixracer](https://docs.px4.io/master/en/flight_controller/pixracer.html)
+    * [Pixhawk 3 Pro](https://docs.px4.io/master/en/flight_controller/pixhawk3_pro.html)
   * FMUv3 (STM32F4, 2014)
-    * [Pixhawk 2](https://docs.px4.io/main/en/flight_controller/pixhawk-2.html)
-    * [Pixhawk Mini](https://docs.px4.io/main/en/flight_controller/pixhawk_mini.html)
-    * [CUAV Pixhack v3](https://docs.px4.io/main/en/flight_controller/pixhack_v3.html)
+    * [Pixhawk 2](https://docs.px4.io/master/en/flight_controller/pixhawk-2.html)
+    * [Pixhawk Mini](https://docs.px4.io/master/en/flight_controller/pixhawk_mini.html)
+    * [CUAV Pixhack v3](https://docs.px4.io/master/en/flight_controller/pixhack_v3.html)
   * FMUv2 (STM32F4, 2013)
-    * [Pixhawk](https://docs.px4.io/main/en/flight_controller/pixhawk.html)
-    * [Pixfalcon](https://docs.px4.io/main/en/flight_controller/pixfalcon.html)
+    * [Pixhawk](https://docs.px4.io/master/en/flight_controller/pixhawk.html)
+    * [Pixfalcon](https://docs.px4.io/master/en/flight_controller/pixfalcon.html)
 
 ### Manufacturer and Community supported
-  * [Holybro Durandal](https://docs.px4.io/main/en/flight_controller/durandal.html)
-  * [Hex Cube Orange](https://docs.px4.io/main/en/flight_controller/cubepilot_cube_orange.html)
-  * [Hex Cube Yellow](https://docs.px4.io/main/en/flight_controller/cubepilot_cube_yellow.html)
+  * [Holybro Durandal](https://docs.px4.io/master/en/flight_controller/durandal.html)
+  * [Hex Cube Orange](https://docs.px4.io/master/en/flight_controller/cubepilot_cube_orange.html)
+  * [Hex Cube Yellow](https://docs.px4.io/master/en/flight_controller/cubepilot_cube_yellow.html)
   * [Airmind MindPX V2.8](http://www.mindpx.net/assets/accessories/UserGuide_MindPX.pdf)
   * [Airmind MindRacer V1.2](http://mindpx.net/assets/accessories/mindracer_user_guide_v1.2.pdf)
-  * [Bitcraze Crazyflie 2.0](https://docs.px4.io/main/en/complete_vehicles/crazyflie2.html)
-  * [Omnibus F4 SD](https://docs.px4.io/main/en/flight_controller/omnibus_f4_sd.html)
-  * [Holybro Kakute F7](https://docs.px4.io/main/en/flight_controller/kakutef7.html)
-  * [Raspberry PI with Navio 2](https://docs.px4.io/main/en/flight_controller/raspberry_pi_navio2.html)
+  * [Bitcraze Crazyflie 2.0](https://docs.px4.io/master/en/complete_vehicles/crazyflie2.html)
+  * [Omnibus F4 SD](https://docs.px4.io/master/en/flight_controller/omnibus_f4_sd.html)
+  * [Holybro Kakute F7](https://docs.px4.io/master/en/flight_controller/kakutef7.html)
+  * [Raspberry PI with Navio 2](https://docs.px4.io/master/en/flight_controller/raspberry_pi_navio2.html)
 
-Additional information about supported hardware can be found in [PX4 user Guide > Autopilot Hardware](https://docs.px4.io/main/en/flight_controller/).
+Additional information about supported hardware can be found in [PX4 user Guide > Autopilot Hardware](https://docs.px4.io/master/en/flight_controller/).
 
 ## Project Roadmap
 
 A high level project roadmap is available [here](https://github.com/orgs/PX4/projects/25).
-
-## Project Governance
-
-The PX4 Autopilot project including all of its trademarks is hosted under [Dronecode](https://www.dronecode.org/), part of the Linux Foundation.
-
-<a href="https://www.dronecode.org/" style="padding:20px" ><img src="https://mavlink.io/assets/site/logo_dronecode.png" alt="Dronecode Logo" width="110px"/></a>
-<a href="https://www.linuxfoundation.org/projects" style="padding:20px;"><img src="https://mavlink.io/assets/site/logo_linux_foundation.png" alt="Linux Foundation Logo" width="80px" /></a>
-<div style="padding:10px">&nbsp;</div>

ROMFS/CMakeLists.txt

@@ -112,17 +112,23 @@ add_custom_command(
 		${PX4_SOURCE_DIR}/Tools/px4airframes/xmlout.py
 		${PX4_SOURCE_DIR}/Tools/serial/generate_config.py
 	)
+set(romfs_extract_stamp ${CMAKE_CURRENT_BINARY_DIR}/romfs_extract.stamp)
+add_custom_command(
+	OUTPUT ${romfs_extract_stamp}
+	COMMAND ${CMAKE_COMMAND} -E remove_directory ${romfs_gen_root_dir}/*
+	COMMAND ${CMAKE_COMMAND} -E tar xf ${romfs_tar_file}
+	COMMAND ${CMAKE_COMMAND} -E touch ${romfs_extract_stamp}
+	WORKING_DIRECTORY ${romfs_gen_root_dir}
+	DEPENDS ${romfs_tar_file}
+	VERBATIM
+	)
 
-
-set(romfs_copy_stamp ${CMAKE_CURRENT_BINARY_DIR}/romfs_copy.stamp)
 add_custom_command(
 	OUTPUT
 		${romfs_gen_root_dir}/init.d/rc.serial
 		${romfs_gen_root_dir}/init.d/rc.autostart
 		${romfs_gen_root_dir}/init.d/rc.autostart.post
-		${romfs_copy_stamp}
-	COMMAND ${CMAKE_COMMAND} -E remove_directory ${romfs_gen_root_dir}/*
-	COMMAND ${CMAKE_COMMAND} -E tar xf ${romfs_tar_file}
+		romfs_copy.stamp
 	COMMAND ${PYTHON_EXECUTABLE} ${PX4_SOURCE_DIR}/Tools/px_process_airframes.py
 		--airframes-path ${romfs_gen_root_dir}/init.d
 		--start-script ${romfs_gen_root_dir}/init.d/rc.autostart
@@ -131,9 +137,9 @@ add_custom_command(
 		--rc-dir ${romfs_gen_root_dir}/init.d
 		--serial-ports ${board_serial_ports} ${added_arguments}
 		--config-files ${module_config_files} #--verbose
-	COMMAND ${CMAKE_COMMAND} -E touch ${romfs_copy_stamp}
-	WORKING_DIRECTORY ${romfs_gen_root_dir}
-	DEPENDS ${romfs_tar_file}
+	COMMAND ${CMAKE_COMMAND} -E touch romfs_copy.stamp
+	DEPENDS
+		${romfs_extract_stamp}
 	COMMENT "ROMFS: copying, generating airframes"
 	)
 
@@ -305,7 +311,7 @@ add_custom_command(OUTPUT romfs_extras.stamp
 
 add_custom_target(romfs_gen_files_target
 	DEPENDS
-		${romfs_copy_stamp}
+		${romfs_extract_stamp}
 		${romfs_gen_root_dir}/init.d/rc.serial
 		romfs_extras.stamp
 	)

ROMFS/px4fmu_common/init.d-posix/airframes/1030_plane

@@ -10,6 +10,7 @@ param set-default EKF2_MAG_YAWLIM 0
 
 param set-default FW_LND_AIRSPD_SC 1
 param set-default FW_LND_ANG 8
+param set-default FW_THR_LND_MAX 0
 
 param set-default FW_L1_PERIOD 12
 
@@ -28,7 +29,7 @@ param set-default FW_SPOILERS_LND 0.4
 
 param set-default FW_THR_MAX 0.6
 param set-default FW_THR_MIN 0.05
-param set-default FW_THR_TRIM 0.25
+param set-default FW_THR_CRUISE 0.25
 
 param set-default FW_T_CLMB_MAX 8
 param set-default FW_T_SINK_MAX 2.7

ROMFS/px4fmu_common/init.d-posix/airframes/1033_rascal

@@ -7,9 +7,12 @@
 
 param set-default FW_LND_AIRSPD_SC 1.1
 param set-default FW_LND_ANG 5
+param set-default FW_THR_LND_MAX 0
+param set-default FW_LND_HHDIST 30
 param set-default FW_LND_FL_PMIN 9.5
 param set-default FW_LND_FL_PMAX 20
 param set-default FW_LND_FLALT 5
+param set-default FW_LND_TLALT 15
 
 param set-default FW_L1_PERIOD 25
 
@@ -35,6 +38,7 @@ param set-default NAV_DLL_ACT 2
 param set-default RWTO_TKOFF 1
 
 param set-default RWTO_MAX_PITCH 20
+param set-default RWTO_MAX_ROLL 10
 
 param set-default RWTO_PSP 8
 param set-default RWTO_AIRSPD_SCL 1.8

ROMFS/px4fmu_common/init.d-posix/airframes/1034_rascal-electric

@@ -7,9 +7,12 @@
 
 param set-default FW_LND_AIRSPD_SC 1.1
 param set-default FW_LND_ANG 5
+param set-default FW_THR_LND_MAX 0
+param set-default FW_LND_HHDIST 30
 param set-default FW_LND_FL_PMIN 9.5
 param set-default FW_LND_FL_PMAX 20
 param set-default FW_LND_FLALT 5
+param set-default FW_LND_TLALT 15
 
 param set-default FW_L1_PERIOD 25
 
@@ -35,6 +38,7 @@ param set-default NAV_DLL_ACT 2
 param set-default RWTO_TKOFF 1
 
 param set-default RWTO_MAX_PITCH 20
+param set-default RWTO_MAX_ROLL 10
 
 param set-default RWTO_PSP 8
 param set-default RWTO_AIRSPD_SCL 1.8

ROMFS/px4fmu_common/init.d-posix/airframes/1035_techpod

@@ -10,6 +10,7 @@ param set-default EKF2_MAG_YAWLIM 0
 
 param set-default FW_LND_AIRSPD_SC 1
 param set-default FW_LND_ANG 8
+param set-default FW_THR_LND_MAX 0
 
 param set-default FW_L1_PERIOD 15
 

ROMFS/px4fmu_common/init.d-posix/airframes/1036_malolo

@@ -7,9 +7,12 @@
 
 param set-default FW_LND_AIRSPD_SC 1.1
 param set-default FW_LND_ANG 5
+param set-default FW_THR_LND_MAX 0
+param set-default FW_LND_HHDIST 30
 param set-default FW_LND_FL_PMIN 9.5
 param set-default FW_LND_FL_PMAX 20
 param set-default FW_LND_FLALT 5
+param set-default FW_LND_TLALT 15
 
 param set-default FW_L1_PERIOD 25
 
@@ -34,6 +37,7 @@ param set-default NAV_DLL_ACT 2
 
 param set-default RWTO_TKOFF 1
 param set-default RWTO_MAX_PITCH 20
+param set-default RWTO_MAX_ROLL 10
 param set-default RWTO_PSP 8
 param set-default RWTO_AIRSPD_SCL 1.8
 

ROMFS/px4fmu_common/init.d-posix/airframes/1037_believer

@@ -10,6 +10,7 @@ param set-default EKF2_MAG_YAWLIM 0
 
 param set-default FW_LND_AIRSPD_SC 1
 param set-default FW_LND_ANG 8
+param set-default FW_THR_LND_MAX 0
 
 param set-default FW_L1_PERIOD 12
 
@@ -26,7 +27,7 @@ param set-default FW_RR_P 0.3
 
 param set-default FW_THR_MAX 0.6
 param set-default FW_THR_MIN 0.05
-param set-default FW_THR_TRIM 0.25
+param set-default FW_THR_CRUISE 0.25
 
 param set-default FW_T_ALT_TC 2
 param set-default FW_T_CLMB_MAX 8

ROMFS/px4fmu_common/init.d-posix/airframes/1038_glider

@@ -5,5 +5,5 @@
 
 . ${R}etc/init.d-posix/airframes/1030_plane
 
-param set-default FW_THR_TRIM 0.0
+param set-default FW_THR_CRUISE 0.0
 param set-default RWTO_TKOFF 0

ROMFS/px4fmu_common/init.d-posix/airframes/1040_standard_vtol

@@ -57,7 +57,7 @@ param set-default FW_P_LIM_MAX 32
 param set-default FW_P_LIM_MIN -15
 param set-default FW_RR_FF 0.1
 param set-default FW_RR_P 0.3
-param set-default FW_THR_TRIM 0.25
+param set-default FW_THR_CRUISE 0.25
 param set-default FW_THR_MAX 0.6
 param set-default FW_THR_MIN 0.05
 param set-default FW_T_CLMB_MAX 8

ROMFS/px4fmu_common/init.d-posix/airframes/1041_tailsitter

@@ -51,7 +51,7 @@ param set-default FW_PSP_OFF 2
 param set-default FW_P_LIM_MAX 32
 param set-default FW_P_LIM_MIN -15
 param set-default FW_RR_P 0.2
-param set-default FW_THR_TRIM 0.33
+param set-default FW_THR_CRUISE 0.33
 param set-default FW_THR_MAX 0.6
 param set-default FW_THR_MIN 0.05
 param set-default FW_T_ALT_TC 2

ROMFS/px4fmu_common/init.d-posix/airframes/1042_tiltrotor

@@ -27,9 +27,7 @@ param set-default CA_ROTOR3_PY 0.1875
 param set-default CA_ROTOR3_KM -0.05
 
 param set-default CA_ROTOR0_TILT 1
-param set-default CA_ROTOR1_TILT 2
 param set-default CA_ROTOR2_TILT 3
-param set-default CA_ROTOR3_TILT 4
 param set-default CA_SV_CS0_TRQ_R -0.5
 param set-default CA_SV_CS0_TYPE 1
 param set-default CA_SV_CS1_TRQ_R 0.5
@@ -64,7 +62,7 @@ param set-default FW_P_LIM_MAX 32
 param set-default FW_P_LIM_MIN -15
 param set-default FW_RR_FF 0.1
 param set-default FW_RR_P 0.3
-param set-default FW_THR_TRIM 0.38
+param set-default FW_THR_CRUISE 0.38
 param set-default FW_THR_MAX 0.6
 param set-default FW_THR_MIN 0.05
 param set-default FW_T_CLMB_MAX 8

ROMFS/px4fmu_common/init.d-posix/airframes/1043_standard_vtol_drop

@@ -16,7 +16,7 @@ param set-default FW_P_LIM_MAX 32
 param set-default FW_P_LIM_MIN -15
 param set-default FW_RR_FF 0.1
 param set-default FW_RR_P 0.3
-param set-default FW_THR_TRIM 0.25
+param set-default FW_THR_CRUISE 0.25
 param set-default FW_THR_MAX 0.6
 param set-default FW_THR_MIN 0.05
 param set-default FW_T_ALT_TC 2

ROMFS/px4fmu_common/init.d-posix/airframes/17001_tf-g1

@@ -41,7 +41,7 @@ param set-default FW_R_LIM 30
 param set-default FW_MAN_P_MAX 30.0
 param set-default FW_MAN_R_MAX 30.0
 
-param set-default FW_THR_TRIM 0.8
+param set-default FW_THR_CRUISE 0.8
 param set-default FW_THR_IDLE 0
 param set-default COM_DISARM_PRFLT 0
 

ROMFS/px4fmu_common/init.d-posix/airframes/17002_tf-g2

@@ -1,55 +0,0 @@
-#!/bin/sh
-#
-# @name ThunderFly TF-G2
-# ThunderFly TF-G2 autogyro airframe. Only for FlightGear simulator
-#
-# @type Autogyro
-# @class Autogyro
-#
-# @url https://github.com/ThunderFly-aerospace/TF-G2/
-#
-#
-
-. ${R}etc/init.d/rc.fw_defaults
-
-param set-default FW_AIRSPD_STALL 5
-
-param set-default FW_P_RMAX_NEG 20.0
-param set-default FW_W_RMAX 10
-param set-default FW_W_EN 1
-
-param set-default FW_RR_P 0.08
-
-param set-default MIS_LTRMIN_ALT 50
-param set-default MIS_TAKEOFF_ALT 7
-
-param set-default NAV_ACC_RAD 20
-param set-default NAV_DLL_ACT 2
-param set-default NAV_LOITER_RAD 50
-
-param set-default RWTO_TKOFF 0
-# Parameters related to autogyro takeoff PR
-#param set-default AG_TKOFF 1
-#param set-default AG_PROT_TYPE 1
-#param set-default AG_PROT_MIN_RPM 50.0
-#param set-default AG_PROT_TRG_RPM 900.0
-#param set-defoult AG_ROTOR_RPM 900.0
-
-param set-default FW_ARSP_SCALE_EN 0
-
-param set-default FW_AIRSPD_MAX 35
-param set-default FW_AIRSPD_MIN 7
-
-param set-default FW_P_LIM_MAX 25
-param set-default FW_P_LIM_MIN -5
-param set-default FW_R_LIM 30
-
-param set-default FW_MAN_P_MAX 30.0
-param set-default FW_MAN_R_MAX 30.0
-
-param set-default FW_THR_CRUISE 0.8
-param set-default FW_THR_IDLE 0
-param set-default COM_DISARM_PRFLT 0
-
-set MIXER_FILE etc/mixers-sitl/autogyro_sitl.main.mix
-set MIXER custom

ROMFS/px4fmu_common/init.d-posix/airframes/CMakeLists.txt

@@ -78,7 +78,6 @@ px4_add_romfs_files(
 	3010_quadrotor_x
 	3011_hexarotor_x
 	17001_tf-g1
-	17002_tf-g2
 	2507_cloudship
 	6011_typhoon_h480
 	6011_typhoon_h480.post

ROMFS/px4fmu_common/init.d/airframes/1000_rc_fw_easystar.hil

@@ -29,6 +29,9 @@ param set-default FW_L1_DAMPING 0.74
 param set-default FW_L1_PERIOD 16
 param set-default FW_LND_ANG 15
 param set-default FW_LND_FLALT 5
+param set-default FW_LND_HVIRT 13
+param set-default FW_LND_TLALT 5
+param set-default FW_THR_LND_MAX 0
 param set-default FW_PR_FF 0.35
 param set-default FW_PR_P 0.2
 param set-default FW_RR_FF 0.6

ROMFS/px4fmu_common/init.d/airframes/13000_generic_vtol_standard

@@ -1,10 +1,22 @@
 #!/bin/sh
 #
-# @name Generic Standard VTOL
+# @name Generic Quadplane VTOL
 #
 # @type Standard VTOL
 # @class VTOL
-
+#
+# @maintainer
+#
+# @output MAIN1 motor 1
+# @output MAIN2 motor 2
+# @output MAIN3 motor 3
+# @output MAIN4 motor 4
+# @output AUX1 Aileron 1
+# @output AUX2 Aileron 2
+# @output AUX3 Elevator
+# @output AUX4 Rudder
+# @output AUX5 Throttle
+#
 # @board px4_fmu-v2 exclude
 # @board bitcraze_crazyflie exclude
 # @board holybro_kakutef7 exclude
@@ -12,21 +24,21 @@
 
 . ${R}etc/init.d/rc.vtol_defaults
 
-param set-default SYS_CTRL_ALLOC 1
 param set-default CA_AIRFRAME 2
 param set-default CA_ROTOR_COUNT 5
-param set-default CA_ROTOR0_PX 1
-param set-default CA_ROTOR0_PY 1
-param set-default CA_ROTOR1_PX -1
-param set-default CA_ROTOR1_PY -1
-param set-default CA_ROTOR2_PX 1
-param set-default CA_ROTOR2_PY -1
+param set-default CA_ROTOR0_PX 0.15
+param set-default CA_ROTOR0_PY 0.15
+param set-default CA_ROTOR1_PX -0.15
+param set-default CA_ROTOR1_PY -0.15
+param set-default CA_ROTOR2_PX 0.15
+param set-default CA_ROTOR2_PY -0.15
 param set-default CA_ROTOR2_KM -0.05
-param set-default CA_ROTOR3_PX -1
-param set-default CA_ROTOR3_PY 1
+param set-default CA_ROTOR3_PX -0.15
+param set-default CA_ROTOR3_PY 0.15
 param set-default CA_ROTOR3_KM -0.05
 param set-default CA_ROTOR4_AX 1.0
 param set-default CA_ROTOR4_AZ 0.0
+param set-default CA_ROTOR4_PX 0.2
 param set-default CA_SV_CS_COUNT 4
 param set-default CA_SV_CS0_TYPE 1
 param set-default CA_SV_CS0_TRQ_R -0.5
@@ -36,5 +48,16 @@ param set-default CA_SV_CS2_TYPE 3
 param set-default CA_SV_CS2_TRQ_P 1.0
 param set-default CA_SV_CS3_TRQ_Y 1.0
 param set-default CA_SV_CS3_TYPE 4
+
+param set-default PWM_AUX_DIS5 950
+
 param set-default VT_TYPE 2
+param set-default VT_MOT_ID 1234
+param set-default VT_FW_MOT_OFFID 1234
+
 param set-default MAV_TYPE 22
+
+set MIXER quad_x
+set MIXER_AUX vtol_AAERT
+
+set PWM_OUT 1234

ROMFS/px4fmu_common/init.d/airframes/13005_vtol_AAERT_quad

@@ -43,7 +43,7 @@ param set-default MPC_YAWRAUTO_MAX 40
 param set-default FW_PR_I 0.02
 param set-default FW_RR_FF 0.6
 param set-default FW_RR_I 0.01
-param set-default FW_THR_TRIM 0.75
+param set-default FW_THR_CRUISE 0.75
 
 param set-default VT_ARSP_BLEND 6
 param set-default VT_ARSP_TRANS 12

ROMFS/px4fmu_common/init.d/airframes/13008_QuadRanger

@@ -14,7 +14,7 @@
 . ${R}etc/init.d/rc.vtol_defaults
 
 
-param set-default FW_THR_TRIM 65
+param set-default FW_THR_CRUISE 65
 param set-default FW_RR_FF 0.6
 
 param set-default MIS_YAW_TMT 10

ROMFS/px4fmu_common/init.d/airframes/13013_deltaquad

@@ -53,7 +53,7 @@ param set-default FW_T_CLMB_MAX 3
 param set-default FW_T_SINK_MAX 3
 param set-default FW_T_SINK_MIN 1
 param set-default FW_T_VERT_ACC 6
-param set-default FW_THR_TRIM 0.70
+param set-default FW_THR_CRUISE 0.70
 param set-default FW_THR_SLEW_MAX 1
 param set-default FW_MAN_P_MAX 30
 param set-default FW_P_LIM_MAX 15

ROMFS/px4fmu_common/init.d/airframes/13014_vtol_babyshark

@@ -39,7 +39,7 @@ param set-default FW_RLL_TO_YAW_FF 0.1
 param set-default FW_RR_P 0.08
 param set-default FW_R_LIM 45
 param set-default FW_R_RMAX 50
-param set-default FW_THR_TRIM 0.65
+param set-default FW_THR_CRUISE 0.65
 param set-default FW_THR_MIN 0.3
 param set-default FW_THR_SLEW_MAX 0.6
 param set-default FW_T_HRATE_FF 0

ROMFS/px4fmu_common/init.d/airframes/13100_generic_vtol_tiltrotor

@@ -1,44 +0,0 @@
-#!/bin/sh
-#
-# @name Generic Tiltrotor VTOL
-#
-# @type VTOL Tiltrotor
-# @class VTOL
-#
-# @board px4_fmu-v2 exclude
-# @board bitcraze_crazyflie exclude
-#
-
-. ${R}etc/init.d/rc.vtol_defaults
-
-param set-default SYS_CTRL_ALLOC 1
-
-param set-default CA_AIRFRAME 3
-param set-default CA_ROTOR_COUNT 4
-param set-default CA_ROTOR0_PX 1
-param set-default CA_ROTOR0_PY 1
-param set-default CA_ROTOR0_TILT 2
-param set-default CA_ROTOR1_PX -1
-param set-default CA_ROTOR1_PY -1
-param set-default CA_ROTOR2_PX 1
-param set-default CA_ROTOR2_PY -1
-param set-default CA_ROTOR2_TILT 1
-param set-default CA_ROTOR2_KM -0.05
-param set-default CA_ROTOR3_PX -1
-param set-default CA_ROTOR3_PY 1
-param set-default CA_ROTOR3_KM -0.05
-param set-default CA_SV_CS_COUNT 4
-param set-default CA_SV_CS0_TYPE 1
-param set-default CA_SV_CS0_TRQ_R -0.5
-param set-default CA_SV_CS1_TYPE 2
-param set-default CA_SV_CS1_TRQ_R 0.5
-param set-default CA_SV_CS2_TYPE 7
-param set-default CA_SV_CS2_TRQ_P 0.5
-param set-default CA_SV_CS2_TRQ_Y 0.5
-param set-default CA_SV_CS3_TYPE 8
-param set-default CA_SV_CS3_TRQ_P 0.5
-param set-default CA_SV_CS3_TRQ_Y -0.5
-param set-default CA_SV_TL_COUNT 2
-
-param set-default MAV_TYPE 21
-param set-default VT_TYPE 1

ROMFS/px4fmu_common/init.d/airframes/13200_generic_vtol_tailsitter

@@ -1,10 +1,17 @@
 #!/bin/sh
 #
-# @name Generic VTOL Tailsitter
+# @name Generic Tailsitter
 #
-# @type VTOL Tailsitter
+# @type VTOL Duo Tailsitter
 # @class VTOL
 #
+# @output MAIN1 motor right
+# @output MAIN2 motor left
+# @output MAIN5 elevon right
+# @output MAIN6 elevon left
+#
+# @maintainer Roman Bapst <roman@px4.io>
+#
 # @board px4_fmu-v2 exclude
 # @board bitcraze_crazyflie exclude
 # @board holybro_kakutef7 exclude
@@ -12,13 +19,18 @@
 
 . ${R}etc/init.d/rc.vtol_defaults
 
-param set-default SYS_CTRL_ALLOC 1
+param set-default MAV_TYPE 19
+
+param set-default VT_ELEV_MC_LOCK 0
+param set-default VT_MOT_COUNT 2
+param set-default VT_TYPE 0
+
 param set-default CA_AIRFRAME 4
 param set-default CA_ROTOR_COUNT 2
 param set-default CA_ROTOR0_KM -0.05
-param set-default CA_ROTOR0_PY -0.2
-param set-default CA_ROTOR1_KM 0.05
-param set-default CA_ROTOR1_PY 0.2
+param set-default CA_ROTOR0_PY 0.2
+param set-default CA_ROTOR1_KM -0.05
+param set-default CA_ROTOR1_PY -0.2
 param set-default CA_SV_CS_COUNT 2
 param set-default CA_SV_CS0_TRQ_P 0.5
 param set-default CA_SV_CS0_TRQ_Y 0.5
@@ -27,6 +39,6 @@ param set-default CA_SV_CS1_TRQ_P 0.5
 param set-default CA_SV_CS1_TRQ_Y -0.5
 param set-default CA_SV_CS1_TYPE 6
 
-param set-default MAV_TYPE 19
-param set-default VT_TYPE 0
-param set-default VT_ELEV_MC_LOCK 0
+set MIXER vtol_tailsitter_duo
+
+set PWM_OUT 1234

ROMFS/px4fmu_common/init.d/airframes/17002_TF-AutoG2

@@ -37,7 +37,7 @@ param set-default SENS_BOARD_ROT 8
 param set-default FW_AIRSPD_MAX 20
 param set-default FW_AIRSPD_MIN 7
 param set-default FW_AIRSPD_TRIM 13
-param set-default FW_THR_TRIM 0.8
+param set-default FW_THR_CRUISE 0.8
 
 param set-default FW_MAN_P_MAX 25
 param set-default FW_MAN_R_MAX 25

ROMFS/px4fmu_common/init.d/airframes/17003_TF-G2

@@ -32,7 +32,7 @@ param set-default SENS_BOARD_ROT 4
 param set-default FW_AIRSPD_MAX 20
 param set-default FW_AIRSPD_MIN 7
 param set-default FW_AIRSPD_TRIM 13
-param set-default FW_THR_TRIM 0.8
+param set-default FW_THR_CRUISE 0.8
 
 param set-default FW_MAN_P_MAX 25
 param set-default FW_MAN_R_MAX 25

ROMFS/px4fmu_common/init.d/airframes/2100_standard_plane

@@ -1,16 +1,28 @@
 #!/bin/sh
 #
-# @name Generic Standard Plane
+# @name Standard Plane
 #
 # @type Standard Plane
 # @class Plane
 #
+# @output MAIN1 aileron
+# @output MAIN2 elevator
+# @output MAIN3 throttle
+# @output MAIN4 rudder
+# @output MAIN5 flaps
+# @output MAIN6 gear
+#
+# @output AUX1 feed-through of RC AUX1 channel
+# @output AUX2 feed-through of RC AUX2 channel
+# @output AUX3 feed-through of RC AUX3 channel
+#
+# @maintainer Lorenz Meier <lorenz@px4.io>
+#
 # @board bitcraze_crazyflie exclude
 #
 
 . ${R}etc/init.d/rc.fw_defaults
 
-param set-default SYS_CTRL_ALLOC 1
 param set-default CA_AIRFRAME 1
 param set-default CA_ROTOR_COUNT 1
 param set-default CA_ROTOR0_PX 0.3
@@ -22,3 +34,11 @@ param set-default CA_SV_CS2_TRQ_P 1.0
 param set-default CA_SV_CS2_TYPE 3
 param set-default CA_SV_CS3_TRQ_Y 1.0
 param set-default CA_SV_CS3_TYPE 4
+
+param set-default PWM_AUX_RATE 50
+param set-default PWM_MAIN_RATE 50
+
+set MIXER AETRFG
+
+# Rate must be set by group (see pwm info).
+# Throttle is in the same group as servos.

ROMFS/px4fmu_common/init.d/airframes/3000_generic_wing

@@ -5,20 +5,19 @@
 # @type Flying Wing
 # @class Plane
 #
+# @output MAIN1 left aileron
+# @output MAIN2 right aileron
+# @output MAIN4 throttle
+#
+# @output AUX1 feed-through of RC AUX1 channel
+# @output AUX2 feed-through of RC AUX2 channel
+# @output AUX3 feed-through of RC AUX3 channel
+#
+# @maintainer
+#
 # @board bitcraze_crazyflie exclude
 #
 
 . ${R}etc/init.d/rc.fw_defaults
 
-param set-default SYS_CTRL_ALLOC 1
-param set-default CA_AIRFRAME 1
-
-param set-default CA_ROTOR_COUNT 1
-param set-default CA_ROTOR0_PX 0.15
-param set-default CA_SV_CS_COUNT 2
-param set-default CA_SV_CS0_TYPE 5
-param set-default CA_SV_CS0_TRQ_P 0.5
-param set-default CA_SV_CS0_TRQ_R -0.5
-param set-default CA_SV_CS1_TYPE 6
-param set-default CA_SV_CS1_TRQ_P 0.5
-param set-default CA_SV_CS1_TRQ_R 0.5
+set MIXER fw_generic_wing

ROMFS/px4fmu_common/init.d/airframes/3032_skywalker_x5

@@ -30,6 +30,9 @@ param set-default FW_L1_DAMPING 0.74
 param set-default FW_L1_PERIOD 16
 param set-default FW_LND_ANG 15
 param set-default FW_LND_FLALT 5
+param set-default FW_LND_HVIRT 13
+param set-default FW_LND_TLALT 5
+param set-default FW_THR_LND_MAX 0
 param set-default FW_PR_FF 0.35
 param set-default FW_RR_FF 0.6
 param set-default FW_RR_P 0.04

ROMFS/px4fmu_common/init.d/airframes/3033_wingwing

@@ -32,6 +32,9 @@ param set-default FW_L1_DAMPING 0.74
 param set-default FW_L1_PERIOD 16
 param set-default FW_LND_ANG 15
 param set-default FW_LND_FLALT 5
+param set-default FW_LND_HVIRT 13
+param set-default FW_LND_TLALT 5
+param set-default FW_THR_LND_MAX 0
 param set-default FW_PR_FF 0.35
 param set-default FW_RR_FF 0.6
 param set-default FW_RR_P 0.04

ROMFS/px4fmu_common/init.d/airframes/3100_tbs_caipirinha

@@ -27,6 +27,9 @@ param set-default FW_AIRSPD_TRIM 16.5
 param set-default FW_L1_PERIOD 15
 param set-default FW_LND_ANG 15
 param set-default FW_LND_FLALT 8
+param set-default FW_LND_HVIRT 13
+param set-default FW_LND_TLALT 10
+param set-default FW_THR_LND_MAX 0
 param set-default FW_P_LIM_MAX 20
 param set-default FW_P_LIM_MIN -30
 param set-default FW_R_LIM 45
@@ -37,7 +40,7 @@ param set-default FW_RR_P 0.013
 param set-default FW_P_RMAX_NEG 70
 param set-default FW_P_RMAX_POS 70
 param set-default FW_R_RMAX 70
-param set-default FW_THR_TRIM 0.55
+param set-default FW_THR_CRUISE 0.55
 
 param set-default LNDFW_AIRSPD_MAX 6
 param set-default LNDFW_XYACC_MAX 4

ROMFS/px4fmu_common/init.d/airframes/CMakeLists.txt

@@ -124,7 +124,6 @@ px4_add_romfs_files(
 	13007_vtol_AAVVT_quad
 	13008_QuadRanger
 	13009_vtol_spt_ranger
-	13100_generic_vtol_tiltrotor
 	13012_convergence
 	13013_deltaquad
 	13014_vtol_babyshark

ROMFS/px4fmu_common/init.d/rcS

@@ -206,26 +206,6 @@ else
 	fi
 	unset BOARD_RC_DEFAULTS
 
-	#
-	# Set parameters and env variables for selected SYS_AUTOSTART.
-	#
-	set AUTOSTART_PATH etc/init.d/rc.autostart
-	if ! param compare SYS_AUTOSTART 0
-	then
-		if param greater SYS_AUTOSTART 1000000
-		then
-			# Use external startup file
-			if [ $SDCARD_AVAILABLE = yes ]
-			then
-				set AUTOSTART_PATH etc/init.d/rc.autostart_ext
-			else
-				echo "ERROR [init] SD card not mounted - trying to load airframe from ROMFS"
-			fi
-		fi
-		. ${R}$AUTOSTART_PATH
-	fi
-	unset AUTOSTART_PATH
-
 	#
 	# Start the tone_alarm driver.
 	# Needs to be started after the parameters are loaded (for CBRK_BUZZER).
@@ -263,6 +243,26 @@ else
 	rgbled start -X -q
 	rgbled_ncp5623c start -X -q
 
+	#
+	# Set parameters and env variables for selected AUTOSTART.
+	#
+	set AUTOSTART_PATH etc/init.d/rc.autostart
+	if ! param compare SYS_AUTOSTART 0
+	then
+		if param greater SYS_AUTOSTART 1000000
+		then
+			# Use external startup file
+			if [ $SDCARD_AVAILABLE = yes ]
+			then
+				set AUTOSTART_PATH etc/init.d/rc.autostart_ext
+			else
+				echo "ERROR [init] SD card not mounted - trying to load airframe from ROMFS"
+			fi
+		fi
+		. ${R}$AUTOSTART_PATH
+	fi
+	unset AUTOSTART_PATH
+
 	#
 	# Override parameters from user configuration file.
 	#
@@ -303,7 +303,7 @@ else
 	then
 		# Check for the mini using build with px4io fw file
 		# but not a px4IO
-		if ver hwtypecmp V5004000 V5006000
+		if ver hwtypecmp V540 V560
 		then
 			param set SYS_USE_IO 0
 		else

Tools/astyle/files_to_check_code_style.sh

@@ -8,23 +8,24 @@ if [ $# -gt 0 ]; then
 fi
 
 exec find boards msg src platforms test \
-    -path msg/templates/urtps -prune -o \
-    -path platforms/nuttx/NuttX -prune -o \
-    -path platforms/qurt/dspal -prune -o \
-    -path src/drivers/uavcan/libuavcan -prune -o \
-    -path src/drivers/uavcan/uavcan_drivers/kinetis/driver/include/uavcan_kinetis -prune -o \
-    -path src/drivers/cyphal/libcanard -prune -o \
-    -path src/lib/crypto/monocypher -prune -o \
-    -path src/lib/events/libevents -prune -o \
-    -path src/lib/parameters/uthash -prune -o \
-    -path src/modules/ekf2/EKF -prune -o \
-    -path src/modules/gyro_fft/CMSIS_5 -prune -o \
-    -path src/modules/mavlink/mavlink -prune -o \
-    -path src/modules/micrortps_bridge/micro-CDR -prune -o \
-    -path src/modules/micrortps_bridge/microRTPS_client -prune -o \
-    -path test/mavsdk_tests/catch2 -prune -o \
-    -path src/lib/crypto/monocypher -prune -o \
-    -path src/lib/crypto/libtomcrypt -prune -o \
-    -path src/lib/crypto/libtommath -prune -o \
-    -path src/modules/microdds_client/Micro-XRCE-DDS-Client -prune -o \
+    -not -path "msg/templates/urtps/*" \
+    -not -path "platforms/nuttx/NuttX/*" \
+    -not -path "platforms/qurt/dspal/*" \
+    -not -path "src/drivers/gps/devices/*" \
+    -not -path "src/drivers/uavcan/libuavcan/*" \
+    -not -path "src/drivers/uavcan/uavcan_drivers/kinetis/driver/include/uavcan_kinetis/*" \
+    -not -path "src/drivers/cyphal/libcanard/*" \
+    -not -path "src/lib/crypto/monocypher/*" \
+    -not -path "src/lib/events/libevents/*" \
+    -not -path "src/lib/parameters/uthash/*" \
+    -not -path "src/modules/ekf2/EKF/*" \
+    -not -path "src/modules/gyro_fft/CMSIS_5/*" \
+    -not -path "src/modules/mavlink/mavlink/*" \
+    -not -path "src/modules/micrortps_bridge/micro-CDR/*" \
+    -not -path "src/modules/micrortps_bridge/microRTPS_client/*" \
+    -not -path "test/mavsdk_tests/catch2/*" \
+    -not -path "src/lib/crypto/monocypher/*" \
+    -not -path "src/lib/crypto/libtomcrypt/*" \
+    -not -path "src/lib/crypto/libtommath/*" \
+    -not -path "src/modules/microdds_client/Micro-XRCE-DDS-Client/*" \
     -type f \( -name "*.c" -o -name "*.h" -o -name "*.cpp" -o -name "*.hpp" \) | grep $PATTERN

boards/airmind/mindpx-v2/nuttx-config/include/board.h

@@ -40,11 +40,11 @@
 /************************************************************************************
  * Included Files
  ************************************************************************************/
-#include "board_dma_map.h"
-
 #include <nuttx/config.h>
+
+#include "board_dma_map.h"
 #ifndef __ASSEMBLY__
-# include <stdint.h>
+#include <stdint.h>
 #endif
 
 #include <stm32.h>
@@ -83,11 +83,11 @@
  * LSE - not installed
  */
 
-#define STM32_BOARD_XTAL        8000000ul
+#define STM32_BOARD_XTAL 8000000ul
 
-#define STM32_HSI_FREQUENCY     16000000ul
-#define STM32_LSI_FREQUENCY     32000
-#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
 //#define STM32_LSE_FREQUENCY     32768
 
 /* Main PLL Configuration.
@@ -103,68 +103,68 @@
  *         = 48,000,000
  */
 
-#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(336)
-#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
-#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(7)
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7)
 
-#define STM32_SYSCLK_FREQUENCY  168000000ul
+#define STM32_SYSCLK_FREQUENCY 168000000ul
 
 /* AHB clock (HCLK) is SYSCLK (168MHz) */
 
-#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK  /* HCLK  = SYSCLK / 1 */
-#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
-#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
 
 /* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
 
-#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4     /* PCLK1 = HCLK / 4 */
-#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/4)
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
+#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 4)
 
 /* Timers driven from APB1 will be twice PCLK1 */
 
-#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
 
 /* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
 
-#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2     /* PCLK2 = HCLK / 2 */
-#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
+#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
 
 /* Timers driven from APB2 will be twice PCLK2 */
 
-#define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM9_CLKIN   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM10_CLKIN  (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM11_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY)
 
 /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
  * otherwise frequency is 2xAPBx.
  * Note: TIM1,8-11 are on APB2, others on APB1
  */
 
-#define BOARD_TIM1_FREQUENCY    STM32_APB2_TIM1_CLKIN
-#define BOARD_TIM2_FREQUENCY    STM32_APB1_TIM2_CLKIN
-#define BOARD_TIM3_FREQUENCY    STM32_APB1_TIM3_CLKIN
-#define BOARD_TIM4_FREQUENCY    STM32_APB1_TIM4_CLKIN
-#define BOARD_TIM5_FREQUENCY    STM32_APB1_TIM5_CLKIN
-#define BOARD_TIM6_FREQUENCY    STM32_APB1_TIM6_CLKIN
-#define BOARD_TIM7_FREQUENCY    STM32_APB1_TIM7_CLKIN
-#define BOARD_TIM8_FREQUENCY    STM32_APB2_TIM8_CLKIN
-#define BOARD_TIM9_FREQUENCY    STM32_APB2_TIM9_CLKIN
-#define BOARD_TIM10_FREQUENCY   STM32_APB2_TIM10_CLKIN
-#define BOARD_TIM11_FREQUENCY   STM32_APB2_TIM11_CLKIN
-#define BOARD_TIM12_FREQUENCY   STM32_APB1_TIM12_CLKIN
-#define BOARD_TIM13_FREQUENCY   STM32_APB1_TIM13_CLKIN
-#define BOARD_TIM14_FREQUENCY   STM32_APB1_TIM14_CLKIN
+#define BOARD_TIM1_FREQUENCY STM32_APB2_TIM1_CLKIN
+#define BOARD_TIM2_FREQUENCY STM32_APB1_TIM2_CLKIN
+#define BOARD_TIM3_FREQUENCY STM32_APB1_TIM3_CLKIN
+#define BOARD_TIM4_FREQUENCY STM32_APB1_TIM4_CLKIN
+#define BOARD_TIM5_FREQUENCY STM32_APB1_TIM5_CLKIN
+#define BOARD_TIM6_FREQUENCY STM32_APB1_TIM6_CLKIN
+#define BOARD_TIM7_FREQUENCY STM32_APB1_TIM7_CLKIN
+#define BOARD_TIM8_FREQUENCY STM32_APB2_TIM8_CLKIN
+#define BOARD_TIM9_FREQUENCY STM32_APB2_TIM9_CLKIN
+#define BOARD_TIM10_FREQUENCY STM32_APB2_TIM10_CLKIN
+#define BOARD_TIM11_FREQUENCY STM32_APB2_TIM11_CLKIN
+#define BOARD_TIM12_FREQUENCY STM32_APB1_TIM12_CLKIN
+#define BOARD_TIM13_FREQUENCY STM32_APB1_TIM13_CLKIN
+#define BOARD_TIM14_FREQUENCY STM32_APB1_TIM14_CLKIN
 
 /* SDIO dividers.  Note that slower clocking is required when DMA is disabled
  * in order to avoid RX overrun/TX underrun errors due to delayed responses
@@ -174,16 +174,16 @@
  * SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(118+2)=400 KHz
  */
 
-#define SDIO_INIT_CLKDIV        (118 << SDIO_CLKCR_CLKDIV_SHIFT)
+#define SDIO_INIT_CLKDIV (118 << SDIO_CLKCR_CLKDIV_SHIFT)
 
 /* DMA ON:  SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
  * DMA OFF: SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(2+2)=12 MHz
  */
 
 #ifdef CONFIG_STM32_SDIO_DMA
-#  define SDIO_MMCXFR_CLKDIV    (1 << SDIO_CLKCR_CLKDIV_SHIFT)
+#define SDIO_MMCXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
 #else
-#  define SDIO_MMCXFR_CLKDIV    (2 << SDIO_CLKCR_CLKDIV_SHIFT)
+#define SDIO_MMCXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
 #endif
 
 /* DMA ON:  SDIOCLK=48MHz, SDIO_CK=SDIOCLK/(1+2)=16 MHz
@@ -191,9 +191,9 @@
  */
 
 #ifdef CONFIG_STM32_SDIO_DMA
-#  define SDIO_SDXFR_CLKDIV     (1 << SDIO_CLKCR_CLKDIV_SHIFT)
+#define SDIO_SDXFR_CLKDIV (1 << SDIO_CLKCR_CLKDIV_SHIFT)
 #else
-#  define SDIO_SDXFR_CLKDIV     (2 << SDIO_CLKCR_CLKDIV_SHIFT)
+#define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT)
 #endif
 
 /* Alternate function pin selections ************************************************/
@@ -201,27 +201,27 @@
 /*
  * UARTs.
  */
-#define GPIO_USART1_RX	GPIO_USART1_RX_2	/* RC_INPUT */
-#define GPIO_USART1_TX	GPIO_USART1_TX_2
+#define GPIO_USART1_RX GPIO_USART1_RX_2 /* RC_INPUT */
+#define GPIO_USART1_TX GPIO_USART1_TX_2
 
-#define GPIO_USART2_RX	GPIO_USART2_RX_2
-#define GPIO_USART2_TX	GPIO_USART2_TX_2
-#define GPIO_USART2_RTS	GPIO_USART2_RTS_2
-#define GPIO_USART2_CTS	GPIO_USART2_CTS_2
+#define GPIO_USART2_RX GPIO_USART2_RX_2
+#define GPIO_USART2_TX GPIO_USART2_TX_2
+#define GPIO_USART2_RTS GPIO_USART2_RTS_2
+#define GPIO_USART2_CTS GPIO_USART2_CTS_2
 
-#define GPIO_USART3_RX	GPIO_USART3_RX_3
-#define GPIO_USART3_TX	GPIO_USART3_TX_3
-#define GPIO_USART3_CTS	0 // unused
-#define GPIO_USART3_RTS	0 // unused
+#define GPIO_USART3_RX GPIO_USART3_RX_3
+#define GPIO_USART3_TX GPIO_USART3_TX_3
+#define GPIO_USART3_CTS 0  // unused
+#define GPIO_USART3_RTS 0  // unused
 
-#define GPIO_UART4_RX	GPIO_UART4_RX_1
-#define GPIO_UART4_TX	GPIO_UART4_TX_1
+#define GPIO_UART4_RX GPIO_UART4_RX_1
+#define GPIO_UART4_TX GPIO_UART4_TX_1
 
-#define GPIO_USART6_RX	GPIO_USART6_RX_2
-#define GPIO_USART6_TX	GPIO_USART6_TX_2
+#define GPIO_USART6_RX GPIO_USART6_RX_2
+#define GPIO_USART6_TX GPIO_USART6_TX_2
 
-#define GPIO_UART7_RX	GPIO_UART7_RX_1
-#define GPIO_UART7_TX	GPIO_UART7_TX_1
+#define GPIO_UART7_RX GPIO_UART7_RX_1
+#define GPIO_UART7_TX GPIO_UART7_TX_1
 
 /* UART8 has no alternate pin config */
 
@@ -230,8 +230,8 @@
  *
  * CAN1 is routed to the onboard transceiver.
  */
-#define GPIO_CAN1_RX	GPIO_CAN1_RX_3
-#define GPIO_CAN1_TX	GPIO_CAN1_TX_3
+#define GPIO_CAN1_RX GPIO_CAN1_RX_3
+#define GPIO_CAN1_TX GPIO_CAN1_TX_3
 
 /*
  * I2C
@@ -240,32 +240,31 @@
  * reset the bus to clear stuck slaves.  They match the pin configuration,
  * but are normally-high GPIOs.
  */
-#define GPIO_I2C1_SCL		GPIO_I2C1_SCL_2
-#define GPIO_I2C1_SDA		GPIO_I2C1_SDA_2
-#define GPIO_I2C1_SCL_GPIO	(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN8)
-#define GPIO_I2C1_SDA_GPIO	(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
+#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN8)
+#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
 
-#define GPIO_I2C2_SCL		GPIO_I2C2_SCL_1
-#define GPIO_I2C2_SDA		GPIO_I2C2_SDA_1
-#define GPIO_I2C2_SCL_GPIO	(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_I2C2_SDA_GPIO	(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
+#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
+#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN11)
 
 /*
  * SPI
  *
  * There are sensors on SPI1, and SPI2 is connected to the FRAM.
  */
-#define GPIO_SPI1_MISO	(GPIO_SPI1_MISO_1|GPIO_SPEED_50MHz)
-#define GPIO_SPI1_MOSI	(GPIO_SPI1_MOSI_2|GPIO_SPEED_50MHz)
-#define GPIO_SPI1_SCK	(GPIO_SPI1_SCK_1|GPIO_SPEED_50MHz)
+#define GPIO_SPI1_MISO (GPIO_SPI1_MISO_1 | GPIO_SPEED_50MHz)
+#define GPIO_SPI1_MOSI (GPIO_SPI1_MOSI_2 | GPIO_SPEED_50MHz)
+#define GPIO_SPI1_SCK (GPIO_SPI1_SCK_1 | GPIO_SPEED_50MHz)
 
-#define GPIO_SPI2_MISO	(GPIO_SPI2_MISO_1|GPIO_SPEED_50MHz)
-#define GPIO_SPI2_MOSI	(GPIO_SPI2_MOSI_1|GPIO_SPEED_50MHz)
-#define GPIO_SPI2_SCK	(GPIO_SPI2_SCK_2|GPIO_SPEED_50MHz)
+#define GPIO_SPI2_MISO (GPIO_SPI2_MISO_1 | GPIO_SPEED_50MHz)
+#define GPIO_SPI2_MOSI (GPIO_SPI2_MOSI_1 | GPIO_SPEED_50MHz)
+#define GPIO_SPI2_SCK (GPIO_SPI2_SCK_2 | GPIO_SPEED_50MHz)
 
-#define GPIO_SPI4_MISO	(GPIO_SPI4_MISO_1|GPIO_SPEED_50MHz)
-#define GPIO_SPI4_MOSI	(GPIO_SPI4_MOSI_1|GPIO_SPEED_50MHz)
-#define GPIO_SPI4_SCK	(GPIO_SPI4_SCK_1|GPIO_SPEED_50MHz)
+#define GPIO_SPI4_MISO (GPIO_SPI4_MISO_1 | GPIO_SPEED_50MHz)
+#define GPIO_SPI4_MOSI (GPIO_SPI4_MOSI_1 | GPIO_SPEED_50MHz)
+#define GPIO_SPI4_SCK (GPIO_SPI4_SCK_1 | GPIO_SPEED_50MHz)
 
-
-#endif  /* __ARCH_BOARD_BOARD_H */
+#endif /* __ARCH_BOARD_BOARD_H */

boards/airmind/mindpx-v2/nuttx-config/include/board_dma_map.h

@@ -33,55 +33,61 @@
 
 #pragma once
 
-
 /*
-|    DMA1    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5         | Stream 6         | Stream 7         |
+|    DMA1    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5
+| Stream 6         | Stream 7         |
 |------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
-| Channel 0  | SPI3_RX_1        | -                | SPI3_RX_2        | SPI2_RX          | SPI2_TX          | SPI3_TX_1        | -                | SPI3_TX_2        |
-| Channel 1  | I2C1_RX          | -                | TIM7_UP_1        |  -               | TIM7_UP_2        | I2C1_RX_1        | I2C1_TX          | I2C1_TX_1        |
-| Channel 2  | TIM4_CH1         | -                | I2C4_RX          | TIM4_CH2         | -                | I2C4_RX          | TIM4_UP          | TIM4_CH3         |
-| Channel 3  | -                | TIM2_UP_1        | I2C3_RX_1        | I2C2_EXT_RX      | I2C3_TX          | TIM2_CH1         | TIM2_CH2         | TIM2_UP_2        |
-|            |                  |   TIM2_CH3       |                  |                  |                  |                  |   TIM2_CH4_1     |   TIM2_CH4_2     |
-| Channel 4  | UART5_RX         | USART3_RX        | UART4_RX         | USART3_TX_1      | UART4_TX         | USART2_RX        | USART2_TX        | UART5_TX         |
-| Channel 5  | UART8_TX         | UART7_TX         | TIM3_CH4         | UART7_RX         | TIM3_CH1         | TIM3_CH2         | UART8_RX         | TIM3_CH3         |
-|            |                  |                  |   TIM3_UP        |                  |   TIM3_TRIG      |                  |                  |                  |
-| Channel 6  | TIM5_CH3         | TIM5_CH4_1       | TIM5_CH1         | TIM5_CH4_2       | TIM5_CH2         | -                | TIM5_UP_2        | -                |
-|            |   TIM5_UP_1      |   TIM5_TRIG_1    |                  |   TIM5_TRIG_2    |                  |                  |                  |                  |
-| Channel 7  | -                | TIM6_UP          | I2C2_RX          | I2C2_RX_1        | USART3_TX_2      | DAC1             | DAC2             | I2C2_TX          |
-|            |                  |                  |                  |                  |                  |                  |                  |                  |
-| Usage      |                  |                  |                  |                  |                  |                  |                  |                  |
+| Channel 0  | SPI3_RX_1        | -                | SPI3_RX_2        | SPI2_RX          | SPI2_TX          | SPI3_TX_1
+| -                | SPI3_TX_2        | | Channel 1  | I2C1_RX          | -                | TIM7_UP_1        |  - |
+TIM7_UP_2        | I2C1_RX_1        | I2C1_TX          | I2C1_TX_1        | | Channel 2  | TIM4_CH1         | - |
+I2C4_RX          | TIM4_CH2         | -                | I2C4_RX          | TIM4_UP          | TIM4_CH3         | |
+Channel 3  | -                | TIM2_UP_1        | I2C3_RX_1        | I2C2_EXT_RX      | I2C3_TX          | TIM2_CH1 |
+TIM2_CH2         | TIM2_UP_2        | |            |                  |   TIM2_CH3       |                  | | | |
+TIM2_CH4_1     |   TIM2_CH4_2     | | Channel 4  | UART5_RX         | USART3_RX        | UART4_RX         | USART3_TX_1
+| UART4_TX         | USART2_RX        | USART2_TX        | UART5_TX         | | Channel 5  | UART8_TX         | UART7_TX
+| TIM3_CH4         | UART7_RX         | TIM3_CH1         | TIM3_CH2         | UART8_RX         | TIM3_CH3         | | |
+|                  |   TIM3_UP        |                  |   TIM3_TRIG      |                  |                  | | |
+Channel 6  | TIM5_CH3         | TIM5_CH4_1       | TIM5_CH1         | TIM5_CH4_2       | TIM5_CH2         | - |
+TIM5_UP_2        | -                | |            |   TIM5_UP_1      |   TIM5_TRIG_1    |                  |
+TIM5_TRIG_2    |                  |                  |                  |                  | | Channel 7  | - | TIM6_UP
+| I2C2_RX          | I2C2_RX_1        | USART3_TX_2      | DAC1             | DAC2             | I2C2_TX          | | |
+|                  |                  |                  |                  |                  |                  | | |
+Usage      |                  |                  |                  |                  |                  | | | |
 
 
-|    DMA2    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5         | Stream 6         | Stream 7         |
+|    DMA2    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5
+| Stream 6         | Stream 7         |
 |------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
-| Channel 0  | ADC1_1           | SAI1_A           | TIM8_CH1_1       | SAI1_A_1         | ADC1_2           | SAI1_B_1         | TIM1_CH1_1       | -                |
-|            |                  |                  |   TIM8_CH2_1     |                  |                  |                  |   TIM1_CH2_1     |                  |
-|            |                  |                  |   TIM8_CH3_1     |                  |                  |                  |   TIM1_CH3_1     |                  |
-| Channel 1  | -                | DCMI_1           | ADC2_1           | ADC2_2           | SAI1_B           | SPI6_TX          | SPI6_RX          | DCMI_2           |
-| Channel 2  | ADC3_1           | ADC3_2           | -                | SPI5_RX_1        | SPI5_TX_1        | CRYP_OUT         | CRYP_IN          | HASH_IN          |
-| Channel 3  | SPI1_RX_1        | -                | SPI1_RX_2        | SPI1_TX_1        | -                | SPI1_TX_2        | -                | QUADSPI          |
-| Channel 4  | SPI4_RX_1        | SPI4_TX_1        | USART1_RX_1      | SDIO             | -                | USART1_RX_2      | SDIO             | USART1_TX        |
-| Channel 5  | -                | USART6_RX_1      | USART6_RX_2      | SPI4_RX_2        | SPI4_TX_2        | -                | USART6_TX_1      | USART6_TX_2      |
-| Channel 6  | TIM1_TRIG_1      | TIM1_CH1_2       | TIM1_CH2_2       | TIM1_CH1         | TIM1_CH4         | TIM1_UP          | TIM1_CH3_2       | -                |
-|            |                  |                  |                  |                  |   TIM1_TRIG_2    |                  |                  |                  |
-|            |                  |                  |                  |                  |   TIM1_COM       |                  |                  |                  |
-| Channel 7  | -                | TIM8_UP          | TIM8_CH1_2       | TIM8_CH2_2       | TIM8_CH3_2       | SPI5_RX_2        | SPI5_TX_2        | TIM8_CH4         |
-|            |                  |                  |                  |                  |                  |                  |                  |   TIM8_TRIG      |
-|            |                  |                  |                  |                  |                  |                  |                  |   TIM8_COM       |
-|            |                  |                  |                  |                  |                  |                  |                  |                  |
-| Usage      | SPI4_RX_1        | USART6_RX_1      | USART1_RX_1      |                  | SPI4_TX_2        |                  | SDIO             |                  |
+| Channel 0  | ADC1_1           | SAI1_A           | TIM8_CH1_1       | SAI1_A_1         | ADC1_2           | SAI1_B_1
+| TIM1_CH1_1       | -                | |            |                  |                  |   TIM8_CH2_1     | | | |
+TIM1_CH2_1     |                  | |            |                  |                  |   TIM8_CH3_1     | | | |
+TIM1_CH3_1     |                  | | Channel 1  | -                | DCMI_1           | ADC2_1           | ADC2_2 |
+SAI1_B           | SPI6_TX          | SPI6_RX          | DCMI_2           | | Channel 2  | ADC3_1           | ADC3_2 | -
+| SPI5_RX_1        | SPI5_TX_1        | CRYP_OUT         | CRYP_IN          | HASH_IN          | | Channel 3  |
+SPI1_RX_1        | -                | SPI1_RX_2        | SPI1_TX_1        | -                | SPI1_TX_2        | - |
+QUADSPI          | | Channel 4  | SPI4_RX_1        | SPI4_TX_1        | USART1_RX_1      | SDIO             | - |
+USART1_RX_2      | SDIO             | USART1_TX        | | Channel 5  | -                | USART6_RX_1      |
+USART6_RX_2      | SPI4_RX_2        | SPI4_TX_2        | -                | USART6_TX_1      | USART6_TX_2      | |
+Channel 6  | TIM1_TRIG_1      | TIM1_CH1_2       | TIM1_CH2_2       | TIM1_CH1         | TIM1_CH4         | TIM1_UP |
+TIM1_CH3_2       | -                | |            |                  |                  |                  | |
+TIM1_TRIG_2    |                  |                  |                  | |            |                  | | | |
+TIM1_COM       |                  |                  |                  | | Channel 7  | -                | TIM8_UP |
+TIM8_CH1_2       | TIM8_CH2_2       | TIM8_CH3_2       | SPI5_RX_2        | SPI5_TX_2        | TIM8_CH4         | | | |
+|                  |                  |                  |                  |                  |   TIM8_TRIG      | | |
+|                  |                  |                  |                  |                  |                  |
+TIM8_COM       | |            |                  |                  |                  |                  | | | | | |
+Usage      | SPI4_RX_1        | USART6_RX_1      | USART1_RX_1      |                  | SPI4_TX_2        | | SDIO | |
  */
 
 // DMA1 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
 
-
 //  DMA2 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
-#define DMACHAN_SPI4_RX    DMAMAP_SPI4_RX_1   // DMA2, Stream 0, Channel 4    (SPI sensors RX)
-#define DMAMAP_USART6_RX   DMAMAP_USART6_RX_1 // DMA2, Stream 1, Channel 4
-#define DMAMAP_USART1_RX   DMAMAP_USART1_RX_1 // DMA2, Stream 2, Channel 4
+#define DMACHAN_SPI4_RX DMAMAP_SPI4_RX_1     // DMA2, Stream 0, Channel 4    (SPI sensors RX)
+#define DMAMAP_USART6_RX DMAMAP_USART6_RX_1  // DMA2, Stream 1, Channel 4
+#define DMAMAP_USART1_RX DMAMAP_USART1_RX_1  // DMA2, Stream 2, Channel 4
 //      AVAILABLE                             // DMA2, Stream 3
-#define DMACHAN_SPI4_TX    DMAMAP_SPI4_TX_2   // DMA2, Stream 4, Channel 5    (SPI sensors TX)
+#define DMACHAN_SPI4_TX DMAMAP_SPI4_TX_2  // DMA2, Stream 4, Channel 5    (SPI sensors TX)
 //      AVAILABLE                             // DMA2, Stream 5, Channel 6
-#define DMAMAP_SDIO        DMAMAP_SDIO_2      // DMA2, Stream 6, Channel 4
+#define DMAMAP_SDIO DMAMAP_SDIO_2  // DMA2, Stream 6, Channel 4

boards/airmind/mindpx-v2/src/board_config.h

@@ -43,8 +43,8 @@
  * Included Files
  ****************************************************************************************************/
 
-#include <px4_platform_common/px4_config.h>
 #include <nuttx/compiler.h>
+#include <px4_platform_common/px4_config.h>
 #include <stdint.h>
 
 /****************************************************************************************************
@@ -52,75 +52,77 @@
  ****************************************************************************************************/
 /* Configuration ************************************************************************************/
 
-
 /* PX4FMU GPIOs ***********************************************************************************/
 /* LEDs */
-#define GPIO_LED1		(GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN8)
-#define BOARD_OVERLOAD_LED     LED_RED
+#define GPIO_LED1 (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN8)
+#define BOARD_OVERLOAD_LED LED_RED
 
 /*
  * ADC channels
  *
- * These are the channel numbers of the ADCs of the microcontroller that can be used by the Px4 Firmware in the adc driver
+ * These are the channel numbers of the ADCs of the microcontroller that can be used by the Px4 Firmware in the adc
+ * driver
  */
 #define ADC_CHANNELS (1 << 4) | (1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) | (1 << 15)
 
 // ADC defines to be used in sensors.cpp to read from a particular channel
-#define ADC_5V_RAIL_SENSE		4
-#define ADC_BATTERY_CURRENT_CHANNEL	10
-#define ADC_BATTERY_VOLTAGE_CHANNEL	12
-#define ADC_RC_RSSI_CHANNEL		11
-#define ADC_AIRSPEED_VOLTAGE_CHANNEL	15
+#define ADC_5V_RAIL_SENSE 4
+#define ADC_BATTERY_CURRENT_CHANNEL 10
+#define ADC_BATTERY_VOLTAGE_CHANNEL 12
+#define ADC_RC_RSSI_CHANNEL 11
+#define ADC_AIRSPEED_VOLTAGE_CHANNEL 15
 
 /* Power supply control and monitoring GPIOs */
-// #define GPIO_VDD_5V_PERIPH_EN	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN8)
-// #define GPIO_VDD_BRICK_VALID	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN5)
-// #define GPIO_VDD_SERVO_VALID	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN7)
-// #define GPIO_VDD_3V3_SENSORS_EN	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3)
-// #define GPIO_VDD_5V_HIPOWER_OC	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN10)
-// #define GPIO_VDD_5V_PERIPH_OC	(GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN15)
+// #define GPIO_VDD_5V_PERIPH_EN
+// (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN8) #define GPIO_VDD_BRICK_VALID
+// (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN5) #define GPIO_VDD_SERVO_VALID
+// (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN7) #define GPIO_VDD_3V3_SENSORS_EN
+// (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTE|GPIO_PIN3) #define GPIO_VDD_5V_HIPOWER_OC
+// (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN10) #define GPIO_VDD_5V_PERIPH_OC
+// (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTE|GPIO_PIN15)
 
 /* Tone alarm output */
-#define TONE_ALARM_TIMER	14	/* timer 14 */
-#define TONE_ALARM_CHANNEL	1	/* channel 1 */
-#define GPIO_TONE_ALARM_IDLE	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_TONE_ALARM		(GPIO_ALT|GPIO_AF9|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
+#define TONE_ALARM_TIMER 14  /* timer 14 */
+#define TONE_ALARM_CHANNEL 1 /* channel 1 */
+#define GPIO_TONE_ALARM_IDLE \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN7)
+#define GPIO_TONE_ALARM (GPIO_ALT | GPIO_AF9 | GPIO_SPEED_2MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN7)
 
 /* AUX PWMs
  */
-#define DIRECT_PWM_OUTPUT_CHANNELS	8
+#define DIRECT_PWM_OUTPUT_CHANNELS 8
 
 /* USB OTG FS
  *
  * PA9  OTG_FS_VBUS VBUS sensing
  */
-#define GPIO_OTGFS_VBUS		(GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9)
-
-
+#define GPIO_OTGFS_VBUS (GPIO_INPUT | GPIO_FLOAT | GPIO_SPEED_100MHz | GPIO_OPENDRAIN | GPIO_PORTA | GPIO_PIN9)
 
 /* High-resolution timer */
-#define HRT_TIMER		8	/* use timer8 for the HRT */
-#define HRT_TIMER_CHANNEL	2	/* use capture/compare channel */
+#define HRT_TIMER 8         /* use timer8 for the HRT */
+#define HRT_TIMER_CHANNEL 2 /* use capture/compare channel */
 
-#define HRT_PPM_CHANNEL		1
-#define GPIO_PPM_IN		GPIO_TIM8_CH1IN_1
+#define HRT_PPM_CHANNEL 1
+#define GPIO_PPM_IN GPIO_TIM8_CH1IN_1
 
 /* PWM input driver. Use FMU AUX5 pins attached to timer4 channel 1 */
-#define PWMIN_TIMER		4
-#define PWMIN_TIMER_CHANNEL	1
-#define GPIO_PWM_IN		GPIO_TIM1_CH1IN_2
+#define PWMIN_TIMER 4
+#define PWMIN_TIMER_CHANNEL 1
+#define GPIO_PWM_IN GPIO_TIM1_CH1IN_2
 
-#define RC_SERIAL_PORT		"/dev/ttyS0"
+#define RC_SERIAL_PORT "/dev/ttyS0"
 
 // #define GPIO_RSSI_IN                (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN1)
-#define GPIO_SBUS_INV                  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN10)
-#define RC_INVERT_INPUT(_invert_true)  px4_arch_gpiowrite(GPIO_SBUS_INV, _invert_true);
+#define GPIO_SBUS_INV (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN10)
+#define RC_INVERT_INPUT(_invert_true) px4_arch_gpiowrite(GPIO_SBUS_INV, _invert_true);
 
-#define GPIO_FRSKY_INV                (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN12)
-#define INVERT_FRSKY(_invert_true)    px4_arch_gpiowrite(GPIO_FRSKY_INV, _invert_true);
+#define GPIO_FRSKY_INV (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12)
+#define INVERT_FRSKY(_invert_true) px4_arch_gpiowrite(GPIO_FRSKY_INV, _invert_true);
 
 /* Power switch controls */
-#define SPEKTRUM_POWER(_on_true)      do { } while (0)
+#define SPEKTRUM_POWER(_on_true) \
+	do {                     \
+	} while (0)
 
 /*
  * MindPXv2 has one RC_IN
@@ -131,22 +133,21 @@
  * The FMU can drive GPIO PPM_IN as an output
  */
 
-#define GPIO_PPM_IN_AS_OUT            (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN6)
-#define SPEKTRUM_RX_AS_GPIO_OUTPUT()  px4_arch_configgpio(GPIO_PPM_IN_AS_OUT)
-#define SPEKTRUM_RX_AS_UART()         px4_arch_configgpio(GPIO_USART1_RX)
-#define SPEKTRUM_OUT(_one_true)       px4_arch_gpiowrite(GPIO_PPM_IN_AS_OUT, (_one_true))
+#define GPIO_PPM_IN_AS_OUT (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN6)
+#define SPEKTRUM_RX_AS_GPIO_OUTPUT() px4_arch_configgpio(GPIO_PPM_IN_AS_OUT)
+#define SPEKTRUM_RX_AS_UART() px4_arch_configgpio(GPIO_USART1_RX)
+#define SPEKTRUM_OUT(_one_true) px4_arch_gpiowrite(GPIO_PPM_IN_AS_OUT, (_one_true))
 
 /* By Providing BOARD_ADC_USB_CONNECTED (using the px4_arch abstraction)
  * this board support the ADC system_power interface, and therefore
  * provides the true logic GPIO BOARD_ADC_xxxx macros.
  */
 #define BOARD_ADC_USB_CONNECTED (px4_arch_gpioread(GPIO_OTGFS_VBUS))
-#define BOARD_ADC_BRICK_VALID   (1)
-#define BOARD_ADC_SERVO_VALID   (1)
-#define BOARD_ADC_PERIPH_5V_OC  (0)
+#define BOARD_ADC_BRICK_VALID (1)
+#define BOARD_ADC_SERVO_VALID (1)
+#define BOARD_ADC_PERIPH_5V_OC (0)
 #define BOARD_ADC_HIPOWER_5V_OC (0)
 
-
 /* This board provides a DMA pool and APIs */
 #define BOARD_DMA_ALLOC_POOL_SIZE 5120
 
@@ -182,10 +183,8 @@ extern void stm32_spiinitialize(void);
 
 extern void stm32_usbinitialize(void);
 
-
 #define board_peripheral_reset(ms)
 
-
 #include <px4_platform_common/board_common.h>
 
 #endif /* __ASSEMBLY__ */

boards/airmind/mindpx-v2/src/can.c

@@ -41,20 +41,17 @@
  * Included Files
  ************************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <errno.h>
+#include <nuttx/can/can.h>
 #include <px4_platform_common/px4_config.h>
 
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/can/can.h>
-#include <arch/board/board.h>
-
-#include "chip.h"
 #include "arm_arch.h"
-
+#include "board_config.h"
+#include "chip.h"
 #include "stm32.h"
 #include "stm32_can.h"
-#include "board_config.h"
 
 #ifdef CONFIG_CAN
 
@@ -64,14 +61,14 @@
 /* Configuration ********************************************************************/
 
 #if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
-#  warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
-#  undef CONFIG_STM32_CAN2
+#warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
+#undef CONFIG_STM32_CAN2
 #endif
 
 #ifdef CONFIG_STM32_CAN1
-#  define CAN_PORT 1
+#define CAN_PORT 1
 #else
-#  define CAN_PORT 2
+#define CAN_PORT 2
 #endif
 
 /************************************************************************************
@@ -91,8 +88,7 @@ int can_devinit(void);
  *
  ************************************************************************************/
 
-int can_devinit(void)
-{
+int can_devinit(void) {
 	static bool initialized = false;
 	struct can_dev_s *can;
 	int ret;

boards/airmind/mindpx-v2/src/i2c.cpp

@@ -37,4 +37,3 @@ constexpr px4_i2c_bus_t px4_i2c_buses[I2C_BUS_MAX_BUS_ITEMS] = {
 	initI2CBusInternal(1),
 	initI2CBusExternal(2),
 };
-

boards/airmind/mindpx-v2/src/init.c

@@ -45,37 +45,32 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <drivers/drv_board_led.h>
+#include <drivers/drv_hrt.h>
+#include <drivers/drv_pwm_output.h>
+#include <errno.h>
+#include <nuttx/analog/adc.h>
+#include <nuttx/board.h>
+#include <nuttx/i2c/i2c_master.h>
+#include <nuttx/mm/gran.h>
+#include <nuttx/mmcsd.h>
+#include <nuttx/sdio.h>
+#include <nuttx/spi/spi.h>
+#include <px4_arch/io_timer.h>
+#include <px4_platform/board_dma_alloc.h>
+#include <px4_platform_common/init.h>
 #include <px4_platform_common/px4_config.h>
 #include <px4_platform_common/tasks.h>
-
 #include <stdbool.h>
 #include <stdio.h>
+#include <stm32.h>
+#include <stm32_uart.h>
 #include <string.h>
-#include <debug.h>
-#include <errno.h>
 #include <syslog.h>
 
-#include <nuttx/board.h>
-#include <nuttx/spi/spi.h>
-#include <nuttx/i2c/i2c_master.h>
-#include <nuttx/sdio.h>
-#include <nuttx/mmcsd.h>
-#include <nuttx/analog/adc.h>
-#include <nuttx/mm/gran.h>
-
-#include <stm32.h>
 #include "board_config.h"
-#include <stm32_uart.h>
-
-#include <arch/board/board.h>
-
-#include <drivers/drv_hrt.h>
-#include <drivers/drv_board_led.h>
-
-#include <px4_platform_common/init.h>
-#include <px4_platform/board_dma_alloc.h>
-#include <drivers/drv_pwm_output.h>
-#include <px4_arch/io_timer.h>
 
 /****************************************************************************
  * Pre-Processor Definitions
@@ -105,8 +100,7 @@ __END_DECLS
  *          0 if just resetting
  *
  ************************************************************************************/
-__EXPORT void board_on_reset(int status)
-{
+__EXPORT void board_on_reset(int status) {
 	/* configure the GPIO pins to outputs and keep them low */
 	for (int i = 0; i < DIRECT_PWM_OUTPUT_CHANNELS; ++i) {
 		px4_arch_configgpio(io_timer_channel_get_gpio_output(i));
@@ -135,9 +129,7 @@ __EXPORT void board_on_reset(int status)
  *
  ************************************************************************************/
 
-__EXPORT void
-stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	// Reset all PWM to Low outputs.
 
 	board_on_reset(-1);
@@ -148,13 +140,13 @@ stm32_boardinitialize(void)
 
 	/* configure ADC pins */
 
-	stm32_configgpio(GPIO_ADC1_IN4);	/* VDD_5V_SENS */
-	stm32_configgpio(GPIO_ADC1_IN10);	/* BATT_CURRENT_SENS */
-	stm32_configgpio(GPIO_ADC1_IN12);	/* BATT_VOLTAGE_SENS */
-	stm32_configgpio(GPIO_ADC1_IN11);	/* RSSI analog in */
-	stm32_configgpio(GPIO_ADC1_IN13);	/* FMU_AUX_ADC_1 */
-	stm32_configgpio(GPIO_ADC1_IN14);	/* FMU_AUX_ADC_2 */
-	stm32_configgpio(GPIO_ADC1_IN15);	/* PRESSURE_SENS */
+	stm32_configgpio(GPIO_ADC1_IN4);  /* VDD_5V_SENS */
+	stm32_configgpio(GPIO_ADC1_IN10); /* BATT_CURRENT_SENS */
+	stm32_configgpio(GPIO_ADC1_IN12); /* BATT_VOLTAGE_SENS */
+	stm32_configgpio(GPIO_ADC1_IN11); /* RSSI analog in */
+	stm32_configgpio(GPIO_ADC1_IN13); /* FMU_AUX_ADC_1 */
+	stm32_configgpio(GPIO_ADC1_IN14); /* FMU_AUX_ADC_2 */
+	stm32_configgpio(GPIO_ADC1_IN15); /* PRESSURE_SENS */
 
 	/* configure power supply control/sense pins */
 
@@ -175,7 +167,6 @@ stm32_boardinitialize(void)
 
 	stm32_configgpio(GPIO_I2C1_SCL);
 	stm32_configgpio(GPIO_I2C1_SDA);
-
 }
 
 /****************************************************************************
@@ -208,8 +199,7 @@ static struct spi_dev_s *spi2;
 static struct spi_dev_s *spi4;
 static struct sdio_dev_s *sdio;
 
-__EXPORT int board_app_initialize(uintptr_t arg)
-{
+__EXPORT int board_app_initialize(uintptr_t arg) {
 	px4_platform_init();
 
 	/* configure the DMA allocator */
@@ -263,14 +253,12 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 	SPI_SETFREQUENCY(spi1, 24 * 1000 * 1000);
 	SPI_SETBITS(spi1, 8);
 
-
 	spi2 = px4_spibus_initialize(2);
 
 	/* Default SPI2 to 10MHz and de-assert the known chip selects. */
 	SPI_SETFREQUENCY(spi2, 10000000);
 	SPI_SETBITS(spi2, 8);
 
-
 #ifdef CONFIG_MMCSD
 	/* First, get an instance of the SDIO interface */
 

boards/airmind/mindpx-v2/src/led.c

@@ -37,14 +37,12 @@
  * PX4FMU LED backend.
  */
 
+#include <arch/board/board.h>
 #include <px4_platform_common/px4_config.h>
-
 #include <stdbool.h>
 
-#include "stm32.h"
 #include "board_config.h"
-
-#include <arch/board/board.h>
+#include "stm32.h"
 
 /*
  * Ideally we'd be able to get these from arm_internal.h,
@@ -60,31 +58,27 @@ extern void led_off(int led);
 extern void led_toggle(int led);
 __END_DECLS
 
-__EXPORT void led_init()
-{
+__EXPORT void led_init() {
 	/* Configure LED1 GPIO for output */
 
 	stm32_configgpio(GPIO_LED1);
 }
 
-__EXPORT void led_on(int led)
-{
+__EXPORT void led_on(int led) {
 	if (led == 1) {
 		/* Pull down to switch on */
 		stm32_gpiowrite(GPIO_LED1, false);
 	}
 }
 
-__EXPORT void led_off(int led)
-{
+__EXPORT void led_off(int led) {
 	if (led == 1) {
 		/* Pull up to switch off */
 		stm32_gpiowrite(GPIO_LED1, true);
 	}
 }
 
-__EXPORT void led_toggle(int led)
-{
+__EXPORT void led_toggle(int led) {
 	if (led == 1) {
 		if (stm32_gpioread(GPIO_LED1)) {
 			stm32_gpiowrite(GPIO_LED1, false);

boards/airmind/mindpx-v2/src/spi.cpp

@@ -31,24 +31,30 @@
  *
  ****************************************************************************/
 
-#include <px4_arch/spi_hw_description.h>
 #include <drivers/drv_sensor.h>
 #include <nuttx/spi/spi.h>
+#include <px4_arch/spi_hw_description.h>
 
 constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
-	initSPIBus(SPI::Bus::SPI1, {
-		initSPIDevice(SPIDEV_FLASH(0), SPI::CS{GPIO::PortE, GPIO::Pin12}),
-	}),
-	initSPIBusExternal(SPI::Bus::SPI2, {
-		initSPIConfigExternal(SPI::CS{GPIO::PortD, GPIO::Pin7}),
-	}),
-	initSPIBus(SPI::Bus::SPI4, {
-		initSPIDevice(DRV_GYR_DEVTYPE_L3GD20, SPI::CS{GPIO::PortB, GPIO::Pin2}, SPI::DRDY{GPIO::PortE, GPIO::Pin4}),
-		initSPIDevice(DRV_IMU_DEVTYPE_LSM303D, SPI::CS{GPIO::PortD, GPIO::Pin11}),
-		initSPIDevice(DRV_BARO_DEVTYPE_MS5611, SPI::CS{GPIO::PortC, GPIO::Pin15}),
-		initSPIDevice(DRV_IMU_DEVTYPE_MPU6000, SPI::CS{GPIO::PortE, GPIO::Pin3}, SPI::DRDY{GPIO::PortE, GPIO::Pin10}),
-		initSPIDevice(DRV_IMU_DEVTYPE_MPU6500, SPI::CS{GPIO::PortE, GPIO::Pin3}, SPI::DRDY{GPIO::PortE, GPIO::Pin10}),
-	}),
+	initSPIBus(SPI::Bus::SPI1,
+		   {
+			   initSPIDevice(SPIDEV_FLASH(0), SPI::CS{GPIO::PortE, GPIO::Pin12}),
+		   }),
+	initSPIBusExternal(SPI::Bus::SPI2,
+			   {
+				   initSPIConfigExternal(SPI::CS{GPIO::PortD, GPIO::Pin7}),
+			   }),
+	initSPIBus(SPI::Bus::SPI4,
+		   {
+			   initSPIDevice(DRV_GYR_DEVTYPE_L3GD20, SPI::CS{GPIO::PortB, GPIO::Pin2},
+					 SPI::DRDY{GPIO::PortE, GPIO::Pin4}),
+			   initSPIDevice(DRV_IMU_DEVTYPE_LSM303D, SPI::CS{GPIO::PortD, GPIO::Pin11}),
+			   initSPIDevice(DRV_BARO_DEVTYPE_MS5611, SPI::CS{GPIO::PortC, GPIO::Pin15}),
+			   initSPIDevice(DRV_IMU_DEVTYPE_MPU6000, SPI::CS{GPIO::PortE, GPIO::Pin3},
+					 SPI::DRDY{GPIO::PortE, GPIO::Pin10}),
+			   initSPIDevice(DRV_IMU_DEVTYPE_MPU6500, SPI::CS{GPIO::PortE, GPIO::Pin3},
+					 SPI::DRDY{GPIO::PortE, GPIO::Pin10}),
+		   }),
 };
 
 static constexpr bool unused = validateSPIConfig(px4_spi_buses);

boards/airmind/mindpx-v2/src/usb.c

@@ -41,18 +41,16 @@
  * Included Files
  ************************************************************************************/
 
-#include <px4_platform_common/px4_config.h>
-
-#include <sys/types.h>
-#include <stdint.h>
-#include <stdbool.h>
+#include <arm_arch.h>
 #include <debug.h>
-
 #include <nuttx/usb/usbdev.h>
 #include <nuttx/usb/usbdev_trace.h>
-
-#include <arm_arch.h>
+#include <px4_platform_common/px4_config.h>
+#include <stdbool.h>
+#include <stdint.h>
 #include <stm32.h>
+#include <sys/types.h>
+
 #include "board_config.h"
 
 /************************************************************************************
@@ -75,8 +73,7 @@
  *
  ************************************************************************************/
 
-__EXPORT void stm32_usbinitialize(void)
-{
+__EXPORT void stm32_usbinitialize(void) {
 	/* The OTG FS has an internal soft pull-up */
 
 	/* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */
@@ -101,8 +98,4 @@ __EXPORT void stm32_usbinitialize(void)
  *
  ************************************************************************************/
 
-__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
-{
-	uinfo("resume: %d\n", resume);
-}
-
+__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); }

boards/ark/can-flow/nuttx-config/include/board.h

@@ -40,7 +40,7 @@
 
 #include <nuttx/config.h>
 #ifndef __ASSEMBLY__
-# include <stdint.h>
+#include <stdint.h>
 #endif
 
 #include <stm32.h>
@@ -50,19 +50,19 @@
  * HSE - 8  MHz Crystal
  * LSE - not installed
  */
-#define STM32_BOARD_USEHSE      1
-#define STM32_BOARD_XTAL        8000000
-#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_BOARD_USEHSE 1
+#define STM32_BOARD_XTAL 8000000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
 
-#define STM32_HSI_FREQUENCY     16000000ul
-#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
 
 /* Main PLL Configuration */
-#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(384)
-#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_4
-#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(8)
-#define STM32_PLLCFG_PLLR       RCC_PLLCFG_PLLR(2)
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
+#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
 
 #define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
@@ -74,63 +74,63 @@
 #define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
 #define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
 
-#define STM32_SYSCLK_FREQUENCY  96000000ul
+#define STM32_SYSCLK_FREQUENCY 96000000ul
 
 /* AHB clock (HCLK) is SYSCLK (96MHz) */
-#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
-#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
-#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
 
 /* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
-#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2     /* PCLK1 = HCLK / 2 */
-#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
+#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
 
 /* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
-#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
 
 /* APB2 clock (PCLK2) is HCLK (96MHz) */
-#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK */
-#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY)
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
+#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
 
 /* Timers driven from APB2 will be PCLK2 since no prescale division */
-#define STM32_APB2_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM9_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM10_CLKIN  (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM11_CLKIN  (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
 
 /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
-#define BOARD_TIM2_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM3_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM4_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM5_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM6_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM7_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM8_FREQUENCY    (2 * STM32_PCLK2_FREQUENCY)
+#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
 
 /* Alternate function pin selections ************************************************/
 
 /* UARTs */
-#define GPIO_USART2_RX	GPIO_USART2_RX_1
-#define GPIO_USART2_TX	GPIO_USART2_TX_1
+#define GPIO_USART2_RX GPIO_USART2_RX_1
+#define GPIO_USART2_TX GPIO_USART2_TX_1
 
 /* CAN */
-#define GPIO_CAN1_RX	GPIO_CAN1_RX_2
-#define GPIO_CAN1_TX	GPIO_CAN1_TX_2
+#define GPIO_CAN1_RX GPIO_CAN1_RX_2
+#define GPIO_CAN1_TX GPIO_CAN1_TX_2
 
 /* SPI */
-#define GPIO_SPI1_MISO  GPIO_SPI1_MISO_1
-#define GPIO_SPI1_MOSI  GPIO_SPI1_MOSI_1
-#define GPIO_SPI1_SCK   GPIO_SPI1_SCK_1
+#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
+#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
+#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
 
-#define GPIO_SPI2_MISO  GPIO_SPI2_MISO_1 /* PB14 */
-#define GPIO_SPI2_MOSI  GPIO_SPI2_MOSI_1 /* PB15 */
-#define GPIO_SPI2_SCK   GPIO_SPI2_SCK_1  /* PB10 */
+#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
+#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
+#define GPIO_SPI2_SCK GPIO_SPI2_SCK_1   /* PB10 */
 
 #endif /* __ARCH_BOARD_BOARD_H */

boards/ark/can-flow/nuttx-config/include/board_dma_map.h

@@ -35,10 +35,10 @@
 
 // DMA1 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
-#define DMACHAN_SPI2_RX    DMAMAP_SPI2_RX   // DMA1, Stream 3, Channel 0
-#define DMACHAN_SPI2_TX    DMAMAP_SPI2_TX   // DMA1, Stream 4, Channel 0
+#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX  // DMA1, Stream 3, Channel 0
+#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX  // DMA1, Stream 4, Channel 0
 
 //  DMA2 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
-#define DMACHAN_SPI1_RX    DMAMAP_SPI1_RX_2   // DMA2, Stream 2, Channel 3
-#define DMACHAN_SPI1_TX    DMAMAP_SPI1_TX_2   // DMA2, Stream 5, Channel 3
+#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2  // DMA2, Stream 2, Channel 3
+#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_2  // DMA2, Stream 5, Channel 3

boards/ark/can-flow/src/board_config.h

@@ -39,40 +39,45 @@
 
 #pragma once
 
-#include <px4_platform_common/px4_config.h>
 #include <nuttx/compiler.h>
+#include <px4_platform_common/px4_config.h>
 #include <stdint.h>
 
 /* CAN  Silent mode control */
-#define GPIO_CAN1_SILENT_S0   /* PA9  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_CAN1_SILENT_S0 /* PA9  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN9)
 
 /* CAN termination software control */
-#define GPIO_CAN1_TERMINATION /* PB13 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_CAN_TERM                    GPIO_CAN1_TERMINATION
+#define GPIO_CAN1_TERMINATION /* PB13 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
 
 /* Boot config */
-#define GPIO_BOOT_CONFIG      /* PC15 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN15|GPIO_EXTI)
+#define GPIO_BOOT_CONFIG /* PC15 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTC | GPIO_PIN15 | GPIO_EXTI)
 
 /* LEDs are driven with push open drain to support Anode to 5V or 3.3V */
-#define GPIO_nLED_RED          /* PB3  */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN3)
-#define GPIO_nLED_BLUE         /* PA8  */ (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN8)
+#define GPIO_nLED_RED /* PB3  */ \
+	(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN3)
+#define GPIO_nLED_BLUE /* PA8  */ \
+	(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN8)
 
 #define BROADCOM_AFBR_S50_S2PI_SPI_BUS 2
-#define BROADCOM_AFBR_S50_S2PI_CS   /* PB12 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN12)
-#define BROADCOM_AFBR_S50_S2PI_IRQ  /* PB4  */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTB|GPIO_PIN4|GPIO_EXTI)
-#define BROADCOM_AFBR_S50_S2PI_CLK  /* PB10 */  GPIO_SPI2_SCK_1
-#define BROADCOM_AFBR_S50_S2PI_MOSI /* PB15 */  GPIO_SPI2_MOSI_1
-#define BROADCOM_AFBR_S50_S2PI_MISO /* PB14 */  GPIO_SPI2_MISO_1
+#define BROADCOM_AFBR_S50_S2PI_CS /* PB12 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN12)
+#define BROADCOM_AFBR_S50_S2PI_IRQ /* PB4  */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTB | GPIO_PIN4 | GPIO_EXTI)
+#define BROADCOM_AFBR_S50_S2PI_CLK /* PB10 */ GPIO_SPI2_SCK_1
+#define BROADCOM_AFBR_S50_S2PI_MOSI /* PB15 */ GPIO_SPI2_MOSI_1
+#define BROADCOM_AFBR_S50_S2PI_MISO /* PB14 */ GPIO_SPI2_MISO_1
 
-#define BOARD_HAS_CONTROL_STATUS_LEDS      1
-#define BOARD_OVERLOAD_LED     LED_RED
-#define BOARD_ARMED_STATE_LED  LED_BLUE
+#define BOARD_HAS_CONTROL_STATUS_LEDS 1
+#define BOARD_OVERLOAD_LED LED_RED
+#define BOARD_ARMED_STATE_LED LED_BLUE
 
 #define FLASH_BASED_PARAMS
 
 /* High-resolution timer */
-#define HRT_TIMER                    3  /* use timer 3 for the HRT */
-#define HRT_TIMER_CHANNEL            4  /* use capture/compare channel 4 */
+#define HRT_TIMER 3         /* use timer 3 for the HRT */
+#define HRT_TIMER_CHANNEL 4 /* use capture/compare channel 4 */
 
 __BEGIN_DECLS
 

boards/ark/can-flow/src/boot.c

@@ -38,16 +38,15 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <nuttx/board.h>
 #include <px4_config.h>
 #include <stdint.h>
-#include "boot_config.h"
-#include "board.h"
-
-#include <debug.h>
 #include <string.h>
-#include <arch/board/board.h>
 
-#include <nuttx/board.h>
+#include "board.h"
+#include "boot_config.h"
 
 __BEGIN_DECLS
 extern void led_init(void);
@@ -65,8 +64,7 @@ __END_DECLS
  *
  ************************************************************************************/
 
-__EXPORT void stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	putreg32(getreg32(STM32_RCC_APB1ENR) | RCC_APB1ENR_CAN1EN, STM32_RCC_APB1ENR);
 	stm32_configgpio(GPIO_CAN1_RX);
 	stm32_configgpio(GPIO_CAN1_TX);
@@ -80,7 +78,6 @@ __EXPORT void stm32_boardinitialize(void)
 #if defined(OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO)
 	stm32_configgpio(GPIO_GETNODEINFO_JUMPER);
 #endif
-
 }
 
 /************************************************************************************
@@ -92,10 +89,7 @@ __EXPORT void stm32_boardinitialize(void)
  *
  ************************************************************************************/
 
-void board_deinitialize(void)
-{
-	putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR);
-}
+void board_deinitialize(void) { putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR); }
 
 /****************************************************************************
  * Name: board_get_product_name
@@ -114,8 +108,7 @@ void board_deinitialize(void)
  *
  ****************************************************************************/
 
-uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
-{
+uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen) {
 	DEBUGASSERT(maxlen > UAVCAN_STRLEN(HW_UAVCAN_NAME));
 	memcpy(product_name, HW_UAVCAN_NAME, UAVCAN_STRLEN(HW_UAVCAN_NAME));
 	return UAVCAN_STRLEN(HW_UAVCAN_NAME);
@@ -136,14 +129,13 @@ uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
  *
  ****************************************************************************/
 
-size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
-{
+size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version) {
 	memset(hw_version, 0, sizeof(uavcan_HardwareVersion_t));
 
 	hw_version->major = HW_VERSION_MAJOR;
 	hw_version->minor = HW_VERSION_MINOR;
 
-	return board_get_mfguid(*(mfguid_t *) hw_version->unique_id);
+	return board_get_mfguid(*(mfguid_t *)hw_version->unique_id);
 }
 
 /****************************************************************************
@@ -160,8 +152,7 @@ size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
  *   None
  *
  ****************************************************************************/
-void board_indicate(uiindication_t indication)
-{
+void board_indicate(uiindication_t indication) {
 	if (indication == off) {
 		bootloader_led_off(GPIO_nLED_RED);
 		bootloader_led_off(GPIO_nLED_BLUE);
@@ -170,8 +161,8 @@ void board_indicate(uiindication_t indication)
 		bootloader_led_on(GPIO_nLED_RED);
 		bootloader_led_on(GPIO_nLED_BLUE);
 
-	} else if ((indication == fw_update_erase_fail) || (indication == fw_update_invalid_response)
-		   || (indication == fw_update_timeout) || (indication == fw_update_invalid_crc)) {
+	} else if ((indication == fw_update_erase_fail) || (indication == fw_update_invalid_response) ||
+		   (indication == fw_update_timeout) || (indication == fw_update_invalid_crc)) {
 		bootloader_led_on(GPIO_nLED_RED);
 		bootloader_led_off(GPIO_nLED_BLUE);
 

boards/ark/can-flow/src/boot_config.h

@@ -50,13 +50,12 @@
  * todo:make this be pulled in from a targed's build
  * files in nuttx*/
 
+#include <nuttx/compiler.h>
+#include <stdint.h>
+#include <stm32_flash.h>
+
 #include "board_config.h"
 #include "uavcan.h"
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include <stm32_flash.h>
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -64,11 +63,11 @@
 
 #define OPT_PREFERRED_NODE_ID ANY_NODE_ID
 
-//todo:wrap OPT_x in in ifdefs for command line definitions
-#define OPT_TBOOT_MS                    5000
-#define OPT_NODE_STATUS_RATE_MS         800
-#define OPT_NODE_INFO_RATE_MS           50
-#define OPT_BL_NUMBER_TIMERS            7
+// todo:wrap OPT_x in in ifdefs for command line definitions
+#define OPT_TBOOT_MS 5000
+#define OPT_NODE_STATUS_RATE_MS 800
+#define OPT_NODE_INFO_RATE_MS 50
+#define OPT_BL_NUMBER_TIMERS 7
 
 /*
  *  This Option set is set to 1 ensure a provider of firmware has an
@@ -91,34 +90,33 @@
  *   no            0                       1       Not Active
  *
  */
-#define OPT_WAIT_FOR_GETNODEINFO                    0
-#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO        1
+#define OPT_WAIT_FOR_GETNODEINFO 0
+#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
 #define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO_INVERT 0
 
-#define OPT_ENABLE_WD           1
+#define OPT_ENABLE_WD 1
 
-#define OPT_RESTART_TIMEOUT_MS          20000
+#define OPT_RESTART_TIMEOUT_MS 20000
 
 /* Reserved for the Booloader */
-#define OPT_BOOTLOADER_SIZE_IN_K        (1024*64)
+#define OPT_BOOTLOADER_SIZE_IN_K (1024 * 64)
 
 /* Reserved for the application out of the total
  * system flash minus the BOOTLOADER_SIZE_IN_K
  */
-#define OPT_APPLICATION_RESERVER_IN_K    0
+#define OPT_APPLICATION_RESERVER_IN_K 0
 
-#define OPT_APPLICATION_IMAGE_OFFSET    OPT_BOOTLOADER_SIZE_IN_K
-#define OPT_APPLICATION_IMAGE_LENGTH    (FLASH_SIZE-(OPT_BOOTLOADER_SIZE_IN_K+OPT_APPLICATION_RESERVER_IN_K))
+#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
+#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE - (OPT_BOOTLOADER_SIZE_IN_K + OPT_APPLICATION_RESERVER_IN_K))
 
-
-#define FLASH_BASE              STM32_FLASH_BASE
-#define FLASH_SIZE              STM32_FLASH_SIZE
+#define FLASH_BASE STM32_FLASH_BASE
+#define FLASH_SIZE STM32_FLASH_SIZE
 
 #define APPLICATION_LOAD_ADDRESS (FLASH_BASE + OPT_APPLICATION_IMAGE_OFFSET)
-#define APPLICATION_SIZE (FLASH_SIZE-OPT_APPLICATION_IMAGE_OFFSET)
-#define APPLICATION_LAST_8BIT_ADDRRESS  ((uint8_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint8_t)))
-#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint32_t)))
-#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint64_t)))
+#define APPLICATION_SIZE (FLASH_SIZE - OPT_APPLICATION_IMAGE_OFFSET)
+#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint8_t)))
+#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint32_t)))
+#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint64_t)))
 
 /* If this board uses big flash that have large sectors */
 

boards/ark/can-flow/src/can.c

@@ -41,20 +41,17 @@
  * Included Files
  ************************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <errno.h>
+#include <nuttx/can/can.h>
 #include <px4_platform_common/px4_config.h>
 
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/can/can.h>
-#include <arch/board/board.h>
-
-#include "chip.h"
 #include "arm_arch.h"
-
+#include "board_config.h"
+#include "chip.h"
 #include "stm32.h"
 #include "stm32_can.h"
-#include "board_config.h"
 
 #ifdef CONFIG_CAN
 
@@ -64,14 +61,14 @@
 /* Configuration ********************************************************************/
 
 #if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
-#  warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
-#  undef CONFIG_STM32_CAN2
+#warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
+#undef CONFIG_STM32_CAN2
 #endif
 
 #ifdef CONFIG_STM32_CAN1
-#  define CAN_PORT 1
+#define CAN_PORT 1
 #else
-#  define CAN_PORT 2
+#define CAN_PORT 2
 #endif
 
 /************************************************************************************
@@ -92,8 +89,7 @@ int can_devinit(void);
  *
  ************************************************************************************/
 
-int can_devinit(void)
-{
+int can_devinit(void) {
 	static bool initialized = false;
 	struct can_dev_s *can;
 	int ret;

boards/ark/can-flow/src/init.c

@@ -41,34 +41,28 @@
  * subsystems and perform board-specific initialization.
  */
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <drivers/drv_board_led.h>
+#include <drivers/drv_hrt.h>
+#include <drivers/drv_watchdog.h>
+#include <errno.h>
+#include <nuttx/board.h>
+#include <px4_platform_common/init.h>
 #include <px4_platform_common/px4_config.h>
 #include <px4_platform_common/tasks.h>
-
 #include <stdbool.h>
 #include <stdio.h>
-#include <string.h>
-#include <debug.h>
-#include <errno.h>
-#include <syslog.h>
-
-#include <nuttx/board.h>
-
 #include <stm32.h>
-#include "board_config.h"
 #include <stm32_uart.h>
-
-#include <arch/board/board.h>
-
-#include <drivers/drv_hrt.h>
-#include <drivers/drv_board_led.h>
-#include <drivers/drv_watchdog.h>
-
+#include <string.h>
+#include <syslog.h>
 #include <systemlib/px4_macros.h>
 
-#include <px4_platform_common/init.h>
+#include "board_config.h"
 
-# if defined(FLASH_BASED_PARAMS)
-#  include <parameters/flashparams/flashfs.h>
+#if defined(FLASH_BASED_PARAMS)
+#include <parameters/flashparams/flashfs.h>
 #endif
 
 __BEGIN_DECLS
@@ -87,8 +81,7 @@ __END_DECLS
  *
  ************************************************************************************/
 
-__EXPORT void stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	watchdog_init();
 
 	// Configure CAN interface
@@ -127,8 +120,7 @@ __EXPORT void stm32_boardinitialize(void)
  *
  ****************************************************************************/
 
-__EXPORT int board_app_initialize(uintptr_t arg)
-{
+__EXPORT int board_app_initialize(uintptr_t arg) {
 	px4_platform_init();
 
 	// Configure LEDs.
@@ -148,7 +140,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 		syslog(LOG_ERR, "[boot] FAILED to init params in FLASH %d\n", result);
 	}
 
-#endif // FLASH_BASED_PARAMS
+#endif  // FLASH_BASED_PARAMS
 
 	/* initial LED state */
 	drv_led_start();

boards/ark/can-flow/src/led.c

@@ -37,14 +37,12 @@
  * board LED backend.
  */
 
+#include <arch/board/board.h>
 #include <px4_platform_common/px4_config.h>
-
 #include <stdbool.h>
 
-#include "stm32.h"
 #include "board_config.h"
-
-#include <arch/board/board.h>
+#include "stm32.h"
 
 /*
  * Ideally we'd be able to get these from up_internal.h,
@@ -62,54 +60,38 @@ extern void led_off(int led);
 extern void led_toggle(int led);
 __END_DECLS
 
-#  define xlat(p) (p)
+#define xlat(p) (p)
 static uint32_t g_ledmap[] = {
 	GPIO_nLED_BLUE,
 	GPIO_nLED_RED,
 };
 
-__EXPORT void led_init(void)
-{
+__EXPORT void led_init(void) {
 	/* Configure LED GPIOs for output */
 	for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
 		stm32_configgpio(g_ledmap[l]);
 	}
 }
 
-__EXPORT void bootloader_led_on(int led)
-{
+__EXPORT void bootloader_led_on(int led) {
 	/* Pull Down to switch on */
 	stm32_gpiowrite(led, false);
 }
 
-__EXPORT void bootloader_led_off(int led)
-{
+__EXPORT void bootloader_led_off(int led) {
 	/* Pull Up to switch on */
 	stm32_gpiowrite(led, true);
 }
 
-static void phy_set_led(int led, bool state)
-{
+static void phy_set_led(int led, bool state) {
 	/* Pull Down to switch on */
 	stm32_gpiowrite(g_ledmap[led], !state);
 }
 
-static bool phy_get_led(int led)
-{
-	return !stm32_gpioread(g_ledmap[led]);
-}
+static bool phy_get_led(int led) { return !stm32_gpioread(g_ledmap[led]); }
 
-__EXPORT void led_on(int led)
-{
-	phy_set_led(xlat(led), true);
-}
+__EXPORT void led_on(int led) { phy_set_led(xlat(led), true); }
 
-__EXPORT void led_off(int led)
-{
-	phy_set_led(xlat(led), false);
-}
+__EXPORT void led_off(int led) { phy_set_led(xlat(led), false); }
 
-__EXPORT void led_toggle(int led)
-{
-	phy_set_led(xlat(led), !phy_get_led(xlat(led)));
-}
+__EXPORT void led_toggle(int led) { phy_set_led(xlat(led), !phy_get_led(xlat(led))); }

boards/ark/can-flow/src/spi.cpp

@@ -31,20 +31,27 @@
  *
  ****************************************************************************/
 
-#include <px4_arch/spi_hw_description.h>
 #include <drivers/drv_sensor.h>
 #include <nuttx/spi/spi.h>
+#include <px4_arch/spi_hw_description.h>
 
 constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
-	initSPIBus(SPI::Bus::SPI1, {
-		initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::PortA, GPIO::Pin15}, SPI::DRDY{GPIO::PortA, GPIO::Pin10}),
-		initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::PortA, GPIO::Pin4}, SPI::DRDY{GPIO::PortB, GPIO::Pin0}),
-		initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortA, GPIO::Pin4}, SPI::DRDY{GPIO::PortB, GPIO::Pin0}),
-		initSPIDevice(DRV_FLOW_DEVTYPE_PAW3902, SPI::CS{GPIO::PortB, GPIO::Pin5}, SPI::DRDY{GPIO::PortB, GPIO::Pin2}),
-	}),
-	initSPIBus(SPI::Bus::SPI2, {
-		initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortB, GPIO::Pin12}, SPI::DRDY{GPIO::PortB, GPIO::Pin4}),
-	}),
+	initSPIBus(SPI::Bus::SPI1,
+		   {
+			   initSPIDevice(DRV_GYR_DEVTYPE_BMI088, SPI::CS{GPIO::PortA, GPIO::Pin15},
+					 SPI::DRDY{GPIO::PortA, GPIO::Pin10}),
+			   initSPIDevice(DRV_ACC_DEVTYPE_BMI088, SPI::CS{GPIO::PortA, GPIO::Pin4},
+					 SPI::DRDY{GPIO::PortB, GPIO::Pin0}),
+			   initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortA, GPIO::Pin4},
+					 SPI::DRDY{GPIO::PortB, GPIO::Pin0}),
+			   initSPIDevice(DRV_FLOW_DEVTYPE_PAW3902, SPI::CS{GPIO::PortB, GPIO::Pin5},
+					 SPI::DRDY{GPIO::PortB, GPIO::Pin2}),
+		   }),
+	initSPIBus(SPI::Bus::SPI2,
+		   {
+			   initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortB, GPIO::Pin12},
+					 SPI::DRDY{GPIO::PortB, GPIO::Pin4}),
+		   }),
 };
 
 static constexpr bool unused = validateSPIConfig(px4_spi_buses);

boards/ark/can-gps/nuttx-config/include/board.h

@@ -40,7 +40,7 @@
 
 #include <nuttx/config.h>
 #ifndef __ASSEMBLY__
-# include <stdint.h>
+#include <stdint.h>
 #endif
 
 #include <stm32.h>
@@ -50,19 +50,19 @@
  * HSE - 8  MHz Crystal
  * LSE - not installed
  */
-#define STM32_BOARD_USEHSE      1
-#define STM32_BOARD_XTAL        8000000
-#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_BOARD_USEHSE 1
+#define STM32_BOARD_XTAL 8000000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
 
-#define STM32_HSI_FREQUENCY     16000000ul
-#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
 
 /* Main PLL Configuration */
-#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(384)
-#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_4
-#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(8)
-#define STM32_PLLCFG_PLLR       RCC_PLLCFG_PLLR(2)
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
+#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
 
 #define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
@@ -74,79 +74,79 @@
 #define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
 #define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
 
-#define STM32_SYSCLK_FREQUENCY  96000000ul
+#define STM32_SYSCLK_FREQUENCY 96000000ul
 
 /* AHB clock (HCLK) is SYSCLK (96MHz) */
-#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
-#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
-#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
 
 /* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
-#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2     /* PCLK1 = HCLK / 2 */
-#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
+#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
 
 /* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
-#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
 
 /* APB2 clock (PCLK2) is HCLK (96MHz) */
-#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK */
-#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY)
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
+#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
 
 /* Timers driven from APB2 will be PCLK2 since no prescale division */
-#define STM32_APB2_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM9_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM10_CLKIN  (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM11_CLKIN  (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
 
 /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
-#define BOARD_TIM2_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM3_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM4_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM5_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM6_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM7_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM8_FREQUENCY    (2 * STM32_PCLK2_FREQUENCY)
+#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
 
 /* Alternate function pin selections ************************************************/
 
 /* UARTs */
-#define GPIO_USART1_RX	GPIO_USART1_RX_2
-#define GPIO_USART1_TX	GPIO_USART1_TX_3
+#define GPIO_USART1_RX GPIO_USART1_RX_2
+#define GPIO_USART1_TX GPIO_USART1_TX_3
 
-#define GPIO_USART2_RX	GPIO_USART2_RX_1
-#define GPIO_USART2_TX	GPIO_USART2_TX_1
+#define GPIO_USART2_RX GPIO_USART2_RX_1
+#define GPIO_USART2_TX GPIO_USART2_TX_1
 
 /* CAN */
-#define GPIO_CAN1_RX	GPIO_CAN1_RX_1
-#define GPIO_CAN1_TX	GPIO_CAN1_TX_1
+#define GPIO_CAN1_RX GPIO_CAN1_RX_1
+#define GPIO_CAN1_TX GPIO_CAN1_TX_1
 
 /* I2C */
 
 #define GPIO_MCU_I2C1_SCL
 #define GPIO_MCU_I2C1_SDA
 
-#define GPIO_I2C1_SCL	GPIO_I2C1_SCL_1
-#define GPIO_I2C1_SDA	GPIO_I2C1_SDA_1
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
 
-#define GPIO_I2C1_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
-#define GPIO_I2C1_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
 
-#define GPIO_I2C2_SCL	GPIO_I2C2_SCL_1
-#define GPIO_I2C2_SDA	GPIO_I2C2_SDA_4
+#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
+#define GPIO_I2C2_SDA GPIO_I2C2_SDA_4
 
-#define GPIO_I2C2_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
-#define GPIO_I2C2_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
 
 /* SPI */
-#define GPIO_SPI1_MISO  GPIO_SPI1_MISO_1
-#define GPIO_SPI1_MOSI  GPIO_SPI1_MOSI_1
-#define GPIO_SPI1_SCK   GPIO_SPI1_SCK_1
+#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
+#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
+#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
 
 #endif /* __ARCH_BOARD_BOARD_H */

boards/ark/can-gps/nuttx-config/include/board_dma_map.h

@@ -36,8 +36,7 @@
 // DMA1 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
 
-
 //  DMA2 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
-#define DMACHAN_SPI1_RX    DMAMAP_SPI1_RX_2   // DMA2, Stream 2, Channel 3
-#define DMACHAN_SPI1_TX    DMAMAP_SPI1_TX_1   // DMA2, Stream 5, Channel 3
+#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2  // DMA2, Stream 2, Channel 3
+#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1  // DMA2, Stream 5, Channel 3

boards/ark/can-gps/src/board_config.h

@@ -39,77 +39,78 @@
 
 #pragma once
 
-#include <px4_platform_common/px4_config.h>
 #include <nuttx/compiler.h>
+#include <px4_platform_common/px4_config.h>
 #include <stdint.h>
 
 /* BUTTON */
-#define GPIO_BTN_SAFETY       /* PB15 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_BTN_SAFETY /* PB15 */ (GPIO_INPUT | GPIO_PULLDOWN | GPIO_PORTB | GPIO_PIN15)
 
 /* Safety LED */
-#define GPIO_LED_SAFETY       /* PA1  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_LED_SAFETY /* PA1  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN1)
 
 /* Tone alarm output. */
-#define TONE_ALARM_TIMER             2    /* timer 2 */
-#define TONE_ALARM_CHANNEL           1    /* channel 1 */
-#define GPIO_TONE_ALARM_IDLE  /* PA0  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_TONE_ALARM       /* PA0  */ (GPIO_ALT|GPIO_AF1|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
+#define TONE_ALARM_TIMER 2   /* timer 2 */
+#define TONE_ALARM_CHANNEL 1 /* channel 1 */
+#define GPIO_TONE_ALARM_IDLE /* PA0  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_TONE_ALARM /* PA0  */ (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_2MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN0)
 
 /* CAN  Silent mode control */
-#define GPIO_CAN1_SILENT_S0   /* PB12 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_CAN1_SILENT_S0 /* PB12 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN12)
 
 /* CAN termination software control */
-#define GPIO_CAN1_TERMINATION /* PB13 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_CAN_TERM                    GPIO_CAN1_TERMINATION
+#define GPIO_CAN1_TERMINATION /* PB13 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
 
 /* ICM42688p FSYNC */
-#define GPIO_42688P_FSYNC     /* PB8  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_42688P_FSYNC /* PB8  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN8)
 
 /* Boot config */
-#define GPIO_BOOT_CONFIG      /* PC15 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN15|GPIO_EXTI)
+#define GPIO_BOOT_CONFIG /* PC15 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTC | GPIO_PIN15 | GPIO_EXTI)
 
 /* LEDs are driven with open drain to support Anode to 5V or 3.3V */
-#define GPIO_TIM1_CH1         /* PA8  */ (GPIO_TIM1_CH1_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
-#define GPIO_TIM1_CH2         /* PA9  */ (GPIO_TIM1_CH2_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
-#define GPIO_TIM1_CH3         /* PA10 */ (GPIO_TIM1_CH3_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
+#define GPIO_TIM1_CH1 /* PA8  */ (GPIO_TIM1_CH1_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
+#define GPIO_TIM1_CH2 /* PA9  */ (GPIO_TIM1_CH2_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
+#define GPIO_TIM1_CH3 /* PA10 */ (GPIO_TIM1_CH3_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
 
-#define GPIO_I2C1_SCL_RESET   /* PB6  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6)
-#define GPIO_I2C1_SDA_RESET   /* PB7  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_I2C1_SCL_RESET /* PB6  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_I2C1_SDA_RESET /* PB7  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7)
 
-#define GPIO_I2C2_SCL_RESET   /* PB10 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_I2C2_SDA_RESET   /* PB9  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C2_SCL_RESET /* PB10 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_I2C2_SDA_RESET /* PB9  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN9)
 
-#define GPIO_USART1_RX_GPIO	(GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
-#define GPIO_USART1_TX_GPIO	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_USART1_RX_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN3)
+#define GPIO_USART1_TX_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN15)
 
-#define GPIO_USART2_RX_GPIO	(GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_USART2_TX_GPIO	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_USART2_RX_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_USART2_TX_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN2)
 
 #define FLASH_BASED_PARAMS
 
 /* High-resolution timer */
-#define HRT_TIMER                    3  /* use timer 3 for the HRT */
-#define HRT_TIMER_CHANNEL            4  /* use capture/compare channel 4 */
+#define HRT_TIMER 3         /* use timer 3 for the HRT */
+#define HRT_TIMER_CHANNEL 4 /* use capture/compare channel 4 */
 
-#define PX4_GPIO_INIT_LIST { \
-		GPIO_BTN_SAFETY,                  \
-		GPIO_LED_SAFETY,                  \
-		GPIO_I2C1_SCL_RESET,              \
-		GPIO_I2C1_SDA_RESET,              \
-		GPIO_I2C2_SCL_RESET,              \
-		GPIO_I2C2_SDA_RESET,              \
-		GPIO_42688P_FSYNC,                \
-		GPIO_BOOT_CONFIG,                 \
-		GPIO_CAN1_TX,                     \
-		GPIO_CAN1_RX,                     \
-		GPIO_CAN1_SILENT_S0,              \
-		GPIO_CAN1_TERMINATION,            \
+#define PX4_GPIO_INIT_LIST                                                                                       \
+	{                                                                                                        \
+		GPIO_BTN_SAFETY, GPIO_LED_SAFETY, GPIO_I2C1_SCL_RESET, GPIO_I2C1_SDA_RESET, GPIO_I2C2_SCL_RESET, \
+			GPIO_I2C2_SDA_RESET, GPIO_42688P_FSYNC, GPIO_BOOT_CONFIG, GPIO_CAN1_TX, GPIO_CAN1_RX,    \
+			GPIO_CAN1_SILENT_S0, GPIO_CAN1_TERMINATION,                                              \
 	}
 
 __BEGIN_DECLS
 
-#define BOARD_HAS_N_S_RGB_LED       1
-#define BOARD_MAX_LEDS              BOARD_HAS_N_S_RGB_LED
+#define BOARD_HAS_N_S_RGB_LED 1
+#define BOARD_MAX_LEDS BOARD_HAS_N_S_RGB_LED
 
 #ifndef __ASSEMBLY__
 

boards/ark/can-gps/src/boot.c

@@ -38,16 +38,15 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <nuttx/board.h>
 #include <px4_config.h>
 #include <stdint.h>
-#include "boot_config.h"
-#include "board.h"
-
-#include <debug.h>
 #include <string.h>
-#include <arch/board/board.h>
 
-#include <nuttx/board.h>
+#include "board.h"
+#include "boot_config.h"
 #include "led.h"
 
 /************************************************************************************
@@ -60,8 +59,7 @@
  *
  ************************************************************************************/
 
-__EXPORT void stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	putreg32(getreg32(STM32_RCC_APB1ENR) | RCC_APB1ENR_CAN1EN, STM32_RCC_APB1ENR);
 	stm32_configgpio(GPIO_CAN1_RX);
 	stm32_configgpio(GPIO_CAN1_TX);
@@ -73,7 +71,6 @@ __EXPORT void stm32_boardinitialize(void)
 #if defined(OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO)
 	stm32_configgpio(GPIO_GETNODEINFO_JUMPER);
 #endif
-
 }
 
 /************************************************************************************
@@ -85,10 +82,7 @@ __EXPORT void stm32_boardinitialize(void)
  *
  ************************************************************************************/
 
-void board_deinitialize(void)
-{
-	putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR);
-}
+void board_deinitialize(void) { putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR); }
 
 /****************************************************************************
  * Name: board_get_product_name
@@ -107,8 +101,7 @@ void board_deinitialize(void)
  *
  ****************************************************************************/
 
-uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
-{
+uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen) {
 	DEBUGASSERT(maxlen > UAVCAN_STRLEN(HW_UAVCAN_NAME));
 	memcpy(product_name, HW_UAVCAN_NAME, UAVCAN_STRLEN(HW_UAVCAN_NAME));
 	return UAVCAN_STRLEN(HW_UAVCAN_NAME);
@@ -129,14 +122,13 @@ uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
  *
  ****************************************************************************/
 
-size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
-{
+size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version) {
 	memset(hw_version, 0, sizeof(uavcan_HardwareVersion_t));
 
 	hw_version->major = HW_VERSION_MAJOR;
 	hw_version->minor = HW_VERSION_MINOR;
 
-	return board_get_mfguid(*(mfguid_t *) hw_version->unique_id);
+	return board_get_mfguid(*(mfguid_t *)hw_version->unique_id);
 }
 
 /****************************************************************************
@@ -153,7 +145,8 @@ size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
  *   None
  *
  ****************************************************************************/
-#define led(n, code, r , g , b, h) {.red = (r),.green = (g), .blue = (b),.hz = (h)}
+#define led(n, code, r, g, b, h) \
+	{ .red = (r), .green = (g), .blue = (b), .hz = (h) }
 
 typedef begin_packed_struct struct led_t {
 	uint8_t red;
@@ -162,27 +155,23 @@ typedef begin_packed_struct struct led_t {
 	uint8_t hz;
 } end_packed_struct led_t;
 
-static const  led_t i2l[] = {
+static const led_t i2l[] = {
 
-	led(0, off,                             0,     0,     0,     0),
-	led(1, reset,                          128,   128,   128,   30),
-	led(2, autobaud_start,                  0,   128,     0,     1),
-	led(3, autobaud_end,                    0,   128,     0,     2),
-	led(4, allocation_start,                0,     0,    64,     2),
-	led(5, allocation_end,                  0,   128,    64,     3),
-	led(6, fw_update_start,                32,   128,    64,     3),
-	led(7, fw_update_erase_fail,           32,   128,    32,     3),
-	led(8, fw_update_invalid_response,     64,     0,     0,     1),
-	led(9, fw_update_timeout,              64,     0,     0,     2),
-	led(a, fw_update_invalid_crc,          64,     0,     0,     4),
-	led(b, jump_to_app,                     0,   128,     0,    10),
+	led(0, off, 0, 0, 0, 0),
+	led(1, reset, 128, 128, 128, 30),
+	led(2, autobaud_start, 0, 128, 0, 1),
+	led(3, autobaud_end, 0, 128, 0, 2),
+	led(4, allocation_start, 0, 0, 64, 2),
+	led(5, allocation_end, 0, 128, 64, 3),
+	led(6, fw_update_start, 32, 128, 64, 3),
+	led(7, fw_update_erase_fail, 32, 128, 32, 3),
+	led(8, fw_update_invalid_response, 64, 0, 0, 1),
+	led(9, fw_update_timeout, 64, 0, 0, 2),
+	led(a, fw_update_invalid_crc, 64, 0, 0, 4),
+	led(b, jump_to_app, 0, 128, 0, 10),
 
 };
 
-void board_indicate(uiindication_t indication)
-{
-	rgb_led(i2l[indication].red,
-		i2l[indication].green,
-		i2l[indication].blue,
-		i2l[indication].hz);
+void board_indicate(uiindication_t indication) {
+	rgb_led(i2l[indication].red, i2l[indication].green, i2l[indication].blue, i2l[indication].hz);
 }

boards/ark/can-gps/src/boot_config.h

@@ -50,13 +50,12 @@
  * todo:make this be pulled in from a targed's build
  * files in nuttx*/
 
+#include <nuttx/compiler.h>
+#include <stdint.h>
+#include <stm32_flash.h>
+
 #include "board_config.h"
 #include "uavcan.h"
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include <stm32_flash.h>
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -64,11 +63,11 @@
 
 #define OPT_PREFERRED_NODE_ID ANY_NODE_ID
 
-//todo:wrap OPT_x in in ifdefs for command line definitions
-#define OPT_TBOOT_MS                    5000
-#define OPT_NODE_STATUS_RATE_MS         800
-#define OPT_NODE_INFO_RATE_MS           50
-#define OPT_BL_NUMBER_TIMERS            7
+// todo:wrap OPT_x in in ifdefs for command line definitions
+#define OPT_TBOOT_MS 5000
+#define OPT_NODE_STATUS_RATE_MS 800
+#define OPT_NODE_INFO_RATE_MS 50
+#define OPT_BL_NUMBER_TIMERS 7
 
 /*
  *  This Option set is set to 1 ensure a provider of firmware has an
@@ -91,34 +90,33 @@
  *   no            0                       1       Not Active
  *
  */
-#define OPT_WAIT_FOR_GETNODEINFO                    0
-#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO        1
+#define OPT_WAIT_FOR_GETNODEINFO 0
+#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
 #define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO_INVERT 0
 
-#define OPT_ENABLE_WD           1
+#define OPT_ENABLE_WD 1
 
-#define OPT_RESTART_TIMEOUT_MS          20000
+#define OPT_RESTART_TIMEOUT_MS 20000
 
 /* Reserved for the Booloader */
-#define OPT_BOOTLOADER_SIZE_IN_K        (1024*64)
+#define OPT_BOOTLOADER_SIZE_IN_K (1024 * 64)
 
 /* Reserved for the application out of the total
  * system flash minus the BOOTLOADER_SIZE_IN_K
  */
-#define OPT_APPLICATION_RESERVER_IN_K    0
+#define OPT_APPLICATION_RESERVER_IN_K 0
 
-#define OPT_APPLICATION_IMAGE_OFFSET    OPT_BOOTLOADER_SIZE_IN_K
-#define OPT_APPLICATION_IMAGE_LENGTH    (FLASH_SIZE-(OPT_BOOTLOADER_SIZE_IN_K+OPT_APPLICATION_RESERVER_IN_K))
+#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
+#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE - (OPT_BOOTLOADER_SIZE_IN_K + OPT_APPLICATION_RESERVER_IN_K))
 
-
-#define FLASH_BASE              STM32_FLASH_BASE
-#define FLASH_SIZE              STM32_FLASH_SIZE
+#define FLASH_BASE STM32_FLASH_BASE
+#define FLASH_SIZE STM32_FLASH_SIZE
 
 #define APPLICATION_LOAD_ADDRESS (FLASH_BASE + OPT_APPLICATION_IMAGE_OFFSET)
-#define APPLICATION_SIZE (FLASH_SIZE-OPT_APPLICATION_IMAGE_OFFSET)
-#define APPLICATION_LAST_8BIT_ADDRRESS  ((uint8_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint8_t)))
-#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint32_t)))
-#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint64_t)))
+#define APPLICATION_SIZE (FLASH_SIZE - OPT_APPLICATION_IMAGE_OFFSET)
+#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint8_t)))
+#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint32_t)))
+#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint64_t)))
 
 /* If this board uses big flash that have large sectors */
 

boards/ark/can-gps/src/can.c

@@ -41,20 +41,17 @@
  * Included Files
  ************************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <errno.h>
+#include <nuttx/can/can.h>
 #include <px4_platform_common/px4_config.h>
 
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/can/can.h>
-#include <arch/board/board.h>
-
-#include "chip.h"
 #include "arm_arch.h"
-
+#include "board_config.h"
+#include "chip.h"
 #include "stm32.h"
 #include "stm32_can.h"
-#include "board_config.h"
 
 #ifdef CONFIG_CAN
 
@@ -64,14 +61,14 @@
 /* Configuration ********************************************************************/
 
 #if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
-#  warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
-#  undef CONFIG_STM32_CAN2
+#warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
+#undef CONFIG_STM32_CAN2
 #endif
 
 #ifdef CONFIG_STM32_CAN1
-#  define CAN_PORT 1
+#define CAN_PORT 1
 #else
-#  define CAN_PORT 2
+#define CAN_PORT 2
 #endif
 
 /************************************************************************************
@@ -92,8 +89,7 @@ int can_devinit(void);
  *
  ************************************************************************************/
 
-int can_devinit(void)
-{
+int can_devinit(void) {
 	static bool initialized = false;
 	struct can_dev_s *can;
 	int ret;

boards/ark/can-gps/src/init.c

@@ -41,36 +41,30 @@
  * subsystems and perform board-specific initialization.
  */
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <drivers/drv_board_led.h>
+#include <drivers/drv_hrt.h>
+#include <drivers/drv_watchdog.h>
+#include <errno.h>
+#include <nuttx/board.h>
+#include <px4_platform/gpio.h>
+#include <px4_platform_common/init.h>
 #include <px4_platform_common/px4_config.h>
 #include <px4_platform_common/tasks.h>
-
 #include <stdbool.h>
 #include <stdio.h>
-#include <string.h>
-#include <debug.h>
-#include <errno.h>
-#include <syslog.h>
-
-#include <nuttx/board.h>
-
 #include <stm32.h>
-#include "board_config.h"
-#include "led.h"
 #include <stm32_uart.h>
-
-#include <arch/board/board.h>
-
-#include <drivers/drv_hrt.h>
-#include <drivers/drv_board_led.h>
-#include <drivers/drv_watchdog.h>
-
+#include <string.h>
+#include <syslog.h>
 #include <systemlib/px4_macros.h>
 
-#include <px4_platform_common/init.h>
-#include <px4_platform/gpio.h>
+#include "board_config.h"
+#include "led.h"
 
-# if defined(FLASH_BASED_PARAMS)
-#  include <parameters/flashparams/flashfs.h>
+#if defined(FLASH_BASED_PARAMS)
+#include <parameters/flashparams/flashfs.h>
 #endif
 
 /************************************************************************************
@@ -83,8 +77,7 @@
  *
  ************************************************************************************/
 
-__EXPORT void stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	watchdog_init();
 
 	/* configure pins */
@@ -135,8 +128,7 @@ __EXPORT void stm32_boardinitialize(void)
  *
  ****************************************************************************/
 
-__EXPORT int board_app_initialize(uintptr_t arg)
-{
+__EXPORT int board_app_initialize(uintptr_t arg) {
 	px4_platform_init();
 
 #if defined(FLASH_BASED_PARAMS)
@@ -153,7 +145,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 		syslog(LOG_ERR, "[boot] FAILED to init params in FLASH %d\n", result);
 	}
 
-#endif // FLASH_BASED_PARAMS
+#endif  // FLASH_BASED_PARAMS
 
 	/* Configure the HW based on the manifest */
 

boards/ark/can-gps/src/led.c

@@ -37,30 +37,26 @@
  * LED backend.
  */
 
-#include <px4_platform_common/px4_config.h>
-
-#include <stdbool.h>
-
-#include "chip.h"
-#include "stm32_gpio.h"
-#include "board_config.h"
-
-#include <nuttx/board.h>
-#include <arch/board/board.h>
-
 #include "led.h"
 
-#define TMR_BASE        STM32_TIM1_BASE
-#define TMR_FREQUENCY   STM32_APB2_TIM1_CLKIN
-#define TMR_REG(o)      (TMR_BASE+(o))
+#include <arch/board/board.h>
+#include <nuttx/board.h>
+#include <px4_platform_common/px4_config.h>
+#include <stdbool.h>
 
-void rgb_led(int r, int g, int b, int freqs)
-{
+#include "board_config.h"
+#include "chip.h"
+#include "stm32_gpio.h"
 
+#define TMR_BASE STM32_TIM1_BASE
+#define TMR_FREQUENCY STM32_APB2_TIM1_CLKIN
+#define TMR_REG(o) (TMR_BASE + (o))
+
+void rgb_led(int r, int g, int b, int freqs) {
 	long fosc = TMR_FREQUENCY;
 	long prescale = 2048;
 	long p1s = fosc / prescale;
-	long p0p5s  = p1s / 2;
+	long p0p5s = p1s / 2;
 	uint16_t val;
 	static bool once = 0;
 
@@ -84,14 +80,14 @@ void rgb_led(int r, int g, int b, int freqs)
 
 		putreg16(ATIM_CR1_CEN | ATIM_CR1_ARPE, TMR_REG(STM32_BTIM_CR1_OFFSET));
 
-
 		putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | ATIM_CCMR1_OC1PE |
-			 (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE, TMR_REG(STM32_GTIM_CCMR1_OFFSET));
-		putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE, TMR_REG(STM32_GTIM_CCMR2_OFFSET));
-		putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P |
-			 ATIM_CCER_CC2E | ATIM_CCER_CC2P |
-			 ATIM_CCER_CC1E | ATIM_CCER_CC1P, TMR_REG(STM32_GTIM_CCER_OFFSET));
-
+				 (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE,
+			 TMR_REG(STM32_GTIM_CCMR1_OFFSET));
+		putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE,
+			 TMR_REG(STM32_GTIM_CCMR2_OFFSET));
+		putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P | ATIM_CCER_CC2E | ATIM_CCER_CC2P | ATIM_CCER_CC1E |
+				 ATIM_CCER_CC1P,
+			 TMR_REG(STM32_GTIM_CCER_OFFSET));
 
 		stm32_configgpio(GPIO_TIM1_CH1);
 		stm32_configgpio(GPIO_TIM1_CH2);
@@ -101,10 +97,10 @@ void rgb_led(int r, int g, int b, int freqs)
 		putreg16(ATIM_BDTR_MOE, (TMR_REG(STM32_ATIM_BDTR_OFFSET)));
 	}
 
-	long p  = freqs == 0 ? p1s : p1s / freqs;
+	long p = freqs == 0 ? p1s : p1s / freqs;
 	putreg32(p, TMR_REG(STM32_BTIM_ARR_OFFSET));
 
-	p  = freqs == 0 ? p1s + 1 : p0p5s / freqs;
+	p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
 
 	putreg32((r * p) / 255, TMR_REG(STM32_GTIM_CCR1_OFFSET));
 	putreg32((g * p) / 255, TMR_REG(STM32_GTIM_CCR2_OFFSET));
@@ -120,5 +116,4 @@ void rgb_led(int r, int g, int b, int freqs)
 	}
 
 	putreg16(val, TMR_REG(STM32_BTIM_CR1_OFFSET));
-
 }

boards/ark/can-gps/src/spi.cpp

@@ -31,14 +31,16 @@
  *
  ****************************************************************************/
 
-#include <px4_arch/spi_hw_description.h>
 #include <drivers/drv_sensor.h>
 #include <nuttx/spi/spi.h>
+#include <px4_arch/spi_hw_description.h>
 
 constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
-	initSPIBus(SPI::Bus::SPI1, {
-		initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortB, GPIO::Pin0}, SPI::DRDY{GPIO::PortB, GPIO::Pin1}),
-	}),
+	initSPIBus(SPI::Bus::SPI1,
+		   {
+			   initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortB, GPIO::Pin0},
+					 SPI::DRDY{GPIO::PortB, GPIO::Pin1}),
+		   }),
 };
 
 static constexpr bool unused = validateSPIConfig(px4_spi_buses);

boards/ark/can-rtk-gps/nuttx-config/include/board.h

@@ -40,7 +40,7 @@
 
 #include <nuttx/config.h>
 #ifndef __ASSEMBLY__
-# include <stdint.h>
+#include <stdint.h>
 #endif
 
 #include <stm32.h>
@@ -50,19 +50,19 @@
  * HSE - 8  MHz Crystal
  * LSE - not installed
  */
-#define STM32_BOARD_USEHSE      1
-#define STM32_BOARD_XTAL        8000000
-#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_BOARD_USEHSE 1
+#define STM32_BOARD_XTAL 8000000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
 
-#define STM32_HSI_FREQUENCY     16000000ul
-#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
 
 /* Main PLL Configuration */
-#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(384)
-#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_4
-#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(8)
-#define STM32_PLLCFG_PLLR       RCC_PLLCFG_PLLR(2)
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
+#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
 
 #define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
@@ -74,79 +74,79 @@
 #define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
 #define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
 
-#define STM32_SYSCLK_FREQUENCY  96000000ul
+#define STM32_SYSCLK_FREQUENCY 96000000ul
 
 /* AHB clock (HCLK) is SYSCLK (96MHz) */
-#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
-#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
-#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
 
 /* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
-#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2     /* PCLK1 = HCLK / 2 */
-#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
+#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
 
 /* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
-#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
 
 /* APB2 clock (PCLK2) is HCLK (96MHz) */
-#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK */
-#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY)
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
+#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
 
 /* Timers driven from APB2 will be PCLK2 since no prescale division */
-#define STM32_APB2_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM9_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM10_CLKIN  (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM11_CLKIN  (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
 
 /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
-#define BOARD_TIM2_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM3_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM4_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM5_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM6_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM7_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM8_FREQUENCY    (2 * STM32_PCLK2_FREQUENCY)
+#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
 
 /* Alternate function pin selections ************************************************/
 
 /* UARTs */
-#define GPIO_USART1_RX	GPIO_USART1_RX_2
-#define GPIO_USART1_TX	GPIO_USART1_TX_3
+#define GPIO_USART1_RX GPIO_USART1_RX_2
+#define GPIO_USART1_TX GPIO_USART1_TX_3
 
-#define GPIO_USART2_RX	GPIO_USART2_RX_1
-#define GPIO_USART2_TX	GPIO_USART2_TX_1
+#define GPIO_USART2_RX GPIO_USART2_RX_1
+#define GPIO_USART2_TX GPIO_USART2_TX_1
 
 /* CAN */
-#define GPIO_CAN1_RX	GPIO_CAN1_RX_1
-#define GPIO_CAN1_TX	GPIO_CAN1_TX_1
+#define GPIO_CAN1_RX GPIO_CAN1_RX_1
+#define GPIO_CAN1_TX GPIO_CAN1_TX_1
 
 /* I2C */
 
 #define GPIO_MCU_I2C1_SCL
 #define GPIO_MCU_I2C1_SDA
 
-#define GPIO_I2C1_SCL	GPIO_I2C1_SCL_1
-#define GPIO_I2C1_SDA	GPIO_I2C1_SDA_1
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1
 
-#define GPIO_I2C1_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
-#define GPIO_I2C1_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
 
-#define GPIO_I2C2_SCL	GPIO_I2C2_SCL_1
-#define GPIO_I2C2_SDA	GPIO_I2C2_SDA_4
+#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
+#define GPIO_I2C2_SDA GPIO_I2C2_SDA_4
 
-#define GPIO_I2C2_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
-#define GPIO_I2C2_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN9)
+#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN10)
 
 /* SPI */
-#define GPIO_SPI1_MISO  GPIO_SPI1_MISO_1
-#define GPIO_SPI1_MOSI  GPIO_SPI1_MOSI_1
-#define GPIO_SPI1_SCK   GPIO_SPI1_SCK_1
+#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
+#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
+#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
 
 #endif /* __ARCH_BOARD_BOARD_H */

boards/ark/can-rtk-gps/nuttx-config/include/board_dma_map.h

@@ -36,11 +36,10 @@
 // DMA1 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
 
-
 //  DMA2 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
-#define DMACHAN_SPI1_RX    DMAMAP_SPI1_RX_1   // DMA2, Stream 0, Channel 3
-#define DMACHAN_SPI1_TX    DMAMAP_SPI1_TX_1   // DMA2, Stream 3, Channel 3
-#define DMACHAN_USART1_RX  DMAMAP_USART1_RX_1 // DMA2, Stream 2, Channel 4
-#define DMAMAP_USART1_RX   DMAMAP_USART1_RX_1
+#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_1      // DMA2, Stream 0, Channel 3
+#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_1      // DMA2, Stream 3, Channel 3
+#define DMACHAN_USART1_RX DMAMAP_USART1_RX_1  // DMA2, Stream 2, Channel 4
+#define DMAMAP_USART1_RX DMAMAP_USART1_RX_1
 //#define DMACHAN_USART1_TX  DMAMAP_USART1_TX   // DMA2, Stream 7, Channel 4

boards/ark/can-rtk-gps/src/board_config.h

@@ -39,80 +39,83 @@
 
 #pragma once
 
-#include <px4_platform_common/px4_config.h>
 #include <nuttx/compiler.h>
+#include <px4_platform_common/px4_config.h>
 #include <stdint.h>
 
 /* BUTTON */
-#define GPIO_BTN_SAFETY       /* PB15 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTB|GPIO_PIN15)
+#define GPIO_BTN_SAFETY /* PB15 */ (GPIO_INPUT | GPIO_PULLDOWN | GPIO_PORTB | GPIO_PIN15)
 
 /* Safety LED */
-#define GPIO_LED_SAFETY       /* PA1  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_LED_SAFETY /* PA1  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTA | GPIO_PIN1)
 
 /* Tone alarm output. */
-#define TONE_ALARM_TIMER             2    /* timer 2 */
-#define TONE_ALARM_CHANNEL           1    /* channel 1 */
-#define GPIO_TONE_ALARM_IDLE  /* PA0  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_TONE_ALARM       /* PA0  */ (GPIO_ALT|GPIO_AF1|GPIO_SPEED_2MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
+#define TONE_ALARM_TIMER 2   /* timer 2 */
+#define TONE_ALARM_CHANNEL 1 /* channel 1 */
+#define GPIO_TONE_ALARM_IDLE /* PA0  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_TONE_ALARM /* PA0  */ (GPIO_ALT | GPIO_AF1 | GPIO_SPEED_2MHz | GPIO_PUSHPULL | GPIO_PORTA | GPIO_PIN0)
 
 /* CAN  Silent mode control */
-#define GPIO_CAN1_SILENT_S0   /* PB12 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_CAN1_SILENT_S0 /* PB12 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN12)
 
 /* CAN termination software control */
-#define GPIO_CAN1_TERMINATION /* PB13 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_CAN_TERM                    GPIO_CAN1_TERMINATION
+#define GPIO_CAN1_TERMINATION /* PB13 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN13)
+#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
 
 /* ICM42688p FSYNC */
-#define GPIO_42688P_FSYNC     /* PB8  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_42688P_FSYNC /* PB8  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN8)
 
 /* Boot config */
-#define GPIO_BOOT_CONFIG      /* PC15 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTC|GPIO_PIN15|GPIO_EXTI)
+#define GPIO_BOOT_CONFIG /* PC15 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTC | GPIO_PIN15 | GPIO_EXTI)
 
 /* LEDs are driven with open drain to support Anode to 5V or 3.3V */
-#define GPIO_TIM1_CH1         /* PA8  */ (GPIO_TIM1_CH1_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
-#define GPIO_TIM1_CH2         /* PA9  */ (GPIO_TIM1_CH2_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
-#define GPIO_TIM1_CH3         /* PA10 */ (GPIO_TIM1_CH3_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
+#define GPIO_TIM1_CH1 /* PA8  */ (GPIO_TIM1_CH1_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
+#define GPIO_TIM1_CH2 /* PA9  */ (GPIO_TIM1_CH2_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
+#define GPIO_TIM1_CH3 /* PA10 */ (GPIO_TIM1_CH3_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
 
-#define GPIO_I2C1_SCL_RESET   /* PB6  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6)
-#define GPIO_I2C1_SDA_RESET   /* PB7  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_I2C1_SCL_RESET /* PB6  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_I2C1_SDA_RESET /* PB7  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7)
 
-#define GPIO_I2C2_SCL_RESET   /* PB10 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_I2C2_SDA_RESET   /* PB9  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C2_SCL_RESET /* PB10 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_I2C2_SDA_RESET /* PB9  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN9)
 
-#define GPIO_I2C2_SCL_RESET   /* PB10 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_I2C2_SDA_RESET   /* PB9  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C2_SCL_RESET /* PB10 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_I2C2_SDA_RESET /* PB9  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN9)
 
-#define GPIO_USART1_RX_GPIO	(GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
-#define GPIO_USART1_TX_GPIO	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_USART1_RX_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN3)
+#define GPIO_USART1_TX_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN15)
 
-#define GPIO_USART2_RX_GPIO	(GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_USART2_TX_GPIO	(GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_USART2_RX_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_USART2_TX_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN2)
 
 #define FLASH_BASED_PARAMS
 
 /* High-resolution timer */
-#define HRT_TIMER                    3  /* use timer 3 for the HRT */
-#define HRT_TIMER_CHANNEL            4  /* use capture/compare channel 4 */
+#define HRT_TIMER 3         /* use timer 3 for the HRT */
+#define HRT_TIMER_CHANNEL 4 /* use capture/compare channel 4 */
 
-#define PX4_GPIO_INIT_LIST { \
-		GPIO_BTN_SAFETY,                  \
-		GPIO_LED_SAFETY,                  \
-		GPIO_I2C1_SCL_RESET,              \
-		GPIO_I2C1_SDA_RESET,              \
-		GPIO_I2C2_SCL_RESET,              \
-		GPIO_I2C2_SDA_RESET,              \
-		GPIO_42688P_FSYNC,                \
-		GPIO_BOOT_CONFIG,                 \
-		GPIO_CAN1_TX,                     \
-		GPIO_CAN1_RX,                     \
-		GPIO_CAN1_SILENT_S0,              \
-		GPIO_CAN1_TERMINATION,            \
+#define PX4_GPIO_INIT_LIST                                                                                       \
+	{                                                                                                        \
+		GPIO_BTN_SAFETY, GPIO_LED_SAFETY, GPIO_I2C1_SCL_RESET, GPIO_I2C1_SDA_RESET, GPIO_I2C2_SCL_RESET, \
+			GPIO_I2C2_SDA_RESET, GPIO_42688P_FSYNC, GPIO_BOOT_CONFIG, GPIO_CAN1_TX, GPIO_CAN1_RX,    \
+			GPIO_CAN1_SILENT_S0, GPIO_CAN1_TERMINATION,                                              \
 	}
 
 __BEGIN_DECLS
 
-#define BOARD_HAS_N_S_RGB_LED       1
-#define BOARD_MAX_LEDS              BOARD_HAS_N_S_RGB_LED
+#define BOARD_HAS_N_S_RGB_LED 1
+#define BOARD_MAX_LEDS BOARD_HAS_N_S_RGB_LED
 
 #ifndef __ASSEMBLY__
 

boards/ark/can-rtk-gps/src/boot.c

@@ -38,16 +38,15 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <nuttx/board.h>
 #include <px4_config.h>
 #include <stdint.h>
-#include "boot_config.h"
-#include "board.h"
-
-#include <debug.h>
 #include <string.h>
-#include <arch/board/board.h>
 
-#include <nuttx/board.h>
+#include "board.h"
+#include "boot_config.h"
 #include "led.h"
 
 /************************************************************************************
@@ -60,8 +59,7 @@
  *
  ************************************************************************************/
 
-__EXPORT void stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	putreg32(getreg32(STM32_RCC_APB1ENR) | RCC_APB1ENR_CAN1EN, STM32_RCC_APB1ENR);
 	stm32_configgpio(GPIO_CAN1_RX);
 	stm32_configgpio(GPIO_CAN1_TX);
@@ -73,7 +71,6 @@ __EXPORT void stm32_boardinitialize(void)
 #if defined(OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO)
 	stm32_configgpio(GPIO_GETNODEINFO_JUMPER);
 #endif
-
 }
 
 /************************************************************************************
@@ -85,10 +82,7 @@ __EXPORT void stm32_boardinitialize(void)
  *
  ************************************************************************************/
 
-void board_deinitialize(void)
-{
-	putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR);
-}
+void board_deinitialize(void) { putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR); }
 
 /****************************************************************************
  * Name: board_get_product_name
@@ -107,8 +101,7 @@ void board_deinitialize(void)
  *
  ****************************************************************************/
 
-uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
-{
+uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen) {
 	DEBUGASSERT(maxlen > UAVCAN_STRLEN(HW_UAVCAN_NAME));
 	memcpy(product_name, HW_UAVCAN_NAME, UAVCAN_STRLEN(HW_UAVCAN_NAME));
 	return UAVCAN_STRLEN(HW_UAVCAN_NAME);
@@ -129,14 +122,13 @@ uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
  *
  ****************************************************************************/
 
-size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
-{
+size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version) {
 	memset(hw_version, 0, sizeof(uavcan_HardwareVersion_t));
 
 	hw_version->major = HW_VERSION_MAJOR;
 	hw_version->minor = HW_VERSION_MINOR;
 
-	return board_get_mfguid(*(mfguid_t *) hw_version->unique_id);
+	return board_get_mfguid(*(mfguid_t *)hw_version->unique_id);
 }
 
 /****************************************************************************
@@ -153,7 +145,8 @@ size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
  *   None
  *
  ****************************************************************************/
-#define led(n, code, r , g , b, h) {.red = (r),.green = (g), .blue = (b),.hz = (h)}
+#define led(n, code, r, g, b, h) \
+	{ .red = (r), .green = (g), .blue = (b), .hz = (h) }
 
 typedef begin_packed_struct struct led_t {
 	uint8_t red;
@@ -162,27 +155,23 @@ typedef begin_packed_struct struct led_t {
 	uint8_t hz;
 } end_packed_struct led_t;
 
-static const  led_t i2l[] = {
+static const led_t i2l[] = {
 
-	led(0, off,                             0,     0,     0,     0),
-	led(1, reset,                          128,   128,   128,   30),
-	led(2, autobaud_start,                  0,   128,     0,     1),
-	led(3, autobaud_end,                    0,   128,     0,     2),
-	led(4, allocation_start,                0,     0,    64,     2),
-	led(5, allocation_end,                  0,   128,    64,     3),
-	led(6, fw_update_start,                32,   128,    64,     3),
-	led(7, fw_update_erase_fail,           32,   128,    32,     3),
-	led(8, fw_update_invalid_response,     64,     0,     0,     1),
-	led(9, fw_update_timeout,              64,     0,     0,     2),
-	led(a, fw_update_invalid_crc,          64,     0,     0,     4),
-	led(b, jump_to_app,                     0,   128,     0,    10),
+	led(0, off, 0, 0, 0, 0),
+	led(1, reset, 128, 128, 128, 30),
+	led(2, autobaud_start, 0, 128, 0, 1),
+	led(3, autobaud_end, 0, 128, 0, 2),
+	led(4, allocation_start, 0, 0, 64, 2),
+	led(5, allocation_end, 0, 128, 64, 3),
+	led(6, fw_update_start, 32, 128, 64, 3),
+	led(7, fw_update_erase_fail, 32, 128, 32, 3),
+	led(8, fw_update_invalid_response, 64, 0, 0, 1),
+	led(9, fw_update_timeout, 64, 0, 0, 2),
+	led(a, fw_update_invalid_crc, 64, 0, 0, 4),
+	led(b, jump_to_app, 0, 128, 0, 10),
 
 };
 
-void board_indicate(uiindication_t indication)
-{
-	rgb_led(i2l[indication].red,
-		i2l[indication].green,
-		i2l[indication].blue,
-		i2l[indication].hz);
+void board_indicate(uiindication_t indication) {
+	rgb_led(i2l[indication].red, i2l[indication].green, i2l[indication].blue, i2l[indication].hz);
 }

boards/ark/can-rtk-gps/src/boot_config.h

@@ -50,13 +50,12 @@
  * todo:make this be pulled in from a targed's build
  * files in nuttx*/
 
+#include <nuttx/compiler.h>
+#include <stdint.h>
+#include <stm32_flash.h>
+
 #include "board_config.h"
 #include "uavcan.h"
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include <stm32_flash.h>
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -64,11 +63,11 @@
 
 #define OPT_PREFERRED_NODE_ID ANY_NODE_ID
 
-//todo:wrap OPT_x in in ifdefs for command line definitions
-#define OPT_TBOOT_MS                    5000
-#define OPT_NODE_STATUS_RATE_MS         800
-#define OPT_NODE_INFO_RATE_MS           50
-#define OPT_BL_NUMBER_TIMERS            7
+// todo:wrap OPT_x in in ifdefs for command line definitions
+#define OPT_TBOOT_MS 5000
+#define OPT_NODE_STATUS_RATE_MS 800
+#define OPT_NODE_INFO_RATE_MS 50
+#define OPT_BL_NUMBER_TIMERS 7
 
 /*
  *  This Option set is set to 1 ensure a provider of firmware has an
@@ -91,34 +90,33 @@
  *   no            0                       1       Not Active
  *
  */
-#define OPT_WAIT_FOR_GETNODEINFO                    0
-#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO        1
+#define OPT_WAIT_FOR_GETNODEINFO 0
+#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
 #define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO_INVERT 0
 
-#define OPT_ENABLE_WD           1
+#define OPT_ENABLE_WD 1
 
-#define OPT_RESTART_TIMEOUT_MS          20000
+#define OPT_RESTART_TIMEOUT_MS 20000
 
 /* Reserved for the Booloader */
-#define OPT_BOOTLOADER_SIZE_IN_K        (1024*64)
+#define OPT_BOOTLOADER_SIZE_IN_K (1024 * 64)
 
 /* Reserved for the application out of the total
  * system flash minus the BOOTLOADER_SIZE_IN_K
  */
-#define OPT_APPLICATION_RESERVER_IN_K    0
+#define OPT_APPLICATION_RESERVER_IN_K 0
 
-#define OPT_APPLICATION_IMAGE_OFFSET    OPT_BOOTLOADER_SIZE_IN_K
-#define OPT_APPLICATION_IMAGE_LENGTH    (FLASH_SIZE-(OPT_BOOTLOADER_SIZE_IN_K+OPT_APPLICATION_RESERVER_IN_K))
+#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
+#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE - (OPT_BOOTLOADER_SIZE_IN_K + OPT_APPLICATION_RESERVER_IN_K))
 
-
-#define FLASH_BASE              STM32_FLASH_BASE
-#define FLASH_SIZE              STM32_FLASH_SIZE
+#define FLASH_BASE STM32_FLASH_BASE
+#define FLASH_SIZE STM32_FLASH_SIZE
 
 #define APPLICATION_LOAD_ADDRESS (FLASH_BASE + OPT_APPLICATION_IMAGE_OFFSET)
-#define APPLICATION_SIZE (FLASH_SIZE-OPT_APPLICATION_IMAGE_OFFSET)
-#define APPLICATION_LAST_8BIT_ADDRRESS  ((uint8_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint8_t)))
-#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint32_t)))
-#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint64_t)))
+#define APPLICATION_SIZE (FLASH_SIZE - OPT_APPLICATION_IMAGE_OFFSET)
+#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint8_t)))
+#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint32_t)))
+#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint64_t)))
 
 /* If this board uses big flash that have large sectors */
 

boards/ark/can-rtk-gps/src/can.c

@@ -41,20 +41,17 @@
  * Included Files
  ************************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <errno.h>
+#include <nuttx/can/can.h>
 #include <px4_platform_common/px4_config.h>
 
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/can/can.h>
-#include <arch/board/board.h>
-
-#include "chip.h"
 #include "arm_arch.h"
-
+#include "board_config.h"
+#include "chip.h"
 #include "stm32.h"
 #include "stm32_can.h"
-#include "board_config.h"
 
 #ifdef CONFIG_CAN
 
@@ -64,14 +61,14 @@
 /* Configuration ********************************************************************/
 
 #if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
-#  warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
-#  undef CONFIG_STM32_CAN2
+#warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
+#undef CONFIG_STM32_CAN2
 #endif
 
 #ifdef CONFIG_STM32_CAN1
-#  define CAN_PORT 1
+#define CAN_PORT 1
 #else
-#  define CAN_PORT 2
+#define CAN_PORT 2
 #endif
 
 /************************************************************************************
@@ -92,8 +89,7 @@ int can_devinit(void);
  *
  ************************************************************************************/
 
-int can_devinit(void)
-{
+int can_devinit(void) {
 	static bool initialized = false;
 	struct can_dev_s *can;
 	int ret;

boards/ark/can-rtk-gps/src/init.c

@@ -41,36 +41,30 @@
  * subsystems and perform board-specific initialization.
  */
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <drivers/drv_board_led.h>
+#include <drivers/drv_hrt.h>
+#include <drivers/drv_watchdog.h>
+#include <errno.h>
+#include <nuttx/board.h>
+#include <px4_platform/gpio.h>
+#include <px4_platform_common/init.h>
 #include <px4_platform_common/px4_config.h>
 #include <px4_platform_common/tasks.h>
-
 #include <stdbool.h>
 #include <stdio.h>
-#include <string.h>
-#include <debug.h>
-#include <errno.h>
-#include <syslog.h>
-
-#include <nuttx/board.h>
-
 #include <stm32.h>
-#include "board_config.h"
-#include "led.h"
 #include <stm32_uart.h>
-
-#include <arch/board/board.h>
-
-#include <drivers/drv_hrt.h>
-#include <drivers/drv_board_led.h>
-#include <drivers/drv_watchdog.h>
-
+#include <string.h>
+#include <syslog.h>
 #include <systemlib/px4_macros.h>
 
-#include <px4_platform_common/init.h>
-#include <px4_platform/gpio.h>
+#include "board_config.h"
+#include "led.h"
 
-# if defined(FLASH_BASED_PARAMS)
-#  include <parameters/flashparams/flashfs.h>
+#if defined(FLASH_BASED_PARAMS)
+#include <parameters/flashparams/flashfs.h>
 #endif
 
 /************************************************************************************
@@ -83,8 +77,7 @@
  *
  ************************************************************************************/
 
-__EXPORT void stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	watchdog_init();
 
 	/* configure pins */
@@ -135,8 +128,7 @@ __EXPORT void stm32_boardinitialize(void)
  *
  ****************************************************************************/
 
-__EXPORT int board_app_initialize(uintptr_t arg)
-{
+__EXPORT int board_app_initialize(uintptr_t arg) {
 	px4_platform_init();
 
 #if defined(SERIAL_HAVE_RXDMA)
@@ -159,7 +151,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 		syslog(LOG_ERR, "[boot] FAILED to init params in FLASH %d\n", result);
 	}
 
-#endif // FLASH_BASED_PARAMS
+#endif  // FLASH_BASED_PARAMS
 
 	/* Configure the HW based on the manifest */
 

boards/ark/can-rtk-gps/src/led.c

@@ -37,30 +37,26 @@
  * LED backend.
  */
 
-#include <px4_platform_common/px4_config.h>
-
-#include <stdbool.h>
-
-#include "chip.h"
-#include "stm32_gpio.h"
-#include "board_config.h"
-
-#include <nuttx/board.h>
-#include <arch/board/board.h>
-
 #include "led.h"
 
-#define TMR_BASE        STM32_TIM1_BASE
-#define TMR_FREQUENCY   STM32_APB2_TIM1_CLKIN
-#define TMR_REG(o)      (TMR_BASE+(o))
+#include <arch/board/board.h>
+#include <nuttx/board.h>
+#include <px4_platform_common/px4_config.h>
+#include <stdbool.h>
 
-void rgb_led(int r, int g, int b, int freqs)
-{
+#include "board_config.h"
+#include "chip.h"
+#include "stm32_gpio.h"
 
+#define TMR_BASE STM32_TIM1_BASE
+#define TMR_FREQUENCY STM32_APB2_TIM1_CLKIN
+#define TMR_REG(o) (TMR_BASE + (o))
+
+void rgb_led(int r, int g, int b, int freqs) {
 	long fosc = TMR_FREQUENCY;
 	long prescale = 2048;
 	long p1s = fosc / prescale;
-	long p0p5s  = p1s / 2;
+	long p0p5s = p1s / 2;
 	uint16_t val;
 	static bool once = 0;
 
@@ -84,14 +80,14 @@ void rgb_led(int r, int g, int b, int freqs)
 
 		putreg16(ATIM_CR1_CEN | ATIM_CR1_ARPE, TMR_REG(STM32_BTIM_CR1_OFFSET));
 
-
 		putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | ATIM_CCMR1_OC1PE |
-			 (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE, TMR_REG(STM32_GTIM_CCMR1_OFFSET));
-		putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE, TMR_REG(STM32_GTIM_CCMR2_OFFSET));
-		putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P |
-			 ATIM_CCER_CC2E | ATIM_CCER_CC2P |
-			 ATIM_CCER_CC1E | ATIM_CCER_CC1P, TMR_REG(STM32_GTIM_CCER_OFFSET));
-
+				 (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE,
+			 TMR_REG(STM32_GTIM_CCMR1_OFFSET));
+		putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE,
+			 TMR_REG(STM32_GTIM_CCMR2_OFFSET));
+		putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P | ATIM_CCER_CC2E | ATIM_CCER_CC2P | ATIM_CCER_CC1E |
+				 ATIM_CCER_CC1P,
+			 TMR_REG(STM32_GTIM_CCER_OFFSET));
 
 		stm32_configgpio(GPIO_TIM1_CH1);
 		stm32_configgpio(GPIO_TIM1_CH2);
@@ -101,10 +97,10 @@ void rgb_led(int r, int g, int b, int freqs)
 		putreg16(ATIM_BDTR_MOE, (TMR_REG(STM32_ATIM_BDTR_OFFSET)));
 	}
 
-	long p  = freqs == 0 ? p1s : p1s / freqs;
+	long p = freqs == 0 ? p1s : p1s / freqs;
 	putreg32(p, TMR_REG(STM32_BTIM_ARR_OFFSET));
 
-	p  = freqs == 0 ? p1s + 1 : p0p5s / freqs;
+	p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
 
 	putreg32((r * p) / 255, TMR_REG(STM32_GTIM_CCR1_OFFSET));
 	putreg32((g * p) / 255, TMR_REG(STM32_GTIM_CCR2_OFFSET));
@@ -120,5 +116,4 @@ void rgb_led(int r, int g, int b, int freqs)
 	}
 
 	putreg16(val, TMR_REG(STM32_BTIM_CR1_OFFSET));
-
 }

boards/ark/can-rtk-gps/src/spi.cpp

@@ -31,14 +31,16 @@
  *
  ****************************************************************************/
 
-#include <px4_arch/spi_hw_description.h>
 #include <drivers/drv_sensor.h>
 #include <nuttx/spi/spi.h>
+#include <px4_arch/spi_hw_description.h>
 
 constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
-	initSPIBus(SPI::Bus::SPI1, {
-		initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortB, GPIO::Pin0}, SPI::DRDY{GPIO::PortB, GPIO::Pin1}),
-	}),
+	initSPIBus(SPI::Bus::SPI1,
+		   {
+			   initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortB, GPIO::Pin0},
+					 SPI::DRDY{GPIO::PortB, GPIO::Pin1}),
+		   }),
 };
 
 static constexpr bool unused = validateSPIConfig(px4_spi_buses);

boards/ark/cannode/nuttx-config/include/board.h

@@ -40,7 +40,7 @@
 
 #include <nuttx/config.h>
 #ifndef __ASSEMBLY__
-# include <stdint.h>
+#include <stdint.h>
 #endif
 
 #include <stm32.h>
@@ -50,19 +50,19 @@
  * HSE - 8  MHz Crystal
  * LSE - not installed
  */
-#define STM32_BOARD_USEHSE      1
-#define STM32_BOARD_XTAL        8000000
-#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_BOARD_USEHSE 1
+#define STM32_BOARD_XTAL 8000000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
 
-#define STM32_HSI_FREQUENCY     16000000ul
-#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
 
 /* Main PLL Configuration */
-#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(384)
-#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_4
-#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(8)
-#define STM32_PLLCFG_PLLR       RCC_PLLCFG_PLLR(2)
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(384)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_4
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(8)
+#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR(2)
 
 #define STM32_RCC_PLLI2SCFGR_PLLI2SM RCC_PLLI2SCFGR_PLLI2SM(16)
 #define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
@@ -74,76 +74,76 @@
 #define STM32_RCC_DCKCFGR2_FMPI2C1SEL RCC_DCKCFGR2_FMPI2C1SEL_APB
 #define STM32_RCC_DCKCFGR2_SDIOSEL RCC_DCKCFGR2_SDIOSEL_48MHZ
 
-#define STM32_SYSCLK_FREQUENCY  96000000ul
+#define STM32_SYSCLK_FREQUENCY 96000000ul
 
 /* AHB clock (HCLK) is SYSCLK (96MHz) */
-#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
-#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
-#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY      /* Same as above, to satisfy compiler */
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* Same as above, to satisfy compiler */
 
 /* APB1 clock (PCLK1) is HCLK/2 (48MHz) */
-#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd2     /* PCLK1 = HCLK / 2 */
-#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2 /* PCLK1 = HCLK / 2 */
+#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
 
 /* Timers driven from APB1 will be twice PCLK1 (see page 112 of reference manual) */
-#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
 
 /* APB2 clock (PCLK2) is HCLK (96MHz) */
-#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK */
-#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY)
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK */
+#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY)
 
 /* Timers driven from APB2 will be PCLK2 since no prescale division */
-#define STM32_APB2_TIM1_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM8_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM9_CLKIN   (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM10_CLKIN  (STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM11_CLKIN  (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN (STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
 
 /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx otherwise frequency is 2xAPBx. */
-#define BOARD_TIM2_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM3_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM4_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM5_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM6_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM7_FREQUENCY    (2 * STM32_PCLK1_FREQUENCY)
-#define BOARD_TIM8_FREQUENCY    (2 * STM32_PCLK2_FREQUENCY)
+#define BOARD_TIM2_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM3_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM4_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM5_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM6_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM7_FREQUENCY (2 * STM32_PCLK1_FREQUENCY)
+#define BOARD_TIM8_FREQUENCY (2 * STM32_PCLK2_FREQUENCY)
 
 /* Alternate function pin selections ************************************************/
 
 /* UARTs */
-#define GPIO_USART1_RX	GPIO_USART1_RX_2
-#define GPIO_USART1_TX	GPIO_USART1_TX_3
+#define GPIO_USART1_RX GPIO_USART1_RX_2
+#define GPIO_USART1_TX GPIO_USART1_TX_3
 
-#define GPIO_USART2_RX	GPIO_USART2_RX_1
-#define GPIO_USART2_TX	GPIO_USART2_TX_1
+#define GPIO_USART2_RX GPIO_USART2_RX_1
+#define GPIO_USART2_TX GPIO_USART2_TX_1
 
 /* CAN */
-#define GPIO_CAN1_RX	GPIO_CAN1_RX_1
-#define GPIO_CAN1_TX	GPIO_CAN1_TX_1
+#define GPIO_CAN1_RX GPIO_CAN1_RX_1
+#define GPIO_CAN1_TX GPIO_CAN1_TX_1
 
 /* SPI */
-#define GPIO_SPI1_MISO  GPIO_SPI1_MISO_1
-#define GPIO_SPI1_MOSI  GPIO_SPI1_MOSI_1
-#define GPIO_SPI1_SCK   GPIO_SPI1_SCK_1
+#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1
+#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_1
+#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1
 
-#define GPIO_SPI2_MISO  GPIO_SPI2_MISO_1 /* PB14 */
-#define GPIO_SPI2_MOSI  GPIO_SPI2_MOSI_1 /* PB15 */
-#define GPIO_SPI2_SCK   GPIO_SPI2_SCK_2  /* PB13 */
+#define GPIO_SPI2_MISO GPIO_SPI2_MISO_1 /* PB14 */
+#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_1 /* PB15 */
+#define GPIO_SPI2_SCK GPIO_SPI2_SCK_2   /* PB13 */
 
 /* I2C */
 #define GPIO_MCU_I2C1_SCL
 #define GPIO_MCU_I2C1_SDA
 
-#define GPIO_I2C1_SCL	GPIO_I2C1_SCL_1
-#define GPIO_I2C1_SDA	GPIO_I2C1_SDA_2
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
 
-#define GPIO_I2C1_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
-#define GPIO_I2C1_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN |GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
+#define GPIO_I2C1_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_I2C1_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN7)
 
 #endif /* __ARCH_BOARD_BOARD_H */

boards/ark/cannode/nuttx-config/include/board_dma_map.h

@@ -35,10 +35,10 @@
 
 // DMA1 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
-#define DMACHAN_SPI2_RX    DMAMAP_SPI2_RX   // DMA1, Stream 3, Channel 0
-#define DMACHAN_SPI2_TX    DMAMAP_SPI2_TX   // DMA1, Stream 4, Channel 0
+#define DMACHAN_SPI2_RX DMAMAP_SPI2_RX  // DMA1, Stream 3, Channel 0
+#define DMACHAN_SPI2_TX DMAMAP_SPI2_TX  // DMA1, Stream 4, Channel 0
 
 //  DMA2 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
-#define DMACHAN_SPI1_RX    DMAMAP_SPI1_RX_2   // DMA2, Stream 2, Channel 3
-#define DMACHAN_SPI1_TX    DMAMAP_SPI1_TX_2   // DMA2, Stream 5, Channel 3
+#define DMACHAN_SPI1_RX DMAMAP_SPI1_RX_2  // DMA2, Stream 2, Channel 3
+#define DMACHAN_SPI1_TX DMAMAP_SPI1_TX_2  // DMA2, Stream 5, Channel 3

boards/ark/cannode/src/board_config.h

@@ -39,69 +39,80 @@
 
 #pragma once
 
-#include <px4_platform_common/px4_config.h>
 #include <nuttx/compiler.h>
+#include <px4_platform_common/px4_config.h>
 #include <stdint.h>
 
 /* CAN  Silent mode control */
-#define GPIO_CAN1_SILENT_S0   /* PC14  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN14)
+#define GPIO_CAN1_SILENT_S0 /* PC14  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN14)
 
 /* CAN termination software control */
-#define GPIO_CAN1_TERMINATION /* PC15 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN15)
-#define GPIO_CAN_TERM                    GPIO_CAN1_TERMINATION
+#define GPIO_CAN1_TERMINATION /* PC15 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTC | GPIO_PIN15)
+#define GPIO_CAN_TERM GPIO_CAN1_TERMINATION
 
 /* Boot config */
-#define GPIO_BOOT_CONFIG      /* PH1 */ (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTH|GPIO_PIN1|GPIO_EXTI)
+#define GPIO_BOOT_CONFIG /* PH1 */ (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTH | GPIO_PIN1 | GPIO_EXTI)
 
 /* ICM42688p FSYNC */
-#define GPIO_42688P_FSYNC     /* PB8  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN8)
+#define GPIO_42688P_FSYNC /* PB8  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN8)
 
 /* LEDs are driven with open drain to support Anode to 5V or 3.3V */
-#define GPIO_TIM1_CH1         /* PA8  */  (GPIO_TIM1_CH1_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
-#define GPIO_TIM1_CH2         /* PA9  */  (GPIO_TIM1_CH2_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
-#define GPIO_TIM1_CH3         /* PA10 */  (GPIO_TIM1_CH3_1|GPIO_OPENDRAIN|GPIO_SPEED_2MHz)
+#define GPIO_TIM1_CH1 /* PA8  */ (GPIO_TIM1_CH1_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
+#define GPIO_TIM1_CH2 /* PA9  */ (GPIO_TIM1_CH2_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
+#define GPIO_TIM1_CH3 /* PA10 */ (GPIO_TIM1_CH3_1 | GPIO_OPENDRAIN | GPIO_SPEED_2MHz)
 
 /* PWM Outputs */
-#define DIRECT_PWM_OUTPUT_CHANNELS  6 // Actually 8
+#define DIRECT_PWM_OUTPUT_CHANNELS 6  // Actually 8
 
-#define GPIO_TIM2_CH1_RESET   /* PA0  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_TIM2_CH2_RESET   /* PA1  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_TIM2_CH3_RESET   /* PB10 */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_TIM3_CH1_RESET   /* PB4  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN4)
-#define GPIO_TIM3_CH2_RESET   /* PB5  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN5)
-#define GPIO_TIM3_CH3_RESET   /* PB0  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_TIM3_CH4_RESET   /* PB1  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_TIM4_CH4_RESET   /* PB7  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_TIM2_CH1_RESET /* PA0  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN0)
+#define GPIO_TIM2_CH2_RESET /* PA1  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN1)
+#define GPIO_TIM2_CH3_RESET /* PB10 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN10)
+#define GPIO_TIM3_CH1_RESET /* PB4  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN4)
+#define GPIO_TIM3_CH2_RESET /* PB5  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN5)
+#define GPIO_TIM3_CH3_RESET /* PB0  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_TIM3_CH4_RESET /* PB1  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN1)
+#define GPIO_TIM4_CH4_RESET /* PB7  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN7)
 
-#define GPIO_I2C1_SCL_RESET   /* PB6  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN6)
-#define GPIO_I2C1_SDA_RESET   /* PB9  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN9)
+#define GPIO_I2C1_SCL_RESET /* PB6  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN6)
+#define GPIO_I2C1_SDA_RESET /* PB9  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN9)
 
-#define GPIO_USART1_RX_GPIO   /* PB3  */  (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTB|GPIO_PIN3)
-#define GPIO_USART1_TX_GPIO   /* PA15  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_USART1_RX_GPIO /* PB3  */ (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTB | GPIO_PIN3)
+#define GPIO_USART1_TX_GPIO /* PA15  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN15)
 
-#define GPIO_USART2_RX_GPIO   /* PA3  */  (GPIO_INPUT|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_USART2_TX_GPIO   /* PA2  */  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_USART2_RX_GPIO /* PA3  */ (GPIO_INPUT | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN3)
+#define GPIO_USART2_TX_GPIO /* PA2  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_PULLUP | GPIO_SPEED_50MHz | GPIO_PORTA | GPIO_PIN2)
 
 #define FLASH_BASED_PARAMS
 
 /* High-resolution timer */
-#define HRT_TIMER                    8  /* use timer 8 for the HRT */
-#define HRT_TIMER_CHANNEL            1  /* use capture/compare channel 1 */
+#define HRT_TIMER 8         /* use timer 8 for the HRT */
+#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel 1 */
 
-#define PX4_GPIO_INIT_LIST { \
-		GPIO_CAN1_SILENT_S0,              \
-		GPIO_CAN1_TERMINATION,            \
-		GPIO_42688P_FSYNC,                \
-		GPIO_CAN1_TX,                     \
-		GPIO_CAN1_RX,                     \
-		GPIO_I2C1_SCL_RESET,              \
-		GPIO_I2C1_SDA_RESET,              \
+#define PX4_GPIO_INIT_LIST                                                                                 \
+	{                                                                                                  \
+		GPIO_CAN1_SILENT_S0, GPIO_CAN1_TERMINATION, GPIO_42688P_FSYNC, GPIO_CAN1_TX, GPIO_CAN1_RX, \
+			GPIO_I2C1_SCL_RESET, GPIO_I2C1_SDA_RESET,                                          \
 	}
 
 __BEGIN_DECLS
 
-#define BOARD_HAS_N_S_RGB_LED       1
-#define BOARD_MAX_LEDS              BOARD_HAS_N_S_RGB_LED
+#define BOARD_HAS_N_S_RGB_LED 1
+#define BOARD_MAX_LEDS BOARD_HAS_N_S_RGB_LED
 
 #ifndef __ASSEMBLY__
 

boards/ark/cannode/src/boot.c

@@ -38,16 +38,15 @@
  * Included Files
  ****************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <nuttx/board.h>
 #include <px4_config.h>
 #include <stdint.h>
-#include "boot_config.h"
-#include "board.h"
-
-#include <debug.h>
 #include <string.h>
-#include <arch/board/board.h>
 
-#include <nuttx/board.h>
+#include "board.h"
+#include "boot_config.h"
 #include "led.h"
 
 /************************************************************************************
@@ -60,8 +59,7 @@
  *
  ************************************************************************************/
 
-__EXPORT void stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	putreg32(getreg32(STM32_RCC_APB1ENR) | RCC_APB1ENR_CAN1EN, STM32_RCC_APB1ENR);
 	stm32_configgpio(GPIO_CAN1_RX);
 	stm32_configgpio(GPIO_CAN1_TX);
@@ -73,7 +71,6 @@ __EXPORT void stm32_boardinitialize(void)
 #if defined(OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO)
 	stm32_configgpio(GPIO_GETNODEINFO_JUMPER);
 #endif
-
 }
 
 /************************************************************************************
@@ -85,10 +82,7 @@ __EXPORT void stm32_boardinitialize(void)
  *
  ************************************************************************************/
 
-void board_deinitialize(void)
-{
-	putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR);
-}
+void board_deinitialize(void) { putreg32(getreg32(STM32_RCC_APB1RSTR) | RCC_APB1RSTR_CAN1RST, STM32_RCC_APB1RSTR); }
 
 /****************************************************************************
  * Name: board_get_product_name
@@ -107,8 +101,7 @@ void board_deinitialize(void)
  *
  ****************************************************************************/
 
-uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
-{
+uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen) {
 	DEBUGASSERT(maxlen > UAVCAN_STRLEN(HW_UAVCAN_NAME));
 	memcpy(product_name, HW_UAVCAN_NAME, UAVCAN_STRLEN(HW_UAVCAN_NAME));
 	return UAVCAN_STRLEN(HW_UAVCAN_NAME);
@@ -129,14 +122,13 @@ uint8_t board_get_product_name(uint8_t *product_name, size_t maxlen)
  *
  ****************************************************************************/
 
-size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
-{
+size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version) {
 	memset(hw_version, 0, sizeof(uavcan_HardwareVersion_t));
 
 	hw_version->major = HW_VERSION_MAJOR;
 	hw_version->minor = HW_VERSION_MINOR;
 
-	return board_get_mfguid(*(mfguid_t *) hw_version->unique_id);
+	return board_get_mfguid(*(mfguid_t *)hw_version->unique_id);
 }
 
 /****************************************************************************
@@ -153,7 +145,8 @@ size_t board_get_hardware_version(uavcan_HardwareVersion_t *hw_version)
  *   None
  *
  ****************************************************************************/
-#define led(n, code, r , g , b, h) {.red = (r),.green = (g), .blue = (b),.hz = (h)}
+#define led(n, code, r, g, b, h) \
+	{ .red = (r), .green = (g), .blue = (b), .hz = (h) }
 
 typedef begin_packed_struct struct led_t {
 	uint8_t red;
@@ -162,27 +155,23 @@ typedef begin_packed_struct struct led_t {
 	uint8_t hz;
 } end_packed_struct led_t;
 
-static const  led_t i2l[] = {
+static const led_t i2l[] = {
 
-	led(0, off,                             0,     0,     0,     0),
-	led(1, reset,                          128,   128,   128,   30),
-	led(2, autobaud_start,                  0,   128,     0,     1),
-	led(3, autobaud_end,                    0,   128,     0,     2),
-	led(4, allocation_start,                0,     0,    64,     2),
-	led(5, allocation_end,                  0,   128,    64,     3),
-	led(6, fw_update_start,                32,   128,    64,     3),
-	led(7, fw_update_erase_fail,           32,   128,    32,     3),
-	led(8, fw_update_invalid_response,     64,     0,     0,     1),
-	led(9, fw_update_timeout,              64,     0,     0,     2),
-	led(a, fw_update_invalid_crc,          64,     0,     0,     4),
-	led(b, jump_to_app,                     0,   128,     0,    10),
+	led(0, off, 0, 0, 0, 0),
+	led(1, reset, 128, 128, 128, 30),
+	led(2, autobaud_start, 0, 128, 0, 1),
+	led(3, autobaud_end, 0, 128, 0, 2),
+	led(4, allocation_start, 0, 0, 64, 2),
+	led(5, allocation_end, 0, 128, 64, 3),
+	led(6, fw_update_start, 32, 128, 64, 3),
+	led(7, fw_update_erase_fail, 32, 128, 32, 3),
+	led(8, fw_update_invalid_response, 64, 0, 0, 1),
+	led(9, fw_update_timeout, 64, 0, 0, 2),
+	led(a, fw_update_invalid_crc, 64, 0, 0, 4),
+	led(b, jump_to_app, 0, 128, 0, 10),
 
 };
 
-void board_indicate(uiindication_t indication)
-{
-	rgb_led(i2l[indication].red,
-		i2l[indication].green,
-		i2l[indication].blue,
-		i2l[indication].hz);
+void board_indicate(uiindication_t indication) {
+	rgb_led(i2l[indication].red, i2l[indication].green, i2l[indication].blue, i2l[indication].hz);
 }

boards/ark/cannode/src/boot_config.h

@@ -50,13 +50,12 @@
  * todo:make this be pulled in from a targed's build
  * files in nuttx*/
 
+#include <nuttx/compiler.h>
+#include <stdint.h>
+#include <stm32_flash.h>
+
 #include "board_config.h"
 #include "uavcan.h"
-#include <nuttx/compiler.h>
-
-#include <stdint.h>
-
-#include <stm32_flash.h>
 
 /****************************************************************************
  * Pre-processor Definitions
@@ -64,11 +63,11 @@
 
 #define OPT_PREFERRED_NODE_ID ANY_NODE_ID
 
-//todo:wrap OPT_x in in ifdefs for command line definitions
-#define OPT_TBOOT_MS                    5000
-#define OPT_NODE_STATUS_RATE_MS         800
-#define OPT_NODE_INFO_RATE_MS           50
-#define OPT_BL_NUMBER_TIMERS            7
+// todo:wrap OPT_x in in ifdefs for command line definitions
+#define OPT_TBOOT_MS 5000
+#define OPT_NODE_STATUS_RATE_MS 800
+#define OPT_NODE_INFO_RATE_MS 50
+#define OPT_BL_NUMBER_TIMERS 7
 
 /*
  *  This Option set is set to 1 ensure a provider of firmware has an
@@ -91,34 +90,33 @@
  *   no            0                       1       Not Active
  *
  */
-#define OPT_WAIT_FOR_GETNODEINFO                    0
-#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO        1
+#define OPT_WAIT_FOR_GETNODEINFO 0
+#define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO 1
 #define OPT_WAIT_FOR_GETNODEINFO_JUMPER_GPIO_INVERT 0
 
-#define OPT_ENABLE_WD           1
+#define OPT_ENABLE_WD 1
 
-#define OPT_RESTART_TIMEOUT_MS          20000
+#define OPT_RESTART_TIMEOUT_MS 20000
 
 /* Reserved for the Booloader */
-#define OPT_BOOTLOADER_SIZE_IN_K        (1024*64)
+#define OPT_BOOTLOADER_SIZE_IN_K (1024 * 64)
 
 /* Reserved for the application out of the total
  * system flash minus the BOOTLOADER_SIZE_IN_K
  */
-#define OPT_APPLICATION_RESERVER_IN_K    0
+#define OPT_APPLICATION_RESERVER_IN_K 0
 
-#define OPT_APPLICATION_IMAGE_OFFSET    OPT_BOOTLOADER_SIZE_IN_K
-#define OPT_APPLICATION_IMAGE_LENGTH    (FLASH_SIZE-(OPT_BOOTLOADER_SIZE_IN_K+OPT_APPLICATION_RESERVER_IN_K))
+#define OPT_APPLICATION_IMAGE_OFFSET OPT_BOOTLOADER_SIZE_IN_K
+#define OPT_APPLICATION_IMAGE_LENGTH (FLASH_SIZE - (OPT_BOOTLOADER_SIZE_IN_K + OPT_APPLICATION_RESERVER_IN_K))
 
-
-#define FLASH_BASE              STM32_FLASH_BASE
-#define FLASH_SIZE              STM32_FLASH_SIZE
+#define FLASH_BASE STM32_FLASH_BASE
+#define FLASH_SIZE STM32_FLASH_SIZE
 
 #define APPLICATION_LOAD_ADDRESS (FLASH_BASE + OPT_APPLICATION_IMAGE_OFFSET)
-#define APPLICATION_SIZE (FLASH_SIZE-OPT_APPLICATION_IMAGE_OFFSET)
-#define APPLICATION_LAST_8BIT_ADDRRESS  ((uint8_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint8_t)))
-#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint32_t)))
-#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS+APPLICATION_SIZE)-sizeof(uint64_t)))
+#define APPLICATION_SIZE (FLASH_SIZE - OPT_APPLICATION_IMAGE_OFFSET)
+#define APPLICATION_LAST_8BIT_ADDRRESS ((uint8_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint8_t)))
+#define APPLICATION_LAST_32BIT_ADDRRESS ((uint32_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint32_t)))
+#define APPLICATION_LAST_64BIT_ADDRRESS ((uint64_t *)((APPLICATION_LOAD_ADDRESS + APPLICATION_SIZE) - sizeof(uint64_t)))
 
 /* If this board uses big flash that have large sectors */
 

boards/ark/cannode/src/can.c

@@ -41,20 +41,17 @@
  * Included Files
  ************************************************************************************/
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <errno.h>
+#include <nuttx/can/can.h>
 #include <px4_platform_common/px4_config.h>
 
-#include <errno.h>
-#include <debug.h>
-
-#include <nuttx/can/can.h>
-#include <arch/board/board.h>
-
-#include "chip.h"
 #include "arm_arch.h"
-
+#include "board_config.h"
+#include "chip.h"
 #include "stm32.h"
 #include "stm32_can.h"
-#include "board_config.h"
 
 #ifdef CONFIG_CAN
 
@@ -64,14 +61,14 @@
 /* Configuration ********************************************************************/
 
 #if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2)
-#  warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
-#  undef CONFIG_STM32_CAN2
+#warning "Both CAN1 and CAN2 are enabled.  Assuming only CAN1."
+#undef CONFIG_STM32_CAN2
 #endif
 
 #ifdef CONFIG_STM32_CAN1
-#  define CAN_PORT 1
+#define CAN_PORT 1
 #else
-#  define CAN_PORT 2
+#define CAN_PORT 2
 #endif
 
 /************************************************************************************
@@ -92,8 +89,7 @@ int can_devinit(void);
  *
  ************************************************************************************/
 
-int can_devinit(void)
-{
+int can_devinit(void) {
 	static bool initialized = false;
 	struct can_dev_s *can;
 	int ret;

boards/ark/cannode/src/init.c

@@ -41,39 +41,32 @@
  * subsystems and perform board-specific initialization.
  */
 
+#include <arch/board/board.h>
+#include <debug.h>
+#include <drivers/drv_board_led.h>
+#include <drivers/drv_hrt.h>
+#include <drivers/drv_pwm_output.h>
+#include <drivers/drv_watchdog.h>
+#include <errno.h>
+#include <nuttx/board.h>
+#include <px4_arch/io_timer.h>
+#include <px4_platform/gpio.h>
+#include <px4_platform_common/init.h>
 #include <px4_platform_common/px4_config.h>
 #include <px4_platform_common/tasks.h>
-
 #include <stdbool.h>
 #include <stdio.h>
-#include <string.h>
-#include <debug.h>
-#include <errno.h>
-#include <syslog.h>
-
-#include <nuttx/board.h>
-
 #include <stm32.h>
-#include "board_config.h"
-#include "led.h"
 #include <stm32_uart.h>
-
-#include <arch/board/board.h>
-
-#include <drivers/drv_hrt.h>
-#include <drivers/drv_board_led.h>
-#include <drivers/drv_watchdog.h>
-
+#include <string.h>
+#include <syslog.h>
 #include <systemlib/px4_macros.h>
 
-#include <px4_platform_common/init.h>
-#include <px4_platform/gpio.h>
+#include "board_config.h"
+#include "led.h"
 
-#include <drivers/drv_pwm_output.h>
-#include <px4_arch/io_timer.h>
-
-# if defined(FLASH_BASED_PARAMS)
-#  include <parameters/flashparams/flashfs.h>
+#if defined(FLASH_BASED_PARAMS)
+#include <parameters/flashparams/flashfs.h>
 #endif
 
 /************************************************************************************
@@ -87,8 +80,7 @@
  *          0 if just resetting
  *
  ************************************************************************************/
-__EXPORT void board_on_reset(int status)
-{
+__EXPORT void board_on_reset(int status) {
 	// Configure the GPIO pins to outputs and keep them low.
 	for (int i = 0; i < DIRECT_PWM_OUTPUT_CHANNELS; ++i) {
 		px4_arch_configgpio(io_timer_channel_get_gpio_output(i));
@@ -114,8 +106,7 @@ __EXPORT void board_on_reset(int status)
  *
  ************************************************************************************/
 
-__EXPORT void stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	// Reset all PWM to Low outputs.
 	board_on_reset(-1);
 
@@ -154,8 +145,7 @@ __EXPORT void stm32_boardinitialize(void)
  *
  ****************************************************************************/
 
-__EXPORT int board_app_initialize(uintptr_t arg)
-{
+__EXPORT int board_app_initialize(uintptr_t arg) {
 	px4_platform_init();
 
 #if defined(SERIAL_HAVE_RXDMA)
@@ -178,7 +168,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 		syslog(LOG_ERR, "[boot] FAILED to init params in FLASH %d\n", result);
 	}
 
-#endif // FLASH_BASED_PARAMS
+#endif  // FLASH_BASED_PARAMS
 
 	/* Configure the HW based on the manifest */
 

boards/ark/cannode/src/led.c

@@ -37,30 +37,26 @@
  * LED backend.
  */
 
-#include <px4_platform_common/px4_config.h>
-
-#include <stdbool.h>
-
-#include "chip.h"
-#include "stm32_gpio.h"
-#include "board_config.h"
-
-#include <nuttx/board.h>
-#include <arch/board/board.h>
-
 #include "led.h"
 
-#define TMR_BASE        STM32_TIM1_BASE
-#define TMR_FREQUENCY   STM32_APB2_TIM1_CLKIN
-#define TMR_REG(o)      (TMR_BASE+(o))
+#include <arch/board/board.h>
+#include <nuttx/board.h>
+#include <px4_platform_common/px4_config.h>
+#include <stdbool.h>
 
-void rgb_led(int r, int g, int b, int freqs)
-{
+#include "board_config.h"
+#include "chip.h"
+#include "stm32_gpio.h"
 
+#define TMR_BASE STM32_TIM1_BASE
+#define TMR_FREQUENCY STM32_APB2_TIM1_CLKIN
+#define TMR_REG(o) (TMR_BASE + (o))
+
+void rgb_led(int r, int g, int b, int freqs) {
 	long fosc = TMR_FREQUENCY;
 	long prescale = 2048;
 	long p1s = fosc / prescale;
-	long p0p5s  = p1s / 2;
+	long p0p5s = p1s / 2;
 	uint16_t val;
 	static bool once = 0;
 
@@ -84,14 +80,14 @@ void rgb_led(int r, int g, int b, int freqs)
 
 		putreg16(ATIM_CR1_CEN | ATIM_CR1_ARPE, TMR_REG(STM32_BTIM_CR1_OFFSET));
 
-
 		putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC1M_SHIFT) | ATIM_CCMR1_OC1PE |
-			 (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE, TMR_REG(STM32_GTIM_CCMR1_OFFSET));
-		putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE, TMR_REG(STM32_GTIM_CCMR2_OFFSET));
-		putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P |
-			 ATIM_CCER_CC2E | ATIM_CCER_CC2P |
-			 ATIM_CCER_CC1E | ATIM_CCER_CC1P, TMR_REG(STM32_GTIM_CCER_OFFSET));
-
+				 (ATIM_CCMR_MODE_PWM1 << ATIM_CCMR1_OC2M_SHIFT) | ATIM_CCMR1_OC2PE,
+			 TMR_REG(STM32_GTIM_CCMR1_OFFSET));
+		putreg16((ATIM_CCMR_MODE_PWM1 << ATIM_CCMR2_OC3M_SHIFT) | ATIM_CCMR2_OC3PE,
+			 TMR_REG(STM32_GTIM_CCMR2_OFFSET));
+		putreg16(ATIM_CCER_CC3E | ATIM_CCER_CC3P | ATIM_CCER_CC2E | ATIM_CCER_CC2P | ATIM_CCER_CC1E |
+				 ATIM_CCER_CC1P,
+			 TMR_REG(STM32_GTIM_CCER_OFFSET));
 
 		stm32_configgpio(GPIO_TIM1_CH1);
 		stm32_configgpio(GPIO_TIM1_CH2);
@@ -101,10 +97,10 @@ void rgb_led(int r, int g, int b, int freqs)
 		putreg16(ATIM_BDTR_MOE, (TMR_REG(STM32_ATIM_BDTR_OFFSET)));
 	}
 
-	long p  = freqs == 0 ? p1s : p1s / freqs;
+	long p = freqs == 0 ? p1s : p1s / freqs;
 	putreg32(p, TMR_REG(STM32_BTIM_ARR_OFFSET));
 
-	p  = freqs == 0 ? p1s + 1 : p0p5s / freqs;
+	p = freqs == 0 ? p1s + 1 : p0p5s / freqs;
 
 	putreg32((r * p) / 255, TMR_REG(STM32_GTIM_CCR1_OFFSET));
 	putreg32((g * p) / 255, TMR_REG(STM32_GTIM_CCR2_OFFSET));
@@ -120,5 +116,4 @@ void rgb_led(int r, int g, int b, int freqs)
 	}
 
 	putreg16(val, TMR_REG(STM32_BTIM_CR1_OFFSET));
-
 }

boards/ark/cannode/src/spi.cpp

@@ -31,18 +31,21 @@
  *
  ****************************************************************************/
 
-#include <px4_arch/spi_hw_description.h>
 #include <drivers/drv_sensor.h>
 #include <nuttx/spi/spi.h>
+#include <px4_arch/spi_hw_description.h>
 
 constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
-	initSPIBus(SPI::Bus::SPI1, {
-		initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortA, GPIO::Pin4}, SPI::DRDY{GPIO::PortB, GPIO::Pin2}),
-	}),
-	initSPIBusExternal(SPI::Bus::SPI2, {
-		initSPIConfigExternal(SPI::CS{GPIO::PortB, GPIO::Pin12}),
-		initSPIConfigExternal(SPI::CS{GPIO::PortC, GPIO::Pin13}),
-	}),
+	initSPIBus(SPI::Bus::SPI1,
+		   {
+			   initSPIDevice(DRV_IMU_DEVTYPE_ICM42688P, SPI::CS{GPIO::PortA, GPIO::Pin4},
+					 SPI::DRDY{GPIO::PortB, GPIO::Pin2}),
+		   }),
+	initSPIBusExternal(SPI::Bus::SPI2,
+			   {
+				   initSPIConfigExternal(SPI::CS{GPIO::PortB, GPIO::Pin12}),
+				   initSPIConfigExternal(SPI::CS{GPIO::PortC, GPIO::Pin13}),
+			   }),
 };
 
 static constexpr bool unused = validateSPIConfig(px4_spi_buses);

boards/ark/cannode/src/timer_config.cpp

@@ -34,9 +34,8 @@
 #include <px4_arch/io_timer_hw_description.h>
 
 constexpr io_timers_t io_timers[MAX_IO_TIMERS] = {
-	initIOTimer(Timer::Timer2),
-	initIOTimer(Timer::Timer3),
-	//initIOTimer(Timer::Timer4),
+	initIOTimer(Timer::Timer2), initIOTimer(Timer::Timer3),
+	// initIOTimer(Timer::Timer4),
 };
 
 constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
@@ -46,8 +45,8 @@ constexpr timer_io_channels_t timer_io_channels[MAX_TIMER_IO_CHANNELS] = {
 	initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel1}, {GPIO::PortB, GPIO::Pin4}),
 	initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel2}, {GPIO::PortB, GPIO::Pin5}),
 	initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel3}, {GPIO::PortB, GPIO::Pin0}),
-	//initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel4}, {GPIO::PortB, GPIO::Pin1}),
-	//initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel2}, {GPIO::PortB, GPIO::Pin7}),
+	// initIOTimerChannel(io_timers, {Timer::Timer3, Timer::Channel4}, {GPIO::PortB, GPIO::Pin1}),
+	// initIOTimerChannel(io_timers, {Timer::Timer4, Timer::Channel2}, {GPIO::PortB, GPIO::Pin7}),
 };
 
 constexpr io_timers_channel_mapping_t io_timers_channel_mapping =

boards/atl/mantis-edu/nuttx-config/include/board.h

@@ -38,12 +38,12 @@
 /************************************************************************************
  * Included Files
  ************************************************************************************/
-#include "board_dma_map.h"
-
 #include <nuttx/config.h>
 
+#include "board_dma_map.h"
+
 #ifndef __ASSEMBLY__
-# include <stdint.h>
+#include <stdint.h>
 #endif
 
 #include "stm32_rcc.h"
@@ -64,12 +64,12 @@
  *   HSE: 16 MHz crystal for HSE
  */
 
-#define STM32_BOARD_XTAL        16000000ul
+#define STM32_BOARD_XTAL 16000000ul
 
-#define STM32_HSI_FREQUENCY     16000000ul
-#define STM32_LSI_FREQUENCY     32000
-#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
-#define STM32_LSE_FREQUENCY     0
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 0
 
 /* Main PLL Configuration.
  *
@@ -103,59 +103,57 @@
  * SYSCLK  = 432 MHz / 2 = 216 MHz
  * USB OTG FS, SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
  */
-#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(216)
-#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
-#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(9)
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
 
-#define STM32_VCO_FREQUENCY     ((STM32_HSE_FREQUENCY / 8) * 216)
-#define STM32_SYSCLK_FREQUENCY  (STM32_VCO_FREQUENCY / 2)
-#define STM32_OTGFS_FREQUENCY   (STM32_VCO_FREQUENCY / 9)
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 216)
+#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
 
 /* Configure factors for  PLLSAI clock */
 #define CONFIG_STM32F7_PLLSAI 1
-#define STM32_RCC_PLLSAICFGR_PLLSAIN    RCC_PLLSAICFGR_PLLSAIN(192)
-#define STM32_RCC_PLLSAICFGR_PLLSAIP    RCC_PLLSAICFGR_PLLSAIP(8)
-#define STM32_RCC_PLLSAICFGR_PLLSAIQ    RCC_PLLSAICFGR_PLLSAIQ(4)
-#define STM32_RCC_PLLSAICFGR_PLLSAIR    RCC_PLLSAICFGR_PLLSAIR(2)
+#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
+#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
+#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
+#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
 
 /* Configure Dedicated Clock Configuration Register */
-#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ  RCC_DCKCFGR1_PLLI2SDIVQ(1)
-#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ  RCC_DCKCFGR1_PLLSAIDIVQ(1)
-#define STM32_RCC_DCKCFGR1_PLLSAIDIVR  RCC_DCKCFGR1_PLLSAIDIVR(0)
-#define STM32_RCC_DCKCFGR1_SAI1SRC     RCC_DCKCFGR1_SAI1SEL(0)
-#define STM32_RCC_DCKCFGR1_SAI2SRC     RCC_DCKCFGR1_SAI2SEL(0)
-#define STM32_RCC_DCKCFGR1_TIMPRESRC   0
-#define STM32_RCC_DCKCFGR1_DFSDM1SRC   0
-#define STM32_RCC_DCKCFGR1_ADFSDM1SRC  0
-
+#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
+#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
+#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
+#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
+#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
+#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
 
 /* Configure factors for  PLLI2S clock */
 #define CONFIG_STM32F7_PLLI2S 1
-#define STM32_RCC_PLLI2SCFGR_PLLI2SN   RCC_PLLI2SCFGR_PLLI2SN(192)
-#define STM32_RCC_PLLI2SCFGR_PLLI2SP   RCC_PLLI2SCFGR_PLLI2SP(2)
-#define STM32_RCC_PLLI2SCFGR_PLLI2SQ   RCC_PLLI2SCFGR_PLLI2SQ(2)
-#define STM32_RCC_PLLI2SCFGR_PLLI2SR   RCC_PLLI2SCFGR_PLLI2SR(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
 
 /* Configure Dedicated Clock Configuration Register 2 */
-#define STM32_RCC_DCKCFGR2_USART1SRC  RCC_DCKCFGR2_USART1SEL_APB
-#define STM32_RCC_DCKCFGR2_USART2SRC  RCC_DCKCFGR2_USART2SEL_APB
-#define STM32_RCC_DCKCFGR2_UART4SRC   RCC_DCKCFGR2_UART4SEL_APB
-#define STM32_RCC_DCKCFGR2_UART5SRC   RCC_DCKCFGR2_UART5SEL_APB
-#define STM32_RCC_DCKCFGR2_USART6SRC  RCC_DCKCFGR2_USART6SEL_APB
-#define STM32_RCC_DCKCFGR2_UART7SRC   RCC_DCKCFGR2_UART7SEL_APB
-#define STM32_RCC_DCKCFGR2_UART8SRC   RCC_DCKCFGR2_UART8SEL_APB
-#define STM32_RCC_DCKCFGR2_I2C1SRC    RCC_DCKCFGR2_I2C1SEL_HSI
-#define STM32_RCC_DCKCFGR2_I2C2SRC    RCC_DCKCFGR2_I2C2SEL_HSI
-#define STM32_RCC_DCKCFGR2_I2C3SRC    RCC_DCKCFGR2_I2C3SEL_HSI
-#define STM32_RCC_DCKCFGR2_I2C4SRC    RCC_DCKCFGR2_I2C4SEL_HSI
-#define STM32_RCC_DCKCFGR2_LPTIM1SRC  RCC_DCKCFGR2_LPTIM1SEL_APB
-#define STM32_RCC_DCKCFGR2_CECSRC     RCC_DCKCFGR2_CECSEL_HSI
-#define STM32_RCC_DCKCFGR2_CK48MSRC   RCC_DCKCFGR2_CK48MSEL_PLL
-#define STM32_RCC_DCKCFGR2_SDMMCSRC   RCC_DCKCFGR2_SDMMCSEL_48MHZ
-#define STM32_RCC_DCKCFGR2_SDMMC2SRC  RCC_DCKCFGR2_SDMMC2SEL_48MHZ
-#define STM32_RCC_DCKCFGR2_DSISRC     RCC_DCKCFGR2_DSISEL_PHY
-
+#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
+#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
+#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
+#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
+#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
+#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
+#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
+#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
+#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
+#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
+#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
 
 /* Several prescalers allow the configuration of the two AHB buses, the
  * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
@@ -165,35 +163,35 @@
  */
 
 /* AHB clock (HCLK) is SYSCLK (216 MHz) */
-#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK  /* HCLK  = SYSCLK / 1 */
-#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
-#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
 
 /* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
-#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4     /* PCLK1 = HCLK / 4 */
-#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/4)
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
+#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 4)
 
 /* Timers driven from APB1 will be twice PCLK1 */
-#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
 
 /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
-#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2     /* PCLK2 = HCLK / 2 */
-#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
+#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
 
 /* Timers driven from APB2 will be twice PCLK2 */
-#define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM9_CLKIN   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM10_CLKIN  (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM11_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY)
 
 /* SDMMC dividers.  Note that slower clocking is required when DMA is disabled
  * in order to avoid RX overrun/TX underrun errors due to delayed responses
@@ -209,27 +207,27 @@
 
 #define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
 
-#define STM32_SDMMC_INIT_CLKDIV         (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 
 /* DMA ON:  SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
  * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
  */
 
 #ifdef CONFIG_STM32F7_SDMMC_DMA
-#  define STM32_SDMMC_MMCXFR_CLKDIV     (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #else
-#  define STM32_SDMMC_MMCXFR_CLKDIV     (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #endif
 
 /* DMA ON:  SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
  * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
  */
-//TODO #warning "Check Freq for 24mHz"
+// TODO #warning "Check Freq for 24mHz"
 
 #ifdef CONFIG_STM32F7_SDMMC_DMA
-#  define STM32_SDMMC_SDXFR_CLKDIV      (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #else
-#  define STM32_SDMMC_SDXFR_CLKDIV      (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #endif
 
 /* FLASH wait states
@@ -248,14 +246,14 @@
 
 /* LED index values for use with board_userled() */
 
-#define BOARD_LED1        0
-#define BOARD_LED2        1
-#define BOARD_LED3        2
-#define BOARD_NLEDS       3
+#define BOARD_LED1 0
+#define BOARD_LED2 1
+#define BOARD_LED3 2
+#define BOARD_NLEDS 3
 
-#define BOARD_LED_RED     BOARD_LED1
-#define BOARD_LED_GREEN   BOARD_LED2
-#define BOARD_LED_BLUE    BOARD_LED3
+#define BOARD_LED_RED BOARD_LED1
+#define BOARD_LED_GREEN BOARD_LED2
+#define BOARD_LED_BLUE BOARD_LED3
 
 /* Thus if the Green LED is statically on, NuttX has successfully booted and
  * is, apparently, running normally.  If the Red LED is flashing at
@@ -265,32 +263,32 @@
 
 /* Alternate function pin selections ************************************************/
 
-#define GPIO_USART1_RX   GPIO_USART1_RX_2   /* PB7  */
-#define GPIO_USART1_TX   GPIO_USART1_TX_2   /* PB6  */
+#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7  */
+#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6  */
 
-#define GPIO_USART2_RX   GPIO_USART2_RX_2   /* PD6  */
-#define GPIO_USART2_TX   GPIO_USART2_TX_2   /* PD5  */
-#define GPIO_USART2_RTS  GPIO_USART2_RTS_2  /* PD4  */
-#define GPIO_USART2_CTS  GPIO_USART2_CTS_2  /* PD3  */
+#define GPIO_USART2_RX GPIO_USART2_RX_2   /* PD6  */
+#define GPIO_USART2_TX GPIO_USART2_TX_2   /* PD5  */
+#define GPIO_USART2_RTS GPIO_USART2_RTS_2 /* PD4  */
+#define GPIO_USART2_CTS GPIO_USART2_CTS_2 /* PD3  */
 
-#define GPIO_USART3_RX   GPIO_USART3_RX_3   /* PD9  */
-#define GPIO_USART3_TX   GPIO_USART3_TX_3   /* PD8  */
-#define GPIO_USART3_RTS  GPIO_USART3_RTS_2  /* PD12 */
-#define GPIO_USART3_CTS  GPIO_USART3_CTS_2  /* PD11 */
+#define GPIO_USART3_RX GPIO_USART3_RX_3   /* PD9  */
+#define GPIO_USART3_TX GPIO_USART3_TX_3   /* PD8  */
+#define GPIO_USART3_RTS GPIO_USART3_RTS_2 /* PD12 */
+#define GPIO_USART3_CTS GPIO_USART3_CTS_2 /* PD11 */
 
-#define GPIO_UART4_RX    GPIO_UART4_RX_4    /* PD0  */
-#define GPIO_UART4_TX    GPIO_UART4_TX_4    /* PD1  */
+#define GPIO_UART4_RX GPIO_UART4_RX_4 /* PD0  */
+#define GPIO_UART4_TX GPIO_UART4_TX_4 /* PD1  */
 
-#define GPIO_UART5_RX    GPIO_UART5_RX_3    /* PB12 */
-#define GPIO_UART5_TX    GPIO_UART5_TX_3    /* PB13 */
+#define GPIO_UART5_RX GPIO_UART5_RX_3 /* PB12 */
+#define GPIO_UART5_TX GPIO_UART5_TX_3 /* PB13 */
 
-#define GPIO_USART6_RX   GPIO_USART6_RX_2   /* PG9  */
-#define GPIO_USART6_TX   GPIO_USART6_TX_2   /* PG14 */
-#define GPIO_USART6_RTS  GPIO_USART6_RTS_2  /* PG8  */
-#define GPIO_USART6_CTS  GPIO_USART6_CTS_2  /* PG15 */
+#define GPIO_USART6_RX GPIO_USART6_RX_2   /* PG9  */
+#define GPIO_USART6_TX GPIO_USART6_TX_2   /* PG14 */
+#define GPIO_USART6_RTS GPIO_USART6_RTS_2 /* PG8  */
+#define GPIO_USART6_CTS GPIO_USART6_CTS_2 /* PG15 */
 
-#define GPIO_UART7_RX    GPIO_UART7_RX_2    /* PF6  */
-#define GPIO_UART7_TX    GPIO_UART7_TX_1    /* PE8  */
+#define GPIO_UART7_RX GPIO_UART7_RX_2 /* PF6  */
+#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE8  */
 
 /* USART8: has no remap
  *
@@ -298,23 +296,21 @@
  *      GPIO_UART8_TX                          PE1[CN11-61]
  */
 
-
 /* SPI */
-#define GPIO_SPI1_MISO   GPIO_SPI1_MISO_1   /* PA6 */
-#define GPIO_SPI1_MOSI   GPIO_SPI1_MOSI_3   /* PD7 */
-#define GPIO_SPI1_SCK    GPIO_SPI1_SCK_3    /* PG11 */
-
-#define GPIO_SPI4_MISO   GPIO_SPI4_MISO_2   /* PE13 */
-#define GPIO_SPI4_MOSI   GPIO_SPI4_MOSI_1   /* PE6 */
-#define GPIO_SPI4_SCK    GPIO_SPI4_SCK_1    /* PE2 */
+#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
+#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_3 /* PD7 */
+#define GPIO_SPI1_SCK GPIO_SPI1_SCK_3   /* PG11 */
 
+#define GPIO_SPI4_MISO GPIO_SPI4_MISO_2 /* PE13 */
+#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE6 */
+#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1   /* PE2 */
 
 /* I2C */
-#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2       /* PF1  */
-#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2       /* PF0  */
+#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 /* PF1  */
+#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 /* PF0  */
 
-#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2       /* PF14 */
-#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2       /* PF15 */
+#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2 /* PF14 */
+#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2 /* PF15 */
 
 /* SDMMC1
  *
@@ -329,4 +325,4 @@
  *      GPIO_SDMMC1_NCD                     PG0
  */
 
-#endif  /*__NUTTX_CONFIG_PX4_FMU_V5_INCLUDE_BOARD_H  */
+#endif /*__NUTTX_CONFIG_PX4_FMU_V5_INCLUDE_BOARD_H  */

boards/atl/mantis-edu/nuttx-config/include/board_dma_map.h

@@ -34,47 +34,58 @@
 #pragma once
 
 /*
-|    DMA1    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5         | Stream 6         | Stream 7         |
+|    DMA1    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5
+| Stream 6         | Stream 7         |
 |------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
-| Channel 0  | SPI3_RX_1        | SPDIFRX_DT       | SPI3_RX_2        | SPI2_RX          | SPI2_TX          | SPI3_TX_1        | SPDIFRX_CS       | SPI3_TX_2        |
-| Channel 1  | I2C1_RX          | I2C3_RX          | TIM7_UP_1        | -                | TIM7_UP_2        |  I2C1_RX_1       | I2C1_TX          | I2C1_TX_1        |
-| Channel 2  | TIM4_CH1         | -                | I2C4_RX          | TIM4_CH2         | -                | I2C4_TX          | TIM4_UP          | TIM4_CH3         |
-| Channel 3  | -                | TIM2_UP_1        | I2C3_RX_1        | -                | I2C3_TX          | TIM2_CH1         | TIM2_CH2         | TIM2_UP_2        |
-|            |                  |   TIM2_CH3       |                  |                  |                  |                  |   TIM2_CH4_1     |   TIM2_CH4_2     |
-| Channel 4  | UART5_RX         | USART3_RX        | UART4_RX         | USART3_TX_1      | UART4_TX         | USART2_RX        | USART2_TX        | UART5_TX         |
-| Channel 5  | UART8_TX         | UART7_TX         | TIM3_CH4         | UART7_RX         | TIM3_CH1         | TIM3_CH2         | UART8_RX         | TIM3_CH3         |
-|            |                  |                  |   TIM3_UP        |                  |   TIM3_TRIG      |                  |                  |                  |
-| Channel 6  | TIM5_CH3         | TIM5_CH4_1       | TIM5_CH1         | TIM5_CH4_2       | TIM5_CH2         | -                | TIM5_UP_2        | -                |
-|            |   TIM5_UP_1      |   TIM5_TRIG_1    |                  |   TIM5_TRIG_2    |                  |                  |                  |                  |
-| Channel 7  | -                | TIM6_UP          | I2C2_RX          | I2C2_RX_1        | USART3_TX_2      | DAC1             | DAC2             | I2C2_TX          |
-| Channel 8  | I2C3_TX_1        | I2C4_RX_1        | -                | -                | I2C2_TX_1        | -                | I2C4_TX_1        | -                |
-| Channel 9  | -                | SPI2_RX          | -                | -                | -                | -                | SPI2_TX          | -                |
-|            |                  |                  |                  |                  |                  |                  |                  |                  |
-| Usage      | UART8_TX         | USART3_RX        | UART4_RX         | USART3_TX_1      |                  | USART2_RX        | UART8_RX         |                  |
+| Channel 0  | SPI3_RX_1        | SPDIFRX_DT       | SPI3_RX_2        | SPI2_RX          | SPI2_TX          | SPI3_TX_1
+| SPDIFRX_CS       | SPI3_TX_2        | | Channel 1  | I2C1_RX          | I2C3_RX          | TIM7_UP_1        | - |
+TIM7_UP_2        |  I2C1_RX_1       | I2C1_TX          | I2C1_TX_1        | | Channel 2  | TIM4_CH1         | - |
+I2C4_RX          | TIM4_CH2         | -                | I2C4_TX          | TIM4_UP          | TIM4_CH3         | |
+Channel 3  | -                | TIM2_UP_1        | I2C3_RX_1        | -                | I2C3_TX          | TIM2_CH1 |
+TIM2_CH2         | TIM2_UP_2        | |            |                  |   TIM2_CH3       |                  | | | |
+TIM2_CH4_1     |   TIM2_CH4_2     | | Channel 4  | UART5_RX         | USART3_RX        | UART4_RX         | USART3_TX_1
+| UART4_TX         | USART2_RX        | USART2_TX        | UART5_TX         | | Channel 5  | UART8_TX         | UART7_TX
+| TIM3_CH4         | UART7_RX         | TIM3_CH1         | TIM3_CH2         | UART8_RX         | TIM3_CH3         | | |
+|                  |   TIM3_UP        |                  |   TIM3_TRIG      |                  |                  | | |
+Channel 6  | TIM5_CH3         | TIM5_CH4_1       | TIM5_CH1         | TIM5_CH4_2       | TIM5_CH2         | - |
+TIM5_UP_2        | -                | |            |   TIM5_UP_1      |   TIM5_TRIG_1    |                  |
+TIM5_TRIG_2    |                  |                  |                  |                  | | Channel 7  | - | TIM6_UP
+| I2C2_RX          | I2C2_RX_1        | USART3_TX_2      | DAC1             | DAC2             | I2C2_TX          | |
+Channel 8  | I2C3_TX_1        | I2C4_RX_1        | -                | -                | I2C2_TX_1        | - |
+I2C4_TX_1        | -                | | Channel 9  | -                | SPI2_RX          | -                | - | - | -
+| SPI2_TX          | -                | |            |                  |                  |                  | | | | |
+| | Usage      | UART8_TX         | USART3_RX        | UART4_RX         | USART3_TX_1      |                  |
+USART2_RX        | UART8_RX         |                  |
 
 
-|    DMA2    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5         | Stream 6         | Stream 7         |
+|    DMA2    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5
+| Stream 6         | Stream 7         |
 |------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
-| Channel 0  | ADC1_1           | SAI1_A           | TIM8_CH1_1       | SAI1_A_2         | ADC1_2           | SAI1_B_1         | TIM1_CH1_1       | SAI1_B_2         |
-|            |                  |                  |   TIM8_CH2_1     |                  |                  |                  |   TIM1_CH2_1     |                  |
-|            |                  |                  |   TIM8_CH3_1     |                  |                  |                  |   TIM1_CH3_1     |                  |
-| Channel 1  | -                | DCMI_1           | ADC2_1           | ADC2_2           | SAI1_B           | SPI6_TX          | SPI6_RX          | DCMI_2           |
-| Channel 2  | ADC3_1           | ADC3_2           | -                | SPI5_RX_1        | SPI5_TX_1        | CRYP_OUT         | CRYP_IN          | HASH_IN          |
-| Channel 3  | SPI1_RX_1        | -                | SPI1_RX_2        | SPI1_TX_1        | SAI2_A           | SPI1_TX_2        | SAI2_B           | QUADSPI          |
-| Channel 4  | SPI4_RX_1        | SPI4_TX_1        | USART1_RX_1      | SDMMC1_1         | -                | USART1_RX_2      | SDMMC1_2         | USART1_TX        |
-| Channel 5  | -                | USART6_RX_1      | USART6_RX_2      | SPI4_RX_2        | SPI4_TX_2        | -                | USART6_TX_1      | USART6_TX_2      |
-| Channel 6  | TIM1_TRIG_1      | TIM1_CH1_2       | TIM1_CH2_2       | TIM1_CH1         | TIM1_CH4         | TIM1_UP          | TIM1_CH3_2       | -                |
-|            |                  |                  |                  |                  |   TIM1_TRIG_2    |                  |                  |                  |
-|            |                  |                  |                  |                  |   TIM1_COM       |                  |                  |                  |
-| Channel 7  | -                | TIM8_UP          | TIM8_CH1_2       | TIM8_CH2_2       | TIM8_CH3_2       | SPI5_RX_2        | SPI5_TX_2        | TIM8_CH4         |
-|            |                  |                  |                  |                  |                  |                  |                  |   TIM8_TRIG      |
-|            |                  |                  |                  |                  |                  |                  |                  |   TIM8_COM       |
-| Channel 8  | DFSDM1_FLT0_1    | DFSDM1_FLT1_1    | DFSDM1_FLT2_1    | DFSDM1_FLT3_1    | DFSDM1_FLT0_2    | DFSDM1_FLT1_2    | DFSDM1_FLT2_2    | DFSDM1_FLT3_2    |
-| Channel 9  | JPEG_IN_1        | JPEG_OUT         | SPI4_TX_3        | JPEG_IN_2        | JPEG_OUT_2       | SPI5_RX_3        | -                | -                |
-| Channel 10 | SAI1_B_3         | SAI2_B_1         | SAI2_A_1         | -                | -                | -                | SAI1_A_3         | -                |
-| Channel 11 | SDMMC2_1         | -                | QUADSPI_1        | -                | -                | SDMMC2_2         | -                | -                |
-|            |                  |                  |                  |                  |                  |                  |                  |                  |
-| Usage      | SPI1_RX_1        |                  | USART6_RX_2      | SPI1_TX_1        |                  | TIM1_UP          | SDMMC1_2         |                  |
+| Channel 0  | ADC1_1           | SAI1_A           | TIM8_CH1_1       | SAI1_A_2         | ADC1_2           | SAI1_B_1
+| TIM1_CH1_1       | SAI1_B_2         | |            |                  |                  |   TIM8_CH2_1     | | | |
+TIM1_CH2_1     |                  | |            |                  |                  |   TIM8_CH3_1     | | | |
+TIM1_CH3_1     |                  | | Channel 1  | -                | DCMI_1           | ADC2_1           | ADC2_2 |
+SAI1_B           | SPI6_TX          | SPI6_RX          | DCMI_2           | | Channel 2  | ADC3_1           | ADC3_2 | -
+| SPI5_RX_1        | SPI5_TX_1        | CRYP_OUT         | CRYP_IN          | HASH_IN          | | Channel 3  |
+SPI1_RX_1        | -                | SPI1_RX_2        | SPI1_TX_1        | SAI2_A           | SPI1_TX_2        | SAI2_B
+| QUADSPI          | | Channel 4  | SPI4_RX_1        | SPI4_TX_1        | USART1_RX_1      | SDMMC1_1         | - |
+USART1_RX_2      | SDMMC1_2         | USART1_TX        | | Channel 5  | -                | USART6_RX_1      |
+USART6_RX_2      | SPI4_RX_2        | SPI4_TX_2        | -                | USART6_TX_1      | USART6_TX_2      | |
+Channel 6  | TIM1_TRIG_1      | TIM1_CH1_2       | TIM1_CH2_2       | TIM1_CH1         | TIM1_CH4         | TIM1_UP |
+TIM1_CH3_2       | -                | |            |                  |                  |                  | |
+TIM1_TRIG_2    |                  |                  |                  | |            |                  | | | |
+TIM1_COM       |                  |                  |                  | | Channel 7  | -                | TIM8_UP |
+TIM8_CH1_2       | TIM8_CH2_2       | TIM8_CH3_2       | SPI5_RX_2        | SPI5_TX_2        | TIM8_CH4         | | | |
+|                  |                  |                  |                  |                  |   TIM8_TRIG      | | |
+|                  |                  |                  |                  |                  |                  |
+TIM8_COM       | | Channel 8  | DFSDM1_FLT0_1    | DFSDM1_FLT1_1    | DFSDM1_FLT2_1    | DFSDM1_FLT3_1    |
+DFSDM1_FLT0_2    | DFSDM1_FLT1_2    | DFSDM1_FLT2_2    | DFSDM1_FLT3_2    | | Channel 9  | JPEG_IN_1        | JPEG_OUT
+| SPI4_TX_3        | JPEG_IN_2        | JPEG_OUT_2       | SPI5_RX_3        | -                | -                | |
+Channel 10 | SAI1_B_3         | SAI2_B_1         | SAI2_A_1         | -                | -                | - | SAI1_A_3
+| -                | | Channel 11 | SDMMC2_1         | -                | QUADSPI_1        | -                | - |
+SDMMC2_2         | -                | -                | |            |                  |                  | | | | | |
+| | Usage      | SPI1_RX_1        |                  | USART6_RX_2      | SPI1_TX_1        |                  | TIM1_UP
+| SDMMC1_2         |                  |
  */
 
 // DMA1 Channel/Stream Selections
@@ -82,18 +93,17 @@
 //      DMAMAP_UART8_TX                       // DMA1, Stream 0, Channel 5    (PX4IO TX)
 //      DMAMAP_USART3_RX                      // DMA1, Stream 1, Channel 4    (TELEM2 RX)
 //      DMAMAP_UART4_RX                       // DMA1, Stream 2, Channel 4    (TELEM4 RX)
-#define DMAMAP_USART3_TX  DMAMAP_USART3_TX_1  // DMA1, Stream 3, Channel 4    (TELEM2 TX)
+#define DMAMAP_USART3_TX DMAMAP_USART3_TX_1  // DMA1, Stream 3, Channel 4    (TELEM2 TX)
 //      DMAMAP_USART2_RX                      // DMA1, Stream 5, Channel 4    (TELEM1 RX)
 //      DMAMAP_UART8_RX                       // DMA1, Stream 6, Channel 5    (PX4IO RX)
 
-
 //  DMA2 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
-#define DMAMAP_SPI1_RX    DMAMAP_SPI1_RX_1    // DMA2, Stream 0, Channel 3    (SPI sensors RX)
+#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1  // DMA2, Stream 0, Channel 3    (SPI sensors RX)
 //      AVAILABLE                             // DMA2, Stream 1
-#define DMAMAP_USART6_RX  DMAMAP_USART6_RX_2  // DMA2, Stream 2, Channel 5
-#define DMAMAP_SPI1_TX    DMAMAP_SPI1_TX_1    // DMA2, Stream 3, Channel 3    (SPI sensors TX)
+#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2  // DMA2, Stream 2, Channel 5
+#define DMAMAP_SPI1_TX DMAMAP_SPI1_TX_1      // DMA2, Stream 3, Channel 3    (SPI sensors TX)
 //      AVAILABLE                             // DMA2, Stream 4
 //      DMAMAP_TIM1_UP                        // DMA2, Stream 5, Channel 6    (DSHOT)
-#define DMAMAP_SDMMC1     DMAMAP_SDMMC1_2     // DMA2, Stream 6, Channel 4
+#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_2  // DMA2, Stream 6, Channel 4
 //      AVAILABLE                             // DMA2, Stream 7

boards/atl/mantis-edu/src/board_config.h

@@ -43,20 +43,22 @@
  * Included Files
  ****************************************************************************************************/
 
-#include <px4_platform_common/px4_config.h>
 #include <nuttx/compiler.h>
+#include <px4_platform_common/px4_config.h>
 #include <stdint.h>
-
 #include <stm32_gpio.h>
 
 /* LEDs are driven with push open drain to support Anode to 5V or 3.3V */
-#define GPIO_nLED_RED        /* PB1 */  (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_nLED_GREEN      /* PC6 */  (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN6)
-#define GPIO_nLED_BLUE       /* PC7 */  (GPIO_OUTPUT|GPIO_OPENDRAIN|GPIO_SPEED_50MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_nLED_RED /* PB1 */ \
+	(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN1)
+#define GPIO_nLED_GREEN /* PC6 */ \
+	(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN6)
+#define GPIO_nLED_BLUE /* PC7 */ \
+	(GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN7)
 
-#define BOARD_HAS_CONTROL_STATUS_LEDS      1
-#define BOARD_OVERLOAD_LED     LED_RED
-#define BOARD_ARMED_STATE_LED  LED_BLUE
+#define BOARD_HAS_CONTROL_STATUS_LEDS 1
+#define BOARD_OVERLOAD_LED LED_RED
+#define BOARD_ARMED_STATE_LED LED_BLUE
 
 #define FLASH_BASED_PARAMS
 #define RAM_BASED_MISSIONS
@@ -75,102 +77,102 @@
  */
 
 /* ADC defines to be used in sensors.cpp to read from a particular channel */
-#define ADC1_CH(n)                  (n)
-#define ADC1_GPIO(n)                GPIO_ADC1_IN##n
+#define ADC1_CH(n) (n)
+#define ADC1_GPIO(n) GPIO_ADC1_IN##n
 
 /* Define GPIO pins used as ADC N.B. Channel numbers must match below */
 
-#define PX4_ADC_GPIO  \
-	/* PA0 */  ADC1_GPIO(0),  \
-	/* PC0 */  ADC1_GPIO(10), \
-	/* PC1 */  ADC1_GPIO(11), \
-	/* PC2 */  ADC1_GPIO(12), \
-	/* PC3 */  ADC1_GPIO(13), \
-	/* PC4 */  ADC1_GPIO(14)
+#define PX4_ADC_GPIO                                                                                       \
+	/* PA0 */ ADC1_GPIO(0), /* PC0 */ ADC1_GPIO(10), /* PC1 */ ADC1_GPIO(11), /* PC2 */ ADC1_GPIO(12), \
+		/* PC3 */ ADC1_GPIO(13), /* PC4 */ ADC1_GPIO(14)
 
 /* Define Channel numbers must match above GPIO pin IN(n)*/
-#define ADC_BATTERY_VOLTAGE_CHANNEL         /* PA0 */  ADC1_CH(0)
+#define ADC_BATTERY_VOLTAGE_CHANNEL /* PA0 */ ADC1_CH(0)
 #define ADC_BATTERY_CURRENT_CHANNEL 0
-#define ADC_SCALED_V5_CHANNEL               /* PC0 */  ADC1_CH(10)
-#define ADC_SCALED_VDD_3V3_SENSORS_CHANNEL  /* PC1 */  ADC1_CH(11)
-#define ADC_HW_VER_SENSE_CHANNEL            /* PC2 */  ADC1_CH(12)
-#define ADC_HW_REV_SENSE_CHANNEL            /* PC3 */  ADC1_CH(13)
-#define ADC1_SPARE_1_CHANNEL                /* PC4 */  ADC1_CH(14) // POWER_AD
+#define ADC_SCALED_V5_CHANNEL /* PC0 */ ADC1_CH(10)
+#define ADC_SCALED_VDD_3V3_SENSORS_CHANNEL /* PC1 */ ADC1_CH(11)
+#define ADC_HW_VER_SENSE_CHANNEL /* PC2 */ ADC1_CH(12)
+#define ADC_HW_REV_SENSE_CHANNEL /* PC3 */ ADC1_CH(13)
+#define ADC1_SPARE_1_CHANNEL /* PC4 */ ADC1_CH(14)  // POWER_AD
 
-#define ADC_CHANNELS \
-	((1 << ADC_BATTERY_VOLTAGE_CHANNEL)        | \
-	 (1 << ADC_SCALED_V5_CHANNEL)              | \
-	 (1 << ADC_SCALED_VDD_3V3_SENSORS_CHANNEL) | \
-	 (1 << ADC_HW_VER_SENSE_CHANNEL)           | \
-	 (1 << ADC_HW_REV_SENSE_CHANNEL)           | \
-	 (1 << ADC1_SPARE_1_CHANNEL))
+#define ADC_CHANNELS                                                                   \
+	((1 << ADC_BATTERY_VOLTAGE_CHANNEL) | (1 << ADC_SCALED_V5_CHANNEL) |           \
+	 (1 << ADC_SCALED_VDD_3V3_SENSORS_CHANNEL) | (1 << ADC_HW_VER_SENSE_CHANNEL) | \
+	 (1 << ADC_HW_REV_SENSE_CHANNEL) | (1 << ADC1_SPARE_1_CHANNEL))
 
 /* HW has to large of R termination on ADC todo:change when HW value is chosen */
-#define BOARD_ADC_OPEN_CIRCUIT_V     (5.6f)
+#define BOARD_ADC_OPEN_CIRCUIT_V (5.6f)
 
 /* HW Version and Revision drive signals Default to 1 to detect */
 #define BOARD_HAS_HW_VERSIONING
 
-#define GPIO_HW_REV_DRIVE    /* PH14  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTH|GPIO_PIN14)
-#define GPIO_HW_REV_SENSE    /* PC3   */ ADC1_GPIO(13)
-#define GPIO_HW_VER_DRIVE    /* PG0   */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTG|GPIO_PIN0)
-#define GPIO_HW_VER_SENSE    /* PC2   */ ADC1_GPIO(12)
-#define HW_INFO_INIT_PREFIX    "VAM"
+#define GPIO_HW_REV_DRIVE /* PH14  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN14)
+#define GPIO_HW_REV_SENSE /* PC3   */ ADC1_GPIO(13)
+#define GPIO_HW_VER_DRIVE /* PG0   */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTG | GPIO_PIN0)
+#define GPIO_HW_VER_SENSE /* PC2   */ ADC1_GPIO(12)
+#define HW_INFO_INIT \
+	{ 'V', '5', 'x', 'x', 0 }
+#define HW_INFO_INIT_VER 2
+#define HW_INFO_INIT_REV 3
 
-#define BOARD_TAP_ESC_MODE 2 // select closed-loop control mode for the esc
+#define BOARD_TAP_ESC_MODE 2  // select closed-loop control mode for the esc
 // #define BOARD_USE_ESC_CURRENT_REPORT
 
 // LED mapping
 #define BOARD_FRONT_LED_MASK (1 << 0) | (1 << 3)
-#define BOARD_REAR_LED_MASK  (1 << 1) | (1 << 2)
+#define BOARD_REAR_LED_MASK (1 << 1) | (1 << 2)
 
 /* HEATER */
-#define GPIO_HEATER_OUTPUT   /* PA7  T14CH1 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_HEATER_OUTPUT /* PA7  T14CH1 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN7)
 
-#define BOARD_HAS_LED_PWM              1
+#define BOARD_HAS_LED_PWM 1
 #define BOARD_LED_PWM_DRIVE_ACTIVE_LOW 1
 
 #define BOARD_UI_LED_PWM_DRIVE_ACTIVE_LOW 1
 
-#define BOARD_ADC_BRICK_VALID           1
-#define BOARD_NUMBER_BRICKS             1
+#define BOARD_ADC_BRICK_VALID 1
+#define BOARD_NUMBER_BRICKS 1
 
-#define GPIO_VDD_3V3_SD_CARD_EN         /* PG7  */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTG|GPIO_PIN7)
-#define VDD_3V3_SD_CARD_EN(on_true)        px4_arch_gpiowrite(GPIO_VDD_3V3_SD_CARD_EN, (on_true))
+#define GPIO_VDD_3V3_SD_CARD_EN /* PG7  */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTG | GPIO_PIN7)
+#define VDD_3V3_SD_CARD_EN(on_true) px4_arch_gpiowrite(GPIO_VDD_3V3_SD_CARD_EN, (on_true))
 
 /* USB OTG FS */
-#define GPIO_OTGFS_VBUS         /* PA9 */ (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_100MHz|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_OTGFS_VBUS /* PA9 */ (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_100MHz | GPIO_PORTA | GPIO_PIN9)
 
 /* High-resolution timer */
-#define HRT_TIMER               8  /* use timer8 for the HRT */
-#define HRT_TIMER_CHANNEL       3  /* use capture/compare channel 3 */
+#define HRT_TIMER 8         /* use timer8 for the HRT */
+#define HRT_TIMER_CHANNEL 3 /* use capture/compare channel 3 */
 
 /* RC Serial port */
-#define RC_SERIAL_PORT                     "/dev/ttyS5"
+#define RC_SERIAL_PORT "/dev/ttyS5"
 #define RC_SERIAL_SINGLEWIRE
 
 /* power on/off */
 #define MS_PWR_BUTTON_DOWN 750
-#define KEY_AD_GPIO    (GPIO_INPUT|GPIO_PULLUP|GPIO_EXTI|GPIO_PORTC|GPIO_PIN4)
-#define POWER_ON_GPIO  (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTC|GPIO_PIN5)
-#define POWER_OFF_GPIO (GPIO_INPUT|GPIO_PULLDOWN|GPIO_PORTC|GPIO_PIN5)
-#define POWER_CHECK_GPIO (GPIO_INPUT|GPIO_PULLUP|GPIO_PORTF|GPIO_PIN0)
+#define KEY_AD_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_EXTI | GPIO_PORTC | GPIO_PIN4)
+#define POWER_ON_GPIO (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTC | GPIO_PIN5)
+#define POWER_OFF_GPIO (GPIO_INPUT | GPIO_PULLDOWN | GPIO_PORTC | GPIO_PIN5)
+#define POWER_CHECK_GPIO (GPIO_INPUT | GPIO_PULLUP | GPIO_PORTF | GPIO_PIN0)
 
-#define SDIO_SLOTNO                    0  /* Only one slot */
-#define SDIO_MINOR                     0
+#define SDIO_SLOTNO 0 /* Only one slot */
+#define SDIO_MINOR 0
 
 /* By Providing BOARD_ADC_USB_CONNECTED (using the px4_arch abstraction)
  * this board support the ADC system_power interface, and therefore
  * provides the true logic GPIO BOARD_ADC_xxxx macros.
  */
 #define BOARD_ADC_USB_CONNECTED (px4_arch_gpioread(GPIO_OTGFS_VBUS))
-#define BOARD_ADC_USB_VALID     BOARD_ADC_USB_CONNECTED
+#define BOARD_ADC_USB_VALID BOARD_ADC_USB_CONNECTED
 
 /* FMUv5 never powers odd the Servo rail */
-#define BOARD_ADC_SERVO_VALID     (1)
+#define BOARD_ADC_SERVO_VALID (1)
 
-#define BOARD_ADC_BRICK1_VALID  (!px4_arch_gpioread(GPIO_nVDD_BRICK1_VALID))
-#define BOARD_ADC_BRICK2_VALID  (0)
+#define BOARD_ADC_BRICK1_VALID (!px4_arch_gpioread(GPIO_nVDD_BRICK1_VALID))
+#define BOARD_ADC_BRICK2_VALID (0)
 
 /* This board provides a DMA pool and APIs */
 #define BOARD_DMA_ALLOC_POOL_SIZE 5120
@@ -179,16 +181,15 @@
 #define BOARD_HAS_ON_RESET 1
 #define BOARD_HAS_POWER_CONTROL 1
 
-#define GPIO_CAM_PWR_ON_H      /* PB0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_SET|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_CAM_PWR_ON_L      /* PB0 */ (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_2MHz|GPIO_OUTPUT_CLEAR|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_CAM_PWR_ON_H /* PB0 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0)
+#define GPIO_CAM_PWR_ON_L /* PB0 */ \
+	(GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHz | GPIO_OUTPUT_CLEAR | GPIO_PORTB | GPIO_PIN0)
 
-#define PX4_GPIO_INIT_LIST { \
-		PX4_ADC_GPIO,                     \
-		GPIO_HW_REV_DRIVE,                \
-		GPIO_HW_VER_DRIVE,                \
-		GPIO_HEATER_OUTPUT,               \
-		GPIO_VDD_3V3_SD_CARD_EN,          \
-		GPIO_OTGFS_VBUS                   \
+#define PX4_GPIO_INIT_LIST                                                                                       \
+	{                                                                                                        \
+		PX4_ADC_GPIO, GPIO_HW_REV_DRIVE, GPIO_HW_VER_DRIVE, GPIO_HEATER_OUTPUT, GPIO_VDD_3V3_SD_CARD_EN, \
+			GPIO_OTGFS_VBUS                                                                          \
 	}
 
 #define BOARD_ENABLE_CONSOLE_BUFFER

boards/atl/mantis-edu/src/init.c

@@ -45,43 +45,42 @@
  * Included Files
  ****************************************************************************/
 
-#include "board_config.h"
-
-#include <stdbool.h>
-#include <stdio.h>
-#include <string.h>
-#include <debug.h>
-#include <errno.h>
-
-#include <nuttx/config.h>
-#include <nuttx/board.h>
-#include <nuttx/spi/spi.h>
-#include <nuttx/sdio.h>
-#include <nuttx/mmcsd.h>
-#include <nuttx/analog/adc.h>
-#include <nuttx/mm/gran.h>
-#include <chip.h>
-#include <stm32_uart.h>
 #include <arch/board/board.h>
-#include "arm_internal.h"
-
-#include <px4_arch/io_timer.h>
-#include <drivers/drv_hrt.h>
+#include <chip.h>
+#include <debug.h>
 #include <drivers/drv_board_led.h>
-#include <systemlib/px4_macros.h>
-#include <px4_platform_common/init.h>
-#include <px4_platform/gpio.h>
+#include <drivers/drv_hrt.h>
+#include <errno.h>
+#include <nuttx/analog/adc.h>
+#include <nuttx/board.h>
+#include <nuttx/config.h>
+#include <nuttx/mm/gran.h>
+#include <nuttx/mmcsd.h>
+#include <nuttx/sdio.h>
+#include <nuttx/spi/spi.h>
+#include <px4_arch/io_timer.h>
 #include <px4_platform/board_determine_hw_info.h>
 #include <px4_platform/board_dma_alloc.h>
+#include <px4_platform/gpio.h>
+#include <px4_platform_common/init.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <stm32_uart.h>
+#include <string.h>
+#include <systemlib/px4_macros.h>
 
-# if defined(FLASH_BASED_PARAMS)
-#  include <parameters/flashparams/flashfs.h>
+#include "arm_internal.h"
+#include "board_config.h"
+
+#if defined(FLASH_BASED_PARAMS)
+#include <parameters/flashparams/flashfs.h>
 #endif
 
 /****************************************************************************
  * Pre-Processor Definitions
  ****************************************************************************/
-#define _GPIO_PULL_DOWN_INPUT(def) (((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT|GPIO_PULLDOWN|GPIO_SPEED_2MHz))
+#define _GPIO_PULL_DOWN_INPUT(def) \
+	(((def) & (GPIO_PORT_MASK | GPIO_PIN_MASK)) | (GPIO_INPUT | GPIO_PULLDOWN | GPIO_SPEED_2MHz))
 
 /* Configuration ************************************************************/
 
@@ -109,8 +108,7 @@ __END_DECLS
  *   Not used
  *
  ************************************************************************************/
-static void cam_pwr_on_pulse(void)
-{
+static void cam_pwr_on_pulse(void) {
 	static bool pwr_on_flag = false;
 
 	if (pwr_on_flag == false) {
@@ -130,9 +128,7 @@ static void cam_pwr_on_pulse(void)
  * Description:
  *
  ************************************************************************************/
-__EXPORT void board_peripheral_reset(int ms)
-{
-}
+__EXPORT void board_peripheral_reset(int ms) {}
 
 /************************************************************************************
  * Name: board_on_reset
@@ -145,9 +141,7 @@ __EXPORT void board_peripheral_reset(int ms)
  *          0 if just resetting
  *
  ************************************************************************************/
-__EXPORT void board_on_reset(int status)
-{
-}
+__EXPORT void board_on_reset(int status) {}
 
 /************************************************************************************
  * Name: stm32_boardinitialize
@@ -159,8 +153,7 @@ __EXPORT void board_on_reset(int status)
  *
  ************************************************************************************/
 
-__EXPORT void stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	/* Hold power state */
 	board_pwr_init(0);
 
@@ -195,8 +188,7 @@ __EXPORT void stm32_boardinitialize(void)
  *
  ****************************************************************************/
 
-__EXPORT int board_app_initialize(uintptr_t arg)
-{
+__EXPORT int board_app_initialize(uintptr_t arg) {
 	/* Power on Interfaces */
 	VDD_3V3_SD_CARD_EN(true);
 
@@ -230,7 +222,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 	/* initial LED state */
 	drv_led_start();
 	led_off(LED_RED);
-	led_on(LED_GREEN); // Indicate Power.
+	led_on(LED_GREEN);  // Indicate Power.
 	led_off(LED_BLUE);
 
 	if (board_hardfault_init(2, true) != 0) {

boards/atl/mantis-edu/src/led.c

@@ -37,16 +37,14 @@
  * PX4FMU LED backend.
  */
 
+#include <arch/board/board.h>
+#include <nuttx/board.h>
 #include <px4_platform_common/px4_config.h>
-
 #include <stdbool.h>
 
+#include "board_config.h"
 #include "chip.h"
 #include "stm32_gpio.h"
-#include "board_config.h"
-
-#include <nuttx/board.h>
-#include <arch/board/board.h>
 
 /*
  * Ideally we'd be able to get these from arm_internal.h,
@@ -64,41 +62,29 @@ __END_DECLS
 
 #define xlat(p) (p)
 static uint32_t g_ledmap[] = {
-	GPIO_nLED_BLUE,                     // Indexed by LED_BLUE
-	GPIO_nLED_RED,                      // Indexed by LED_RED, LED_AMBER
-	GPIO_nLED_GREEN,                    // Indexed by LED_GREEN
+	GPIO_nLED_BLUE,   // Indexed by LED_BLUE
+	GPIO_nLED_RED,    // Indexed by LED_RED, LED_AMBER
+	GPIO_nLED_GREEN,  // Indexed by LED_GREEN
 };
 
-__EXPORT void led_init(void)
-{
+__EXPORT void led_init(void) {
 	for (size_t l = 0; l < (sizeof(g_ledmap) / sizeof(g_ledmap[0])); l++) {
 		stm32_configgpio(g_ledmap[l]);
 	}
 }
 
-static void phy_set_led(int led, bool state)
-{
+static void phy_set_led(int led, bool state) {
 	/* Drive Low to switch on */
 	stm32_gpiowrite(g_ledmap[led], !state);
 }
 
-static bool phy_get_led(int led)
-{
+static bool phy_get_led(int led) {
 	/* If Low it is on */
 	return !stm32_gpioread(g_ledmap[led]);
 }
 
-__EXPORT void led_on(int led)
-{
-	phy_set_led(xlat(led), true);
-}
+__EXPORT void led_on(int led) { phy_set_led(xlat(led), true); }
 
-__EXPORT void led_off(int led)
-{
-	phy_set_led(xlat(led), false);
-}
+__EXPORT void led_off(int led) { phy_set_led(xlat(led), false); }
 
-__EXPORT void led_toggle(int led)
-{
-	phy_set_led(xlat(led), !phy_get_led(xlat(led)));
-}
+__EXPORT void led_toggle(int led) { phy_set_led(xlat(led), !phy_get_led(xlat(led))); }

boards/atl/mantis-edu/src/pwr.cpp

@@ -42,36 +42,31 @@
  * Included Files
  ************************************************************************************/
 
-#include <px4_platform_common/px4_config.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <time.h>
-#include <debug.h>
-
 #include <arch/board/board.h>
+#include <arm_arch.h>
+#include <debug.h>
 #include <nuttx/arch.h>
-
+#include <px4_platform_common/px4_config.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stm32_pwr.h>
+#include <time.h>
 #include <uORB/uORB.h>
+
 #include <uORB/Publication.hpp>
 
-#include <arm_arch.h>
 #include "board_config.h"
-#include <stm32_pwr.h>
 
 extern void led_on(int led);
 extern void led_off(int led);
 
 static struct timespec time_down;
 
-
-static int default_power_button_state_notification(board_power_button_state_notification_e request)
-{
-//	syslog(0,"%d\n", request);
+static int default_power_button_state_notification(board_power_button_state_notification_e request) {
+	//	syslog(0,"%d\n", request);
 	return PWR_BUTTON_RESPONSE_SHUT_DOWN_NOW;
 }
 
-
 static power_button_state_notification_t power_state_notification = default_power_button_state_notification;
 
 /****************************************************************************
@@ -82,13 +77,9 @@ static power_button_state_notification_t power_state_notification = default_powe
  *
  ****************************************************************************/
 
-static bool board_pwr_button_down(void)
-{
-	return 0 == stm32_gpioread(KEY_AD_GPIO);
-}
+static bool board_pwr_button_down(void) { return 0 == stm32_gpioread(KEY_AD_GPIO); }
 
-int board_register_power_state_notification_cb(power_button_state_notification_t cb)
-{
+int board_register_power_state_notification_cb(power_button_state_notification_t cb) {
 	power_state_notification = cb;
 
 	if (board_pwr_button_down() && (time_down.tv_nsec != 0 || time_down.tv_sec != 0)) {
@@ -99,8 +90,7 @@ int board_register_power_state_notification_cb(power_button_state_notification_t
 	return OK;
 }
 
-int board_power_off(int status)
-{
+int board_power_off(int status) {
 	led_on(BOARD_LED_BLUE);
 
 	// disable the interrups
@@ -108,15 +98,14 @@ int board_power_off(int status)
 
 	stm32_configgpio(POWER_OFF_GPIO);
 
-	while (1);
+	while (1)
+		;
 
 	return 0;
 }
 
-static int board_button_irq(int irq, FAR void *context, FAR void *args)
-{
+static int board_button_irq(int irq, FAR void *context, FAR void *args) {
 	if (board_pwr_button_down()) {
-
 		led_on(BOARD_LED_RED);
 		clock_gettime(CLOCK_REALTIME, &time_down);
 		power_state_notification(PWR_BUTTON_DOWN);
@@ -134,10 +123,10 @@ static int board_button_irq(int irq, FAR void *context, FAR void *args)
 		uint64_t tnow_ms = now.tv_sec * 1000 + now.tv_nsec / 1000000;
 
 		if (tdown_ms != 0 && (tnow_ms - tdown_ms) >= MS_PWR_BUTTON_DOWN) {
-
 			led_on(BOARD_LED_BLUE);
 
-			if (power_state_notification(PWR_BUTTON_REQUEST_SHUT_DOWN) == PWR_BUTTON_RESPONSE_SHUT_DOWN_NOW) {
+			if (power_state_notification(PWR_BUTTON_REQUEST_SHUT_DOWN) ==
+			    PWR_BUTTON_RESPONSE_SHUT_DOWN_NOW) {
 				up_mdelay(200);
 				board_power_off(0);
 			}
@@ -145,7 +134,6 @@ static int board_button_irq(int irq, FAR void *context, FAR void *args)
 		} else {
 			power_state_notification(PWR_BUTTON_IDEL);
 		}
-
 	}
 
 	return OK;
@@ -162,8 +150,7 @@ static int board_button_irq(int irq, FAR void *context, FAR void *args)
  *
  ************************************************************************************/
 
-void board_pwr_init(int stage)
-{
+void board_pwr_init(int stage) {
 	if (stage == 0) {
 		stm32_configgpio(POWER_ON_GPIO);
 		stm32_configgpio(KEY_AD_GPIO);

boards/atl/mantis-edu/src/sdio.c

@@ -36,34 +36,31 @@
  * Included Files
  ****************************************************************************/
 
-#include <nuttx/config.h>
 #include <board_config.h>
-
-#include <stdbool.h>
-#include <stdio.h>
 #include <debug.h>
 #include <errno.h>
-
-#include <nuttx/sdio.h>
+#include <nuttx/config.h>
 #include <nuttx/mmcsd.h>
+#include <nuttx/sdio.h>
+#include <stdbool.h>
+#include <stdio.h>
 
-#include "chip.h"
 #include "board_config.h"
+#include "chip.h"
 #include "stm32_gpio.h"
 #include "stm32_sdmmc.h"
 
 #ifdef CONFIG_MMCSD
 
-
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 
 /* Card detections requires card support and a card detection GPIO */
 
-#define HAVE_NCD   1
+#define HAVE_NCD 1
 #if !defined(GPIO_SDMMC1_NCD)
-#  undef HAVE_NCD
+#undef HAVE_NCD
 #endif
 
 /****************************************************************************
@@ -88,8 +85,7 @@ static bool g_sd_inserted = 0xff; /* Impossible value */
  ****************************************************************************/
 
 #ifdef HAVE_NCD
-static int stm32_ncd_interrupt(int irq, FAR void *context)
-{
+static int stm32_ncd_interrupt(int irq, FAR void *context) {
 	bool present;
 
 	present = !stm32_gpioread(GPIO_SDMMC1_NCD);
@@ -115,8 +111,7 @@ static int stm32_ncd_interrupt(int irq, FAR void *context)
  *
  ****************************************************************************/
 
-int stm32_sdio_initialize(void)
-{
+int stm32_sdio_initialize(void) {
 	int ret;
 
 #ifdef HAVE_NCD

boards/atl/mantis-edu/src/spi.cpp

@@ -31,17 +31,19 @@
  *
  ****************************************************************************/
 
-#include <px4_arch/spi_hw_description.h>
 #include <drivers/drv_sensor.h>
 #include <nuttx/spi/spi.h>
+#include <px4_arch/spi_hw_description.h>
 
 constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
-	initSPIBus(SPI::Bus::SPI1, {
-		initSPIDevice(DRV_IMU_DEVTYPE_ICM20602, SPI::CS{GPIO::PortF, GPIO::Pin3}),
-	}),
-	initSPIBus(SPI::Bus::SPI4, {
-		initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortF, GPIO::Pin10}),
-	}),
+	initSPIBus(SPI::Bus::SPI1,
+		   {
+			   initSPIDevice(DRV_IMU_DEVTYPE_ICM20602, SPI::CS{GPIO::PortF, GPIO::Pin3}),
+		   }),
+	initSPIBus(SPI::Bus::SPI4,
+		   {
+			   initSPIDevice(DRV_DEVTYPE_UNUSED, SPI::CS{GPIO::PortF, GPIO::Pin10}),
+		   }),
 };
 
 static constexpr bool unused = validateSPIConfig(px4_spi_buses);

boards/atl/mantis-edu/src/timer_config.cpp

@@ -34,9 +34,9 @@
 #include <px4_arch/io_timer_hw_description.h>
 
 constexpr io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
-#  if defined(BOARD_HAS_LED_PWM) && !defined(BOARD_HAS_CONTROL_STATUS_LEDS)
+#if defined(BOARD_HAS_LED_PWM) && !defined(BOARD_HAS_CONTROL_STATUS_LEDS)
 	initIOTimer(Timer::Timer3),
-#  endif
+#endif
 };
 
 /* Support driving active low (preferred) or active high LED
@@ -46,38 +46,37 @@ constexpr io_timers_t led_pwm_timers[MAX_LED_TIMERS] = {
  * if the LED has a 5 Volt supply that the LED will be
  * off when high.
  */
-#define CCER_C1_NUM_BITS   4
-#define ACTIVE_LOW(c)      (GTIM_CCER_CC1P << (((c)-1) * CCER_C1_NUM_BITS))
-#define ACTIVE_HIGH(c)     0
+#define CCER_C1_NUM_BITS 4
+#define ACTIVE_LOW(c) (GTIM_CCER_CC1P << (((c)-1) * CCER_C1_NUM_BITS))
+#define ACTIVE_HIGH(c) 0
 
 #if defined(BOARD_LED_PWM_DRIVE_ACTIVE_LOW)
-#  define POLARITY(c)      ACTIVE_LOW(c)
-#  define DRIVE_TYPE(p)    ((p)|GPIO_OPENDRAIN)
+#define POLARITY(c) ACTIVE_LOW(c)
+#define DRIVE_TYPE(p) ((p) | GPIO_OPENDRAIN)
 #else
-#  define POLARITY(c)      ACTIVE_HIGH((c))
-#  define DRIVE_TYPE(p)    (p)
+#define POLARITY(c) ACTIVE_HIGH((c))
+#define DRIVE_TYPE(p) (p)
 #endif
 
 #if defined(BOARD_UI_LED_PWM_DRIVE_ACTIVE_LOW)
-#  define UI_POLARITY(c)    ACTIVE_LOW(c)
-#  define UI_DRIVE_TYPE(p)  ((p)|GPIO_OPENDRAIN)
+#define UI_POLARITY(c) ACTIVE_LOW(c)
+#define UI_DRIVE_TYPE(p) ((p) | GPIO_OPENDRAIN)
 #else
-#  define UI_POLARITY(c)    ACTIVE_HIGH((c))
-#  define UI_DRIVE_TYPE(p)  (p)
+#define UI_POLARITY(c) ACTIVE_HIGH((c))
+#define UI_DRIVE_TYPE(p) (p)
 #endif
 
 static inline constexpr timer_io_channels_t initIOTimerChannelUILED(const io_timers_t io_timers_conf[MAX_LED_TIMERS],
-		Timer::TimerChannel timer, GPIO::GPIOPin pin, int ui_polarity)
-{
+								    Timer::TimerChannel timer, GPIO::GPIOPin pin,
+								    int ui_polarity) {
 	timer_io_channels_t ret = initIOTimerChannel(io_timers_conf, timer, pin);
 	ret.gpio_out = UI_DRIVE_TYPE(ret.gpio_out);
 	ret.masks = UI_POLARITY(ui_polarity);
 	return ret;
 }
 
-static inline constexpr timer_io_channels_t initIOTimerChannelControlLED(const io_timers_t
-		io_timers_conf[MAX_LED_TIMERS], Timer::TimerChannel timer, GPIO::GPIOPin pin, int polarity)
-{
+static inline constexpr timer_io_channels_t initIOTimerChannelControlLED(
+	const io_timers_t io_timers_conf[MAX_LED_TIMERS], Timer::TimerChannel timer, GPIO::GPIOPin pin, int polarity) {
 	timer_io_channels_t ret = initIOTimerChannel(io_timers_conf, timer, pin);
 	ret.gpio_out = DRIVE_TYPE(ret.gpio_out);
 	ret.masks = POLARITY(polarity);
@@ -85,9 +84,9 @@ static inline constexpr timer_io_channels_t initIOTimerChannelControlLED(const i
 }
 
 constexpr timer_io_channels_t led_pwm_channels[MAX_TIMER_LED_CHANNELS] = {
-#  if defined(BOARD_HAS_LED_PWM) && !defined(BOARD_HAS_CONTROL_STATUS_LEDS)
+#if defined(BOARD_HAS_LED_PWM) && !defined(BOARD_HAS_CONTROL_STATUS_LEDS)
 	initIOTimerChannelControlLED(led_pwm_timers, {Timer::Timer3, Timer::Channel4}, {GPIO::PortB, GPIO::Pin1}, 4),
 	initIOTimerChannelControlLED(led_pwm_timers, {Timer::Timer3, Timer::Channel1}, {GPIO::PortC, GPIO::Pin6}, 1),
 	initIOTimerChannelControlLED(led_pwm_timers, {Timer::Timer3, Timer::Channel2}, {GPIO::PortC, GPIO::Pin7}, 2),
-#  endif
+#endif
 };

boards/atl/mantis-edu/src/usb.c

@@ -37,13 +37,14 @@
  * Board-specific USB functions.
  */
 
-#include "board_config.h"
+#include <debug.h>
 #include <nuttx/usb/usbdev.h>
 #include <nuttx/usb/usbdev_trace.h>
 #include <stm32_otg.h>
-#include <debug.h>
 #include <syslog.h>
 
+#include "board_config.h"
+
 /************************************************************************************
  * Name:  stm32_usbsuspend
  *
@@ -54,7 +55,4 @@
  *   while the USB is suspended.
  *
  ************************************************************************************/
-__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume)
-{
-	uinfo("resume: %d\n", resume);
-}
+__EXPORT void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) { uinfo("resume: %d\n", resume); }

boards/av/x-v1/nuttx-config/include/board.h

@@ -37,12 +37,12 @@
 /************************************************************************************
  * Included Files
  ************************************************************************************/
-#include "board_dma_map.h"
-
 #include <nuttx/config.h>
 
+#include "board_dma_map.h"
+
 #ifndef __ASSEMBLY__
-# include <stdint.h>
+#include <stdint.h>
 #endif
 
 #include "stm32_rcc.h"
@@ -65,12 +65,12 @@
  *   HSE: 16 MHz crystal for HSE
  */
 
-#define STM32_BOARD_XTAL        16000000ul
+#define STM32_BOARD_XTAL 16000000ul
 
-#define STM32_HSI_FREQUENCY     16000000ul
-#define STM32_LSI_FREQUENCY     32000
-#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
-#define STM32_LSE_FREQUENCY     0
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 0
 
 /* Main PLL Configuration.
  *
@@ -104,64 +104,61 @@
  * SDMMC and RNG Clock = 432 MHz / 9 = 48 MHz
  */
 
-#define STM32_PLLCFG_PLLM       RCC_PLLCFG_PLLM(8)
-#define STM32_PLLCFG_PLLN       RCC_PLLCFG_PLLN(216)
-#define STM32_PLLCFG_PLLP       RCC_PLLCFG_PLLP_2
-#define STM32_PLLCFG_PLLQ       RCC_PLLCFG_PLLQ(9)
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(8)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(216)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(9)
 
-#define STM32_VCO_FREQUENCY     ((STM32_HSE_FREQUENCY / 8) * 216)
-#define STM32_SYSCLK_FREQUENCY  (STM32_VCO_FREQUENCY / 2)
-#define STM32_OTGFS_FREQUENCY   (STM32_VCO_FREQUENCY / 9)
+#define STM32_VCO_FREQUENCY ((STM32_HSE_FREQUENCY / 8) * 216)
+#define STM32_SYSCLK_FREQUENCY (STM32_VCO_FREQUENCY / 2)
+#define STM32_OTGFS_FREQUENCY (STM32_VCO_FREQUENCY / 9)
 
 /* Configure factors for  PLLSAI clock */
 
 #define CONFIG_STM32F7_PLLSAI 1
-#define STM32_RCC_PLLSAICFGR_PLLSAIN    RCC_PLLSAICFGR_PLLSAIN(192)
-#define STM32_RCC_PLLSAICFGR_PLLSAIP    RCC_PLLSAICFGR_PLLSAIP(8)
-#define STM32_RCC_PLLSAICFGR_PLLSAIQ    RCC_PLLSAICFGR_PLLSAIQ(4)
-#define STM32_RCC_PLLSAICFGR_PLLSAIR    RCC_PLLSAICFGR_PLLSAIR(2)
+#define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192)
+#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8)
+#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4)
+#define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2)
 
 /* Configure Dedicated Clock Configuration Register */
 
-#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ  RCC_DCKCFGR1_PLLI2SDIVQ(1)
-#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ  RCC_DCKCFGR1_PLLSAIDIVQ(1)
-#define STM32_RCC_DCKCFGR1_PLLSAIDIVR  RCC_DCKCFGR1_PLLSAIDIVR(0)
-#define STM32_RCC_DCKCFGR1_SAI1SRC     RCC_DCKCFGR1_SAI1SEL(0)
-#define STM32_RCC_DCKCFGR1_SAI2SRC     RCC_DCKCFGR1_SAI2SEL(0)
-#define STM32_RCC_DCKCFGR1_TIMPRESRC   0
-#define STM32_RCC_DCKCFGR1_DFSDM1SRC   0
-#define STM32_RCC_DCKCFGR1_ADFSDM1SRC  0
-
-
+#define STM32_RCC_DCKCFGR1_PLLI2SDIVQ RCC_DCKCFGR1_PLLI2SDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVQ RCC_DCKCFGR1_PLLSAIDIVQ(1)
+#define STM32_RCC_DCKCFGR1_PLLSAIDIVR RCC_DCKCFGR1_PLLSAIDIVR(0)
+#define STM32_RCC_DCKCFGR1_SAI1SRC RCC_DCKCFGR1_SAI1SEL(0)
+#define STM32_RCC_DCKCFGR1_SAI2SRC RCC_DCKCFGR1_SAI2SEL(0)
+#define STM32_RCC_DCKCFGR1_TIMPRESRC 0
+#define STM32_RCC_DCKCFGR1_DFSDM1SRC 0
+#define STM32_RCC_DCKCFGR1_ADFSDM1SRC 0
 
 /* Configure factors for  PLLI2S clock */
 
 #define CONFIG_STM32F7_PLLI2S 1
-#define STM32_RCC_PLLI2SCFGR_PLLI2SN   RCC_PLLI2SCFGR_PLLI2SN(192)
-#define STM32_RCC_PLLI2SCFGR_PLLI2SP   RCC_PLLI2SCFGR_PLLI2SP(2)
-#define STM32_RCC_PLLI2SCFGR_PLLI2SQ   RCC_PLLI2SCFGR_PLLI2SQ(2)
-#define STM32_RCC_PLLI2SCFGR_PLLI2SR   RCC_PLLI2SCFGR_PLLI2SR(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SN RCC_PLLI2SCFGR_PLLI2SN(192)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SP RCC_PLLI2SCFGR_PLLI2SP(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SQ RCC_PLLI2SCFGR_PLLI2SQ(2)
+#define STM32_RCC_PLLI2SCFGR_PLLI2SR RCC_PLLI2SCFGR_PLLI2SR(2)
 
 /* Configure Dedicated Clock Configuration Register 2 */
 
-#define STM32_RCC_DCKCFGR2_USART1SRC  RCC_DCKCFGR2_USART1SEL_APB
-#define STM32_RCC_DCKCFGR2_USART2SRC  RCC_DCKCFGR2_USART2SEL_APB
-#define STM32_RCC_DCKCFGR2_UART4SRC   RCC_DCKCFGR2_UART4SEL_APB
-#define STM32_RCC_DCKCFGR2_UART5SRC   RCC_DCKCFGR2_UART5SEL_APB
-#define STM32_RCC_DCKCFGR2_USART6SRC  RCC_DCKCFGR2_USART6SEL_APB
-#define STM32_RCC_DCKCFGR2_UART7SRC   RCC_DCKCFGR2_UART7SEL_APB
-#define STM32_RCC_DCKCFGR2_UART8SRC   RCC_DCKCFGR2_UART8SEL_APB
-#define STM32_RCC_DCKCFGR2_I2C1SRC    RCC_DCKCFGR2_I2C1SEL_HSI
-#define STM32_RCC_DCKCFGR2_I2C2SRC    RCC_DCKCFGR2_I2C2SEL_HSI
-#define STM32_RCC_DCKCFGR2_I2C3SRC    RCC_DCKCFGR2_I2C3SEL_HSI
-#define STM32_RCC_DCKCFGR2_I2C4SRC    RCC_DCKCFGR2_I2C4SEL_HSI
-#define STM32_RCC_DCKCFGR2_LPTIM1SRC  RCC_DCKCFGR2_LPTIM1SEL_APB
-#define STM32_RCC_DCKCFGR2_CECSRC     RCC_DCKCFGR2_CECSEL_HSI
-#define STM32_RCC_DCKCFGR2_CK48MSRC   RCC_DCKCFGR2_CK48MSEL_PLL
-#define STM32_RCC_DCKCFGR2_SDMMCSRC   RCC_DCKCFGR2_SDMMCSEL_48MHZ
-#define STM32_RCC_DCKCFGR2_SDMMC2SRC  RCC_DCKCFGR2_SDMMC2SEL_48MHZ
-#define STM32_RCC_DCKCFGR2_DSISRC     RCC_DCKCFGR2_DSISEL_PHY
-
+#define STM32_RCC_DCKCFGR2_USART1SRC RCC_DCKCFGR2_USART1SEL_APB
+#define STM32_RCC_DCKCFGR2_USART2SRC RCC_DCKCFGR2_USART2SEL_APB
+#define STM32_RCC_DCKCFGR2_UART4SRC RCC_DCKCFGR2_UART4SEL_APB
+#define STM32_RCC_DCKCFGR2_UART5SRC RCC_DCKCFGR2_UART5SEL_APB
+#define STM32_RCC_DCKCFGR2_USART6SRC RCC_DCKCFGR2_USART6SEL_APB
+#define STM32_RCC_DCKCFGR2_UART7SRC RCC_DCKCFGR2_UART7SEL_APB
+#define STM32_RCC_DCKCFGR2_UART8SRC RCC_DCKCFGR2_UART8SEL_APB
+#define STM32_RCC_DCKCFGR2_I2C1SRC RCC_DCKCFGR2_I2C1SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C2SRC RCC_DCKCFGR2_I2C2SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C3SRC RCC_DCKCFGR2_I2C3SEL_HSI
+#define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI
+#define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB
+#define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI
+#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL
+#define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ
+#define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ
+#define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_PHY
 
 /* Several prescalers allow the configuration of the two AHB buses, the
  * high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum
@@ -172,39 +169,39 @@
 
 /* AHB clock (HCLK) is SYSCLK (216 MHz) */
 
-#define STM32_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK  /* HCLK  = SYSCLK / 1 */
-#define STM32_HCLK_FREQUENCY    STM32_SYSCLK_FREQUENCY
-#define STM32_BOARD_HCLK        STM32_HCLK_FREQUENCY  /* same as above, to satisfy compiler */
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK  = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
 
 /* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
 
-#define STM32_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLKd4     /* PCLK1 = HCLK / 4 */
-#define STM32_PCLK1_FREQUENCY   (STM32_HCLK_FREQUENCY/4)
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
+#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 4)
 
 /* Timers driven from APB1 will be twice PCLK1 */
 
-#define STM32_APB1_TIM2_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM3_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM4_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM5_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM6_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM7_CLKIN   (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM12_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM13_CLKIN  (2*STM32_PCLK1_FREQUENCY)
-#define STM32_APB1_TIM14_CLKIN  (2*STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM2_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM3_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM4_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM5_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM6_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM7_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM12_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM13_CLKIN (2 * STM32_PCLK1_FREQUENCY)
+#define STM32_APB1_TIM14_CLKIN (2 * STM32_PCLK1_FREQUENCY)
 
 /* APB2 clock (PCLK2) is HCLK/2 (108MHz) */
 
-#define STM32_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLKd2     /* PCLK2 = HCLK / 2 */
-#define STM32_PCLK2_FREQUENCY   (STM32_HCLK_FREQUENCY/2)
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */
+#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 2)
 
 /* Timers driven from APB2 will be twice PCLK2 */
 
-#define STM32_APB2_TIM1_CLKIN   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM8_CLKIN   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM9_CLKIN   (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM10_CLKIN  (2*STM32_PCLK2_FREQUENCY)
-#define STM32_APB2_TIM11_CLKIN  (2*STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM1_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM8_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM9_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM10_CLKIN (2 * STM32_PCLK2_FREQUENCY)
+#define STM32_APB2_TIM11_CLKIN (2 * STM32_PCLK2_FREQUENCY)
 
 /* SDMMC dividers.  Note that slower clocking is required when DMA is disabled
  * in order to avoid RX overrun/TX underrun errors due to delayed responses
@@ -220,27 +217,27 @@
 
 #define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
 
-#define STM32_SDMMC_INIT_CLKDIV         (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 
 /* DMA ON:  SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
  * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
  */
 
 #ifdef CONFIG_STM32F7_SDMMC_DMA
-#  define STM32_SDMMC_MMCXFR_CLKDIV     (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #else
-#  define STM32_SDMMC_MMCXFR_CLKDIV     (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #endif
 
 /* DMA ON:  SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
  * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
  */
-//TODO #warning "Check Freq for 24mHz"
+// TODO #warning "Check Freq for 24mHz"
 
 #ifdef CONFIG_STM32F7_SDMMC_DMA
-#  define STM32_SDMMC_SDXFR_CLKDIV      (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #else
-#  define STM32_SDMMC_SDXFR_CLKDIV      (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
 #endif
 
 /* FLASH wait states
@@ -259,27 +256,27 @@
 
 /* Alternate function pin selections ************************************************/
 
-#define GPIO_USART1_RX   GPIO_USART1_RX_2   /* PB7 */
-#define GPIO_USART1_TX   GPIO_USART1_TX_2   /* PB6 */
+#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */
+#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */
 
-#define GPIO_USART2_RX   GPIO_USART2_RX_2   /* PD6 */
-#define GPIO_USART2_TX   GPIO_USART2_TX_2   /* PD5 */
+#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */
+#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */
 
-#define GPIO_USART3_RX   GPIO_USART3_RX_3   /* PD9 */
-#define GPIO_USART3_TX   GPIO_USART3_TX_3   /* PD8 */
+#define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */
+#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */
 
-#define GPIO_UART4_RX    GPIO_UART4_RX_4    /* PD0 */
-#define GPIO_UART4_TX    GPIO_UART4_TX_3    /* PA12 */
-#define GPIO_UART4_RS485_DIR GPIO_UART4_RTS_2	/* PB14 */
+#define GPIO_UART4_RX GPIO_UART4_RX_4         /* PD0 */
+#define GPIO_UART4_TX GPIO_UART4_TX_3         /* PA12 */
+#define GPIO_UART4_RS485_DIR GPIO_UART4_RTS_2 /* PB14 */
 
-#define GPIO_UART5_RX    GPIO_UART5_RX_4    /* PB8 */
-#define GPIO_UART5_TX    GPIO_UART5_TX_4    /* PB9 */
+#define GPIO_UART5_RX GPIO_UART5_RX_4 /* PB8 */
+#define GPIO_UART5_TX GPIO_UART5_TX_4 /* PB9 */
 
-#define GPIO_USART6_RX   GPIO_USART6_RX_2   /* PG9 */
-#define GPIO_USART6_TX   GPIO_USART6_TX_2   /* PG14 */
+#define GPIO_USART6_RX GPIO_USART6_RX_2 /* PG9 */
+#define GPIO_USART6_TX GPIO_USART6_TX_2 /* PG14 */
 
-#define GPIO_UART7_RX    GPIO_UART7_RX_1    /* PE8 */
-#define GPIO_UART7_TX    GPIO_UART7_TX_1    /* PE7 */
+#define GPIO_UART7_RX GPIO_UART7_RX_1 /* PE8 */
+#define GPIO_UART7_TX GPIO_UART7_TX_1 /* PE7 */
 
 /* USART8: has no remap
  *
@@ -291,28 +288,28 @@
  *
  * CAN1 is routed to transceiver.
  */
-#define GPIO_CAN1_RX     GPIO_CAN1_RX_5     /* PI9  */
-#define GPIO_CAN1_TX     GPIO_CAN1_TX_3     /* PD1 */
+#define GPIO_CAN1_RX GPIO_CAN1_RX_5 /* PI9  */
+#define GPIO_CAN1_TX GPIO_CAN1_TX_3 /* PD1 */
 
 /* SPI
  * SPI1-SPI4 sensors
  */
 
-#define GPIO_SPI1_MISO   GPIO_SPI1_MISO_1   /* PA6 */
-#define GPIO_SPI1_MOSI   GPIO_SPI1_MOSI_2   /* PB5 */
-#define GPIO_SPI1_SCK    GPIO_SPI1_SCK_1    /* PA5 */
+#define GPIO_SPI1_MISO GPIO_SPI1_MISO_1 /* PA6 */
+#define GPIO_SPI1_MOSI GPIO_SPI1_MOSI_2 /* PB5 */
+#define GPIO_SPI1_SCK GPIO_SPI1_SCK_1   /* PA5 */
 
-#define GPIO_SPI2_MISO   GPIO_SPI2_MISO_3   /* PI2 */
-#define GPIO_SPI2_MOSI   GPIO_SPI2_MOSI_3   /* PI3 */
-#define GPIO_SPI2_SCK    GPIO_SPI2_SCK_4    /* PD3 */
+#define GPIO_SPI2_MISO GPIO_SPI2_MISO_3 /* PI2 */
+#define GPIO_SPI2_MOSI GPIO_SPI2_MOSI_3 /* PI3 */
+#define GPIO_SPI2_SCK GPIO_SPI2_SCK_4   /* PD3 */
 
-#define GPIO_SPI4_MISO   GPIO_SPI4_MISO_1   /* PE5 */
-#define GPIO_SPI4_MOSI   GPIO_SPI4_MOSI_1   /* PE6 */
-#define GPIO_SPI4_SCK    GPIO_SPI4_SCK_1    /* PE2 */
+#define GPIO_SPI4_MISO GPIO_SPI4_MISO_1 /* PE5 */
+#define GPIO_SPI4_MOSI GPIO_SPI4_MOSI_1 /* PE6 */
+#define GPIO_SPI4_SCK GPIO_SPI4_SCK_1   /* PE2 */
 
-#define GPIO_SPI5_MISO   GPIO_SPI5_MISO_1   /* PF8 */
-#define GPIO_SPI5_MOSI   GPIO_SPI5_MOSI_2   /* PF11 */
-#define GPIO_SPI5_SCK    GPIO_SPI5_SCK_2    /* PH6 */
+#define GPIO_SPI5_MISO GPIO_SPI5_MISO_1 /* PF8 */
+#define GPIO_SPI5_MOSI GPIO_SPI5_MOSI_2 /* PF11 */
+#define GPIO_SPI5_SCK GPIO_SPI5_SCK_2   /* PH6 */
 
 /* The STM32 F7 connects to a SMSC LAN8720A PHY using these pins:
  *
@@ -337,31 +334,31 @@
  * receive errors can be detected using GPIO pin PD5
  */
 
-#define GPIO_ETH_RMII_TX_EN   GPIO_ETH_RMII_TX_EN_1
-#define GPIO_ETH_RMII_TXD0    GPIO_ETH_RMII_TXD0_1
-#define GPIO_ETH_RMII_TXD1    GPIO_ETH_RMII_TXD1_1
+#define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_1
+#define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_1
+#define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_1
 
 /* I2C Mapping
  *
  */
 
-#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2       /* PF1 */
-#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2       /* PF0 */
+#define GPIO_I2C2_SCL GPIO_I2C2_SCL_2 /* PF1 */
+#define GPIO_I2C2_SDA GPIO_I2C2_SDA_2 /* PF0 */
 
-#define GPIO_I2C2_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET |GPIO_PORTF | GPIO_PIN1)
-#define GPIO_I2C2_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET |GPIO_PORTF | GPIO_PIN0)
+#define GPIO_I2C2_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN1)
+#define GPIO_I2C2_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN0)
 
-#define GPIO_I2C3_SCL GPIO_I2C3_SCL_2       /* PH7 */
-#define GPIO_I2C3_SDA GPIO_I2C3_SDA_2       /* PH8 */
+#define GPIO_I2C3_SCL GPIO_I2C3_SCL_2 /* PH7 */
+#define GPIO_I2C3_SDA GPIO_I2C3_SDA_2 /* PH8 */
 
-#define GPIO_I2C3_SCL_GPIO                  (GPIO_OUTPUT |GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN7)
-#define GPIO_I2C3_SDA_GPIO                  (GPIO_OUTPUT |GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN8)
+#define GPIO_I2C3_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN7)
+#define GPIO_I2C3_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTH | GPIO_PIN8)
 
-#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2       /* PF14 */
-#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2       /* PF15 */
+#define GPIO_I2C4_SCL GPIO_I2C4_SCL_2 /* PF14 */
+#define GPIO_I2C4_SDA GPIO_I2C4_SDA_2 /* PF15 */
 
-#define GPIO_I2C4_SCL_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN14)
-#define GPIO_I2C4_SDA_GPIO                  (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN15)
+#define GPIO_I2C4_SCL_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN14)
+#define GPIO_I2C4_SDA_GPIO (GPIO_OUTPUT | GPIO_OPENDRAIN | GPIO_SPEED_50MHz | GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN15)
 
 /* SDMMC1
  *
@@ -374,4 +371,3 @@
  *      SDMMC1_D2                           PC10
  *      SDMMC1_D3                           PC11
  */
-

boards/av/x-v1/nuttx-config/include/board_dma_map.h

@@ -34,41 +34,51 @@
 #pragma once
 
 /*
-|    DMA1    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5         | Stream 6         | Stream 7         |
+|    DMA1    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5
+| Stream 6         | Stream 7         |
 |------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
-| Channel 0  | SPI3_RX_1        | SPDIFRX_DT       | SPI3_RX_2        | SPI2_RX          | SPI2_TX          | SPI3_TX_1        | SPDIFRX_CS       | SPI3_TX_2        |
-| Channel 1  | I2C1_RX          | I2C3_RX          | TIM7_UP_1        | -                | TIM7_UP_2        |  I2C1_RX_1       | I2C1_TX          | I2C1_TX_1        |
-| Channel 2  | TIM4_CH1         | -                | I2C4_RX          | TIM4_CH2         | -                | I2C4_RX          | TIM4_UP          | TIM4_CH3         |
-| Channel 3  | -                | TIM2_UP_1        | I2C3_RX_1        | -                | I2C3_TX          | TIM2_CH1         | TIM2_CH2         | TIM2_UP_2        |
-|            |                  |   TIM2_CH3       |                  |                  |                  |                  |   TIM2_CH4_1     |   TIM2_CH4_2     |
-| Channel 4  | UART5_RX         | USART3_RX        | UART4_RX         | USART3_TX_1      | UART4_TX         | USART2_RX        | USART2_TX        | UART5_TX         |
-| Channel 5  | UART8_TX         | UART7_TX         | TIM3_CH4         | UART7_RX         | TIM3_CH1         | TIM3_CH2         | UART8_RX         | TIM3_CH3         |
-|            |                  |                  |   TIM3_UP        |                  |   TIM3_TRIG      |                  |                  |                  |
-| Channel 6  | TIM5_CH3         | TIM5_CH4_1       | TIM5_CH1         | TIM5_CH4_2       | TIM5_CH2         | -                | TIM5_UP_2        | -                |
-|            |   TIM5_UP_1      |   TIM5_TRIG_1    |                  |   TIM5_TRIG_2    |                  |                  |                  |                  |
-| Channel 7  | -                | TIM6_UP          | I2C2_RX          | I2C2_RX_1        | USART3_TX_2      | DAC1             | DAC2             | I2C2_TX          |
-|            |                  |                  |                  |                  |                  |                  |                  |                  |
-| Usage      | UART5_RX         | USART3_RX        |                  | SPI2_RX          | SPI2_TX          | USART2_RX        | UART8_RX         |                  |
+| Channel 0  | SPI3_RX_1        | SPDIFRX_DT       | SPI3_RX_2        | SPI2_RX          | SPI2_TX          | SPI3_TX_1
+| SPDIFRX_CS       | SPI3_TX_2        | | Channel 1  | I2C1_RX          | I2C3_RX          | TIM7_UP_1        | - |
+TIM7_UP_2        |  I2C1_RX_1       | I2C1_TX          | I2C1_TX_1        | | Channel 2  | TIM4_CH1         | - |
+I2C4_RX          | TIM4_CH2         | -                | I2C4_RX          | TIM4_UP          | TIM4_CH3         | |
+Channel 3  | -                | TIM2_UP_1        | I2C3_RX_1        | -                | I2C3_TX          | TIM2_CH1 |
+TIM2_CH2         | TIM2_UP_2        | |            |                  |   TIM2_CH3       |                  | | | |
+TIM2_CH4_1     |   TIM2_CH4_2     | | Channel 4  | UART5_RX         | USART3_RX        | UART4_RX         | USART3_TX_1
+| UART4_TX         | USART2_RX        | USART2_TX        | UART5_TX         | | Channel 5  | UART8_TX         | UART7_TX
+| TIM3_CH4         | UART7_RX         | TIM3_CH1         | TIM3_CH2         | UART8_RX         | TIM3_CH3         | | |
+|                  |   TIM3_UP        |                  |   TIM3_TRIG      |                  |                  | | |
+Channel 6  | TIM5_CH3         | TIM5_CH4_1       | TIM5_CH1         | TIM5_CH4_2       | TIM5_CH2         | - |
+TIM5_UP_2        | -                | |            |   TIM5_UP_1      |   TIM5_TRIG_1    |                  |
+TIM5_TRIG_2    |                  |                  |                  |                  | | Channel 7  | - | TIM6_UP
+| I2C2_RX          | I2C2_RX_1        | USART3_TX_2      | DAC1             | DAC2             | I2C2_TX          | | |
+|                  |                  |                  |                  |                  |                  | | |
+Usage      | UART5_RX         | USART3_RX        |                  | SPI2_RX          | SPI2_TX          | USART2_RX |
+UART8_RX         |                  |
 
 
-|    DMA2    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5         | Stream 6         | Stream 7         |
+|    DMA2    | Stream 0         | Stream 1         | Stream 2         | Stream 3         | Stream 4         | Stream 5
+| Stream 6         | Stream 7         |
 |------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|------------------|
-| Channel 0  | ADC1_1           | SAI1_A           | TIM8_CH1_1       | SAI1_A_1         | ADC1_2           | SAI1_B_1         | TIM1_CH1_1       | SAI2_B_2         |
-|            |                  |                  |   TIM8_CH2_1     |                  |                  |                  |   TIM1_CH2_1     |                  |
-|            |                  |                  |   TIM8_CH3_1     |                  |                  |                  |   TIM1_CH3_1     |                  |
-| Channel 1  | -                | DCMI_1           | ADC2_1           | ADC2_2           | SAI1_B           | SPI6_TX          | SPI6_RX          | DCMI_2           |
-| Channel 2  | ADC3_1           | ADC3_2           | -                | SPI5_RX_1        | SPI5_TX_1        | CRYP_OUT         | CRYP_IN          | HASH_IN          |
-| Channel 3  | SPI1_RX_1        | -                | SPI1_RX_2        | SPI1_TX_1        | SAI2_A           | SPI1_TX_2        | SAI2_B           | QUADSPI          |
-| Channel 4  | SPI4_RX_1        | SPI4_TX_1        | USART1_RX_1      | SDMMC1_1         | -                | USART1_RX_2      | SDMMC1_2         | USART1_TX        |
-| Channel 5  | -                | USART6_RX_1      | USART6_RX_2      | SPI4_RX_2        | SPI4_TX_2        | -                | USART6_TX_1      | USART6_TX_2      |
-| Channel 6  | TIM1_TRIG_1      | TIM1_CH1_2       | TIM1_CH2_2       | TIM1_CH1         | TIM1_CH4         | TIM1_UP          | TIM1_CH3_2       | -                |
-|            |                  |                  |                  |                  |   TIM1_TRIG_2    |                  |                  |                  |
-|            |                  |                  |                  |                  |   TIM1_COM       |                  |                  |                  |
-| Channel 7  | -                | TIM8_UP          | TIM8_CH1_2       | TIM8_CH2_2       | TIM8_CH3_2       | SPI5_RX_2        | SPI5_TX_2        | TIM8_CH4         |
-|            |                  |                  |                  |                  |                  |                  |                  |   TIM8_TRIG      |
-|            |                  |                  |                  |                  |                  |                  |                  |   TIM8_COM       |
-|            |                  |                  |                  |                  |                  |                  |                  |                  |
-| Usage      | SPI1_RX_1        |                  | USART6_RX_2      | SPI1_TX_1        |                  | USART1_RX_2      | SDMMC1_2         |                  |
+| Channel 0  | ADC1_1           | SAI1_A           | TIM8_CH1_1       | SAI1_A_1         | ADC1_2           | SAI1_B_1
+| TIM1_CH1_1       | SAI2_B_2         | |            |                  |                  |   TIM8_CH2_1     | | | |
+TIM1_CH2_1     |                  | |            |                  |                  |   TIM8_CH3_1     | | | |
+TIM1_CH3_1     |                  | | Channel 1  | -                | DCMI_1           | ADC2_1           | ADC2_2 |
+SAI1_B           | SPI6_TX          | SPI6_RX          | DCMI_2           | | Channel 2  | ADC3_1           | ADC3_2 | -
+| SPI5_RX_1        | SPI5_TX_1        | CRYP_OUT         | CRYP_IN          | HASH_IN          | | Channel 3  |
+SPI1_RX_1        | -                | SPI1_RX_2        | SPI1_TX_1        | SAI2_A           | SPI1_TX_2        | SAI2_B
+| QUADSPI          | | Channel 4  | SPI4_RX_1        | SPI4_TX_1        | USART1_RX_1      | SDMMC1_1         | - |
+USART1_RX_2      | SDMMC1_2         | USART1_TX        | | Channel 5  | -                | USART6_RX_1      |
+USART6_RX_2      | SPI4_RX_2        | SPI4_TX_2        | -                | USART6_TX_1      | USART6_TX_2      | |
+Channel 6  | TIM1_TRIG_1      | TIM1_CH1_2       | TIM1_CH2_2       | TIM1_CH1         | TIM1_CH4         | TIM1_UP |
+TIM1_CH3_2       | -                | |            |                  |                  |                  | |
+TIM1_TRIG_2    |                  |                  |                  | |            |                  | | | |
+TIM1_COM       |                  |                  |                  | | Channel 7  | -                | TIM8_UP |
+TIM8_CH1_2       | TIM8_CH2_2       | TIM8_CH3_2       | SPI5_RX_2        | SPI5_TX_2        | TIM8_CH4         | | | |
+|                  |                  |                  |                  |                  |   TIM8_TRIG      | | |
+|                  |                  |                  |                  |                  |                  |
+TIM8_COM       | |            |                  |                  |                  |                  | | | | | |
+Usage      | SPI1_RX_1        |                  | USART6_RX_2      | SPI1_TX_1        |                  | USART1_RX_2
+| SDMMC1_2         |                  |
  */
 
 // DMA1 Channel/Stream Selections
@@ -76,17 +86,17 @@
 //      DMAMAP_UART5_RX                       // DMA1, Stream 0, Channel 4
 //      DMAMAP_USART3_RX                      // DMA1, Stream 1, Channel 4
 //      AVAILABLE                             // DMA1, Stream 2, Channel 4
-#define DMAMAP_SPI2_RX    DMAMAP_SPI2_RX_2    // DMA1, Stream 3, Channel 0    (SPI2 RX)
-#define DMAMAP_SPI2_TX    DMAMAP_SPI2_TX_2    // DMA1, Stream 4, Channel 0    (SPI2 TX)
+#define DMAMAP_SPI2_RX DMAMAP_SPI2_RX_2  // DMA1, Stream 3, Channel 0    (SPI2 RX)
+#define DMAMAP_SPI2_TX DMAMAP_SPI2_TX_2  // DMA1, Stream 4, Channel 0    (SPI2 TX)
 //      DMAMAP_USART2_RX                      // DMA1, Stream 5, Channel 4
 //      DMAMAP_UART8_RX                       // DMA1, Stream 6, Channel 5    (CONSOLE)
 
 //  DMA2 Channel/Stream Selections
 //--------------------------------------------//---------------------------//----------------
-#define DMAMAP_SPI1_RX    DMAMAP_SPI1_RX_1    // DMA2, Stream 0, Channel 3    (SPI1 RX)
+#define DMAMAP_SPI1_RX DMAMAP_SPI1_RX_1  // DMA2, Stream 0, Channel 3    (SPI1 RX)
 //      AVAILABLE                             // DMA2, Stream 1
-#define DMAMAP_USART6_RX  DMAMAP_USART6_RX_2  // DMA2, Stream 2, Channel 5
-#define DMAMAP_SPI1_TX    DMAMAP_SPI1_TX_1    // DMA2, Stream 3, Channel 3    (SPI1 TX)
+#define DMAMAP_USART6_RX DMAMAP_USART6_RX_2  // DMA2, Stream 2, Channel 5
+#define DMAMAP_SPI1_TX DMAMAP_SPI1_TX_1      // DMA2, Stream 3, Channel 3    (SPI1 TX)
 //      AVAILABLE                             // DMA2, Stream 4
-#define DMAMAP_USART1_RX  DMAMAP_USART1_RX_2  // DMA2, Stream 5, Channel 4
-#define DMAMAP_SDMMC1     DMAMAP_SDMMC1_2     // DMA2, Stream 6, Channel 4
+#define DMAMAP_USART1_RX DMAMAP_USART1_RX_2  // DMA2, Stream 5, Channel 4
+#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_2        // DMA2, Stream 6, Channel 4

boards/av/x-v1/src/board_config.h

@@ -43,16 +43,15 @@
  * Included Files
  ****************************************************************************************************/
 
-#include <px4_platform_common/px4_config.h>
 #include <nuttx/compiler.h>
+#include <px4_platform_common/px4_config.h>
 #include <stdint.h>
-
 #include <stm32_gpio.h>
 
 /* Configuration ************************************************************************************/
 
-#define BOARD_HAS_NBAT_V              1 // Only one Vbat to ADC
-#define BOARD_HAS_NBAT_I              0 // No Ibat ADC
+#define BOARD_HAS_NBAT_V 1  // Only one Vbat to ADC
+#define BOARD_HAS_NBAT_I 0  // No Ibat ADC
 
 /*
  * ADC channels
@@ -63,53 +62,44 @@
 
 /* ADC defines to be used in sensors.cpp to read from a particular channel */
 
-#define ADC1_CH(n)                      (n)
-#define ADC1_GPIO(n)                    GPIO_ADC1_IN##n
+#define ADC1_CH(n) (n)
+#define ADC1_GPIO(n) GPIO_ADC1_IN##n
 
 /* Define GPIO pins used as ADC N.B. Channel numbers must match below */
 
-#define PX4_ADC_GPIO  \
-	/* PA0 */  ADC1_GPIO(0),  \
-	/* PA1 */  ADC1_GPIO(1),  \
-	/* PA2 */  ADC1_GPIO(2),  \
-	/* PA3 */  ADC1_GPIO(3),  \
-	/* PA4 */  ADC1_GPIO(4),  \
-	/* PB8 */  ADC1_GPIO(8),  \
-	/* PC0 */  ADC1_GPIO(10), \
-	/* PC1 */  ADC1_GPIO(11), \
-	/* PC2 */  ADC1_GPIO(12), \
-	/* PC3 */  ADC1_GPIO(13), \
-	/* PC4 */  ADC1_GPIO(14)
+#define PX4_ADC_GPIO                                                                                              \
+	/* PA0 */ ADC1_GPIO(0), /* PA1 */ ADC1_GPIO(1), /* PA2 */ ADC1_GPIO(2), /* PA3 */ ADC1_GPIO(3),           \
+		/* PA4 */ ADC1_GPIO(4), /* PB8 */ ADC1_GPIO(8), /* PC0 */ ADC1_GPIO(10), /* PC1 */ ADC1_GPIO(11), \
+		/* PC2 */ ADC1_GPIO(12), /* PC3 */ ADC1_GPIO(13), /* PC4 */ ADC1_GPIO(14)
 
 /* Define Channel numbers must match above GPIO pin IN(n)*/
 
-#define ADC_BATTERY1_VOLTAGE_CHANNEL        /* PA0 */  ADC1_CH(0)
+#define ADC_BATTERY1_VOLTAGE_CHANNEL /* PA0 */ ADC1_CH(0)
 
-#define ADC_CHANNELS \
-	((1 << ADC_BATTERY1_VOLTAGE_CHANNEL))
+#define ADC_CHANNELS ((1 << ADC_BATTERY1_VOLTAGE_CHANNEL))
 
 /* HW has to large of R termination on ADC todo:change when HW value is chosen */
 
-#define BOARD_ADC_OPEN_CIRCUIT_V               (5.6f)
+#define BOARD_ADC_OPEN_CIRCUIT_V (5.6f)
 
 /* PWM
  */
-#define DIRECT_PWM_OUTPUT_CHANNELS  9
+#define DIRECT_PWM_OUTPUT_CHANNELS 9
 
-#define BOARD_CAPTURE_GPIO /* PD14 */  (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTD|GPIO_PIN14)
+#define BOARD_CAPTURE_GPIO /* PD14 */ (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | GPIO_PORTD | GPIO_PIN14)
 
 /* High-resolution timer */
-#define HRT_TIMER		     5  /* use timer5 for the HRT */
-#define HRT_TIMER_CHANNEL    1  /* use capture/compare channel 3 */
+#define HRT_TIMER 5         /* use timer5 for the HRT */
+#define HRT_TIMER_CHANNEL 1 /* use capture/compare channel 3 */
 
 /* RC Serial port */
 
-#define RC_SERIAL_PORT                     "/dev/ttyS4"
+#define RC_SERIAL_PORT "/dev/ttyS4"
 
 /* Power switch controls ******************************************************/
 
-#define SDIO_SLOTNO                    0  /* Only one slot */
-#define SDIO_MINOR                     0
+#define SDIO_SLOTNO 0 /* Only one slot */
+#define SDIO_MINOR 0
 
 /* SD card bringup does not work if performed on the IDLE thread because it
  * will cause waiting.  Use either:
@@ -119,20 +109,19 @@
  */
 
 #if defined(CONFIG_BOARD_INITIALIZE) && !defined(CONFIG_LIB_BOARDCTL) && !defined(CONFIG_BOARD_INITTHREAD)
-#  warning SDIO initialization cannot be perfomed on the IDLE thread
+#warning SDIO initialization cannot be perfomed on the IDLE thread
 #endif
 
 /* AV-X_V1 never powers off the Servo rail */
 
-#define BOARD_ADC_SERVO_VALID     (1)
+#define BOARD_ADC_SERVO_VALID (1)
 
-#define ADC_BATTERY_VOLTAGE_CHANNEL  0
-#define ADC_BATTERY_CURRENT_CHANNEL  1 // TODO: review
+#define ADC_BATTERY_VOLTAGE_CHANNEL 0
+#define ADC_BATTERY_CURRENT_CHANNEL 1  // TODO: review
 
-#define BOARD_ADC_PERIPH_5V_OC  (!px4_arch_gpioread(GPIO_nVDD_5V_PERIPH_OC))
+#define BOARD_ADC_PERIPH_5V_OC (!px4_arch_gpioread(GPIO_nVDD_5V_PERIPH_OC))
 #define BOARD_ADC_HIPOWER_5V_OC (!px4_arch_gpioread(GPIO_nVDD_5V_HIPOWER_OC))
 
-
 /* This board provides a DMA pool and APIs */
 #define BOARD_DMA_ALLOC_POOL_SIZE 5120
 
@@ -140,11 +129,8 @@
 
 #define BOARD_HAS_ON_RESET 1
 
-#define PX4_GPIO_INIT_LIST { \
-		PX4_ADC_GPIO,                     \
-		GPIO_CAN1_RX,                     \
-		GPIO_CAN1_TX,                     \
-	}
+#define PX4_GPIO_INIT_LIST \
+	{ PX4_ADC_GPIO, GPIO_CAN1_RX, GPIO_CAN1_TX, }
 
 #define BOARD_ENABLE_CONSOLE_BUFFER
 
@@ -188,7 +174,6 @@ extern void stm32_spiinitialize(void);
 
 #define board_peripheral_reset(ms)
 
-
 #include <px4_platform_common/board_common.h>
 
 #endif /* __ASSEMBLY__ */

boards/av/x-v1/src/init.c

@@ -45,35 +45,33 @@
  * Included Files
  ****************************************************************************/
 
-#include "board_config.h"
-
+#include <arch/board/board.h>
+#include <chip.h>
+#include <debug.h>
+#include <drivers/drv_board_led.h>
+#include <drivers/drv_hrt.h>
+#include <errno.h>
+#include <nuttx/analog/adc.h>
+#include <nuttx/board.h>
+#include <nuttx/config.h>
+#include <nuttx/i2c/i2c_master.h>
+#include <nuttx/mm/gran.h>
+#include <nuttx/mmcsd.h>
+#include <nuttx/sdio.h>
+#include <nuttx/spi/spi.h>
+#include <px4_arch/io_timer.h>
+#include <px4_platform/board_dma_alloc.h>
+#include <px4_platform/gpio.h>
+#include <px4_platform_common/init.h>
 #include <stdbool.h>
 #include <stdio.h>
-#include <string.h>
-#include <debug.h>
-#include <errno.h>
-#include <syslog.h>
-
-#include <nuttx/config.h>
-#include <nuttx/board.h>
-#include <nuttx/spi/spi.h>
-#include <nuttx/i2c/i2c_master.h>
-#include <nuttx/sdio.h>
-#include <nuttx/mmcsd.h>
-#include <nuttx/analog/adc.h>
-#include <nuttx/mm/gran.h>
-#include <chip.h>
 #include <stm32_uart.h>
-#include <arch/board/board.h>
-#include "arm_internal.h"
-
-#include <px4_arch/io_timer.h>
-#include <drivers/drv_hrt.h>
-#include <drivers/drv_board_led.h>
+#include <string.h>
+#include <syslog.h>
 #include <systemlib/px4_macros.h>
-#include <px4_platform_common/init.h>
-#include <px4_platform/gpio.h>
-#include <px4_platform/board_dma_alloc.h>
+
+#include "arm_internal.h"
+#include "board_config.h"
 
 static int configure_switch(void);
 
@@ -88,8 +86,7 @@ static int configure_switch(void);
  *          0 if just resetting
  *
  ************************************************************************************/
-__EXPORT void board_on_reset(int status)
-{
+__EXPORT void board_on_reset(int status) {
 	for (int i = 0; i < DIRECT_PWM_OUTPUT_CHANNELS; ++i) {
 		px4_arch_configgpio(PX4_MAKE_GPIO_INPUT(io_timer_channel_get_as_pwm_input(i)));
 	}
@@ -109,9 +106,7 @@ __EXPORT void board_on_reset(int status)
  *
  ************************************************************************************/
 
-__EXPORT void
-stm32_boardinitialize(void)
-{
+__EXPORT void stm32_boardinitialize(void) {
 	board_on_reset(-1); /* Reset PWM first thing */
 
 	/* configure LEDs */
@@ -150,9 +145,7 @@ stm32_boardinitialize(void)
  *
  ****************************************************************************/
 
-
-__EXPORT int board_app_initialize(uintptr_t arg)
-{
+__EXPORT int board_app_initialize(uintptr_t arg) {
 	px4_platform_init();
 
 	/* configure the DMA allocator */
@@ -167,7 +160,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
 	hrt_call_every(&serial_dma_call, 1000, 1000, (hrt_callout)stm32_serial_dma_poll, NULL);
 #endif
 
-	(void) board_hardfault_init(2, true);
+	(void)board_hardfault_init(2, true);
 
 #ifdef CONFIG_MMCSD
 
@@ -195,8 +188,7 @@ __EXPORT int board_app_initialize(uintptr_t arg)
  * Configure KSZ9897R ethernet switch on i2c
  *
  ************************************************************************************/
-static int configure_switch(void)
-{
+static int configure_switch(void) {
 	int ret = PX4_ERROR;
 
 	// attach to the i2c bus (internal)
@@ -207,7 +199,7 @@ static int configure_switch(void)
 	}
 
 	// ethernet switch enable
-	uint8_t txdata[] = {0x51, 0x00, 0x21, 0x00}; //0x5100, 0x2100 MSB to LSB here.
+	uint8_t txdata[] = {0x51, 0x00, 0x21, 0x00};  // 0x5100, 0x2100 MSB to LSB here.
 
 	struct i2c_msg_s msgv;
 

boards/av/x-v1/src/sdio.c

@@ -36,34 +36,31 @@
  * Included Files
  ****************************************************************************/
 
-#include <nuttx/config.h>
 #include <board_config.h>
-
-#include <stdbool.h>
-#include <stdio.h>
 #include <debug.h>
 #include <errno.h>
-
-#include <nuttx/sdio.h>
+#include <nuttx/config.h>
 #include <nuttx/mmcsd.h>
+#include <nuttx/sdio.h>
+#include <stdbool.h>
+#include <stdio.h>
 
-#include "chip.h"
 #include "board_config.h"
+#include "chip.h"
 #include "stm32_gpio.h"
 #include "stm32_sdmmc.h"
 
 #ifdef CONFIG_MMCSD
 
-
 /****************************************************************************
  * Pre-processor Definitions
  ****************************************************************************/
 
 /* Card detections requires card support and a card detection GPIO */
 
-#define HAVE_NCD   1
+#define HAVE_NCD 1
 #if !defined(GPIO_SDMMC1_NCD)
-#  undef HAVE_NCD
+#undef HAVE_NCD
 #endif
 
 /****************************************************************************
@@ -88,8 +85,7 @@ static bool g_sd_inserted = 0xff; /* Impossible value */
  ****************************************************************************/
 
 #ifdef HAVE_NCD
-static int stm32_ncd_interrupt(int irq, FAR void *context)
-{
+static int stm32_ncd_interrupt(int irq, FAR void *context) {
 	bool present;
 
 	present = !stm32_gpioread(GPIO_SDMMC1_NCD);
@@ -115,8 +111,7 @@ static int stm32_ncd_interrupt(int irq, FAR void *context)
  *
  ****************************************************************************/
 
-int stm32_sdio_initialize(void)
-{
+int stm32_sdio_initialize(void) {
 	int ret;
 
 #ifdef HAVE_NCD

boards/av/x-v1/src/spi.cpp

@@ -31,24 +31,32 @@
  *
  ****************************************************************************/
 
-#include <px4_arch/spi_hw_description.h>
 #include <drivers/drv_sensor.h>
 #include <nuttx/spi/spi.h>
+#include <px4_arch/spi_hw_description.h>
 
 constexpr px4_spi_bus_t px4_spi_buses[SPI_BUS_MAX_BUS_ITEMS] = {
-	initSPIBus(SPI::Bus::SPI1, {
-		initSPIDevice(DRV_IMU_DEVTYPE_ADIS16477, SPI::CS{GPIO::PortG, GPIO::Pin10}, SPI::DRDY{GPIO::PortJ, GPIO::Pin0}),
-	}),
-	initSPIBusExternal(SPI::Bus::SPI2, {
-		initSPIConfigExternal(SPI::CS{GPIO::PortI, GPIO::Pin0}),
-	}),
-	initSPIBus(SPI::Bus::SPI4, {
-		initSPIDevice(DRV_BARO_DEVTYPE_LPS22HB, SPI::CS{GPIO::PortE, GPIO::Pin4}, SPI::DRDY{GPIO::PortK, GPIO::Pin1}),
-	}),
-	initSPIBus(SPI::Bus::SPI5, {
-		initSPIDevice(DRV_MAG_DEVTYPE_LSM303AGR, SPI::CS{GPIO::PortH, GPIO::Pin5}, SPI::DRDY{GPIO::PortK, GPIO::Pin7}),
-		initSPIDevice(DRV_ACC_DEVTYPE_LSM303AGR, SPI::CS{GPIO::PortB, GPIO::Pin0}, SPI::DRDY{GPIO::PortD, GPIO::Pin12}),
-	}),
+	initSPIBus(SPI::Bus::SPI1,
+		   {
+			   initSPIDevice(DRV_IMU_DEVTYPE_ADIS16477, SPI::CS{GPIO::PortG, GPIO::Pin10},
+					 SPI::DRDY{GPIO::PortJ, GPIO::Pin0}),
+		   }),
+	initSPIBusExternal(SPI::Bus::SPI2,
+			   {
+				   initSPIConfigExternal(SPI::CS{GPIO::PortI, GPIO::Pin0}),
+			   }),
+	initSPIBus(SPI::Bus::SPI4,
+		   {
+			   initSPIDevice(DRV_BARO_DEVTYPE_LPS22HB, SPI::CS{GPIO::PortE, GPIO::Pin4},
+					 SPI::DRDY{GPIO::PortK, GPIO::Pin1}),
+		   }),
+	initSPIBus(SPI::Bus::SPI5,
+		   {
+			   initSPIDevice(DRV_MAG_DEVTYPE_LSM303AGR, SPI::CS{GPIO::PortH, GPIO::Pin5},
+					 SPI::DRDY{GPIO::PortK, GPIO::Pin7}),
+			   initSPIDevice(DRV_ACC_DEVTYPE_LSM303AGR, SPI::CS{GPIO::PortB, GPIO::Pin0},
+					 SPI::DRDY{GPIO::PortD, GPIO::Pin12}),
+		   }),
 };
 
 static constexpr bool unused = validateSPIConfig(px4_spi_buses);