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drivers/imu/bosch/bmi055: remove interrupt latch

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- the latch would actually cause more problems if the backup schedule hit
 - this reduces the number of cycles where the FIFO is actually empty at max rate (when there's only 1 sample in the FIFO expected)
This commit is contained in:
Daniel Agar
2020-07-09 10:15:33 -04:00
committed by GitHub
parent 194029d010
commit fa8ba09f50
4 changed files with 2 additions and 19 deletions
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src/drivers/imu/bosch/bmi055/BMI055_Accelerometer.hpp
+1 -2
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@@ -110,7 +110,7 @@ private:
uint8_t _fifo_accel_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / ACCEL_RATE))}; uint8_t _fifo_accel_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / ACCEL_RATE))};
uint8_t _checked_register{0}; uint8_t _checked_register{0};
static constexpr uint8_t size_register_cfg{8}; static constexpr uint8_t size_register_cfg{7};
register_config_t _register_cfg[size_register_cfg] { register_config_t _register_cfg[size_register_cfg] {
// Register | Set bits, Clear bits // Register | Set bits, Clear bits
{ Register::PMU_RANGE, PMU_RANGE_BIT::range_16g, Bit1 | Bit0}, { Register::PMU_RANGE, PMU_RANGE_BIT::range_16g, Bit1 | Bit0},
@@ -118,7 +118,6 @@ private:
{ Register::INT_EN_1, INT_EN_1_BIT::int_fwm_en, 0}, { Register::INT_EN_1, INT_EN_1_BIT::int_fwm_en, 0},
{ Register::INT_MAP_1, INT_MAP_1_BIT::int1_fwm, 0}, { Register::INT_MAP_1, INT_MAP_1_BIT::int1_fwm, 0},
{ Register::INT_OUT_CTRL, 0, INT_OUT_CTRL_BIT::int1_od | INT_OUT_CTRL_BIT::int1_lvl}, { Register::INT_OUT_CTRL, 0, INT_OUT_CTRL_BIT::int1_od | INT_OUT_CTRL_BIT::int1_lvl},
{ Register::INT_RST_LATCH, INT_RST_LATCH_BIT::temporary_250us, 0},
{ Register::FIFO_CONFIG_0, 0, 0 }, // fifo_water_mark_level_trigger_retain<5:0> { Register::FIFO_CONFIG_0, 0, 0 }, // fifo_water_mark_level_trigger_retain<5:0>
{ Register::FIFO_CONFIG_1, FIFO_CONFIG_1_BIT::fifo_mode, 0}, { Register::FIFO_CONFIG_1, FIFO_CONFIG_1_BIT::fifo_mode, 0},
}; };
src/drivers/imu/bosch/bmi055/BMI055_Gyroscope.hpp
+1 -2
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@@ -108,7 +108,7 @@ private:
uint8_t _fifo_gyro_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))}; uint8_t _fifo_gyro_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
uint8_t _checked_register{0}; uint8_t _checked_register{0};
static constexpr uint8_t size_register_cfg{9}; static constexpr uint8_t size_register_cfg{8};
register_config_t _register_cfg[size_register_cfg] { register_config_t _register_cfg[size_register_cfg] {
// Register | Set bits, Clear bits // Register | Set bits, Clear bits
{ Register::RANGE, RANGE_BIT::gyro_range_2000_dps, 0 }, { Register::RANGE, RANGE_BIT::gyro_range_2000_dps, 0 },
@@ -117,7 +117,6 @@ private:
{ Register::INT_EN_1, 0, INT_EN_1_BIT::int1_od | INT_EN_1_BIT::int1_lvl }, { Register::INT_EN_1, 0, INT_EN_1_BIT::int1_od | INT_EN_1_BIT::int1_lvl },
{ Register::INT_MAP_1, INT_MAP_1_BIT::int1_fifo, 0 }, { Register::INT_MAP_1, INT_MAP_1_BIT::int1_fifo, 0 },
{ Register::FIFO_WM_ENABLE, FIFO_WM_ENABLE_BIT::fifo_wm_enable, 0 }, { Register::FIFO_WM_ENABLE, FIFO_WM_ENABLE_BIT::fifo_wm_enable, 0 },
{ Register::INT_RST_LATCH, INT_RST_LATCH_BIT::temporary_250us, 0 },
{ Register::FIFO_CONFIG_0, 0, FIFO_CONFIG_0_BIT::tag }, // fifo_water_mark_level_trigger_retain<6:0> { Register::FIFO_CONFIG_0, 0, FIFO_CONFIG_0_BIT::tag }, // fifo_water_mark_level_trigger_retain<6:0>
{ Register::FIFO_CONFIG_1, FIFO_CONFIG_1_BIT::fifo_mode, 0 }, { Register::FIFO_CONFIG_1, FIFO_CONFIG_1_BIT::fifo_mode, 0 },
}; };
src/drivers/imu/bosch/bmi055/Bosch_BMI055_Accelerometer_Registers.hpp
-7
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@@ -69,7 +69,6 @@ enum class Register : uint8_t {
INT_MAP_1 = 0x1A, INT_MAP_1 = 0x1A,
INT_OUT_CTRL = 0x20, INT_OUT_CTRL = 0x20,
INT_RST_LATCH = 0x21,
FIFO_CONFIG_0 = 0x30, FIFO_CONFIG_0 = 0x30,
@@ -128,12 +127,6 @@ enum INT_OUT_CTRL_BIT : uint8_t {
int1_lvl = Bit0, int1_lvl = Bit0,
}; };
// INT_RST_LATCH
enum INT_RST_LATCH_BIT : uint8_t {
// latch_int<3:0>
temporary_250us = Bit3 | Bit0, // 1001b -> temporary, 250 us
};
// FIFO_CONFIG_1 // FIFO_CONFIG_1
enum FIFO_CONFIG_1_BIT : uint8_t { enum FIFO_CONFIG_1_BIT : uint8_t {
fifo_mode = Bit6, fifo_mode = Bit6,
src/drivers/imu/bosch/bmi055/Bosch_BMI055_Gyroscope_Registers.hpp
-8
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@@ -66,8 +66,6 @@ enum class Register : uint8_t {
FIFO_WM_ENABLE = 0x1E, FIFO_WM_ENABLE = 0x1E,
INT_RST_LATCH = 0x21,
FIFO_CONFIG_0 = 0x3D, FIFO_CONFIG_0 = 0x3D,
FIFO_CONFIG_1 = 0x3E, FIFO_CONFIG_1 = 0x3E,
FIFO_DATA = 0x3F, FIFO_DATA = 0x3F,
@@ -116,12 +114,6 @@ enum FIFO_WM_ENABLE_BIT : uint8_t {
fifo_wm_enable = Bit7, fifo_wm_enable = Bit7,
}; };
// INT_RST_LATCH
enum INT_RST_LATCH_BIT : uint8_t {
// latch_int<3:0>
temporary_250us = Bit3 | Bit0, // 1001b -> temporary, 250 us
};
// FIFO_CONFIG_0 // FIFO_CONFIG_0
enum FIFO_CONFIG_0_BIT : uint8_t { enum FIFO_CONFIG_0_BIT : uint8_t {
tag = Bit7, tag = Bit7,