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Merge pull request #106 from EShamaev/stm32_filtering_support
stm32 driver configuration of filters
This commit is contained in:
@@ -23,6 +23,7 @@ static const uavcan::int16_t ErrUnsupportedFrame = 1004; ///< Frame not s
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static const uavcan::int16_t ErrMsrInakNotSet = 1005; ///< INAK bit of the MSR register is not 1
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static const uavcan::int16_t ErrMsrInakNotSet = 1005; ///< INAK bit of the MSR register is not 1
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static const uavcan::int16_t ErrMsrInakNotCleared = 1006; ///< INAK bit of the MSR register is not 0
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static const uavcan::int16_t ErrMsrInakNotCleared = 1006; ///< INAK bit of the MSR register is not 0
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static const uavcan::int16_t ErrBitRateNotDetected = 1007; ///< Auto bit rate detection could not be finished
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static const uavcan::int16_t ErrBitRateNotDetected = 1007; ///< Auto bit rate detection could not be finished
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static const uavcan::int16_t ErrFilterNumConfigs = 1008; ///< Number of filters is more than supported
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/**
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/**
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* RX queue item.
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* RX queue item.
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@@ -450,11 +450,84 @@ uavcan::int16_t CanIface::receive(uavcan::CanFrame& out_frame, uavcan::Monotonic
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uavcan::int16_t CanIface::configureFilters(const uavcan::CanFilterConfig* filter_configs,
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uavcan::int16_t CanIface::configureFilters(const uavcan::CanFilterConfig* filter_configs,
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uavcan::uint16_t num_configs)
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uavcan::uint16_t num_configs)
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{
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{
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// TODO: Hardware filter support
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if (num_configs <= NumFilters)
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CriticalSectionLocker lock;
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{
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(void)filter_configs;
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CriticalSectionLocker lock;
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(void)num_configs;
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return -ErrNotImplemented;
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can_->FMR |= bxcan::FMR_FINIT;
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// Slave (CAN2) gets half of the filters
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can_->FMR &= ~0x00003F00UL;
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can_->FMR |= static_cast<uint32_t>(NumFilters) << 8;
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can_->FFA1R = 0x0AAAAAAA; // FIFO's are interleaved between filters
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can_->FM1R = 0; // Identifier Mask mode
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can_->FS1R = 0x7ffffff; // Single 32-bit for all
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const uint8_t filter_start_index = (self_index_ == 0) ? 0 : NumFilters;
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if (num_configs == 0)
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{
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can_->FilterRegister[filter_start_index].FR1 = 0;
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can_->FilterRegister[filter_start_index].FR2 = 0;
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can_->FA1R = 1 << filter_start_index;
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}
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else
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{
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for (uint8_t i = 0; i < NumFilters; i++)
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{
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if (i < num_configs)
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{
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uint32_t id = 0;
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uint32_t mask = 0;
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const uavcan::CanFilterConfig* const cfg = filter_configs + i;
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if ((cfg->id & uavcan::CanFrame::FlagEFF) || !(cfg->mask & uavcan::CanFrame::FlagEFF))
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{
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id = (cfg->id & uavcan::CanFrame::MaskExtID) << 3;
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mask = (cfg->mask & uavcan::CanFrame::MaskExtID) << 3;
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id |= bxcan::RIR_IDE;
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}
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else
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{
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id = (cfg->id & uavcan::CanFrame::MaskStdID) << 21; // Regular std frames, nothing fancy.
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mask = (cfg->mask & uavcan::CanFrame::MaskStdID) << 21; // Boring.
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}
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if (cfg->id & uavcan::CanFrame::FlagRTR)
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{
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id |= bxcan::RIR_RTR;
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}
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if (cfg->mask & uavcan::CanFrame::FlagEFF)
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{
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mask |= bxcan::RIR_IDE;
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}
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if (cfg->mask & uavcan::CanFrame::FlagRTR)
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{
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mask |= bxcan::RIR_RTR;
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}
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can_->FilterRegister[filter_start_index + i].FR1 = id;
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can_->FilterRegister[filter_start_index + i].FR2 = mask;
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can_->FA1R |= (1 << (filter_start_index + i));
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}
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else
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{
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can_->FA1R &= ~(1 << (filter_start_index + i));
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}
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}
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}
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can_->FMR &= ~bxcan::FMR_FINIT;
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return 0;
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}
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return -ErrFilterNumConfigs;
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}
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}
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bool CanIface::waitMsrINakBitStateChange(bool target_state)
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bool CanIface::waitMsrINakBitStateChange(bool target_state)
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