fly316/PX4-Autopilot
7
0
Fork 0
mirror of https://gitee.com/mirrors_PX4/PX4-Autopilot.git synced 2026-04-14 10:07:39 +08:00
Code Issues Packages Projects Releases Wiki Activity

Removed BACKPORT patches in upstream

Browse Source
This commit is contained in:
David Sidrane 2017-03-24 15:27:18 -10:00 committed by Daniel Agar
parent 5f92fe7e51
commit f50b9ddbae
9 changed files with 0 additions and 1905 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

217
nuttx-patches/00010-BACKPORT-stm32-flash-F4-dcache-corruption-fix-no-HSI-on.patch
View File

@ -1,217 +0,0 @@
diff --git NuttX/nuttx/arch/arm/src/stm32/Kconfig NuttX/nuttx/arch/arm/src/stm32/Kconfig
index b6c0458..8ebf8df 100644
--- NuttX/nuttx/arch/arm/src/stm32/Kconfig
+++ NuttX/nuttx/arch/arm/src/stm32/Kconfig
@@ -2514,6 +2514,14 @@ config STM32_FLASH_PREFETCH
on F1 parts). Some early revisions of F4 parts do not support FLASH pre-fetch
properly and enabling this option may interfere with ADC accuracy.
+config STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
+ bool "Workaround for FLASH data cache corruption"
+ default n
+ ---help---
+ Enable the workaround to fix flash data cache corruption when reading
+ from one flash bank while writing on other flash bank. See your STM32
+ errata to check if your STM32 is affected by this problem.
+
choice
prompt "JTAG Configuration"
default STM32_JTAG_DISABLE
diff --git NuttX/nuttx/arch/arm/src/stm32/chip/stm32_flash.h NuttX/nuttx/arch/arm/src/stm32/chip/stm32_flash.h
index 70e6d62..82d8f09 100644
--- NuttX/nuttx/arch/arm/src/stm32/chip/stm32_flash.h
+++ NuttX/nuttx/arch/arm/src/stm32/chip/stm32_flash.h
@@ -322,10 +322,11 @@
# define FLASH_CR_SER (1 << 1) /* Bit 1: Sector Erase */
# define FLASH_CR_MER (1 << 2) /* Bit 2: Mass Erase sectors 0..11 */
# define FLASH_CR_SNB_SHIFT (3) /* Bits 3-6: Sector number */
-# define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT)
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429)
+# define FLASH_CR_SNB_MASK (31 << FLASH_CR_SNB_SHIFT)
# define FLASH_CR_SNB(n) (((n % 12) << FLASH_CR_SNB_SHIFT) | ((n / 12) << 7)) /* Sector n, n=0..23 */
#else
+# define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT)
# define FLASH_CR_SNB(n) ((n) << FLASH_CR_SNB_SHIFT) /* Sector n, n=0..11 */
#endif
# define FLASH_CR_PSIZE_SHIFT (8) /* Bits 8-9: Program size */
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
index 73f1419..fb1e1ca 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_flash.c
@@ -47,6 +47,10 @@
#include <nuttx/config.h>
#include <nuttx/arch.h>
+
+#include <stdbool.h>
+#include <semaphore.h>
+#include <assert.h>
#include <errno.h>
#include "stm32_flash.h"
@@ -81,13 +85,29 @@
#endif
/************************************************************************************
- * Private Functions
+ * Private Data
************************************************************************************/
+static sem_t g_sem = SEM_INITIALIZER(1);
+
/************************************************************************************
- * Public Functions
+ * Private Functions
************************************************************************************/
-void stm32_flash_unlock(void)
+
+static void sem_lock(void)
+{
+ while (sem_wait(&g_sem) < 0)
+ {
+ DEBUGASSERT(errno == EINTR);
+ }
+}
+
+static inline void sem_unlock(void)
+{
+ sem_post(&g_sem);
+}
+
+static void flash_unlock(void)
{
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY)
{
@@ -103,14 +123,48 @@ void stm32_flash_unlock(void)
}
}
-void stm32_flash_lock(void)
+static void flash_lock(void)
{
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_LOCK);
}
+#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
+static void data_cache_disable(void)
+{
+ modifyreg32(STM32_FLASH_ACR, FLASH_ACR_DCEN, 0);
+}
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+static void data_cache_enable(void)
+{
+ /* Reset data cache */
+
+ modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCRST);
+
+ /* Enable data cache */
+
+ modifyreg32(STM32_FLASH_ACR, 0, FLASH_ACR_DCEN);
+}
+#endif /* defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW) */
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+void stm32_flash_unlock(void)
+{
+ sem_lock();
+ flash_unlock();
+ sem_unlock();
+}
+void stm32_flash_lock(void)
+{
+ sem_lock();
+ flash_lock();
+ sem_unlock();
+}
+
+#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
size_t up_progmem_pagesize(size_t page)
{
return STM32_FLASH_PAGESIZE;
@@ -231,14 +285,19 @@ ssize_t up_progmem_erasepage(size_t page)
return -EFAULT;
}
- /* Get flash ready and begin erasing single page */
+ sem_lock();
+#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
+ sem_unlock();
return -EPERM;
}
+#endif
+
+ /* Get flash ready and begin erasing single page */
- stm32_flash_unlock();
+ flash_unlock();
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PAGE_ERASE);
@@ -257,6 +316,7 @@ ssize_t up_progmem_erasepage(size_t page)
while (getreg32(STM32_FLASH_SR) & FLASH_SR_BSY) up_waste();
modifyreg32(STM32_FLASH_CR, FLASH_CR_PAGE_ERASE, 0);
+ sem_unlock();
/* Verify */
if (up_progmem_ispageerased(page) == 0)
@@ -318,14 +378,23 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
return -EFAULT;
}
- /* Get flash ready and begin flashing */
+ sem_lock();
+#if !defined(CONFIG_STM32_STM32F40XX)
if (!(getreg32(STM32_RCC_CR) & RCC_CR_HSION))
{
+ sem_unlock();
return -EPERM;
}
+#endif
+
+ /* Get flash ready and begin flashing */
+
+ flash_unlock();
- stm32_flash_unlock();
+#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
+ data_cache_disable();
+#endif
modifyreg32(STM32_FLASH_CR, 0, FLASH_CR_PG);
@@ -347,17 +416,25 @@ ssize_t up_progmem_write(size_t addr, const void *buf, size_t count)
if (getreg32(STM32_FLASH_SR) & FLASH_SR_WRITE_PROTECTION_ERROR)
{
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
+ sem_unlock();
return -EROFS;
}
if (getreg16(addr) != *hword)
{
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
+ sem_unlock();
return -EIO;
}
}
modifyreg32(STM32_FLASH_CR, FLASH_CR_PG, 0);
+
+#if defined(CONFIG_STM32_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW)
+ data_cache_enable();
+#endif
+
+ sem_unlock();
return written;
}

456
nuttx-patches/00011-BACKPORT-priority-restoration-fix.patch
View File

@ -1,456 +0,0 @@
diff --git NuttX/nuttx/include/semaphore.h NuttX/nuttx/include/semaphore.h
index 8821b12..0056909 100644
--- NuttX/nuttx/include/semaphore.h
+++ NuttX/nuttx/include/semaphore.h
@@ -93,7 +93,7 @@ struct sem_s
# if CONFIG_SEM_PREALLOCHOLDERS > 0
FAR struct semholder_s *hhead; /* List of holders of semaphore counts */
# else
- struct semholder_s holder; /* Single holder */
+ struct semholder_s holder[2]; /* Slot for old and new holder */
# endif
#endif
};
@@ -104,12 +104,15 @@ typedef struct sem_s sem_t;
#ifdef CONFIG_PRIORITY_INHERITANCE
# if CONFIG_SEM_PREALLOCHOLDERS > 0
-# define SEM_INITIALIZER(c) {(c), 0, NULL} /* semcount, flags, hhead */
+# define SEM_INITIALIZER(c) \
+ {(c), 0, NULL} /* semcount, flags, hhead */
# else
-# define SEM_INITIALIZER(c) {(c), 0, SEMHOLDER_INITIALIZER} /* semcount, flags, holder */
+# define SEM_INITIALIZER(c) \
+ {(c), 0, {SEMHOLDER_INITIALIZER, SEMHOLDER_INITIALIZER}} /* semcount, flags, holder[2] */
# endif
#else
-# define SEM_INITIALIZER(c) {(c)} /* semcount */
+# define SEM_INITIALIZER(c) \
+ {(c)} /* semcount */
#endif
/****************************************************************************
diff --git NuttX/nuttx/libc/semaphore/sem_init.c NuttX/nuttx/libc/semaphore/sem_init.c
index f4037d3..ec7de27 100644
--- NuttX/nuttx/libc/semaphore/sem_init.c
+++ NuttX/nuttx/libc/semaphore/sem_init.c
@@ -83,17 +83,19 @@ int sem_init(FAR sem_t *sem, int pshared, unsigned int value)
{
/* Initialize the seamphore count */
- sem->semcount = (int16_t)value;
+ sem->semcount = (int16_t)value;
/* Initialize to support priority inheritance */
#ifdef CONFIG_PRIORITY_INHERITANCE
- sem->flags = 0;
+ sem->flags = 0;
# if CONFIG_SEM_PREALLOCHOLDERS > 0
- sem->hhead = NULL;
+ sem->hhead = NULL;
# else
- sem->holder.htcb = NULL;
- sem->holder.counts = 0;
+ sem->holder[0].htcb = NULL;
+ sem->holder[0].counts = 0;
+ sem->holder[1].htcb = NULL;
+ sem->holder[1].counts = 0;
# endif
#endif
return OK;
diff --git NuttX/nuttx/sched/semaphore/sem_holder.c NuttX/nuttx/sched/semaphore/sem_holder.c
index 6b9f05a..003b0ab 100644
--- NuttX/nuttx/sched/semaphore/sem_holder.c
+++ NuttX/nuttx/sched/semaphore/sem_holder.c
@@ -93,7 +93,7 @@ static inline FAR struct semholder_s *sem_allocholder(sem_t *sem)
#if CONFIG_SEM_PREALLOCHOLDERS > 0
pholder = g_freeholders;
- if (pholder)
+ if (pholder != NULL)
{
/* Remove the holder from the free list an put it into the semaphore's
* holder list
@@ -108,18 +108,24 @@ static inline FAR struct semholder_s *sem_allocholder(sem_t *sem)
pholder->counts = 0;
}
#else
- if (!sem->holder.htcb)
+ if (sem->holder[0].htcb == NULL)
{
- pholder = &sem->holder;
+ pholder = &sem->holder[0];
+ pholder->counts = 0;
+ }
+ else if (sem->holder[1].htcb == NULL)
+ {
+ pholder = &sem->holder[1];
pholder->counts = 0;
}
#endif
else
{
serr("ERROR: Insufficient pre-allocated holders\n");
- pholder = NULL;
+ pholder = NULL;
}
+ DEBUGASSERT(pholder != NULL);
return pholder;
}
@@ -132,16 +138,29 @@ static FAR struct semholder_s *sem_findholder(sem_t *sem,
{
FAR struct semholder_s *pholder;
+#if CONFIG_SEM_PREALLOCHOLDERS > 0
/* Try to find the holder in the list of holders associated with this
* semaphore
*/
-#if CONFIG_SEM_PREALLOCHOLDERS > 0
- for (pholder = sem->hhead; pholder; pholder = pholder->flink)
+ for (pholder = sem->hhead; pholder != NULL; pholder = pholder->flink)
+ {
+ if (pholder->htcb == htcb)
+ {
+ /* Got it! */
+
+ return pholder;
+ }
+ }
#else
- pholder = &sem->holder;
-#endif
+ int i;
+ pholder = NULL;
+
+ /* We have two hard-allocated holder structures in sem_t */
+
+ for (i = 0; i < 2; i++)
{
+ pholder = &sem->holder[i];
if (pholder->htcb == htcb)
{
/* Got it! */
@@ -149,6 +168,7 @@ static FAR struct semholder_s *sem_findholder(sem_t *sem,
return pholder;
}
}
+#endif
/* The holder does not appear in the list */
@@ -194,11 +214,11 @@ static inline void sem_freeholder(sem_t *sem, FAR struct semholder_s *pholder)
curr && curr != pholder;
prev = curr, curr = curr->flink);
- if (curr)
+ if (curr != NULL)
{
/* Remove the holder from the list */
- if (prev)
+ if (prev != NULL)
{
prev->flink = pholder->flink;
}
@@ -216,6 +236,24 @@ static inline void sem_freeholder(sem_t *sem, FAR struct semholder_s *pholder)
}
/****************************************************************************
+ * Name: sem_findandfreeholder
+ ****************************************************************************/
+
+static inline void sem_findandfreeholder(sem_t *sem, FAR struct tcb_s *htcb)
+{
+ FAR struct semholder_s *pholder = sem_findholder(sem, htcb);
+
+ /* When no more counts are held, remove the holder from the list. The
+ * count was decremented in sem_releaseholder.
+ */
+
+ if (pholder != NULL && pholder->counts <= 0)
+ {
+ sem_freeholder(sem, pholder);
+ }
+}
+
+/****************************************************************************
* Name: sem_foreachholder
****************************************************************************/
@@ -223,31 +261,47 @@ static int sem_foreachholder(FAR sem_t *sem, holderhandler_t handler,
FAR void *arg)
{
FAR struct semholder_s *pholder;
-#if CONFIG_SEM_PREALLOCHOLDERS > 0
- FAR struct semholder_s *next;
-#endif
int ret = 0;
#if CONFIG_SEM_PREALLOCHOLDERS > 0
+ FAR struct semholder_s *next;
+
for (pholder = sem->hhead; pholder && ret == 0; pholder = next)
-#else
- pholder = &sem->holder;
-#endif
{
-#if CONFIG_SEM_PREALLOCHOLDERS > 0
/* In case this holder gets deleted */
next = pholder->flink;
-#endif
- /* The initial "built-in" container may hold a NULL holder */
- if (pholder->htcb)
+ /* Check if there is a handler... there should always be one
+ * in this configuration.
+ */
+
+ if (pholder->htcb != NULL)
{
/* Call the handler */
ret = handler(pholder, sem, arg);
}
}
+#else
+ int i;
+
+ /* We have two hard-allocated holder structures in sem_t */
+
+ for (i = 0; i < 2; i++)
+ {
+ pholder = &sem->holder[i];
+
+ /* The hard-allocated containers may hold a NULL holder */
+
+ if (pholder->htcb != NULL)
+ {
+ /* Call the handler */
+
+ ret = handler(pholder, sem, arg);
+ }
+ }
+#endif
return ret;
}
@@ -284,11 +338,11 @@ static int sem_boostholderprio(FAR struct semholder_s *pholder,
if (!sched_verifytcb(htcb))
{
serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb);
+ DEBUGASSERT(sched_verifytcb(htcb));
sem_freeholder(sem, pholder);
}
#if CONFIG_SEM_NNESTPRIO > 0
-
/* If the priority of the thread that is waiting for a count is greater
* than the base priority of the thread holding a count, then we may need
* to adjust the holder's priority now or later to that priority.
@@ -322,6 +376,7 @@ static int sem_boostholderprio(FAR struct semholder_s *pholder,
else
{
serr("ERROR: CONFIG_SEM_NNESTPRIO exceeded\n");
+ DEBUGASSERT(htcb->npend_reprio < CONFIG_SEM_NNESTPRIO);
}
}
@@ -342,8 +397,16 @@ static int sem_boostholderprio(FAR struct semholder_s *pholder,
* saved priority and not to the base priority.
*/
- htcb->pend_reprios[htcb->npend_reprio] = rtcb->sched_priority;
- htcb->npend_reprio++;
+ if (htcb->npend_reprio < CONFIG_SEM_NNESTPRIO)
+ {
+ htcb->pend_reprios[htcb->npend_reprio] = rtcb->sched_priority;
+ htcb->npend_reprio++;
+ }
+ else
+ {
+ serr("ERROR: CONFIG_SEM_NNESTPRIO exceeded\n");
+ DEBUGASSERT(htcb->npend_reprio < CONFIG_SEM_NNESTPRIO);
+ }
}
}
@@ -415,10 +478,10 @@ static int sem_dumpholder(FAR struct semholder_s *pholder, FAR sem_t *sem,
* Name: sem_restoreholderprio
****************************************************************************/
-static int sem_restoreholderprio(FAR struct semholder_s *pholder,
+static int sem_restoreholderprio(FAR struct tcb_s *htcb,
FAR sem_t *sem, FAR void *arg)
{
- FAR struct tcb_s *htcb = (FAR struct tcb_s *)pholder->htcb;
+ FAR struct semholder_s *pholder = 0;
#if CONFIG_SEM_NNESTPRIO > 0
FAR struct tcb_s *stcb = (FAR struct tcb_s *)arg;
int rpriority;
@@ -435,7 +498,12 @@ static int sem_restoreholderprio(FAR struct semholder_s *pholder,
if (!sched_verifytcb(htcb))
{
serr("ERROR: TCB 0x%08x is a stale handle, counts lost\n", htcb);
- sem_freeholder(sem, pholder);
+ DEBUGASSERT(sched_verifytcb(htcb));
+ pholder = sem_findholder(sem, htcb);
+ if (pholder != NULL)
+ {
+ sem_freeholder(sem, pholder);
+ }
}
/* Was the priority of the holder thread boosted? If so, then drop its
@@ -555,6 +623,20 @@ static int sem_restoreholderprio(FAR struct semholder_s *pholder,
}
/****************************************************************************
+ * Name: sem_restoreholderprioall
+ *
+ * Description:
+ * Reprioritize all holders
+ *
+ ****************************************************************************/
+
+static int sem_restoreholderprioall(FAR struct semholder_s *pholder,
+ FAR sem_t *sem, FAR void *arg)
+{
+ return sem_restoreholderprio(pholder->htcb, sem, arg);
+}
+
+/****************************************************************************
* Name: sem_restoreholderprioA
*
* Description:
@@ -568,7 +650,7 @@ static int sem_restoreholderprioA(FAR struct semholder_s *pholder,
FAR struct tcb_s *rtcb = this_task();
if (pholder->htcb != rtcb)
{
- return sem_restoreholderprio(pholder, sem, arg);
+ return sem_restoreholderprio(pholder->htcb, sem, arg);
}
return 0;
@@ -586,9 +668,22 @@ static int sem_restoreholderprioB(FAR struct semholder_s *pholder,
FAR sem_t *sem, FAR void *arg)
{
FAR struct tcb_s *rtcb = this_task();
+
if (pholder->htcb == rtcb)
{
- (void)sem_restoreholderprio(pholder, sem, arg);
+
+ /* The running task has given up a count on the semaphore */
+
+#if CONFIG_SEM_PREALLOCHOLDERS == 0
+ /* In the case where there are only 2 holders. This step
+ * is necessary to insure we have space. Release the holder
+ * if all counts have been given up. before reprioritizing
+ * causes a context switch.
+ */
+
+ sem_findandfreeholder(sem, rtcb);
+#endif
+ (void)sem_restoreholderprio(rtcb, sem, arg);
return 1;
}
@@ -637,11 +732,11 @@ static inline void sem_restorebaseprio_irq(FAR struct tcb_s *stcb,
* next highest pending priority.
*/
- if (stcb)
+ if (stcb != NULL)
{
/* Drop the priority of all holder threads */
- (void)sem_foreachholder(sem, sem_restoreholderprio, stcb);
+ (void)sem_foreachholder(sem, sem_restoreholderprioall, stcb);
}
/* If there are no tasks waiting for available counts, then all holders
@@ -692,7 +787,6 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb,
FAR sem_t *sem)
{
FAR struct tcb_s *rtcb = this_task();
- FAR struct semholder_s *pholder;
/* Perform the following actions only if a new thread was given a count.
* The thread that received the count should be the highest priority
@@ -701,7 +795,7 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb,
* next highest pending priority.
*/
- if (stcb)
+ if (stcb != NULL)
{
/* The currently executed thread should be the lower priority
* thread that just posted the count and caused this action.
@@ -735,18 +829,8 @@ static inline void sem_restorebaseprio_task(FAR struct tcb_s *stcb,
* counts, then we need to remove it from the list of holders.
*/
- pholder = sem_findholder(sem, rtcb);
- if (pholder)
- {
- /* When no more counts are held, remove the holder from the list. The
- * count was decremented in sem_releaseholder.
- */
+ sem_findandfreeholder(sem, rtcb);
- if (pholder->counts <= 0)
- {
- sem_freeholder(sem, pholder);
- }
- }
}
/****************************************************************************
@@ -817,18 +901,21 @@ void sem_destroyholder(FAR sem_t *sem)
*/
#if CONFIG_SEM_PREALLOCHOLDERS > 0
- if (sem->hhead)
+ if (sem->hhead != NULL)
{
serr("ERROR: Semaphore destroyed with holders\n");
+ DEBUGASSERT(sem->hhead == NULL);
(void)sem_foreachholder(sem, sem_recoverholders, NULL);
}
#else
- if (sem->holder.htcb)
+ if (sem->holder[0].htcb != NULL || sem->holder[1].htcb != NULL)
{
+ DEBUGASSERT(sem->holder[0].htcb == NULL || sem->holder[1].htcb == NULL);
serr("ERROR: Semaphore destroyed with holder\n");
}
- sem->holder.htcb = NULL;
+ sem->holder[0].htcb = NULL;
+ sem->holder[1].htcb = NULL;
#endif
}
@@ -952,7 +1039,7 @@ void sem_releaseholder(FAR sem_t *sem)
/* Find the container for this holder */
pholder = sem_findholder(sem, rtcb);
- if (pholder && pholder->counts > 0)
+ if (pholder != NULL && pholder->counts > 0)
{
/* Decrement the counts on this holder -- the holder will be freed
* later in sem_restorebaseprio.
@@ -1048,7 +1135,7 @@ void sem_canceled(FAR struct tcb_s *stcb, FAR sem_t *sem)
/* Adjust the priority of every holder as necessary */
- (void)sem_foreachholder(sem, sem_restoreholderprio, stcb);
+ (void)sem_foreachholder(sem, sem_restoreholderprioall, stcb);
}
#endif

494
nuttx-patches/00012-BACKPORT-stack-coloration-overreach-fix.patch
View File

@ -1,494 +0,0 @@
diff --git NuttX/nuttx/arch/arm/src/a1x/a1x_irq.c NuttX/nuttx/arch/arm/src/a1x/a1x_irq.c
index ecabb5f..21c074d 100644
--- NuttX/nuttx/arch/arm/src/a1x/a1x_irq.c
+++ NuttX/nuttx/arch/arm/src/a1x/a1x_irq.c
@@ -159,16 +159,6 @@ void up_irqinitialize(void)
(void)getreg32(A1X_INTC_IRQ_PEND(i)); /* Reading status clears pending interrupts */
}
- /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- {
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
- }
-#endif
-
/* Set the interrupt base address to zero. We do not use the vectored
* interrupts.
*/
diff --git NuttX/nuttx/arch/arm/src/armv7-m/gnu/up_exception.S NuttX/nuttx/arch/arm/src/armv7-m/gnu/up_exception.S
index 0010136..4f2927b 100644
--- NuttX/nuttx/arch/arm/src/armv7-m/gnu/up_exception.S
+++ NuttX/nuttx/arch/arm/src/armv7-m/gnu/up_exception.S
@@ -323,7 +323,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
- .skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
diff --git NuttX/nuttx/arch/arm/src/armv7-m/gnu/up_lazyexception.S NuttX/nuttx/arch/arm/src/armv7-m/gnu/up_lazyexception.S
index 08ce8be..eb3e270 100644
--- NuttX/nuttx/arch/arm/src/armv7-m/gnu/up_lazyexception.S
+++ NuttX/nuttx/arch/arm/src/armv7-m/gnu/up_lazyexception.S
@@ -235,7 +235,7 @@ exception_common:
*
* Here:
* r0 = Address of the register save area
-
+
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
@@ -355,7 +355,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
- .skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
diff --git NuttX/nuttx/arch/arm/src/common/up_createstack.c NuttX/nuttx/arch/arm/src/common/up_createstack.c
index 70d83a8..4503e15 100644
--- NuttX/nuttx/arch/arm/src/common/up_createstack.c
+++ NuttX/nuttx/arch/arm/src/common/up_createstack.c
@@ -66,22 +66,11 @@
# define HAVE_KERNEL_HEAP 1
#endif
-/* ARM requires at least a 4-byte stack alignment. For use with EABI and
- * floating point, the stack must be aligned to 8-byte addresses.
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
+ * addresses.
*/
-#ifndef CONFIG_STACK_ALIGNMENT
-
-/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you
- * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
- */
-
-# ifdef __ARM_EABI__
-# define CONFIG_STACK_ALIGNMENT 8
-# else
-# define CONFIG_STACK_ALIGNMENT 4
-# endif
-#endif
+#define CONFIG_STACK_ALIGNMENT 8
/* Stack alignment macros */
@@ -233,9 +222,9 @@ int up_create_stack(FAR struct tcb_s *tcb, size_t stack_size, uint8_t ttype)
top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
- /* The ARM stack must be aligned; 4 byte alignment for OABI and
- * 8-byte alignment for EABI. If necessary top_of_stack must be
- * rounded down to the next boundary
+ /* The ARM stack must be aligned to 8-byte alignment for EABI.
+ * If necessary top_of_stack must be rounded down to the next
+ * boundary
*/
top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
diff --git NuttX/nuttx/arch/arm/src/common/up_stackframe.c NuttX/nuttx/arch/arm/src/common/up_stackframe.c
index b5712b2..dace2e9 100644
--- NuttX/nuttx/arch/arm/src/common/up_stackframe.c
+++ NuttX/nuttx/arch/arm/src/common/up_stackframe.c
@@ -53,22 +53,11 @@
* Pre-processor Macros
****************************************************************************/
-/* ARM requires at least a 4-byte stack alignment. For use with EABI and
- * floating point, the stack must be aligned to 8-byte addresses.
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
+ * addresses.
*/
-#ifndef CONFIG_STACK_ALIGNMENT
-
-/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you
- * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
- */
-
-# ifdef __ARM_EABI__
-# define CONFIG_STACK_ALIGNMENT 8
-# else
-# define CONFIG_STACK_ALIGNMENT 4
-# endif
-#endif
+#define CONFIG_STACK_ALIGNMENT 8
/* Stack alignment macros */
diff --git NuttX/nuttx/arch/arm/src/common/up_usestack.c NuttX/nuttx/arch/arm/src/common/up_usestack.c
index 8873879..f8072a6 100644
--- NuttX/nuttx/arch/arm/src/common/up_usestack.c
+++ NuttX/nuttx/arch/arm/src/common/up_usestack.c
@@ -56,22 +56,11 @@
* Pre-processor Macros
****************************************************************************/
-/* ARM requires at least a 4-byte stack alignment. For use with EABI and
- * floating point, the stack must be aligned to 8-byte addresses.
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
+ * addresses.
*/
-#ifndef CONFIG_STACK_ALIGNMENT
-
-/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you
- * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
- */
-
-# ifdef __ARM_EABI__
-# define CONFIG_STACK_ALIGNMENT 8
-# else
-# define CONFIG_STACK_ALIGNMENT 4
-# endif
-#endif
+#define CONFIG_STACK_ALIGNMENT 8
/* Stack alignment macros */
@@ -143,9 +132,9 @@ int up_use_stack(struct tcb_s *tcb, void *stack, size_t stack_size)
top_of_stack = (uint32_t)tcb->stack_alloc_ptr + stack_size - 4;
- /* The ARM stack must be aligned; 4 byte alignment for OABI and 8-byte
- * alignment for EABI. If necessary top_of_stack must be rounded down
- * to the next boundary
+ /* The ARM stack must be aligned to 8-byte alignment for EABI.
+ * If necessary top_of_stack must be rounded down to the next
+ * boundary
*/
top_of_stack = STACK_ALIGN_DOWN(top_of_stack);
diff --git NuttX/nuttx/arch/arm/src/common/up_vfork.c NuttX/nuttx/arch/arm/src/common/up_vfork.c
index e655ab1..5a69e31 100644
--- NuttX/nuttx/arch/arm/src/common/up_vfork.c
+++ NuttX/nuttx/arch/arm/src/common/up_vfork.c
@@ -56,22 +56,11 @@
* Pre-processor Definitions
****************************************************************************/
-/* ARM requires at least a 4-byte stack alignment. For use with EABI and
- * floating point, the stack must be aligned to 8-byte addresses.
+/* For use with EABI and floating point, the stack must be aligned to 8-byte
+ * addresses.
*/
-#ifndef CONFIG_STACK_ALIGNMENT
-
-/* The symbol __ARM_EABI__ is defined by GCC if EABI is being used. If you
- * are not using GCC, make sure that CONFIG_STACK_ALIGNMENT is set correctly!
- */
-
-# ifdef __ARM_EABI__
-# define CONFIG_STACK_ALIGNMENT 8
-# else
-# define CONFIG_STACK_ALIGNMENT 4
-# endif
-#endif
+#define CONFIG_STACK_ALIGNMENT 8
/****************************************************************************
* Public Functions
diff --git NuttX/nuttx/arch/arm/src/efm32/efm32_irq.c NuttX/nuttx/arch/arm/src/efm32/efm32_irq.c
index db5992d..db31e68 100644
--- NuttX/nuttx/arch/arm/src/efm32/efm32_irq.c
+++ NuttX/nuttx/arch/arm/src/efm32/efm32_irq.c
@@ -319,16 +319,6 @@ void up_irqinitialize(void)
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- /* Colorize the interrupt stack for debug purposes */
-
- {
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
- }
-#endif
-
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
diff --git NuttX/nuttx/arch/arm/src/imx6/imx_irq.c NuttX/nuttx/arch/arm/src/imx6/imx_irq.c
index b15a9a4..d5248ef 100644
--- NuttX/nuttx/arch/arm/src/imx6/imx_irq.c
+++ NuttX/nuttx/arch/arm/src/imx6/imx_irq.c
@@ -93,16 +93,6 @@ void up_irqinitialize(void)
* access to the GIC.
*/
- /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- {
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
- }
-#endif
-
/* Initialize the Generic Interrupt Controller (GIC) for CPU0 */
arm_gic0_initialize(); /* Initialization unique to CPU0 */
diff --git NuttX/nuttx/arch/arm/src/kinetis/kinetis_vectors.S NuttX/nuttx/arch/arm/src/kinetis/kinetis_vectors.S
index 48c74c7..3094019 100644
--- NuttX/nuttx/arch/arm/src/kinetis/kinetis_vectors.S
+++ NuttX/nuttx/arch/arm/src/kinetis/kinetis_vectors.S
@@ -484,7 +484,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
- .skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
diff --git NuttX/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S NuttX/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
index 6cee7d9..9881472 100644
--- NuttX/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
+++ NuttX/nuttx/arch/arm/src/lpc17xx/lpc17_vectors.S
@@ -348,7 +348,7 @@ exception_common:
*
* Here:
* r0 = Address of the register save area
-
+
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
@@ -468,7 +468,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
- .skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
diff --git NuttX/nuttx/arch/arm/src/sam34/sam_irq.c NuttX/nuttx/arch/arm/src/sam34/sam_irq.c
index 0b3286d..a75caaf 100644
--- NuttX/nuttx/arch/arm/src/sam34/sam_irq.c
+++ NuttX/nuttx/arch/arm/src/sam34/sam_irq.c
@@ -385,16 +385,6 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
- /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- {
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
- }
-#endif
-
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
diff --git NuttX/nuttx/arch/arm/src/sam34/sam_vectors.S NuttX/nuttx/arch/arm/src/sam34/sam_vectors.S
index 9765f61..9de7d24 100644
--- NuttX/nuttx/arch/arm/src/sam34/sam_vectors.S
+++ NuttX/nuttx/arch/arm/src/sam34/sam_vectors.S
@@ -362,7 +362,7 @@ exception_common:
*
* Here:
* r0 = Address of the register save area
-
+
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
@@ -482,7 +482,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
- .skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
diff --git NuttX/nuttx/arch/arm/src/sama5/sam_irq.c NuttX/nuttx/arch/arm/src/sama5/sam_irq.c
index c8cf1f5..fd4dfd8 100644
--- NuttX/nuttx/arch/arm/src/sama5/sam_irq.c
+++ NuttX/nuttx/arch/arm/src/sama5/sam_irq.c
@@ -431,16 +431,6 @@ void up_irqinitialize(void)
* access to the AIC.
*/
- /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- {
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
- }
-#endif
-
/* Redirect all interrupts to the AIC if so configured */
sam_aic_redirection();
diff --git NuttX/nuttx/arch/arm/src/samv7/sam_irq.c NuttX/nuttx/arch/arm/src/samv7/sam_irq.c
index 08537f6..74d73d9 100644
--- NuttX/nuttx/arch/arm/src/samv7/sam_irq.c
+++ NuttX/nuttx/arch/arm/src/samv7/sam_irq.c
@@ -381,16 +381,6 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
- /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- {
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
- }
-#endif
-
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
diff --git NuttX/nuttx/arch/arm/src/stm32/gnu/stm32_vectors.S NuttX/nuttx/arch/arm/src/stm32/gnu/stm32_vectors.S
index a1a39df..6d2d193 100644
--- NuttX/nuttx/arch/arm/src/stm32/gnu/stm32_vectors.S
+++ NuttX/nuttx/arch/arm/src/stm32/gnu/stm32_vectors.S
@@ -493,7 +493,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
- .skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
diff --git NuttX/nuttx/arch/arm/src/stm32/iar/stm32_vectors.S NuttX/nuttx/arch/arm/src/stm32/iar/stm32_vectors.S
index cb9069d..450a9bc 100644
--- NuttX/nuttx/arch/arm/src/stm32/iar/stm32_vectors.S
+++ NuttX/nuttx/arch/arm/src/stm32/iar/stm32_vectors.S
@@ -1051,7 +1051,7 @@ l5:
.global g_intstackbase
.align 8
g_intstackalloc:
- .skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_irq.c NuttX/nuttx/arch/arm/src/stm32/stm32_irq.c
index ff40bf8..23313f5 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_irq.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_irq.c
@@ -310,16 +310,6 @@ void up_irqinitialize(void)
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
- /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- {
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
- }
-#endif
-
/* The standard location for the vector table is at the beginning of FLASH
* at address 0x0800:0000. If we are using the STMicro DFU bootloader, then
* the vector table will be offset to a different location in FLASH and we
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_irq.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_irq.c
index 758f32b..2a61490 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_irq.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_irq.c
@@ -415,16 +415,6 @@ void up_irqinitialize(void)
putreg32(0, regaddr);
}
- /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- {
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
- }
-#endif
-
/* Make sure that we are using the correct vector table. The default
* vector address is 0x0000:0000 but if we are executing code that is
* positioned in SRAM or in external FLASH, then we may need to reset
diff --git NuttX/nuttx/arch/arm/src/stm32l4/stm32l4_irq.c NuttX/nuttx/arch/arm/src/stm32l4/stm32l4_irq.c
index 720c05e..d9aeffd 100644
--- NuttX/nuttx/arch/arm/src/stm32l4/stm32l4_irq.c
+++ NuttX/nuttx/arch/arm/src/stm32l4/stm32l4_irq.c
@@ -304,16 +304,6 @@ void up_irqinitialize(void)
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
}
- /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- {
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
- }
-#endif
-
/* The standard location for the vector table is at the beginning of FLASH
* at address 0x0800:0000. If we are using the STMicro DFU bootloader, then
* the vector table will be offset to a different location in FLASH and we
diff --git NuttX/nuttx/arch/arm/src/tiva/tiva_vectors.S NuttX/nuttx/arch/arm/src/tiva/tiva_vectors.S
index 4f56269..943581c 100644
--- NuttX/nuttx/arch/arm/src/tiva/tiva_vectors.S
+++ NuttX/nuttx/arch/arm/src/tiva/tiva_vectors.S
@@ -339,7 +339,7 @@ exception_common:
*
* Here:
* r0 = Address of the register save area
-
+
* NOTE: It is a requirement that up_restorefpu() preserve the value of
* r0!
*/
@@ -459,7 +459,7 @@ exception_common:
.global g_intstackbase
.align 8
g_intstackalloc:
- .skip (CONFIG_ARCH_INTERRUPTSTACK & ~7)
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK + 4) & ~7)
g_intstackbase:
.size g_intstackalloc, .-g_intstackalloc
#endif
diff --git NuttX/nuttx/arch/arm/src/tms570/tms570_irq.c NuttX/nuttx/arch/arm/src/tms570/tms570_irq.c
index da9f8c5..be7cb05 100644
--- NuttX/nuttx/arch/arm/src/tms570/tms570_irq.c
+++ NuttX/nuttx/arch/arm/src/tms570/tms570_irq.c
@@ -115,14 +115,6 @@ void up_irqinitialize(void)
FAR uintptr_t *vimram;
int i;
- /* Colorize the interrupt stack for debug purposes */
-
-#if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3
- size_t intstack_size = (CONFIG_ARCH_INTERRUPTSTACK & ~3);
- up_stack_color((FAR void *)((uintptr_t)&g_intstackbase - intstack_size),
- intstack_size);
-#endif
-
/* Initialize VIM RAM vectors. These vectors are not used in the current
* interrupt handler logic.
*/

158
nuttx-patches/00015-BACKPORT-stm32f7-DTCM.patch
View File

@ -1,158 +0,0 @@
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_allocateheap.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_allocateheap.c
index 8b21ad6..ffa6d27 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_allocateheap.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_allocateheap.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/up_allocateheap.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
*
* Redistribution and use in source and binary forms, with or without
@@ -57,10 +57,12 @@
#include "up_arch.h"
#include "up_internal.h"
#include "stm32_mpuinit.h"
+#include "stm32_dtcm.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Internal SRAM is available in all members of the STM32 family. The
* following definitions must be provided to specify the size and
* location of internal(system) SRAM:
@@ -92,6 +94,20 @@
#define SRAM2_START STM32_SRAM2_BASE
#define SRAM2_END (SRAM2_START + STM32F7_SRAM2_SIZE)
+/* The STM32 F7 has DTCM memory */
+
+#undef HAVE_DTCM
+#define HAVE_DTCM 1
+#if !defined(DTCM_START) || !defined(DTCM_END)
+# undef HAVE_DTCM
+#endif
+
+/* DTCM to be excluded from the main heap. */
+
+#ifdef CONFIG_STM32F7_DTCMEXCLUDE
+# undef HAVE_DTCM
+#endif
+
/* We can't possibly have FSMC SRAM if the FSMC is not enabled */
#ifndef CONFIG_STM32F7_FSMC
@@ -110,7 +126,7 @@
# endif
#endif
-/* There are 3 possible heap configurations:
+/* There are 4 possible heap configurations:
*
* Configuration 1. System SRAM1 (only)
* CONFIG_MM_REGIONS == 1
@@ -118,9 +134,18 @@
* Configuration 2. System SRAM1 and SRAM2
* CONFIG_MM_REGIONS == 2
* CONFIG_STM32F7_FSMC_SRAM NOT defined
- * Configuration 3. System SRAM1 and SRAM2 and FSMC SRAM
+ * Configuration 3. System SRAM1 and SRAM2 and DTCM
+ * CONFIG_MM_REGIONS == 3
+ * CONFIG_STM32F7_FSMC_SRAM undefined
+ * HAVE_DTCM defined
+ * Configuration 4. System SRAM1 and SRAM2 and FSMC SRAM
* CONFIG_MM_REGIONS == 3
* CONFIG_STM32F7_FSMC_SRAM defined
+ * HAVE_DTCM undefined
+ * Configuration 5. System SRAM1 and SRAM2 and DTCM and FSMC SRAM
+ * CONFIG_MM_REGIONS == 4
+ * CONFIG_STM32F7_FSMC_SRAM defined
+ * HAVE_DTCM defined
*
* Let's make sure that all definitions are consistent before doing
* anything else
@@ -128,24 +153,48 @@
#if CONFIG_MM_REGIONS < 2
# ifdef CONFIG_STM32F7_FSMC_SRAM
-# warning FSMC SRAM and SRAM2 excluded from the heap
-# else
-# warning "SRAM2 excluded from the heap"
+# warning "FSMC SRAM excluded from the heap"
+# undef CONFIG_STM32F7_FSMC_SRAM
+# endif
+# ifdef HAVE_DTCM
+# warning "DTCM excluded from the heap"
+# undef HAVE_DTCM
# endif
+# warning "SRAM2 excluded from the heap"
#elif CONFIG_MM_REGIONS < 3
# ifdef CONFIG_STM32F7_FSMC_SRAM
-# warning FSMC SRAM excluded from the heap
+# warning "FSMC SRAM excluded from the heap"
+# undef CONFIG_STM32F7_FSMC_SRAM
+# endif
+# ifdef HAVE_DTCM
+# warning "DTCM excluded from the heap"
+# undef HAVE_DTCM
# endif
#elif CONFIG_MM_REGIONS < 4
-# ifndef CONFIG_STM32F7_FSMC_SRAM
-# error CONFIG_MM_REGIONS > 2 but I do not know what some of the region(s) are
+# if defined(CONFIG_STM32F7_FSMC_SRAM) && defined(HAVE_DTCM)
+# warning "CONFIG_MM_REGIONS == 3 but have both FSMC SRAM and DTCM. DTCM excluded from the heap."
+# undef HAVE_DTCM
+# elif !defined(CONFIG_STM32F7_FSMC_SRAM) && !defined(HAVE_DTCM)
+# error "CONFIG_MM_REGIONS == 3 but I do not know what some of the region(s) are"
+# undef CONFIG_MM_REGIONS
+# define CONFIG_MM_REGIONS 2
+# endif
+#elif CONFIG_MM_REGIONS < 5
+# if !defined(CONFIG_STM32F7_FSMC_SRAM) && !defined(HAVE_DTCM)
+# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 2
+# elif !defined(CONFIG_STM32F7_FSMC_SRAM) || !defined(HAVE_DTCM)
+# error "CONFIG_MM_REGIONS == 4 but I do not know what some of the region(s) are"
+# undef CONFIG_MM_REGIONS
+# define CONFIG_MM_REGIONS 3
# endif
#else
-# error CONFIG_MM_REGIONS > 3 but I do not know what some of the region(s) are
+# error "CONFIG_MM_REGIONS > 4 but I do not know what some of the region(s) are"
# undef CONFIG_MM_REGIONS
-# ifdef CONFIG_STM32F7_FSMC_SRAM
+# if defined(CONFIG_STM32F7_FSMC_SRAM) && defined(HAVE_DTCM)
+# define CONFIG_MM_REGIONS 4
+# elif defined(CONFIG_STM32F7_FSMC_SRAM) || defined(HAVE_DTCM)
# define CONFIG_MM_REGIONS 3
# else
# define CONFIG_MM_REGIONS 2
@@ -338,6 +387,24 @@ void up_addregion(void)
kumm_addregion((FAR void *)SRAM2_START, SRAM2_END-SRAM2_START);
+#ifdef HAVE_DTCM
+#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
+
+ /* Allow user-mode access to the DTCM heap */
+
+ stm32_mpu_uheap((uintptr_t)DTCM_START, DTCM_END-DTCM_START);
+
+#endif
+
+ /* Colorize the heap for debug */
+
+ up_heap_color((FAR void *)DTCM_START, DTCM_END-DTCM_START);
+
+ /* Add the DTCM user heap region. */
+
+ kumm_addregion((FAR void *)DTCM_START, DTCM_END-DTCM_START);
+#endif
+
#ifdef CONFIG_STM32F7_FSMC_SRAM
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)

17
nuttx-patches/00017-BACKPORT-cdcacm.patch
View File

@ -1,17 +0,0 @@
diff --git NuttX/nuttx/drivers/usbdev/cdcacm.c NuttX/nuttx/drivers/usbdev/cdcacm.c
index 64e2e68..15f92dd 100644
--- NuttX/nuttx/drivers/usbdev/cdcacm.c
+++ NuttX/nuttx/drivers/usbdev/cdcacm.c
@@ -243,6 +243,12 @@ static const struct uart_ops_s g_uartops =
#ifdef CONFIG_SERIAL_IFLOWCONTROL
cdcuart_rxflowcontrol, /* rxflowcontrol */
#endif
+#ifdef CONFIG_SERIAL_DMA
+ NULL, /* dmasend */
+ NULL, /* dmareceive */
+ NULL, /* dmarxfree */
+ NULL, /* dmatxavail */
+#endif
NULL, /* send */
cdcuart_txint, /* txinit */
NULL, /* txready */

29
nuttx-patches/00019-BACKPORT-stm32-rcc-keep-HSI-on.patch
View File

@ -1,29 +0,0 @@
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 5e2ba73..adda863 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -95,10 +95,10 @@ static inline void rcc_reset(void)
putreg32(0x00000000, STM32_RCC_CFGR);
- /* Reset HSION, HSEON, CSSON and PLLON bits */
+ /* Reset HSEON, CSSON and PLLON bits */
regval = getreg32(STM32_RCC_CR);
- regval &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
+ regval &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON);
putreg32(regval, STM32_RCC_CR);
/* Reset PLLCFGR register to reset default */
@@ -619,11 +619,6 @@ static void stm32_stdclockconfig(void)
volatile int32_t timeout;
#ifdef STM32_BOARD_USEHSI
- /* Enable Internal High-Speed Clock (HSI) */
-
- regval = getreg32(STM32_RCC_CR);
- regval |= RCC_CR_HSION; /* Enable HSI */
- putreg32(regval, STM32_RCC_CR);
/* Wait until the HSI is ready (or until a timeout elapsed) */

24
nuttx-patches/00021-BACKPORT-stm32f3x-add-BKP.patch
View File

@ -1,24 +0,0 @@
diff --git NuttX/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h NuttX/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
index 51cca40..a7cbc46 100644
--- NuttX/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
+++ NuttX/nuttx/arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
@@ -93,6 +93,7 @@
#define STM32_TIM6_BASE 0x40001000 /* 0x40001000-0x400013ff TIM6 */
#define STM32_TIM7_BASE 0x40001400 /* 0x40001400-0x400017ff TIM7 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
+#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x4000288c BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_I2S2EXT_BASE 0x40003400 /* 0x40003400-0x400037ff I2S2ext */
diff --git NuttX/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h NuttX/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
index 4c703be..49bfa2e 100644
--- NuttX/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
+++ NuttX/nuttx/arch/arm/src/stm32/chip/stm32f37xxx_memorymap.h
@@ -94,6 +94,7 @@
#define STM32_TIM13_BASE 0x40001c00 /* 0x40001c00-0x40001fff TIM13 */
#define STM32_TIM14_BASE 0x40002000 /* 0x40002000-0x400023ff TIM14 */
#define STM32_RTC_BASE 0x40002800 /* 0x40002800-0x40002bff RTC */
+#define STM32_BKP_BASE 0x40002850 /* 0x40002850-0x400028cc BKP */
#define STM32_WWDG_BASE 0x40002c00 /* 0x40002c00-0x40002fff WWDG */
#define STM32_IWDG_BASE 0x40003000 /* 0x40003000-0x400033ff IWDG */
#define STM32_SPI2_BASE 0x40003800 /* 0x40003800-0x40003bff SPI2, or */

181
nuttx-patches/00022-BACKPORT-stm32-bkp-reference-fix.patch
View File

@ -1,181 +0,0 @@
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.c NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.c
index 13fbdb3..b2aee60 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.c
@@ -2,9 +2,10 @@
* arch/arm/src/stm32/stm32_pwr.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
- * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2015-2017 Gregory Nutt. All rights reserved.
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <gnutt@nuttx.org>
+ * David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -54,6 +55,12 @@
#if defined(CONFIG_STM32_PWR)
/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+static uint16_t g_bkp_writable_counter = 0;
+
+/************************************************************************************
* Private Functions
************************************************************************************/
@@ -115,6 +122,39 @@ void stm32_pwr_enablesdadc(uint8_t sdadc)
}
#endif
+/************************************************************************************
+ * Name: stm32_pwr_initbkp
+ *
+ * Description:
+ * Insures the referenced count access to the backup domain (RTC registers,
+ * RTC backup data registers and backup SRAM is consistent with the HW state
+ * without relying on a variable.
+ *
+ * NOTE: This function should only be called by SoC Start up code.
+ *
+ * Input Parameters:
+ * writable - True: enable ability to write to backup domain registers
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+void stm32_pwr_initbkp(bool writable)
+{
+ uint16_t regval;
+
+ /* Make the HW not writable */
+
+ regval = stm32_pwr_getreg(STM32_PWR_CR_OFFSET);
+ regval &= ~PWR_CR_DBP;
+ stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
+
+ /* Make the reference count agree */
+
+ g_bkp_writable_counter = 0;
+ stm32_pwr_enablebkp(writable);
+}
/************************************************************************************
* Name: stm32_pwr_enablebkp
@@ -137,7 +177,6 @@ void stm32_pwr_enablesdadc(uint8_t sdadc)
void stm32_pwr_enablebkp(bool writable)
{
- static uint16_t writable_counter = 0;
irqstate_t flags;
uint16_t regval;
bool waswritable;
@@ -152,24 +191,24 @@ void stm32_pwr_enablebkp(bool writable)
if (writable)
{
- DEBUGASSERT(writable_counter < UINT16_MAX);
- writable_counter++;
+ DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX);
+ g_bkp_writable_counter++;
}
- else if (writable_counter > 0)
+ else if (g_bkp_writable_counter > 0)
{
- writable_counter--;
+ g_bkp_writable_counter--;
}
/* Enable or disable the ability to write */
- if (waswritable && writable_counter == 0)
+ if (waswritable && g_bkp_writable_counter == 0)
{
/* Disable backup domain access */
regval &= ~PWR_CR_DBP;
stm32_pwr_putreg(STM32_PWR_CR_OFFSET, regval);
}
- else if (!waswritable && writable_counter > 0)
+ else if (!waswritable && g_bkp_writable_counter > 0)
{
/* Enable backup domain access */
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.h NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.h
index 700dd60..ab33eb9 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.h
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_pwr.h
@@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/src/stm32/stm32_pwr.h
*
- * Copyright (C) 2009, 2013, 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
+ * Copyright (C) 2009, 2013, 2015, 2017 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt <gnutt@nuttx.org>
+ * David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -85,6 +86,27 @@ void stm32_pwr_enablesdadc(uint8_t sdadc);
#endif
/************************************************************************************
+ * Name: stm32_pwr_initbkp
+ *
+ * Description:
+ * Insures the referenced count access to the backup domain (RTC registers,
+ * RTC backup data registers and backup SRAM is consistent with the HW state
+ * without relying on a variable.
+ *
+ * NOTE: This function should only be called by SoC Start up code.
+ *
+ * Input Parameters:
+ * writable - set the initial state of the enable and the
+ * bkp_writable_counter
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+void stm32_pwr_initbkp(bool writable);
+
+/************************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
diff --git NuttX/nuttx/arch/arm/src/stm32/stm32_rcc.c NuttX/nuttx/arch/arm/src/stm32/stm32_rcc.c
index cf3c115..71fd4f7 100644
--- NuttX/nuttx/arch/arm/src/stm32/stm32_rcc.c
+++ NuttX/nuttx/arch/arm/src/stm32/stm32_rcc.c
@@ -1,8 +1,9 @@
/****************************************************************************
* arch/arm/src/stm32/stm32_rcc.c
*
- * Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gnutt@nuttx.org>
+ * Copyright (C) 2009, 2011-2012, 2017 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt <gnutt@nuttx.org>
+ * David Sidrane <david_s5@nscdg.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -125,9 +126,12 @@ static inline void rcc_resetbkp(void)
/* Check if the RTC is already configured */
+ stm32_pwr_initbkp(false);
+
regval = getreg32(RTC_MAGIC_REG);
if (regval != RTC_MAGIC)
{
+
stm32_pwr_enablebkp(true);
/* We might be changing RTCSEL - to ensure such changes work, we must

329
nuttx-patches/00023-BACKPORT-stm32f7-bkp-reference-fix.patch
View File

@ -1,329 +0,0 @@
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c
index bd653cf..71adbcf 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_bbsram.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_bbsram.c
*
- * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@@ -257,7 +257,7 @@ static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv)
static inline void stm32_bbsram_unlock(void)
{
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
}
/****************************************************************************
@@ -277,7 +277,7 @@ static inline void stm32_bbsram_unlock(void)
static inline void stm32_bbsram_lock(void)
{
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
}
/****************************************************************************
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c
index 961eaf4..c9d2d5d 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.c
@@ -2,7 +2,7 @@
* arch/arm/src/stm32f7/stm32_pwr.c
*
* Copyright (C) 2011 Uros Platise. All rights reserved.
- * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2015, 2017 Gregory Nutt. All rights reserved.
* Authors: Uros Platise <uros.platise@isotel.eu>
* Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
@@ -53,6 +53,12 @@
#if defined(CONFIG_STM32F7_PWR)
/************************************************************************************
+ * Private Data
+ ************************************************************************************/
+
+static uint16_t g_bkp_writable_counter = 0;
+
+/************************************************************************************
* Private Functions
************************************************************************************/
@@ -76,52 +82,108 @@ static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint1
************************************************************************************/
/************************************************************************************
+ * Name: stm32_pwr_initbkp
+ *
+ * Description:
+ * Insures the referenced count access to the backup domain (RTC registers,
+ * RTC backup data registers and backup SRAM is consistent with the HW state
+ * without relying on a variable.
+ *
+ * NOTE: This function should only be called by SoC Start up code.
+ *
+ * Input Parameters:
+ * writable - True: enable ability to write to backup domain registers
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+void stm32_pwr_initbkp(bool writable)
+{
+ uint16_t regval;
+
+ /* Make the HW not writable */
+
+ regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
+ regval &= ~PWR_CR1_DBP;
+ stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
+
+ /* Make the reference count agree */
+
+ g_bkp_writable_counter = 0;
+ stm32_pwr_enablebkp(writable);
+}
+
+/************************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
* Enables access to the backup domain (RTC registers, RTC backup data registers
* and backup SRAM).
*
+ * NOTE: Reference counting is used in order to supported nested calls to this
+ * function. As a consequence, every call to stm32_pwr_enablebkp(true) must
+ * be followed by a matching call to stm32_pwr_enablebkp(false).
+ *
* Input Parameters:
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
- * True: The backup domain was previously writable.
+ * None
*
************************************************************************************/
-bool stm32_pwr_enablebkp(bool writable)
+void stm32_pwr_enablebkp(bool writable)
{
+ irqstate_t flags;
uint16_t regval;
bool waswritable;
+ bool wait = false;
+
+ flags = enter_critical_section();
/* Get the current state of the STM32 PWR control register */
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
waswritable = ((regval & PWR_CR1_DBP) != 0);
+ if (writable)
+ {
+ DEBUGASSERT(g_bkp_writable_counter < UINT16_MAX);
+ g_bkp_writable_counter++;
+ }
+ else if (g_bkp_writable_counter > 0)
+ {
+ g_bkp_writable_counter--;
+ }
/* Enable or disable the ability to write */
- if (waswritable && !writable)
+ if (waswritable && g_bkp_writable_counter == 0)
{
/* Disable backup domain access */
regval &= ~PWR_CR1_DBP;
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
}
- else if (!waswritable && writable)
+ else if (!waswritable && g_bkp_writable_counter > 0)
{
/* Enable backup domain access */
regval |= PWR_CR1_DBP;
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
+ wait = true;
+ }
+
+ leave_critical_section(flags);
+
+ if (wait)
+ {
/* Enable does not happen right away */
up_udelay(4);
}
-
- return waswritable;
}
/************************************************************************************
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h
index 772851d..c80de12 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_pwr.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/stm32f7/stm32_pwr.h
*
- * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2016-2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@@ -68,6 +68,27 @@ extern "C"
************************************************************************************/
/************************************************************************************
+ * Name: stm32_pwr_initbkp
+ *
+ * Description:
+ * Insures the referenced count access to the backup domain (RTC registers,
+ * RTC backup data registers and backup SRAM is consistent with the HW state
+ * without relying on a variable.
+ *
+ * NOTE: This function should only be called by SoC Start up code.
+ *
+ * Input Parameters:
+ * writable - set the initial state of the enable and the
+ * bkp_writable_counter
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+void stm32_pwr_initbkp(bool writable);
+
+/************************************************************************************
* Name: stm32_pwr_enablebkp
*
* Description:
@@ -78,11 +99,11 @@ extern "C"
* writable - True: enable ability to write to backup domain registers
*
* Returned Value:
- * True: The backup domain was previously writeable.
+ * none
*
************************************************************************************/
-bool stm32_pwr_enablebkp(bool writable);
+void stm32_pwr_enablebkp(bool writable);
/************************************************************************************
* Name: stm32_pwr_enablebreg
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c
index 21cac17..a64ce09 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_rcc.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_rcc.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
* Authors: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@@ -52,6 +52,7 @@
#include "chip/stm32_flash.h"
#include "stm32_rcc.h"
+#include "stm32_pwr.h"
/****************************************************************************
* Pre-processor Definitions
@@ -113,6 +114,13 @@ void stm32_clockconfig(void)
rcc_reset();
+#if defined(CONFIG_STM32F7_PWR)
+
+ /* Insure the bkp is initialized */
+
+ stm32_pwr_initbkp(false);
+#endif
+
#if defined(CONFIG_STM32F7_CUSTOM_CLOCKCONFIG)
/* Invoke Board Custom Clock Configuration */
diff --git NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c
index bd42b83..5445c01 100644
--- NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c
+++ NuttX/nuttx/arch/arm/src/stm32f7/stm32_rtc.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/stm32f7/stm32_rtc.c
*
- * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2011, 2015-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>
* David Sidrane <david_s5@nscdg.com>
*
@@ -261,7 +261,7 @@ static void rtc_wprunlock(void)
* registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* The following steps are required to unlock the write protection on all the
* RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR).
@@ -300,7 +300,7 @@ static inline void rtc_wprlock(void)
* data registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
}
/****************************************************************************
@@ -850,7 +850,7 @@ int up_rtc_initialize(void)
regval = getreg32(RTC_MAGIC_REG);
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
if (regval != RTC_MAGIC)
{
@@ -943,7 +943,7 @@ int up_rtc_initialize(void)
}
}
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
/* Loop, attempting to initialize/resume the RTC. This loop is necessary
* because it seems that occasionally it takes longer to initialize the
@@ -994,7 +994,7 @@ int up_rtc_initialize(void)
* backup data registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(true);
+ stm32_pwr_enablebkp(true);
/* Remember that the RTC is initialized */
@@ -1014,7 +1014,7 @@ int up_rtc_initialize(void)
* data registers and backup SRAM).
*/
- (void)stm32_pwr_enablebkp(false);
+ stm32_pwr_enablebkp(false);
if (ret != OK && nretry > 0)
{