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DShot: updated driver to use NuttX DMA functions (#13233)

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This commit is contained in:
Igor Mišić
2019-10-25 09:49:03 +02:00
committed by Beat Küng
parent 7ebaf9a1cb
commit f4ee9141cb
11 changed files with 80 additions and 308 deletions
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boards/holybro/kakutef7/src/timer_config.c
+8 -12
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@@ -61,9 +61,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM3,
.dshot = {
.dma_base = DSHOT_DMA1_BASE,
.channel = DShot_Channel5,
.stream = DShot_Stream2,
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM3_UP,
.start_ccr_register = TIM_DMABASE_CCR3,
.channels_number = 2u /* CCR3 and CCR4 */
}
@@ -78,9 +77,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = DSHOT_DMA2_BASE,
.channel = DShot_Channel6,
.stream = DShot_Stream5,
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 2u /* CCR1 and CCR2 */
}
@@ -95,9 +93,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM8CC,
.dshot = {
.dma_base = DSHOT_DMA2_BASE,
.channel = DShot_Channel7,
.stream = DShot_Stream1,
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM8_UP,
.start_ccr_register = TIM_DMABASE_CCR4,
.channels_number = 1u /* CCR4 */
}
@@ -112,9 +109,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler3,
.vectorno = STM32_IRQ_TIM5,
.dshot = {
.dma_base = DSHOT_DMA1_BASE,
.channel = DShot_Channel6,
.stream = DShot_Stream6, // alternatively DShot_Stream0
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM5_UP_2,
.start_ccr_register = TIM_DMABASE_CCR4,
.channels_number = 1u /* CCR4 */
}
boards/modalai/fc-v1/src/timer_config.c
+2 -3
View File
@@ -76,9 +76,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = DSHOT_DMA2_BASE,
.channel = DShot_Channel6,
.stream = DShot_Stream5,
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
boards/omnibus/f4sd/src/timer_config.c
+4 -6
View File
@@ -61,9 +61,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM2,
.dshot = {
.dma_base = DSHOT_DMA1_BASE,
.channel = DShot_Channel3,
.stream = DShot_Stream1,
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM2_UP_1,
.start_ccr_register = TIM_DMABASE_CCR3,
.channels_number = 2u /* CCR3 and CCR4 */
}
@@ -78,9 +77,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler2,
.vectorno = STM32_IRQ_TIM3,
.dshot = {
.dma_base = DSHOT_DMA1_BASE,
.channel = DShot_Channel5,
.stream = DShot_Stream2,
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM3_UP,
.start_ccr_register = TIM_DMABASE_CCR3,
.channels_number = 2u /* CCR3 and CCR4 */
}
boards/px4/fmu-v2/src/timer_config.c
+4 -6
View File
@@ -61,9 +61,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = DSHOT_DMA2_BASE,
.channel = DShot_Channel6,
.stream = DShot_Stream5,
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
@@ -78,9 +77,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = DSHOT_DMA1_BASE,
.channel = DShot_Channel2,
.stream = DShot_Stream6,
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM4_UP,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 2u /* CCR2 and CCR3 */
}
boards/px4/fmu-v3/src/timer_config.c
+4 -6
View File
@@ -61,9 +61,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = DSHOT_DMA2_BASE,
.channel = DShot_Channel6,
.stream = DShot_Stream5,
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
@@ -78,9 +77,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = DSHOT_DMA1_BASE,
.channel = DShot_Channel2,
.stream = DShot_Stream6,
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM4_UP,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 2u /* CCR2 and CCR3 */
}
boards/px4/fmu-v4/src/timer_config.c
+6 -7
View File
@@ -61,9 +61,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = DSHOT_DMA2_BASE,
.channel = DShot_Channel6,
.stream = DShot_Stream5,
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}
@@ -79,12 +78,12 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler1,
.vectorno = STM32_IRQ_TIM4,
.dshot = {
.dma_base = DSHOT_DMA1_BASE,
.channel = DShot_Channel2,
.stream = DShot_Stream6,
.dma_base = STM32_DMA1_BASE,
.dmamap = DMAMAP_TIM4_UP,
.start_ccr_register = TIM_DMABASE_CCR2,
.channels_number = 2u /* CCR2 and CCR3 */
.channels_number = 2u // CCR2 and CCR3
}
}
};
boards/px4/fmu-v5/src/timer_config.c
+2 -3
View File
@@ -61,9 +61,8 @@ __EXPORT const io_timers_t io_timers[MAX_IO_TIMERS] = {
.handler = io_timer_handler0,
.vectorno = STM32_IRQ_TIM1CC,
.dshot = {
.dma_base = DSHOT_DMA2_BASE,
.channel = DShot_Channel6,
.stream = DShot_Stream5,
.dma_base = STM32_DMA2_BASE,
.dmamap = DMAMAP_TIM1_UP,
.start_ccr_register = TIM_DMABASE_CCR1,
.channels_number = 4u /* CCR1, CCR2, CCR3 and CCR4 */
}