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synced 2026-04-30 15:54:06 +08:00
Don't do retries, since it just complicates things.
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7c7112a157
commit
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@ -94,46 +94,41 @@ transfer(uint8_t address, uint8_t *send, unsigned send_len, uint8_t *recv, unsig
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struct i2c_msg_s msgv[2];
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unsigned msgs;
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int ret;
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unsigned tries = 0;
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do {
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// debug("transfer out %p/%u in %p/%u", send, send_len, recv, recv_len);
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// debug("transfer out %p/%u in %p/%u", send, send_len, recv, recv_len);
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msgs = 0;
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msgs = 0;
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if (send_len > 0) {
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msgv[msgs].addr = address;
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msgv[msgs].flags = 0;
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msgv[msgs].buffer = send;
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msgv[msgs].length = send_len;
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msgs++;
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}
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if (send_len > 0) {
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msgv[msgs].addr = address;
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msgv[msgs].flags = 0;
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msgv[msgs].buffer = send;
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msgv[msgs].length = send_len;
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msgs++;
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}
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if (recv_len > 0) {
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msgv[msgs].addr = address;
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msgv[msgs].flags = I2C_M_READ;
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msgv[msgs].buffer = recv;
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msgv[msgs].length = recv_len;
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msgs++;
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}
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if (recv_len > 0) {
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msgv[msgs].addr = address;
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msgv[msgs].flags = I2C_M_READ;
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msgv[msgs].buffer = recv;
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msgv[msgs].length = recv_len;
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msgs++;
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}
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if (msgs == 0)
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return -1;
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if (msgs == 0)
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return -1;
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/*
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* I2C architecture means there is an unavoidable race here
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* if there are any devices on the bus with a different frequency
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* preference. Really, this is pointless.
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*/
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I2C_SETFREQUENCY(i2c, 320000);
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ret = I2C_TRANSFER(i2c, &msgv[0], msgs);
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/*
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* I2C architecture means there is an unavoidable race here
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* if there are any devices on the bus with a different frequency
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* preference. Really, this is pointless.
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*/
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I2C_SETFREQUENCY(i2c, 320000);
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ret = I2C_TRANSFER(i2c, &msgv[0], msgs);
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if (ret == OK)
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break;
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// reset the I2C bus to unwedge on error
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// reset the I2C bus to unwedge on error
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if (ret != OK)
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up_i2creset(i2c);
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} while (tries++ < 5);
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return ret;
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}
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