mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-10-17 18:03:33 +08:00
CAN node STM32F7 support and Freefly RTK GPS CAN node
This commit is contained in:
Daniel Agar
@@ -45,4 +45,4 @@ add_subdirectory(../stm32_common/tone_alarm tone_alarm)
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add_subdirectory(../stm32_common/version version)
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add_subdirectory(px4io_serial)
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add_subdirectory(watchdog)
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@@ -39,11 +39,15 @@ __BEGIN_DECLS
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#define PX4_SOC_ARCH_ID PX4_SOC_ARCH_ID_STM32F7
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#include <chip.h>
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#include <stm32_gpio.h>
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#include <stm32_can.h>
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#include <hardware/stm32_flash.h>
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#include <arm_internal.h> //include up_systemreset() which is included on stm32.h
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#include <stm32_bbsram.h>
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#define PX4_BBSRAM_SIZE STM32F7_BBSRAM_SIZE
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#define PX4_BBSRAM_GETDESC_IOCTL STM32F7_BBSRAM_GETDESC_IOCTL
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#if defined(CONFIG_STM32F7_BKPSRAM)
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# include <stm32_bbsram.h>
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# define PX4_BBSRAM_SIZE STM32F7_BBSRAM_SIZE
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# define PX4_BBSRAM_GETDESC_IOCTL STM32F7_BBSRAM_GETDESC_IOCTL
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#endif // CONFIG_STM32F7_BKPSRAM
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#define PX4_FLASH_BASE 0x08000000
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#define PX4_NUMBER_I2C_BUSES STM32F7_NI2C
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#define PX4_ADC_INTERNAL_TEMP_SENSOR_CHANNEL 18
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@@ -0,0 +1,36 @@
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############################################################################
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#
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# Copyright (c) 2021 PX4 Development Team. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions
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# are met:
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#
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# 1. Redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer.
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# 2. Redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in
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# the documentation and/or other materials provided with the
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# distribution.
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# 3. Neither the name PX4 nor the names of its contributors may be
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# used to endorse or promote products derived from this software
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# without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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############################################################################
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px4_add_library(arch_watchdog_iwdg
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iwdg.c
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)
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@@ -0,0 +1,104 @@
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/****************************************************************************
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*
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* Copyright (c) 2021 PX4 Development Team. All rights reserved.
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* Author: David Sidrane <david.sidrane@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#include <nuttx/config.h>
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#include "arm_internal.h"
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#include "arm_arch.h"
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#include "chip.h"
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#include "nvic.h"
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#include "stm32_wdg.h"
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/****************************************************************************
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* Name: watchdog_pet()
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*
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* Description:
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* This function resets the Independent watchdog (IWDG)
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*
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*
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* Input Parameters:
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* none.
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*
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* Returned value:
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* none.
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*
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****************************************************************************/
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void watchdog_pet(void)
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{
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putreg32(IWDG_KR_KEY_RELOAD, STM32_IWDG_KR);
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}
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/****************************************************************************
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* Name: watchdog_init()
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*
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* Description:
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* This function initialize the Independent watchdog (IWDG)
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*
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*
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* Input Parameters:
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* none.
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*
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* Returned value:
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* none.
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*
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****************************************************************************/
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void watchdog_init(void)
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{
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#if defined(CONFIG_STM32F7_JTAG_FULL_ENABLE) || \
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defined(CONFIG_STM32F7_JTAG_NOJNTRST_ENABLE) || \
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defined(CONFIG_STM32F7_JTAG_SW_ENABLE)
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putreg32(getreg32(STM32_DBGMCU_APB1_FZ) | DBGMCU_APB1_IWDGSTOP, STM32_DBGMCU_APB1_FZ);
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#endif
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/* unlock */
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putreg32(IWDG_KR_KEY_ENABLE, STM32_IWDG_KR);
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/* Set the prescale value */
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putreg32(IWDG_PR_DIV16, STM32_IWDG_PR);
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/* Set the reload value */
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putreg32(IWDG_RLR_MAX, STM32_IWDG_RLR);
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/* Start the watch dog */
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putreg32(IWDG_KR_KEY_START, STM32_IWDG_KR);
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watchdog_pet();
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}
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@@ -0,0 +1,162 @@
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/************************************************************************************
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* arch/arm/src/stm32/hardware/stm32_wdg.h
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*
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* Copyright (C) 2009, 2011-2013 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H
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#define __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_IWDG_KR_OFFSET 0x0000 /* Key register (32-bit) */
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#define STM32_IWDG_PR_OFFSET 0x0004 /* Prescaler register (32-bit) */
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#define STM32_IWDG_RLR_OFFSET 0x0008 /* Reload register (32-bit) */
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#define STM32_IWDG_SR_OFFSET 0x000c /* Status register (32-bit) */
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#if defined(CONFIG_STM32_STM32F30XX)
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# define STM32_IWDG_WINR_OFFSET 0x000c /* Window register (32-bit) */
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#endif
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#define STM32_WWDG_CR_OFFSET 0x0000 /* Control Register (32-bit) */
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#define STM32_WWDG_CFR_OFFSET 0x0004 /* Configuration register (32-bit) */
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#define STM32_WWDG_SR_OFFSET 0x0008 /* Status register (32-bit) */
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/* Register Addresses ***************************************************************/
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#define STM32_IWDG_KR (STM32_IWDG_BASE+STM32_IWDG_KR_OFFSET)
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#define STM32_IWDG_PR (STM32_IWDG_BASE+STM32_IWDG_PR_OFFSET)
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#define STM32_IWDG_RLR (STM32_IWDG_BASE+STM32_IWDG_RLR_OFFSET)
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#define STM32_IWDG_SR (STM32_IWDG_BASE+STM32_IWDG_SR_OFFSET)
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#if defined(CONFIG_STM32_STM32F30XX)
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# define STM32_IWDG_WINR (STM32_IWDG_BASE+STM32_IWDG_WINR_OFFSET)
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#endif
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#define STM32_WWDG_CR (STM32_WWDG_BASE+STM32_WWDG_CR_OFFSET)
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#define STM32_WWDG_CFR (STM32_WWDG_BASE+STM32_WWDG_CFR_OFFSET)
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#define STM32_WWDG_SR (STM32_WWDG_BASE+STM32_WWDG_SR_OFFSET)
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/* Register Bitfield Definitions ****************************************************/
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/* Key register (32-bit) */
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#define IWDG_KR_KEY_SHIFT (0) /* Bits 15-0: Key value (write only, read 0000h) */
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#define IWDG_KR_KEY_MASK (0xffff << IWDG_KR_KEY_SHIFT)
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#define IWDG_KR_KEY_ENABLE (0x5555) /* Enable register access */
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#define IWDG_KR_KEY_DISABLE (0x0000) /* Disable register access */
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#define IWDG_KR_KEY_RELOAD (0xaaaa) /* Reload the counter */
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#define IWDG_KR_KEY_START (0xcccc) /* Start the watchdog */
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/* Prescaler register (32-bit) */
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#define IWDG_PR_SHIFT (0) /* Bits 2-0: Prescaler divider */
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#define IWDG_PR_MASK (7 << IWDG_PR_SHIFT)
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# define IWDG_PR_DIV4 (0 << IWDG_PR_SHIFT) /* 000: divider /4 */
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# define IWDG_PR_DIV8 (1 << IWDG_PR_SHIFT) /* 001: divider /8 */
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# define IWDG_PR_DIV16 (2 << IWDG_PR_SHIFT) /* 010: divider /16 */
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# define IWDG_PR_DIV32 (3 << IWDG_PR_SHIFT) /* 011: divider /32 */
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# define IWDG_PR_DIV64 (4 << IWDG_PR_SHIFT) /* 100: divider /64 */
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# define IWDG_PR_DIV128 (5 << IWDG_PR_SHIFT) /* 101: divider /128 */
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# define IWDG_PR_DIV256 (6 << IWDG_PR_SHIFT) /* 11x: divider /256 */
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/* Reload register (32-bit) */
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#define IWDG_RLR_RL_SHIFT (0) /* Bits11:0 RL[11:0]: Watchdog counter reload value */
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#define IWDG_RLR_RL_MASK (0x0fff << IWDG_RLR_RL_SHIFT)
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#define IWDG_RLR_MAX (0xfff)
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/* Status register (32-bit) */
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#define IWDG_SR_PVU (1 << 0) /* Bit 0: Watchdog prescaler value update */
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#define IWDG_SR_RVU (1 << 1) /* Bit 1: Watchdog counter reload value update */
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#if defined(CONFIG_STM32_STM32F30XX)
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# define IWDG_SR_WVU (1 << 2) /* Bit 2: */
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#endif
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/* Window register (32-bit) */
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#if defined(CONFIG_STM32_STM32F30XX)
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# define IWDG_WINR_SHIFT (0)
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# define IWDG_WINR_MASK (0x0fff << IWDG_WINR_SHIFT)
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#endif
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/* Control Register (32-bit) */
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#define WWDG_CR_T_SHIFT (0) /* Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) */
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#define WWDG_CR_T_MASK (0x7f << WWDG_CR_T_SHIFT)
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# define WWDG_CR_T_MAX (0x3f << WWDG_CR_T_SHIFT)
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# define WWDG_CR_T_RESET (0x40 << WWDG_CR_T_SHIFT)
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#define WWDG_CR_WDGA (1 << 7) /* Bit 7: Activation bit */
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/* Configuration register (32-bit) */
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#define WWDG_CFR_W_SHIFT (0) /* Bits 6:0 W[6:0] 7-bit window value */
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#define WWDG_CFR_W_MASK (0x7f << WWDG_CFR_W_SHIFT)
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#define WWDG_CFR_WDGTB_SHIFT (7) /* Bits 8:7 [1:0]: Timer Base */
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#define WWDG_CFR_WDGTB_MASK (3 << WWDG_CFR_WDGTB_SHIFT)
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# define WWDG_CFR_PCLK1 (0 << WWDG_CFR_WDGTB_SHIFT) /* 00: CK Counter Clock (PCLK1 div 4096) div 1 */
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# define WWDG_CFR_PCLK1d2 (1 << WWDG_CFR_WDGTB_SHIFT) /* 01: CK Counter Clock (PCLK1 div 4096) div 2 */
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# define WWDG_CFR_PCLK1d4 (2 << WWDG_CFR_WDGTB_SHIFT) /* 10: CK Counter Clock (PCLK1 div 4096) div 4 */
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# define WWDG_CFR_PCLK1d8 (3 << WWDG_CFR_WDGTB_SHIFT) /* 11: CK Counter Clock (PCLK1 div 4096) div 8 */
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#define WWDG_CFR_EWI (1 << 9) /* Bit 9: Early Wakeup Interrupt */
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/* Status register (32-bit) */
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#define WWDG_SR_EWIF (1 << 0) /* Bit 0: Early Wakeup Interrupt Flag */
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_SRC_STM32_HARDWARE_STM32_WDG_H */
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