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Intial Commit PX4 FMUV6RT

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nxp/rt117x:Fix Pin IRQ

nxp/rt117x:Support 4 i2c busses

nxp/rt117x:Add px4io_serial support

nxp/imxrt:Expand ToneAlarmInterface to GPT 3 & 4

px4_fmu-6xrt:Using imxrt_flexspi_nor_octal

px4_fmu-6xrt:Entry is start

px4_fmu-6xrt:Add Proper MTD

px4_fmu-6xrt:Set I2C Buses

px4_fmu-6xrt:Proper SPI usage

px4_fmu-6xrt:Adjust memory Map to use the 2 MB

px4_fmu-6xrt:Bring in ROMAPI

px4_fmu-6xrt:Push FLASH to 200Mhz

px4_fmu-6xrt:Use BOARD_I2C_LATEINIT

px4_fmu-6xrt:Clock Config remove unused devices

px4_fmu-6xrt:Remove EVK SDRAM IO

px4_fmu-6xrt:Enable SE550 using HW_VER_REV_DRIVE

px4_fmu-6xrt:Use MTD to mount FRAM on Flex SPI

px4_fmu-6xrt:Manifest

px4_fmu-6xrt:Restore board_peripheral_reset

px4_fmu-6xrt:Set I2C buss Interna/Externa and startup

nxp/rt117x:Set 6 I2C busses

px4_fmu-6xrt:Correct Clock Sources and Freqency Settings

px4_fmu-6xrt:Correct ADC Settings

px4_fmu-6xrt:Tune FlexSPI config and sync header with debug variant Linker prep for rodata ahb partitioning

px4_fmu-6xrt:FlexSPI prefetch partition split .text and .rodata

   Current config
     1KB Prefetch .rodata
     3KB Prefetch .text

px4_fmu-6xrt:Run imxrt_flash_setup_prefetch_partition from ram with barriers

px4_fmu-6xrt:Use All OCTL setting from FLASH g_flash_config SANS lookupTable

px4_fmu-6xrt:Octal spi boot/debug problem bypass

px4_fmu-6xrt:Add PWM test

px4_fmu-6xrt:Fix clockconfig and USB vbus sense

px4_fmu-6xrt: Use TCM

px4_fmu-6xrt: Ethernet bringup

imxrt: use unique_id register for board_identity

px4_fmu-6xrt: update ITCM mapping, todo proper trap on pc hitting 0x0

px4_fmu-6xrt:correct rotation icm42688p onboard imu

rt117x: Add SSARC HP RAM driver for memory dumps

px4_fmu-6xrt: Enable hardfault_log

px4_fmu-6xrt: Enable DMA pool

px4_fmu-6xrt: fix uart mapping

px4_fmu-6xrt: enable SocketCAN & DroneCAN

px4_fmu-6xrt:Command line history TAB completion

px4_fmu-6xrt:Fix pinning duplication

px4_fmu-6xrt:Support conditional PHY address based on selected PHY

px4_fmu-6xrt:Add Pull Downs on CTS, use GPIO for RTS

px4_fmu-6xrt:Set TelemN TX Slew rate and Drive Strenth to max

px4_fmu-6xrt::Set TELEM Buffers add HW HS

px4_fmu-6xrt:Turn off DMA poll

px4_fmu-6xrt:RC_SERIAL_PORT needed to be px4io to disable rc_input using TELEM2!

px4_fmu-6xrt: bootloader (#22228)

* imxrt:Add bootloader support
* bootloader:imxrt clear BOOT_RTC_SIGNATURE
* px4_fmu-6xrt:Add bootloader
* px4_fmu-6xrt:bootloader removed ADC
* px4_fmu-6xrt:bootloader base bootloader script off of script.ld
* px4_fmu-6xrt:add _bootdelay_signature & change entry from 0x30000000 to 0x30040000
* px4_fmu-6xrt:hw_config Bootloader has to have 12 bytes

px4_fmu-6xrt:Default to use LAN8742A PHY

px4_fmu-v6xrt:VID Set to Drone Code

board_reset:Enable ability to write RTC GP regs

px4_fmu-6xrt:Fix CMP0079 error

rt117x:micro_hal Add a PX4_MAKE_GPIO_PULLED_INPUT

px4_fmu-v6xrt:Set CTS High before VDD_5V applided to ports to avoid radios fro entering bootloaders

fmu-v6xrt: increase 5v down time

fmu-v6xrt:Ready for Release DEBUGASSERTS off and Console 57600,
Bootloder updated.

imxrt:board_hw_rev_ver Rework for 3.893V Ref

px4_fmu-v6xrt:Move ADC to Port3
This commit is contained in:
David Sidrane
2023-11-15 11:10:47 -05:00
committed by Daniel Agar
parent e3f8d53718
commit e90e8ae0ea
69 changed files with 11080 additions and 308 deletions
Download Patch File Download Diff File Expand all files Collapse all files
platforms/nuttx/src/px4/nxp/imxrt/version/board_identity.c
+2 -19
View File
@@ -81,25 +81,8 @@ void board_get_uuid(uuid_byte_t uuid_bytes)
void board_get_uuid32(uuid_uint32_t uuid_words)
{
/* IMXRT_OCOTP_CFG1:0x420[10:0], IMXRT_OCOTP_CFG0:0x410[31:0] LOT_NO_ENC[42:0](SJC_CHALL/UNIQUE_ID[42:0])
* 43 bits FSL-wide unique,encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
* 0x420[15:11] WAFER_NO[4:0]( SJC_CHALL[47:43] /UNIQUE_ID[47:43])
* 5 bits The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID
* 0x420[23:16] DIE-YCORDINATE[7:0]( SJC_CHALL[55:48] /UNIQUE_ID[55:48])
* 8 bits The Y-coordinate of the die location on the wafer/SJC CHALLENGE/Unique ID
* 0x420[31:24] DIE-XCORDINATE[7:0]( SJC_CHALL[63:56] /UNIQUE_ID[63:56] )
* 8 bits The X-coordinate of the die location on the wafer/SJC CHALLENGE/Unique ID
*
* word [0] word[1]
* SJC_CHALL[63:32] [31:00]
*/
#ifdef CONFIG_ARCH_FAMILY_IMXRT117x
uuid_words[0] = getreg32(IMXRT_OCOTP_FUSE(0x10));
uuid_words[1] = getreg32(IMXRT_OCOTP_FUSE(0x11));
#else
uuid_words[0] = getreg32(IMXRT_OCOTP_CFG1);
uuid_words[1] = getreg32(IMXRT_OCOTP_CFG0);
#endif
uuid_words[0] = getreg32(IMXRT_OCOTP_UNIQUE_ID_MSB);
uuid_words[1] = getreg32(IMXRT_OCOTP_UNIQUE_ID_LSB);
}
int board_get_uuid32_formated(char *format_buffer, int size,