mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-10-28 00:53:33 +08:00
Intial Commit PX4 FMUV6RT
nxp/rt117x:Fix Pin IRQ
nxp/rt117x:Support 4 i2c busses
nxp/rt117x:Add px4io_serial support
nxp/imxrt:Expand ToneAlarmInterface to GPT 3 & 4
px4_fmu-6xrt:Using imxrt_flexspi_nor_octal
px4_fmu-6xrt:Entry is start
px4_fmu-6xrt:Add Proper MTD
px4_fmu-6xrt:Set I2C Buses
px4_fmu-6xrt:Proper SPI usage
px4_fmu-6xrt:Adjust memory Map to use the 2 MB
px4_fmu-6xrt:Bring in ROMAPI
px4_fmu-6xrt:Push FLASH to 200Mhz
px4_fmu-6xrt:Use BOARD_I2C_LATEINIT
px4_fmu-6xrt:Clock Config remove unused devices
px4_fmu-6xrt:Remove EVK SDRAM IO
px4_fmu-6xrt:Enable SE550 using HW_VER_REV_DRIVE
px4_fmu-6xrt:Use MTD to mount FRAM on Flex SPI
px4_fmu-6xrt:Manifest
px4_fmu-6xrt:Restore board_peripheral_reset
px4_fmu-6xrt:Set I2C buss Interna/Externa and startup
nxp/rt117x:Set 6 I2C busses
px4_fmu-6xrt:Correct Clock Sources and Freqency Settings
px4_fmu-6xrt:Correct ADC Settings
px4_fmu-6xrt:Tune FlexSPI config and sync header with debug variant Linker prep for rodata ahb partitioning
px4_fmu-6xrt:FlexSPI prefetch partition split .text and .rodata
Current config
1KB Prefetch .rodata
3KB Prefetch .text
px4_fmu-6xrt:Run imxrt_flash_setup_prefetch_partition from ram with barriers
px4_fmu-6xrt:Use All OCTL setting from FLASH g_flash_config SANS lookupTable
px4_fmu-6xrt:Octal spi boot/debug problem bypass
px4_fmu-6xrt:Add PWM test
px4_fmu-6xrt:Fix clockconfig and USB vbus sense
px4_fmu-6xrt: Use TCM
px4_fmu-6xrt: Ethernet bringup
imxrt: use unique_id register for board_identity
px4_fmu-6xrt: update ITCM mapping, todo proper trap on pc hitting 0x0
px4_fmu-6xrt:correct rotation icm42688p onboard imu
rt117x: Add SSARC HP RAM driver for memory dumps
px4_fmu-6xrt: Enable hardfault_log
px4_fmu-6xrt: Enable DMA pool
px4_fmu-6xrt: fix uart mapping
px4_fmu-6xrt: enable SocketCAN & DroneCAN
px4_fmu-6xrt:Command line history TAB completion
px4_fmu-6xrt:Fix pinning duplication
px4_fmu-6xrt:Support conditional PHY address based on selected PHY
px4_fmu-6xrt:Add Pull Downs on CTS, use GPIO for RTS
px4_fmu-6xrt:Set TelemN TX Slew rate and Drive Strenth to max
px4_fmu-6xrt::Set TELEM Buffers add HW HS
px4_fmu-6xrt:Turn off DMA poll
px4_fmu-6xrt:RC_SERIAL_PORT needed to be px4io to disable rc_input using TELEM2!
px4_fmu-6xrt: bootloader (#22228)
* imxrt:Add bootloader support
* bootloader:imxrt clear BOOT_RTC_SIGNATURE
* px4_fmu-6xrt:Add bootloader
* px4_fmu-6xrt:bootloader removed ADC
* px4_fmu-6xrt:bootloader base bootloader script off of script.ld
* px4_fmu-6xrt:add _bootdelay_signature & change entry from 0x30000000 to 0x30040000
* px4_fmu-6xrt:hw_config Bootloader has to have 12 bytes
px4_fmu-6xrt:Default to use LAN8742A PHY
px4_fmu-v6xrt:VID Set to Drone Code
board_reset:Enable ability to write RTC GP regs
px4_fmu-6xrt:Fix CMP0079 error
rt117x:micro_hal Add a PX4_MAKE_GPIO_PULLED_INPUT
px4_fmu-v6xrt:Set CTS High before VDD_5V applided to ports to avoid radios fro entering bootloaders
fmu-v6xrt: increase 5v down time
fmu-v6xrt:Ready for Release DEBUGASSERTS off and Console 57600,
Bootloder updated.
imxrt:board_hw_rev_ver Rework for 3.893V Ref
px4_fmu-v6xrt:Move ADC to Port3
This commit is contained in:
David Sidrane
committed by
Daniel Agar
Daniel Agar
parent
e3f8d53718
commit
e90e8ae0ea
@@ -73,23 +73,26 @@ static char hw_info[HW_INFO_SIZE] = {0};
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static int dn_to_ordinal(uint16_t dn)
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{
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// Refernece is 3.8933 = (1.825f * 64.0f / 30.0f)
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// LSB is 0.000950521 = 3.8933 / 4096
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// DN's are V/LSB
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const struct {
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uint16_t low; // High(n-1) + 1
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uint16_t high; // Average High(n)+Low(n+1) EX. 1356 = AVRG(1331,1382)
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} dn2o[] = {
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// R1(up) R2(down) V min V Max DN Min DN Max
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{0, 0 }, // 0 No Resistors
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{1, 579 }, // 1 24.9K 442K 0.166255191 0.44102252 204 553
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{580, 967 }, // 2 32.4K 174K 0.492349322 0.770203609 605 966
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{968, 1356}, // 3 38.3K 115K 0.787901749 1.061597759 968 1331
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{1357, 1756}, // 4 46.4K 84.5K 1.124833577 1.386007306 1382 1738
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{1757, 2137}, // 5 51.1K 61.9K 1.443393279 1.685367869 1774 2113
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{2138, 2519}, // 6 61.9K 51.1K 1.758510242 1.974702534 2161 2476
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{2520, 2919}, // 7 84.5K 46.4K 2.084546498 2.267198261 2562 2842
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{2920, 3308}, // 8 115K 38.3K 2.437863827 2.57656294 2996 3230
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{3309, 3699}, // 9 174K 32.4K 2.755223792 2.847933804 3386 3571
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{3700, 4095}, // 10 442K 24.9K 3.113737849 3.147347506 3827 3946
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// R2(down) R1(up) V min V Max DN Min DN Max
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{0, 0 }, // 0 No Resistors
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{1, 490 }, // 1 24.9K 442K 0.166255191 0.44102252 174 463
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{491, 819 }, // 2 32.4K 174K 0.492349322 0.770203609 517 810
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{820, 1149}, // 3 38.3K 115K 0.787901749 1.061597759 828 1116
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{1150, 1488}, // 4 46.4K 84.5K 1.124833577 1.386007306 1183 1458
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{1489, 1811}, // 5 51.1K 61.9K 1.443393279 1.685367869 1518 1773
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{1812, 2135}, // 6 61.9K 51.1K 1.758510242 1.974702534 1850 2077
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{2136, 2474}, // 7 84.5K 46.4K 2.084546498 2.267198261 2193 2385
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{2475, 2804}, // 8 115K 38.3K 2.437863827 2.57656294 2564 2710
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{2805, 3135}, // 9 174K 32.4K 2.755223792 2.847933804 2898 2996
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{3136, 4095}, // 10 442K 24.9K 3.113737849 3.147347506 3275 3311
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};
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for (unsigned int i = 0; i < arraySize(dn2o); i++) {
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@@ -141,77 +144,87 @@ static int read_id_dn(int *id, uint32_t gpio_drive, uint32_t gpio_sense, int adc
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/*
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* Step one is there resistors?
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*
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* If we set the mid-point of the ladder which is the ADC input to an
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* output, then whatever state is driven out should be seen by the GPIO
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* that is on the bottom of the ladder that is switched to an input.
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* The SENCE line is effectively an output with a high value pullup
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* resistor on it driving an input through a series resistor with a pull up.
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* If present the series resistor will form a low pass filter due to stray
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* capacitance, but this is fine as long as we give it time to settle.
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* With the common REV/VER Drive we have to look at the ADC values.
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* to determine if the R's are hooked up. This is because the
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* the REV and VER pairs will influence each other and not make
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* digital thresholds.
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*
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* I.E
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*
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* VDD
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* 442K
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* REV is a Float
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* 24.9K
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* Drive as input
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* 442K
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* VER is 0.
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* 24.9K
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* VDD
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*
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* This is 466K up and 442K down.
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*
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* Driving VER Low and reading DRIVE will result in approximately mid point
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* values not a digital Low.
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*/
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/* Turn the drive lines to digital inputs with No pull up */
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imxrt_config_gpio(PX4_MAKE_GPIO_INPUT(gpio_drive) & ~IOMUX_PULL_MASK);
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/* Turn the sense lines to digital outputs LOW */
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imxrt_config_gpio(PX4_MAKE_GPIO_OUTPUT_CLEAR(gpio_sense));
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up_udelay(100); /* About 10 TC assuming 485 K */
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/* Read Drive lines while sense are driven low */
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int low = imxrt_gpio_read(PX4_MAKE_GPIO_INPUT(gpio_drive));
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/* Write the sense lines HIGH */
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imxrt_gpio_write(PX4_MAKE_GPIO_OUTPUT_CLEAR(gpio_sense), 1);
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up_udelay(100); /* About 10 TC assuming 485 K */
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/* Read Drive lines while sense are driven high */
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int high = imxrt_gpio_read(PX4_MAKE_GPIO_INPUT(gpio_drive));
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/* restore the pins to ANALOG */
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uint32_t dn_sum = 0;
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uint32_t dn = 0;
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uint32_t high = 0;
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uint32_t low = 0;
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imxrt_config_gpio(gpio_sense);
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/* Turn the drive lines to digital outputs High */
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imxrt_config_gpio(gpio_drive);
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up_udelay(100); /* About 10 TC assuming 485 K */
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for (unsigned av = 0; av < samples; av++) {
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if (px4_arch_adc_init(HW_REV_VER_ADC_BASE) == OK) {
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dn = px4_arch_adc_sample(HW_REV_VER_ADC_BASE, adc_channel);
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if (dn == UINT32_MAX) {
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break;
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}
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dn_sum += dn;
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}
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}
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if (dn != UINT32_MAX) {
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high = dn_sum / samples;
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}
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/* Turn the drive lines to digital outputs LOW */
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imxrt_config_gpio(gpio_drive ^ GPIO_OUTPUT_SET);
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up_udelay(100); /* About 10 TC assuming 485 K */
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/* Are Resistors in place ?*/
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dn_sum = 0;
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uint32_t dn_sum = 0;
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uint32_t dn = 0;
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for (unsigned av = 0; av < samples; av++) {
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if ((high ^ low) && low == 0) {
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/* Yes - Fire up the ADC (it has once control) */
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if (px4_arch_adc_init(HW_REV_VER_ADC_BASE) == OK) {
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dn = px4_arch_adc_sample(HW_REV_VER_ADC_BASE, adc_channel);
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/* Read the value */
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for (unsigned av = 0; av < samples; av++) {
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dn = px4_arch_adc_sample(HW_REV_VER_ADC_BASE, adc_channel);
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if (dn == UINT32_MAX) {
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break;
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}
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dn_sum += dn;
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}
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if (dn != UINT32_MAX) {
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*id = dn_sum / samples;
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rv = OK;
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}
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if (dn == UINT32_MAX) {
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break;
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}
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dn_sum += dn;
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}
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if (dn != UINT32_MAX) {
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low = dn_sum / samples;
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}
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if ((high > low) && high > ((px4_arch_adc_dn_fullcount() * 800) / 1000)) {
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*id = low;
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rv = OK;
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} else {
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/* No - No Resistors is ID 0 */
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*id = 0;
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@@ -41,9 +41,11 @@
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#include <errno.h>
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#include <nuttx/board.h>
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#include <arm_internal.h>
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#include <hardware/imxrt_snvs.h>
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#include <hardware/rt117x/imxrt117x_snvs.h>
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#define PX4_IMXRT_RTC_REBOOT_REG 3 // Must be common with bootloader and:
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#define BOOT_RTC_SIGNATURE 0xb007b007
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#define PX4_IMXRT_RTC_REBOOT_REG 3
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#define PX4_IMXRT_RTC_REBOOT_REG_ADDRESS IMXRT_SNVS_LPGPR3
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#if CONFIG_IMXRT_RTC_MAGIC_REG == PX4_IMXRT_RTC_REBOOT_REG
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# error CONFIG_IMXRT_RTC_MAGIC_REG can nt have the save value as PX4_IMXRT_RTC_REBOOT_REG
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@@ -51,8 +53,9 @@
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static int board_reset_enter_bootloader()
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{
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uint32_t regvalue = 0xb007b007;
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putreg32(regvalue, IMXRT_SNVS_LPGPR(PX4_IMXRT_RTC_REBOOT_REG));
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uint32_t regvalue = BOOT_RTC_SIGNATURE;
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modifyreg32(IMXRT_SNVS_LPCR, 0, SNVS_LPCR_GPR_Z_DIS);
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putreg32(regvalue, PX4_IMXRT_RTC_REBOOT_REG_ADDRESS);
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return OK;
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}
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@@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (C) 2020 PX4 Development Team. All rights reserved.
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* Copyright (C) 2020, 2023 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -47,6 +47,8 @@ typedef struct {
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int hi;
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} lh_t;
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#if defined(CONFIG_ARCH_FAMILY_IMXRT106x)
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const lh_t port_to_irq[9] = {
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{_IMXRT_GPIO1_0_15_BASE, _IMXRT_GPIO1_16_31_BASE}, {_IMXRT_GPIO2_0_15_BASE, _IMXRT_GPIO2_16_31_BASE},
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{_IMXRT_GPIO3_0_15_BASE, _IMXRT_GPIO3_16_31_BASE}, {_IMXRT_GPIO4_0_15_BASE, _IMXRT_GPIO4_16_31_BASE},
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@@ -54,6 +56,41 @@ const lh_t port_to_irq[9] = {
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{_IMXRT_GPIO7_0_15_BASE, _IMXRT_GPIO7_16_31_BASE}, {_IMXRT_GPIO8_0_15_BASE, _IMXRT_GPIO8_16_31_BASE},
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{_IMXRT_GPIO9_0_15_BASE, _IMXRT_GPIO9_16_31_BASE},
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};
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#endif
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#if defined(CONFIG_ARCH_FAMILY_IMXRT117x)
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const lh_t port_to_irq[13] = {
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{_IMXRT_GPIO1_0_15_BASE, _IMXRT_GPIO1_16_31_BASE},
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{_IMXRT_GPIO2_0_15_BASE, _IMXRT_GPIO2_16_31_BASE},
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{_IMXRT_GPIO3_0_15_BASE, _IMXRT_GPIO3_16_31_BASE},
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{_IMXRT_GPIO4_0_15_BASE, _IMXRT_GPIO4_16_31_BASE},
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{_IMXRT_GPIO5_0_15_BASE, _IMXRT_GPIO5_16_31_BASE},
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{_IMXRT_GPIO6_0_15_BASE, _IMXRT_GPIO6_16_31_BASE},
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{0, 0}, // GPIO7 Not on CM7
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{0, 0}, // GPIO8 Not on CM7
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{0, 0}, // GPIO9 Not on CM7
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{0, 0}, // GPIO10 Not on CM7
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{0, 0}, // GPIO11 Not on CM7
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{0, 0}, // GPIO12 Not on CM7
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{_IMXRT_GPIO13_BASE, _IMXRT_GPIO13_BASE},
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};
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#endif
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static int imxrt_pin_irq(gpio_pinset_t pinset)
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{
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volatile int irq = -1;
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volatile int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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volatile int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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lh_t irqlh = port_to_irq[port];
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if (irqlh.low != 0 && irqlh.hi != 0) {
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irq = (pin < 16) ? irqlh.low : irqlh.hi;
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irq += pin % 16;
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}
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return irq;
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}
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/****************************************************************************
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* Name: imxrt_pin_irqattach
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@@ -75,15 +112,16 @@ const lh_t port_to_irq[9] = {
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static int imxrt_pin_irqattach(gpio_pinset_t pinset, xcpt_t func, void *arg)
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{
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volatile int port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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volatile int pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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volatile int irq;
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lh_t irqlh = port_to_irq[port];
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irq = (pin < 16) ? irqlh.low : irqlh.hi;
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irq += pin % 16;
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irq_attach(irq, func, arg);
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up_enable_irq(irq);
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return 0;
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int rv = -EINVAL;
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int irq = imxrt_pin_irq(pinset);
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if (irq != -1) {
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rv = OK;
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irq_attach(irq, func, arg);
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up_enable_irq(irq);
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}
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return rv;
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}
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/****************************************************************************
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@@ -109,28 +147,31 @@ int imxrt_gpiosetevent(uint32_t pinset, bool risingedge, bool fallingedge,
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bool event, xcpt_t func, void *arg)
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{
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int ret = -ENOSYS;
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int irq = imxrt_pin_irq(pinset);
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if (func == NULL) {
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imxrt_gpioirq_disable(pinset);
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pinset &= ~GPIO_INTCFG_MASK;
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ret = imxrt_config_gpio(pinset);
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if (irq != -1) {
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if (func == NULL) {
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imxrt_gpioirq_disable(irq);
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pinset &= ~GPIO_INTCFG_MASK;
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ret = imxrt_config_gpio(pinset);
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} else {
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} else {
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pinset &= ~GPIO_INTCFG_MASK;
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pinset &= ~GPIO_INTCFG_MASK;
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if (risingedge & fallingedge) {
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pinset |= GPIO_INTBOTH_EDGES;
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if (risingedge & fallingedge) {
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pinset |= GPIO_INTBOTH_EDGES;
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} else if (risingedge) {
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pinset |= GPIO_INT_RISINGEDGE;
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} else if (risingedge) {
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pinset |= GPIO_INT_RISINGEDGE;
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} else if (fallingedge) {
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pinset |= GPIO_INT_FALLINGEDGE;
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} else if (fallingedge) {
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pinset |= GPIO_INT_FALLINGEDGE;
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}
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imxrt_gpioirq_configure(pinset);
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ret = imxrt_pin_irqattach(pinset, func, arg);
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}
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imxrt_gpioirq_configure(pinset);
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ret = imxrt_pin_irqattach(pinset, func, arg);
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}
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return ret;
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@@ -0,0 +1,39 @@
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############################################################################
|
||||
#
|
||||
# Copyright (c) 2023 PX4 Development Team. All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name PX4 nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
px4_add_library(arch_spi
|
||||
spi.cpp
|
||||
)
|
||||
target_compile_options(arch_spi PRIVATE ${MAX_CUSTOM_OPT_LEVEL})
|
||||
|
||||
target_link_libraries (arch_spi PRIVATE drivers_board) # px4_spi_buses
|
||||
@@ -0,0 +1,521 @@
|
||||
/****************************************************************************
|
||||
*
|
||||
* Copyright (c) 2023 PX4 Development Team. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name PX4 nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <board_config.h>
|
||||
#include <systemlib/px4_macros.h>
|
||||
#include <px4_platform_common/spi.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include <nuttx/spi/spi.h>
|
||||
#include <arch/board/board.h>
|
||||
#include <arm_internal.h>
|
||||
#include <chip.h>
|
||||
#include "imxrt_gpio.h"
|
||||
|
||||
static const px4_spi_bus_t *_spi_bus1;
|
||||
static const px4_spi_bus_t *_spi_bus2;
|
||||
static const px4_spi_bus_t *_spi_bus3;
|
||||
static const px4_spi_bus_t *_spi_bus4;
|
||||
static const px4_spi_bus_t *_spi_bus5;
|
||||
static const px4_spi_bus_t *_spi_bus6;
|
||||
|
||||
static void spi_bus_configgpio_cs(const px4_spi_bus_t *bus)
|
||||
{
|
||||
for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
|
||||
if (bus->devices[i].cs_gpio != 0) {
|
||||
px4_arch_configgpio(bus->devices[i].cs_gpio);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
__EXPORT void imxrt_spiinitialize()
|
||||
{
|
||||
px4_set_spi_buses_from_hw_version();
|
||||
board_control_spi_sensors_power_configgpio();
|
||||
board_control_spi_sensors_power(true, 0xffff);
|
||||
|
||||
for (int i = 0; i < SPI_BUS_MAX_BUS_ITEMS; ++i) {
|
||||
switch (px4_spi_buses[i].bus) {
|
||||
case 1: _spi_bus1 = &px4_spi_buses[i]; break;
|
||||
|
||||
case 2: _spi_bus2 = &px4_spi_buses[i]; break;
|
||||
|
||||
case 3: _spi_bus3 = &px4_spi_buses[i]; break;
|
||||
|
||||
case 4: _spi_bus4 = &px4_spi_buses[i]; break;
|
||||
|
||||
case 5: _spi_bus5 = &px4_spi_buses[i]; break;
|
||||
|
||||
case 6: _spi_bus6 = &px4_spi_buses[i]; break;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPSPI1
|
||||
ASSERT(_spi_bus1);
|
||||
|
||||
if (board_has_bus(BOARD_SPI_BUS, 1)) {
|
||||
spi_bus_configgpio_cs(_spi_bus1);
|
||||
}
|
||||
|
||||
#endif // CONFIG_IMXRT_LPSPI1
|
||||
|
||||
|
||||
#if defined(CONFIG_IMXRT_LPSPI2)
|
||||
ASSERT(_spi_bus2);
|
||||
|
||||
if (board_has_bus(BOARD_SPI_BUS, 2)) {
|
||||
spi_bus_configgpio_cs(_spi_bus2);
|
||||
}
|
||||
|
||||
#endif // CONFIG_IMXRT_LPSPI2
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPSPI3
|
||||
ASSERT(_spi_bus3);
|
||||
|
||||
if (board_has_bus(BOARD_SPI_BUS, 3)) {
|
||||
spi_bus_configgpio_cs(_spi_bus3);
|
||||
}
|
||||
|
||||
#endif // CONFIG_IMXRT_LPSPI3
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPSPI4
|
||||
ASSERT(_spi_bus4);
|
||||
|
||||
if (board_has_bus(BOARD_SPI_BUS, 4)) {
|
||||
spi_bus_configgpio_cs(_spi_bus4);
|
||||
}
|
||||
|
||||
#endif // CONFIG_IMXRT_LPSPI4
|
||||
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPSPI5
|
||||
ASSERT(_spi_bus5);
|
||||
|
||||
if (board_has_bus(BOARD_SPI_BUS, 5)) {
|
||||
spi_bus_configgpio_cs(_spi_bus5);
|
||||
}
|
||||
|
||||
#endif // CONFIG_IMXRT_LPSPI5
|
||||
|
||||
|
||||
#ifdef CONFIG_IMXRT_LPSPI6
|
||||
ASSERT(_spi_bus6);
|
||||
|
||||
if (board_has_bus(BOARD_SPI_BUS, 6)) {
|
||||
spi_bus_configgpio_cs(_spi_bus6);
|
||||
}
|
||||
|
||||
#endif // CONFIG_IMXRT_LPSPI6
|
||||
}
|
||||
|
||||
static inline void imxrt_lpspixselect(const px4_spi_bus_t *bus, struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
|
||||
if (bus->devices[i].cs_gpio == 0) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (devid == bus->devices[i].devid) {
|
||||
// SPI select is active low, so write !selected to select the device
|
||||
imxrt_gpio_write(bus->devices[i].cs_gpio, !selected);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_lpspi1select and imxrt_lpspi1select
|
||||
*
|
||||
* Description:
|
||||
* Called by imxrt spi driver on bus 1.
|
||||
*
|
||||
************************************************************************************/
|
||||
#ifdef CONFIG_IMXRT_LPSPI1
|
||||
|
||||
__EXPORT void imxrt_lpspi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
imxrt_lpspixselect(_spi_bus1, dev, devid, selected);
|
||||
}
|
||||
|
||||
__EXPORT uint8_t imxrt_lpspi1status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif // CONFIG_IMXRT_LPSPI1
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_lpspi2select and imxrt_lpspi2select
|
||||
*
|
||||
* Description:
|
||||
* Called by imxrt spi driver on bus 2.
|
||||
*
|
||||
************************************************************************************/
|
||||
#if defined(CONFIG_IMXRT_LPSPI2)
|
||||
__EXPORT void imxrt_lpspi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
imxrt_lpspixselect(_spi_bus2, dev, devid, selected);
|
||||
}
|
||||
|
||||
__EXPORT uint8_t imxrt_lpspi2status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif // CONFIG_IMXRT_LPSPI2
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_lpspi3select and imxrt_lpspi3select
|
||||
*
|
||||
* Description:
|
||||
* Called by imxrt spi driver on bus 3.
|
||||
*
|
||||
************************************************************************************/
|
||||
#if defined(CONFIG_IMXRT_LPSPI3)
|
||||
__EXPORT void imxrt_lpspi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
imxrt_lpspixselect(_spi_bus3, dev, devid, selected);
|
||||
}
|
||||
|
||||
__EXPORT uint8_t imxrt_lpspi3status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif // CONFIG_IMXRT_LPSPI3
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_lpspi4select and imxrt_lpspi4select
|
||||
*
|
||||
* Description:
|
||||
* Called by imxrt spi driver on bus 4.
|
||||
*
|
||||
************************************************************************************/
|
||||
#ifdef CONFIG_IMXRT_LPSPI4
|
||||
|
||||
__EXPORT void imxrt_lpspi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
imxrt_lpspixselect(_spi_bus4, dev, devid, selected);
|
||||
}
|
||||
|
||||
__EXPORT uint8_t imxrt_lpspi4status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif // CONFIG_IMXRT_LPSPI4
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_lpspi5select and imxrt_lpspi5select
|
||||
*
|
||||
* Description:
|
||||
* Called by imxrt spi driver on bus 5.
|
||||
*
|
||||
************************************************************************************/
|
||||
#ifdef CONFIG_IMXRT_LPSPI5
|
||||
|
||||
__EXPORT void imxrt_lpspi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
imxrt_lpspixselect(_spi_bus5, dev, devid, selected);
|
||||
}
|
||||
|
||||
__EXPORT uint8_t imxrt_lpspi5status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif // CONFIG_IMXRT_LPSPI5
|
||||
|
||||
/************************************************************************************
|
||||
* Name: imxrt_lpspi6select and imxrt_lpspi6select
|
||||
*
|
||||
* Description:
|
||||
* Called by imxrt spi driver on bus 6.
|
||||
*
|
||||
************************************************************************************/
|
||||
#ifdef CONFIG_IMXRT_LPSPI6
|
||||
|
||||
__EXPORT void imxrt_lpspi6select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
|
||||
{
|
||||
imxrt_lpspixselect(_spi_bus6, dev, devid, selected);
|
||||
}
|
||||
|
||||
__EXPORT uint8_t imxrt_lpspi6status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
return SPI_STATUS_PRESENT;
|
||||
}
|
||||
#endif // CONFIG_IMXRT_LPSPI6
|
||||
|
||||
|
||||
void board_control_spi_sensors_power(bool enable_power, int bus_mask)
|
||||
{
|
||||
const px4_spi_bus_t *buses = px4_spi_buses;
|
||||
// this might be called very early on boot where we have not yet determined the hw version
|
||||
// (we expect all versions to have the same power GPIO)
|
||||
#if BOARD_NUM_SPI_CFG_HW_VERSIONS > 1
|
||||
|
||||
if (!buses) {
|
||||
buses = &px4_spi_buses_all_hw[0].buses[0];
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
|
||||
if (buses[bus].bus == -1) {
|
||||
break;
|
||||
}
|
||||
|
||||
const bool bus_matches = bus_mask & (1 << (buses[bus].bus - 1));
|
||||
|
||||
if (buses[bus].power_enable_gpio == 0 ||
|
||||
!board_has_bus(BOARD_SPI_BUS, buses[bus].bus) ||
|
||||
!bus_matches) {
|
||||
continue;
|
||||
}
|
||||
|
||||
px4_arch_gpiowrite(buses[bus].power_enable_gpio, enable_power ? 1 : 0);
|
||||
}
|
||||
}
|
||||
|
||||
void board_control_spi_sensors_power_configgpio()
|
||||
{
|
||||
const px4_spi_bus_t *buses = px4_spi_buses;
|
||||
// this might be called very early on boot where we have yet not determined the hw version
|
||||
// (we expect all versions to have the same power GPIO)
|
||||
#if BOARD_NUM_SPI_CFG_HW_VERSIONS > 1
|
||||
|
||||
if (!buses) {
|
||||
buses = &px4_spi_buses_all_hw[0].buses[0];
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
|
||||
if (buses[bus].bus == -1) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (buses[bus].power_enable_gpio == 0 ||
|
||||
!board_has_bus(BOARD_SPI_BUS, buses[bus].bus)) {
|
||||
continue;
|
||||
}
|
||||
|
||||
px4_arch_configgpio(buses[bus].power_enable_gpio);
|
||||
}
|
||||
}
|
||||
|
||||
__EXPORT void board_spi_reset(int ms, int bus_mask)
|
||||
{
|
||||
bool has_power_enable = false;
|
||||
|
||||
// disable SPI bus
|
||||
for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
|
||||
if (px4_spi_buses[bus].bus == -1) {
|
||||
break;
|
||||
}
|
||||
|
||||
const bool bus_requested = bus_mask & (1 << (px4_spi_buses[bus].bus - 1));
|
||||
|
||||
if (px4_spi_buses[bus].power_enable_gpio == 0 ||
|
||||
!board_has_bus(BOARD_SPI_BUS, px4_spi_buses[bus].bus) ||
|
||||
!bus_requested) {
|
||||
continue;
|
||||
}
|
||||
|
||||
has_power_enable = true;
|
||||
|
||||
for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
|
||||
if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
|
||||
px4_arch_configgpio(_PIN_OFF(px4_spi_buses[bus].devices[i].cs_gpio));
|
||||
}
|
||||
|
||||
if (px4_spi_buses[bus].devices[i].drdy_gpio != 0) {
|
||||
px4_arch_configgpio(_PIN_OFF(px4_spi_buses[bus].devices[i].drdy_gpio));
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_IMXRT_LPSPI1)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 1) {
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI1_SCK));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI1_MISO));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI1_MOSI));
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI2)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 2) {
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI2_SCK));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI2_MISO));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI2_MOSI));
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI3)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 3) {
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI3_SCK));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI3_MISO));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI3_MOSI));
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI4)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 4) {
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI4_SCK));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI4_MISO));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI4_MOSI));
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI5)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 5) {
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI5_SCK));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI5_MISO));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI5_MOSI));
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI6)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 6) {
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI6_SCK));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI6_MISO));
|
||||
px4_arch_configgpio(_PIN_OFF(GPIO_LPSPI6_MOSI));
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
if (!has_power_enable) {
|
||||
// board does not have power control over any of the sensor buses
|
||||
return;
|
||||
}
|
||||
|
||||
// set the sensor rail(s) off
|
||||
board_control_spi_sensors_power(false, bus_mask);
|
||||
|
||||
// wait for the sensor rail to reach GND
|
||||
usleep(ms * 1000);
|
||||
syslog(LOG_DEBUG, "reset done, %d ms\n", ms);
|
||||
|
||||
/* re-enable power */
|
||||
|
||||
// switch the sensor rail back on
|
||||
board_control_spi_sensors_power(true, bus_mask);
|
||||
|
||||
/* wait a bit before starting SPI, different times didn't influence results */
|
||||
usleep(100);
|
||||
|
||||
/* reconfigure the SPI pins */
|
||||
for (int bus = 0; bus < SPI_BUS_MAX_BUS_ITEMS; ++bus) {
|
||||
if (px4_spi_buses[bus].bus == -1) {
|
||||
break;
|
||||
}
|
||||
|
||||
const bool bus_requested = bus_mask & (1 << (px4_spi_buses[bus].bus - 1));
|
||||
|
||||
if (px4_spi_buses[bus].power_enable_gpio == 0 ||
|
||||
!board_has_bus(BOARD_SPI_BUS, px4_spi_buses[bus].bus) ||
|
||||
!bus_requested) {
|
||||
continue;
|
||||
}
|
||||
|
||||
for (int i = 0; i < SPI_BUS_MAX_DEVICES; ++i) {
|
||||
if (px4_spi_buses[bus].devices[i].cs_gpio != 0) {
|
||||
px4_arch_configgpio(px4_spi_buses[bus].devices[i].cs_gpio);
|
||||
}
|
||||
|
||||
if (px4_spi_buses[bus].devices[i].drdy_gpio != 0) {
|
||||
px4_arch_configgpio(px4_spi_buses[bus].devices[i].drdy_gpio);
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(CONFIG_IMXRT_LPSPI1)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 1) {
|
||||
px4_arch_configgpio(GPIO_LPSPI1_SCK);
|
||||
px4_arch_configgpio(GPIO_LPSPI1_MISO);
|
||||
px4_arch_configgpio(GPIO_LPSPI1_MOSI);
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI2)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 2) {
|
||||
px4_arch_configgpio(GPIO_LPSPI2_SCK);
|
||||
px4_arch_configgpio(GPIO_LPSPI2_MISO);
|
||||
px4_arch_configgpio(GPIO_LPSPI2_MOSI);
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI3)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 3) {
|
||||
px4_arch_configgpio(GPIO_LPSPI3_SCK);
|
||||
px4_arch_configgpio(GPIO_LPSPI3_MISO);
|
||||
px4_arch_configgpio(GPIO_LPSPI3_MOSI);
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI4)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 4) {
|
||||
px4_arch_configgpio(GPIO_LPSPI4_SCK);
|
||||
px4_arch_configgpio(GPIO_LPSPI4_MISO);
|
||||
px4_arch_configgpio(GPIO_LPSPI4_MOSI);
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI5)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 5) {
|
||||
px4_arch_configgpio(GPIO_LPSPI5_SCK);
|
||||
px4_arch_configgpio(GPIO_LPSPI5_MISO);
|
||||
px4_arch_configgpio(GPIO_LPSPI5_MOSI);
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(CONFIG_IMXRT_LPSPI6)
|
||||
|
||||
if (px4_spi_buses[bus].bus == 6) {
|
||||
px4_arch_configgpio(GPIO_LPSPI6_SCK);
|
||||
px4_arch_configgpio(GPIO_LPSPI6_MISO);
|
||||
px4_arch_configgpio(GPIO_LPSPI6_MOSI);
|
||||
}
|
||||
|
||||
#endif
|
||||
}
|
||||
}
|
||||
@@ -72,12 +72,20 @@
|
||||
# define TONE_ALARM_CLOCK_ALL() imxrt_clockall_gpt_bus() /* The Clock Gating macro for this GPT */
|
||||
#elif TONE_ALARM_TIMER == 2
|
||||
# define TONE_ALARM_CLOCK_ALL() imxrt_clockall_gpt2_bus() /* The Clock Gating macro for this GPT */
|
||||
#elif TONE_ALARM_TIMER == 3
|
||||
# define TONE_ALARM_CLOCK_ALL() imxrt_clockall_gpt3_bus() /* The Clock Gating macro for this GPT */
|
||||
#elif TONE_ALARM_TIMER == 4
|
||||
# define TONE_ALARM_CLOCK_ALL() imxrt_clockall_gpt4_bus() /* The Clock Gating macro for this GPT */
|
||||
#endif
|
||||
|
||||
#if TONE_ALARM_TIMER == 1 && defined(CONFIG_IMXRT_GPT1)
|
||||
# error must not set CONFIG_IMXRT_GPT1=y and TONE_ALARM_TIMER=1
|
||||
#elif TONE_ALARM_TIMER == 2 && defined(CONFIG_IMXRT_GPT2)
|
||||
# error must not set CONFIG_IMXRT_GPT2=y and TONE_ALARM_TIMER=2
|
||||
#elif TONE_ALARM_TIMER == 3 && defined(CONFIG_IMXRT_GPT3)
|
||||
# error must not set CONFIG_IMXRT_GPT3=y and TONE_ALARM_TIMER=3
|
||||
#elif TONE_ALARM_TIMER == 4 && defined(CONFIG_IMXRT_GPT4)
|
||||
# error must not set CONFIG_IMXRT_GPT4=y and TONE_ALARM_TIMER=4
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
@@ -81,25 +81,8 @@ void board_get_uuid(uuid_byte_t uuid_bytes)
|
||||
|
||||
void board_get_uuid32(uuid_uint32_t uuid_words)
|
||||
{
|
||||
/* IMXRT_OCOTP_CFG1:0x420[10:0], IMXRT_OCOTP_CFG0:0x410[31:0] LOT_NO_ENC[42:0](SJC_CHALL/UNIQUE_ID[42:0])
|
||||
* 43 bits FSL-wide unique,encoded LOT ID STD II/SJC CHALLENGE/ Unique ID
|
||||
* 0x420[15:11] WAFER_NO[4:0]( SJC_CHALL[47:43] /UNIQUE_ID[47:43])
|
||||
* 5 bits The wafer number of the wafer on which the device was fabricated/SJC CHALLENGE/ Unique ID
|
||||
* 0x420[23:16] DIE-YCORDINATE[7:0]( SJC_CHALL[55:48] /UNIQUE_ID[55:48])
|
||||
* 8 bits The Y-coordinate of the die location on the wafer/SJC CHALLENGE/Unique ID
|
||||
* 0x420[31:24] DIE-XCORDINATE[7:0]( SJC_CHALL[63:56] /UNIQUE_ID[63:56] )
|
||||
* 8 bits The X-coordinate of the die location on the wafer/SJC CHALLENGE/Unique ID
|
||||
*
|
||||
* word [0] word[1]
|
||||
* SJC_CHALL[63:32] [31:00]
|
||||
*/
|
||||
#ifdef CONFIG_ARCH_FAMILY_IMXRT117x
|
||||
uuid_words[0] = getreg32(IMXRT_OCOTP_FUSE(0x10));
|
||||
uuid_words[1] = getreg32(IMXRT_OCOTP_FUSE(0x11));
|
||||
#else
|
||||
uuid_words[0] = getreg32(IMXRT_OCOTP_CFG1);
|
||||
uuid_words[1] = getreg32(IMXRT_OCOTP_CFG0);
|
||||
#endif
|
||||
uuid_words[0] = getreg32(IMXRT_OCOTP_UNIQUE_ID_MSB);
|
||||
uuid_words[1] = getreg32(IMXRT_OCOTP_UNIQUE_ID_LSB);
|
||||
}
|
||||
|
||||
int board_get_uuid32_formated(char *format_buffer, int size,
|
||||
|
||||
Reference in New Issue
Block a user