[BACKPORT] px4_fmu-v6xrt:Use multi-PHY

boards/px4/fmu-v6xrt/nuttx-config/include/board.h

@@ -267,6 +267,7 @@
 
 // This is the ENET_1G interface.
 
+// Compile time selection
 #if defined(CONFIG_ETH0_PHY_TJA1103)
 #  define BOARD_PHY_ADDR (18)
 #endif
@@ -274,6 +275,35 @@
 #  define BOARD_PHY_ADDR (0)
 #endif
 
+/* Run time selection see mii.h */
+
+#define BOARD_ETH0_PHY_LIST \
+	{                                   \
+		"LAN8742A",                      \
+		MII_PHYID1_LAN8742A,             \
+		MII_PHYID2_LAN8742A,             \
+		MII_LAN8740_SCSR,                \
+		0,                               \
+		0xffff,                          \
+		MII_LAN8720_SPSCR_10MBPS,        \
+		MII_LAN8720_SPSCR_100MBPS,       \
+		MII_LAN8720_SPSCR_DUPLEX,        \
+		22,                              \
+	},                                  \
+	{                                   \
+		"TJA1103",                       \
+		MII_PHYID1_TJA1103,              \
+		MII_PHYID2_TJA1103,              \
+		0xffff,                          \
+		18,                              \
+		0xffff,                          \
+		0,                               \
+		MII_LAN8720_SPSCR_100MBPS,       \
+		MII_LAN8720_SPSCR_DUPLEX,        \
+		45,                              \
+	},                                  \
+
+
 #define GPIO_ENET2_TX_DATA00  (GPIO_ENET_1G_TX_DATA0_1|IOMUX_ENET_DATA_DEFAULT)  /* GPIO_DISP_B1_09 */
 #define GPIO_ENET2_TX_DATA01  (GPIO_ENET_1G_TX_DATA1_1|IOMUX_ENET_DATA_DEFAULT)  /* GPIO_DISP_B1_08 */
 #define GPIO_ENET2_RX_DATA00  (GPIO_ENET_1G_RX_DATA0_2|IOMUX_ENET_DATA_DEFAULT)  /* GPIO_EMC_B2_15  */

boards/px4/fmu-v6xrt/nuttx-config/nsh/defconfig

@@ -51,7 +51,7 @@ CONFIG_DEBUG_SYMBOLS=y
 CONFIG_DEBUG_TCBINFO=y
 CONFIG_DEV_FIFO_SIZE=0
 CONFIG_DEV_PIPE_SIZE=70
-CONFIG_ETH0_PHY_LAN8742A=y
+CONFIG_ETH0_PHY_MULTI=y
 CONFIG_FAT_DMAMEMORY=y
 CONFIG_FAT_LCNAMES=y
 CONFIG_FAT_LFN=y