mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-10-16 02:13:35 +08:00
PX4 System changes Supporting STM32H7
stm32:ToneAlarmInterfacePWM TIM15-TIM17 have a BDTR Register common:board_crashdump Add H7 support stm32/board_mcu_version:Support H7 PX4 ADC:Use 32 interface and resoution abstraction Added PX4 stm32h7 ADC driver stm32h7:adc fix ADC ready check fmu: handle BOARD_HAS_PWM==5 cmake: improve error handling for NuttX olddefconfig failures WorkQueueManager:Quiet loadmon stack warning camera_trigger:GPIO support < 6 GPIO Adjust stack sizes (under hw stack check) PX4 System changes Supporting STM32H7 PX4IO Driver aerotenna_ocpoc:ADC add px4_arch_adc_dn_fullcount init.cmake:Track Upstream change needing Make.def at config time PX4 System changes Supporting STM32H7 NuttX CMakeLists.txt Track upstream changes Common board_crashdump add header and px4 config NuttX simplify callinb make libapps Use UINT32_MAX for error return drivers:uavcannode NuttX chip is now hardware drivers:uavcanesc NuttX chip is now hardware px4io:Avoid Race on AP to PX4 IO upgrade
This commit is contained in:
David Sidrane
committed by
Lorenz Meier
Lorenz Meier
parent
58799dc7d1
commit
e847698c9f
+10
-9
@@ -37,7 +37,7 @@
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* Driver for an ADC.
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*
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*/
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#include <stdint.h>
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#include <drivers/drv_adc.h>
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#include <drivers/drv_hrt.h>
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#include <lib/cdev/CDev.hpp>
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@@ -82,9 +82,9 @@ private:
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* Sample a single channel and return the measured value.
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*
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* @param channel The channel to sample.
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* @return The sampled value, or 0xffff if sampling failed.
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* @return The sampled value, or UINT32_MAX if sampling failed.
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*/
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uint16_t sample(unsigned channel);
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uint32_t sample(unsigned channel);
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void update_adc_report(hrt_abstime now);
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void update_system_power(hrt_abstime now);
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@@ -233,7 +233,8 @@ ADC::update_adc_report(hrt_abstime now)
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for (unsigned i = 0; i < max_num; i++) {
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adc.channel_id[i] = _samples[i].am_channel;
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adc.channel_value[i] = _samples[i].am_data * 3.3f / 4096.0f;
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adc.channel_value[i] = _samples[i].am_data * 3.3f / px4_arch_adc_dn_fullcount();
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;
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}
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_to_adc_report.publish(adc);
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@@ -258,7 +259,7 @@ ADC::update_system_power(hrt_abstime now)
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if (_samples[i].am_channel == ADC_SCALED_V5_SENSE) {
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// it is 2:1 scaled
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system_power.voltage5v_v = _samples[i].am_data * (ADC_V5_V_FULL_SCALE / 4096.0f);
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system_power.voltage5v_v = _samples[i].am_data * (ADC_V5_V_FULL_SCALE / px4_arch_adc_dn_fullcount());
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cnt--;
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} else
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@@ -267,7 +268,7 @@ ADC::update_system_power(hrt_abstime now)
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{
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if (_samples[i].am_channel == ADC_SCALED_V3V3_SENSORS_SENSE) {
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// it is 2:1 scaled
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system_power.voltage3v3_v = _samples[i].am_data * (ADC_3V3_SCALE * (3.3f / 4096.0f));
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system_power.voltage3v3_v = _samples[i].am_data * (ADC_3V3_SCALE * (3.3f / px4_arch_adc_dn_fullcount()));
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system_power.v3v3_valid = 1;
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cnt--;
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}
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@@ -323,13 +324,13 @@ ADC::update_system_power(hrt_abstime now)
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#endif // BOARD_ADC_USB_CONNECTED
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}
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uint16_t
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uint32_t
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ADC::sample(unsigned channel)
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{
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perf_begin(_sample_perf);
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uint16_t result = px4_arch_adc_sample(_base_address, channel);
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uint32_t result = px4_arch_adc_sample(_base_address, channel);
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if (result == 0xffff) {
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if (result == UINT32_MAX) {
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PX4_ERR("sample timeout");
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}
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@@ -3,7 +3,7 @@
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#include "gpio.h"
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#include <cstring>
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constexpr uint32_t CameraInterfaceGPIO::_gpios[6];
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constexpr uint32_t CameraInterfaceGPIO::_gpios[ngpios];
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CameraInterfaceGPIO::CameraInterfaceGPIO():
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CameraInterface(),
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@@ -25,7 +25,7 @@ void CameraInterfaceGPIO::setup()
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{
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for (unsigned i = 0, t = 0; i < arraySize(_pins); i++) {
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// Pin range is from 1 to 6, indexes are 0 to 5
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// Pin range is from 1 to 5 or 6, indexes are 0 to 4 or 5
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if (_pins[i] >= 0 && _pins[i] < (int)arraySize(_gpios)) {
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uint32_t gpio = _gpios[_pins[i]];
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@@ -50,9 +50,17 @@ void CameraInterfaceGPIO::trigger(bool trigger_on_true)
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void CameraInterfaceGPIO::info()
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{
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PX4_INFO("GPIO trigger mode, pins enabled : [%d][%d][%d][%d][%d][%d], polarity : %s",
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_pins[5], _pins[4], _pins[3], _pins[2], _pins[1], _pins[0],
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_trigger_invert ? "ACTIVE_LOW" : "ACTIVE_HIGH");
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if (ngpios == 6) {
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PX4_INFO("GPIO trigger mode, pins enabled : [%d][%d][%d][%d][%d][%d], polarity : %s",
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_pins[5], _pins[4], _pins[3], _pins[2], _pins[1], _pins[0],
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_trigger_invert ? "ACTIVE_LOW" : "ACTIVE_HIGH");
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}
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if (ngpios == 5) {
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PX4_INFO("GPIO trigger mode, pins enabled : [%d][%d][%d][%d][%d], polarity : %s",
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_pins[4], _pins[3], _pins[2], _pins[1], _pins[0],
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_trigger_invert ? "ACTIVE_LOW" : "ACTIVE_HIGH");
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}
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}
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#endif /* ifdef __PX4_NUTTX */
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@@ -21,6 +21,11 @@ public:
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void trigger(bool trigger_on_true);
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void info();
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#if defined(GPIO_GPIO5_OUTPUT)
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static const int ngpios = 6;
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#else
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static const int ngpios = 5;
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#endif
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private:
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@@ -30,13 +35,15 @@ private:
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bool _trigger_invert;
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static constexpr uint32_t _gpios[6] = {
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static constexpr uint32_t _gpios[ngpios] = {
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GPIO_GPIO0_OUTPUT,
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GPIO_GPIO1_OUTPUT,
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GPIO_GPIO2_OUTPUT,
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GPIO_GPIO3_OUTPUT,
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GPIO_GPIO4_OUTPUT,
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#if defined(GPIO_GPIO5_OUTPUT)
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GPIO_GPIO5_OUTPUT
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#endif
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};
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uint32_t _triggers[arraySize(_gpios)];
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@@ -1,6 +1,6 @@
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/****************************************************************************
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*
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* Copyright (C) 2012 PX4 Development Team. All rights reserved.
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* Copyright (C) 2012, 2019 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -78,14 +78,19 @@ void px4_arch_adc_uninit(uint32_t base_address);
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* Read a sample from the ADC
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* @param base_address architecture-specific address to specify the ADC
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* @param channel specify the channel
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* @return sample, 0xffff on error
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* @return sample, 0xffffffff on error
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*/
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uint16_t px4_arch_adc_sample(uint32_t base_address, unsigned channel);
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uint32_t px4_arch_adc_sample(uint32_t base_address, unsigned channel);
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/**
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* Get the temperature sensor channel bitmask
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*/
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uint32_t px4_arch_adc_temp_sensor_mask(void);
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/**
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* Get the adc digital number full count
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*/
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uint32_t px4_arch_adc_dn_fullcount(void);
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__END_DECLS
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@@ -83,6 +83,8 @@ struct GPS_Sat_Info {
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struct satellite_info_s _data;
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};
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static constexpr int TASK_STACK_SIZE = 1620;
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class GPS : public ModuleBase<GPS>
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{
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@@ -1069,7 +1071,7 @@ int GPS::task_spawn(int argc, char *argv[], Instance instance)
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}
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int task_id = px4_task_spawn_cmd("gps", SCHED_DEFAULT,
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SCHED_PRIORITY_SLOW_DRIVER, 1700,
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SCHED_PRIORITY_SLOW_DRIVER, TASK_STACK_SIZE,
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entry_point, (char *const *)argv);
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if (task_id < 0) {
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@@ -33,6 +33,7 @@
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px4_add_module(
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MODULE drivers__blinkm
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MAIN blinkm
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STACK_MAIN 1240
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COMPILE_FLAGS
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SRCS
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blinkm.cpp
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@@ -94,70 +94,14 @@
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#error PWMIN defines are needed in board_config.h for this board
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#endif
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/* PWMIN configuration */
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#if PWMIN_TIMER == 1
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# define PWMIN_TIMER_BASE STM32_TIM1_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB2ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB2ENR_TIM1EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM1CC
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# define PWMIN_TIMER_CLOCK STM32_APB2_TIM1_CLKIN
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#elif PWMIN_TIMER == 2
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# define PWMIN_TIMER_BASE STM32_TIM2_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB1ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB1ENR_TIM2EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM2
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# define PWMIN_TIMER_CLOCK STM32_APB1_TIM2_CLKIN
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#elif PWMIN_TIMER == 3
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# define PWMIN_TIMER_BASE STM32_TIM3_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB1ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB1ENR_TIM3EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM3
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# define PWMIN_TIMER_CLOCK STM32_APB1_TIM3_CLKIN
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#elif PWMIN_TIMER == 4
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# define PWMIN_TIMER_BASE STM32_TIM4_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB1ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB1ENR_TIM4EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM4
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# define PWMIN_TIMER_CLOCK STM32_APB1_TIM4_CLKIN
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#elif PWMIN_TIMER == 5
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# define PWMIN_TIMER_BASE STM32_TIM5_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB1ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB1ENR_TIM5EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM5
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# define PWMIN_TIMER_CLOCK STM32_APB1_TIM5_CLKIN
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#elif PWMIN_TIMER == 8
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# define PWMIN_TIMER_BASE STM32_TIM8_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB2ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB2ENR_TIM8EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM8CC
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# define PWMIN_TIMER_CLOCK STM32_APB2_TIM8_CLKIN
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#elif PWMIN_TIMER == 9
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# define PWMIN_TIMER_BASE STM32_TIM9_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB2ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB2ENR_TIM9EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM1BRK
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# define PWMIN_TIMER_CLOCK STM32_APB2_TIM9_CLKIN
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#elif PWMIN_TIMER == 10
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# define PWMIN_TIMER_BASE STM32_TIM10_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB2ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB2ENR_TIM10EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM1UP
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# define PWMIN_TIMER_CLOCK STM32_APB2_TIM10_CLKIN
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#elif PWMIN_TIMER == 11
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# define PWMIN_TIMER_BASE STM32_TIM11_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB2ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB2ENR_TIM11EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM1TRGCOM
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# define PWMIN_TIMER_CLOCK STM32_APB2_TIM11_CLKIN
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#elif PWMIN_TIMER == 12
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# define PWMIN_TIMER_BASE STM32_TIM12_BASE
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# define PWMIN_TIMER_POWER_REG STM32_RCC_APB1ENR
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# define PWMIN_TIMER_POWER_BIT RCC_APB1ENR_TIM12EN
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# define PWMIN_TIMER_VECTOR STM32_IRQ_TIM8BRK
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# define PWMIN_TIMER_CLOCK STM32_APB1_TIM12_CLKIN
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#else
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# error PWMIN_TIMER must be a value between 1 and 12
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#endif
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/* Get the timer defines */
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#define INPUT_TIMER PWMIN_TIMER
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#include "timer_registers.h"
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#define PWMIN_TIMER_BASE TIMER_BASE
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#define PWMIN_TIMER_CLOCK TIMER_CLOCK
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#define PWMIN_TIMER_POWER_REG TIMER_CLOCK_POWER_REG
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#define PWMIN_TIMER_POWER_BIT TIMER_CLOCK_POWER_BIT
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#define PWMIN_TIMER_VECTOR TIMER_IRQ_REG
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/*
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* HRT clock must be at least 1MHz
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@@ -0,0 +1,188 @@
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/****************************************************************************
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*
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* Copyright (C) 2019 PX4 Development Team. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
|
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/**
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* @file timer_registers.h
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*
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* Get architecture-specific timer register defines.
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* Usage:
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* #define INPUT_TIMER <timer>
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* #include "timer_registers.h"
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* # define <xy>_TIMER_BASE TIMER_BASE
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* # define <xy>_TIMER_CLOCK TIMER_CLOCK
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* # define <xy>_TIMER_POWER_REG TIMER_CLOCK_POWER_REG
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* # define <xy>_TIMER_POWER_BIT TIMER_CLOCK_POWER_BIT
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* # define <xy>_TIMER_VECTOR TIMER_IRQ_REG
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*
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*/
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#include <px4_platform_common/px4_config.h>
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#ifndef INPUT_TIMER
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# error "need to define INPUT_TIMER to use this header"
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#endif
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#ifdef TIMER_BASE
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#undef TIMER_BASE
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#endif
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#ifdef TIMER_CLOCK_POWER_REG
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#undef TIMER_CLOCK_POWER_REG
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#endif
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#ifdef TIMER_CLOCK_POWER_BIT
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#undef TIMER_CLOCK_POWER_BIT
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#endif
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#ifdef TIMER_CLOCK
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#undef TIMER_CLOCK
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#endif
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#ifdef TIMER_IRQ_REG
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#undef TIMER_IRQ_REG
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#endif
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#if defined(CONFIG_ARCH_CHIP_STM32H7)
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#if INPUT_TIMER == 1
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# define TIMER_BASE STM32_TIM1_BASE
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# define TIMER_CLOCK_POWER_REG STM32_RCC_APB2ENR
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# define TIMER_CLOCK_POWER_BIT RCC_APB2ENR_TIM1EN
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# define TIMER_IRQ_REG STM32_IRQ_TIMCC
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# define TIMER_CLOCK STM32_APB2_TIM1_CLKIN
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#elif INPUT_TIMER == 2
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# define TIMER_BASE STM32_TIM2_BASE
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# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1LENR
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# define TIMER_CLOCK_POWER_BIT RCC_APB1LENR_TIM2EN
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# define TIMER_IRQ_REG STM32_IRQ_TIM2
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# define TIMER_CLOCK STM32_APB1_TIM2_CLKIN
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#elif INPUT_TIMER == 3
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# define TIMER_BASE STM32_TIM3_BASE
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# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1LENR
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# define TIMER_CLOCK_POWER_BIT RCC_APB1LENR_TIM3EN
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# define TIMER_IRQ_REG STM32_IRQ_TIM3
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# define TIMER_CLOCK STM32_APB1_TIM3_CLKIN
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#elif INPUT_TIMER == 4
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# define TIMER_BASE STM32_TIM4_BASE
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# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1LENR
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# define TIMER_CLOCK_POWER_BIT RCC_APB1LENR_TIM4EN
|
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# define TIMER_IRQ_REG STM32_IRQ_TIM4
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# define TIMER_CLOCK STM32_APB1_TIM4_CLKIN
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#elif INPUT_TIMER == 5
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# define TIMER_BASE STM32_TIM5_BASE
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# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1LENR
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# define TIMER_CLOCK_POWER_BIT RCC_APB1LENR_TIM5EN
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# define TIMER_IRQ_REG STM32_IRQ_TIM5
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# define TIMER_CLOCK STM32_APB1_TIM5_CLKIN
|
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#elif INPUT_TIMER == 8
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# define TIMER_BASE STM32_TIM8_BASE
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# define TIMER_CLOCK_POWER_REG STM32_RCC_APB2ENR
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# define TIMER_CLOCK_POWER_BIT RCC_APB2ENR_TIM8EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM8CC
|
||||
# define TIMER_CLOCK STM32_APB2_TIM8_CLKIN
|
||||
#elif INPUT_TIMER == 12
|
||||
# define TIMER_BASE STM32_TIM12_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1LENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB1LENR_TIM12EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM12
|
||||
# define TIMER_CLOCK STM32_APB1_TIM12_CLKIN
|
||||
#else
|
||||
# error INPUT_TIMER must be a value between 1 and 12
|
||||
#endif
|
||||
|
||||
|
||||
#else // F4, F7
|
||||
|
||||
#if INPUT_TIMER == 1
|
||||
# define TIMER_BASE STM32_TIM1_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB2ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB2ENR_TIM1EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM1CC
|
||||
# define TIMER_CLOCK STM32_APB2_TIM1_CLKIN
|
||||
#elif INPUT_TIMER == 2
|
||||
# define TIMER_BASE STM32_TIM2_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB1ENR_TIM2EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM2
|
||||
# define TIMER_CLOCK STM32_APB1_TIM2_CLKIN
|
||||
#elif INPUT_TIMER == 3
|
||||
# define TIMER_BASE STM32_TIM3_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB1ENR_TIM3EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM3
|
||||
# define TIMER_CLOCK STM32_APB1_TIM3_CLKIN
|
||||
#elif INPUT_TIMER == 4
|
||||
# define TIMER_BASE STM32_TIM4_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB1ENR_TIM4EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM4
|
||||
# define TIMER_CLOCK STM32_APB1_TIM4_CLKIN
|
||||
#elif INPUT_TIMER == 5
|
||||
# define TIMER_BASE STM32_TIM5_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB1ENR_TIM5EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM5
|
||||
# define TIMER_CLOCK STM32_APB1_TIM5_CLKIN
|
||||
#elif INPUT_TIMER == 8
|
||||
# define TIMER_BASE STM32_TIM8_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB2ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB2ENR_TIM8EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM8CC
|
||||
# define TIMER_CLOCK STM32_APB2_TIM8_CLKIN
|
||||
#elif INPUT_TIMER == 9
|
||||
# define TIMER_BASE STM32_TIM9_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB2ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB2ENR_TIM9EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM1BRK
|
||||
# define TIMER_CLOCK STM32_APB2_TIM9_CLKIN
|
||||
#elif INPUT_TIMER == 10
|
||||
# define TIMER_BASE STM32_TIM10_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB2ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB2ENR_TIM10EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM1UP
|
||||
# define TIMER_CLOCK STM32_APB2_TIM10_CLKIN
|
||||
#elif INPUT_TIMER == 11
|
||||
# define TIMER_BASE STM32_TIM11_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB2ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB2ENR_TIM11EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM1TRGCOM
|
||||
# define TIMER_CLOCK STM32_APB2_TIM11_CLKIN
|
||||
#elif INPUT_TIMER == 12
|
||||
# define TIMER_BASE STM32_TIM12_BASE
|
||||
# define TIMER_CLOCK_POWER_REG STM32_RCC_APB1ENR
|
||||
# define TIMER_CLOCK_POWER_BIT RCC_APB1ENR_TIM12EN
|
||||
# define TIMER_IRQ_REG STM32_IRQ_TIM8BRK
|
||||
# define TIMER_CLOCK STM32_APB1_TIM12_CLKIN
|
||||
#else
|
||||
# error INPUT_TIMER must be a value between 1 and 12
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1146,9 +1146,12 @@ PX4FMU::pwm_ioctl(file *filp, int cmd, unsigned long arg)
|
||||
break;
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(BOARD_HAS_PWM) && BOARD_HAS_PWM >= 5
|
||||
|
||||
/* FALLTHROUGH */
|
||||
case PWM_SERVO_SET(4):
|
||||
if (_mode < MODE_5PWM1CAP) {
|
||||
if (_mode < MODE_5PWM) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
@@ -1216,9 +1219,12 @@ PX4FMU::pwm_ioctl(file *filp, int cmd, unsigned long arg)
|
||||
break;
|
||||
}
|
||||
|
||||
#endif
|
||||
#if defined(BOARD_HAS_PWM) && BOARD_HAS_PWM >= 5
|
||||
|
||||
/* FALLTHROUGH */
|
||||
case PWM_SERVO_GET(4):
|
||||
if (_mode < MODE_5PWM1CAP) {
|
||||
if (_mode < MODE_5PWM) {
|
||||
ret = -EINVAL;
|
||||
break;
|
||||
}
|
||||
@@ -1249,8 +1255,10 @@ PX4FMU::pwm_ioctl(file *filp, int cmd, unsigned long arg)
|
||||
case PWM_SERVO_GET_RATEGROUP(1):
|
||||
case PWM_SERVO_GET_RATEGROUP(2):
|
||||
case PWM_SERVO_GET_RATEGROUP(3):
|
||||
#if defined(BOARD_HAS_PWM) && BOARD_HAS_PWM >= 6
|
||||
#if defined(BOARD_HAS_PWM) && BOARD_HAS_PWM >= 5
|
||||
case PWM_SERVO_GET_RATEGROUP(4):
|
||||
#endif
|
||||
#if defined(BOARD_HAS_PWM) && BOARD_HAS_PWM >= 6
|
||||
case PWM_SERVO_GET_RATEGROUP(5):
|
||||
#endif
|
||||
#if defined(BOARD_HAS_PWM) && BOARD_HAS_PWM >= 8
|
||||
@@ -1677,6 +1685,9 @@ PX4FMU::fmu_new_mode(PortMode new_mode)
|
||||
/* select 4-pin PWM mode */
|
||||
servo_mode = PX4FMU::MODE_4PWM;
|
||||
#endif
|
||||
#if defined(BOARD_HAS_PWM) && BOARD_HAS_PWM == 5
|
||||
servo_mode = PX4FMU::MODE_5PWM;
|
||||
#endif
|
||||
#if defined(BOARD_HAS_PWM) && BOARD_HAS_PWM == 6
|
||||
servo_mode = PX4FMU::MODE_6PWM;
|
||||
#endif
|
||||
@@ -2109,6 +2120,9 @@ int PX4FMU::custom_command(int argc, char *argv[])
|
||||
} else if (!strcmp(verb, "mode_pwm6")) {
|
||||
new_mode = PORT_PWM6;
|
||||
|
||||
#endif
|
||||
#if defined(BOARD_HAS_PWM) && BOARD_HAS_PWM >= 5
|
||||
|
||||
} else if (!strcmp(verb, "mode_pwm5")) {
|
||||
new_mode = PORT_PWM5;
|
||||
|
||||
|
||||
@@ -2822,6 +2822,7 @@ PX4IO::ioctl(file *filep, int cmd, unsigned long arg)
|
||||
}
|
||||
|
||||
/* reboot into bootloader - arg must be PX4IO_REBOOT_BL_MAGIC */
|
||||
usleep(1);
|
||||
io_reg_set(PX4IO_PAGE_SETUP, PX4IO_P_SETUP_REBOOT_BL, arg);
|
||||
// we don't expect a reply from this operation
|
||||
ret = OK;
|
||||
|
||||
@@ -36,7 +36,7 @@
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include "chip/stm32_tim.h"
|
||||
#include "hardware/stm32_tim.h"
|
||||
|
||||
|
||||
#include "led.hpp"
|
||||
|
||||
@@ -36,7 +36,7 @@
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include "chip/stm32_tim.h"
|
||||
#include "hardware/stm32_tim.h"
|
||||
|
||||
|
||||
#include "led.hpp"
|
||||
|
||||
@@ -72,6 +72,8 @@ __BEGIN_DECLS
|
||||
__EXPORT int dataman_main(int argc, char *argv[]);
|
||||
__END_DECLS
|
||||
|
||||
static constexpr int TASK_STACK_SIZE = 1220;
|
||||
|
||||
/* Private File based Operations */
|
||||
static ssize_t _file_write(dm_item_t item, unsigned index, dm_persitence_t persistence, const void *buf,
|
||||
size_t count);
|
||||
@@ -1446,7 +1448,8 @@ start()
|
||||
px4_sem_setprotocol(&g_init_sema, SEM_PRIO_NONE);
|
||||
|
||||
/* start the worker thread with low priority for disk IO */
|
||||
if ((task = px4_task_spawn_cmd("dataman", SCHED_DEFAULT, SCHED_PRIORITY_DEFAULT - 10, 1200, task_main, nullptr)) < 0) {
|
||||
if ((task = px4_task_spawn_cmd("dataman", SCHED_DEFAULT, SCHED_PRIORITY_DEFAULT - 10, TASK_STACK_SIZE, task_main,
|
||||
nullptr)) < 0) {
|
||||
px4_sem_destroy(&g_init_sema);
|
||||
PX4_ERR("task start failed");
|
||||
return -1;
|
||||
|
||||
@@ -58,7 +58,9 @@
|
||||
|
||||
__EXPORT int bl_update_main(int argc, char *argv[]);
|
||||
|
||||
#if defined (CONFIG_STM32_STM32F4XXX) || defined (CONFIG_ARCH_CHIP_STM32F7)
|
||||
#if defined (CONFIG_STM32_STM32F4XXX) || defined (CONFIG_ARCH_CHIP_STM32F7) || \
|
||||
defined (CONFIG_ARCH_CHIP_STM32H7)
|
||||
|
||||
static int setopt(void);
|
||||
|
||||
static void print_usage(const char *reason)
|
||||
@@ -81,7 +83,8 @@ static void print_usage(const char *reason)
|
||||
int
|
||||
bl_update_main(int argc, char *argv[])
|
||||
{
|
||||
#if !(defined (CONFIG_STM32_STM32F4XXX) || defined (CONFIG_ARCH_CHIP_STM32F7))
|
||||
#if !(defined (CONFIG_STM32_STM32F4XXX) || defined (CONFIG_ARCH_CHIP_STM32F7) \
|
||||
|| defined (CONFIG_ARCH_CHIP_STM32H7))
|
||||
PX4_ERR("Not supported on this HW");
|
||||
return 1;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user