ist8308: improve configuration

- disable noise suppression filter
 - select more appropriate dynamic range
 - carefully set and clear all ODR, DR, and OSRCNTL bits
 - retry in probe multiple times
This commit is contained in:
Daniel Agar
2021-05-18 13:20:21 -04:00
parent 4acc18ca60
commit e498023d0f
3 changed files with 34 additions and 24 deletions
@@ -1,6 +1,6 @@
/**************************************************************************** /****************************************************************************
* *
* Copyright (c) 2020 PX4 Development Team. All rights reserved. * Copyright (c) 2020-2021 PX4 Development Team. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@@ -86,14 +86,20 @@ void IST8308::print_status()
int IST8308::probe() int IST8308::probe()
{ {
const uint8_t WAI = RegisterRead(Register::WAI); _retries = 2;
if (WAI != Device_ID) { for (int retry = 0; retry < 3; retry++) {
DEVICE_DEBUG("unexpected WAI 0x%02x", WAI); const uint8_t WAI = RegisterRead(Register::WAI);
return PX4_ERROR;
if (WAI == Device_ID) {
return PX4_OK;
} else {
DEVICE_DEBUG("unexpected WAI 0x%02x", WAI);
}
} }
return PX4_OK; return PX4_ERROR;
} }
void IST8308::RunImpl() void IST8308::RunImpl()
@@ -240,7 +246,7 @@ bool IST8308::Configure()
} }
// 1 Microtesla = 0.01 Gauss // 1 Microtesla = 0.01 Gauss
_px4_mag.set_scale(1.f / 6.6f * 0.01f); // 6.6 LSB/uT _px4_mag.set_scale(1.f / 13.2f * 0.01f); // 13.2 LSB/uT
return success; return success;
} }
@@ -1,6 +1,6 @@
/**************************************************************************** /****************************************************************************
* *
* Copyright (c) 2020 PX4 Development Team. All rights reserved. * Copyright (c) 2020-2021 PX4 Development Team. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@@ -103,13 +103,14 @@ private:
} _state{STATE::RESET}; } _state{STATE::RESET};
uint8_t _checked_register{0}; uint8_t _checked_register{0};
static constexpr uint8_t size_register_cfg{5}; static constexpr uint8_t size_register_cfg{6};
register_config_t _register_cfg[size_register_cfg] { register_config_t _register_cfg[size_register_cfg] {
// Register | Set bits, Clear bits // Register | Set bits, Clear bits
{ Register::ACTR, 0, ACTR_BIT::SUSPEND_EN }, { Register::ACTR, 0, ACTR_BIT::SUSPEND_EN },
{ Register::CNTL1, CNTL1_BIT::NSF_Low, 0 }, { Register::CNTL1, 0, CNTL1_BIT::NSF_DISABLE },
{ Register::CNTL2, CNTL2_BIT::MODE_ODR_50Hz, 0 }, { Register::CNTL2, CNTL2_BIT::MODE_ODR_50HZ_SET, CNTL2_BIT::MODE_ODR_50HZ_CLEAR },
{ Register::CNTL3, 0, CNTL3_BIT::SRST }, { Register::CNTL3, 0, CNTL3_BIT::SRST },
{ Register::OSRCNTL, OSRCNTL_BIT::OSR_y_32 | OSRCNTL_BIT::OSR_xz_32, 0 }, { Register::CNTL4, CNTL4_BIT::DR_200UT_SET, CNTL4_BIT::DR_200UT_CLEAR },
{ Register::OSRCNTL, OSRCNTL_BIT::OSR_Y_32_SET | OSRCNTL_BIT::OSR_XZ_32_SET, OSRCNTL_BIT::OSR_Y_32_CLEAR | OSRCNTL_BIT::OSR_XZ_32_CLEAR },
}; };
}; };
@@ -1,6 +1,6 @@
/**************************************************************************** /****************************************************************************
* *
* Copyright (c) 2020 PX4 Development Team. All rights reserved. * Copyright (c) 2020-2021 PX4 Development Team. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions * modification, are permitted provided that the following conditions
@@ -96,18 +96,14 @@ enum ACTR_BIT : uint8_t {
// CNTL1 // CNTL1
enum CNTL1_BIT : uint8_t { enum CNTL1_BIT : uint8_t {
// 6:5 NSF[1:0]: Noise Suppression Filter setting // 6:5 NSF[1:0]: Noise Suppression Filter setting
NSF_Low = Bit5, NSF_DISABLE = Bit6 | Bit5, // Disable
NSF_Middle = Bit6,
NSF_High = Bit6 | Bit5,
}; };
// CNTL2 // CNTL2
enum CNTL2_BIT : uint8_t { enum CNTL2_BIT : uint8_t {
// 4:0 MODE [4:0]: Operation mode setting // 4:0 MODE [4:0]: Operation mode setting
MODE_ODR_10Hz = Bit1, // 5’h02: Continuous Measurement Mode with ODR 10Hz MODE_ODR_50HZ_SET = Bit2 | Bit1, // 5’h06: Continuous Measurement Mode with ODR 50Hz
MODE_ODR_20Hz = Bit2, // 5’h04: Continuous Measurement Mode with ODR 20Hz MODE_ODR_50HZ_CLEAR = Bit3 | Bit0,
MODE_ODR_50Hz = Bit2 | Bit1, // 5’h06: Continuous Measurement Mode with ODR 50Hz
MODE_ODR_100Hz = Bit3, // 5’h08: Continuous Measurement Mode with ODR 100Hz
}; };
// CNTL3 // CNTL3
@@ -115,15 +111,22 @@ enum CNTL3_BIT : uint8_t {
SRST = Bit0, // Soft reset, perform the same routine as POR SRST = Bit0, // Soft reset, perform the same routine as POR
}; };
// CNTL4
enum CNTL4_BIT : uint8_t {
// DR [1:0]: Sensor Dynamic Range and Sensitivity setting
DR_200UT_SET = Bit0, // ±200 uT, Sensitivity=13.2 LSB/uT
DR_200UT_CLEAR = Bit1
};
// OSRCNTL // OSRCNTL
enum OSRCNTL_BIT : uint8_t { enum OSRCNTL_BIT : uint8_t {
// 5:3 // 5:3
OSR_y_16 = Bit5, // 3’b100: OSR=16 (ODRmax=100) (Default) OSR_Y_32_SET = Bit5 | Bit3, // 3’b101: OSR=32 (ODRmax=50)
OSR_y_32 = Bit5 | Bit3, // 3’b101: OSR=32 (ODRmax=50) OSR_Y_32_CLEAR = Bit4,
// 2:0 // 2:0
OSR_xz_16 = Bit2, // 3’b100: OSR=16 (ODRmax=100) (Default) OSR_XZ_32_SET = Bit2 | Bit0, // 3’b101: OSR=32 (ODRmax=50)
OSR_xz_32 = Bit2 | Bit0, // 3’b101: OSR=32 (ODRmax=50) OSR_XZ_32_CLEAR = Bit1,
}; };
} // namespace iSentek_IST8308 } // namespace iSentek_IST8308