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Correct last set of changes to configuration logic

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git-svn-id: https://nuttx.svn.sourceforge.net/svnroot/nuttx/trunk@4237 7fd9a85b-ad96-42d3-883c-3090e2eb8679
This commit is contained in:
patacongo
2011-12-29 12:52:15 +00:00
parent 67c0262d13
commit e136368c1f
6 changed files with 83 additions and 11 deletions
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nuttx/arch/arm/src/stm32/stm32_gpio.c
+29 -1
View File
@@ -47,6 +47,8 @@
#include <errno.h>
#include <debug.h>
#include <arch/irq.h>
#include "up_arch.h"
#include "chip.h"
@@ -202,7 +204,12 @@ static inline void stm32_gpioremap(void)
* Based on configuration within the .config file, it does:
* - Remaps positions of alternative functions.
*
* Typically called from stm32_start().
* Typically called from stm32_start().
*
* Assumptions:
* This function is called early in the initialization sequence so that
* no mutual exlusion is necessary.
*
****************************************************************************/
void stm32_gpioinit(void)
@@ -244,6 +251,7 @@ int stm32_configgpio(uint32_t cfgset)
unsigned int pin;
unsigned int pos;
unsigned int modecnf;
irqstate_t flags;
bool input;
/* Verify that this hardware supports the select GPIO port */
@@ -278,6 +286,12 @@ int stm32_configgpio(uint32_t cfgset)
input = ((cfgset & GPIO_INPUT) != 0);
/* Interrupts must be disabled from here on out so that we have mutually
* exclusive access to all of the GPIO configuration registers.
*/
flags = irqsave();
/* Decode the mode and configuration */
regval = getreg32(cr);
@@ -316,6 +330,7 @@ int stm32_configgpio(uint32_t cfgset)
{
/* Its an alternate function pin... we can return early */
irqrestore(flags);
return OK;
}
}
@@ -342,6 +357,7 @@ int stm32_configgpio(uint32_t cfgset)
{
/* Neither... we can return early */
irqrestore(flags);
return OK;
}
}
@@ -367,6 +383,8 @@ int stm32_configgpio(uint32_t cfgset)
regval = getreg32(regaddr);
regval |= (1 << pin);
putreg32(regval, regaddr);
irqrestore(flags);
return OK;
}
#endif
@@ -386,6 +404,7 @@ int stm32_configgpio(uint32_t cfgset)
unsigned int pin;
unsigned int pos;
unsigned int pinmode;
irqstate_t flags;
/* Verify that this hardware supports the select GPIO port */
@@ -427,6 +446,14 @@ int stm32_configgpio(uint32_t cfgset)
break;
}
/* Interrupts must be disabled from here on out so that we have mutually
* exclusive access to all of the GPIO configuration registers.
*/
flags = irqsave();
/* Now apply the configuration to the mode register */
regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
regval &= ~GPIO_MODER_MASK(pin);
regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin));
@@ -572,6 +599,7 @@ int stm32_configgpio(uint32_t cfgset)
stm32_gpiowrite(cfgset, value);
}
irqrestore(flags);
return OK;
}
#endif