Merge commit '0f2decb70f505b108999fcdb80e89d7aae6760ce' into nuttx-merge-0f2decb

2026-10-24 03:03:36 +08:00 · 2013-01-01 15:33:39 -08:00
parent c08135ffef 0f2decb70f
commit dc50d96b5d
594 changed files with 30116 additions and 3932 deletions
@@ -36,58 +36,90 @@
 -include $(TOPDIR)/Make.defs
 -include chip/Make.defs

-ARCH_SRCDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src
 ifeq ($(CONFIG_ARCH_CORTEXM3),y)   # Cortex-M3 is ARMv7-M
-ARCH_SUBDIR	= armv7-m
+ARCH_SUBDIR = armv7-m
 else
 ifeq ($(CONFIG_ARCH_CORTEXM4),y)   # Cortex-M4 is ARMv7E-M
-ARCH_SUBDIR	= armv7-m
+ARCH_SUBDIR = armv7-m
 else
-ARCH_SUBDIR	= arm
+ARCH_SUBDIR = arm
 endif
 endif

+ifeq ($(CONFIG_WINDOWS_NATIVE),y)
+  ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src
+  NUTTX = "$(TOPDIR)\nuttx$(EXEEXT)"
+  CFLAGS += -I$(ARCH_SRCDIR)\chip
+  CFLAGS += -I$(ARCH_SRCDIR)\common
+  CFLAGS += -I$(ARCH_SRCDIR)\$(ARCH_SUBDIR)
+  CFLAGS += -I$(TOPDIR)\sched
+else
+  ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+ifeq ($(WINTOOL),y)
+  NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}"
+  CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}"
+  CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}"
+  CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}"
+  CFLAGS += -I "${shell cygpath -w $(TOPDIR)/sched}"
+else
+  NUTTX = "$(TOPDIR)/nuttx$(EXEEXT)"
+  CFLAGS += -I$(ARCH_SRCDIR)/chip
+  CFLAGS += -I$(ARCH_SRCDIR)/common
+  CFLAGS += -I$(ARCH_SRCDIR)/$(ARCH_SUBDIR)
+  CFLAGS += -I$(TOPDIR)/sched
+endif
+endif
+
+HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT))
+
+ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS)
+AOBJS = $(ASRCS:.S=$(OBJEXT))
+
+CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS)
+COBJS = $(CSRCS:.c=$(OBJEXT))
+
+SRCS = $(ASRCS) $(CSRCS)
+OBJS = $(AOBJS) $(COBJS)
+
+LDFLAGS += $(ARCHSCRIPT)
+
+EXTRA_LIBS ?=
+EXTRA_LIBPATHS ?=
+LINKLIBS ?=
+
+ifeq ($(CONFIG_WINDOWS_NATIVE),y)
+  BOARDMAKE = $(if $(wildcard .\board\Makefile),y,)
+  LIBPATHS += -L"$(TOPDIR)\lib"
+ifeq ($(BOARDMAKE),y)
+  LIBPATHS += -L"$(TOPDIR)\arch\$(CONFIG_ARCH)\src\board"
+endif
+
+else
+  BOARDMAKE = $(if $(wildcard ./board/Makefile),y,)
+
 ifeq ($(WINTOOL),y)
-  NUTTX		= "${shell cygpath -w $(TOPDIR)/nuttx}"
-  CFLAGS	+= -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
-  		   -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
-		   -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}" \
-		   -I "${shell cygpath -w $(TOPDIR)/sched}"
-else
-  NUTTX		= $(TOPDIR)/nuttx
-  CFLAGS	+= -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common \
-		   -I$(ARCH_SRCDIR)/$(ARCH_SUBDIR) -I$(TOPDIR)/sched
+  LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/lib"}"
+ifeq ($(BOARDMAKE),y)
+  LIBPATHS += -L"${shell cygpath -w "$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"}"
 endif

-HEAD_OBJ	= $(HEAD_ASRC:.S=$(OBJEXT))
-
-ASRCS		= $(CHIP_ASRCS) $(CMN_ASRCS)
-AOBJS		= $(ASRCS:.S=$(OBJEXT))
-
-CSRCS		= $(CHIP_CSRCS) $(CMN_CSRCS)
-COBJS		= $(CSRCS:.c=$(OBJEXT))
-
-SRCS		= $(ASRCS) $(CSRCS)
-OBJS		= $(AOBJS) $(COBJS)
-
-LDFLAGS		= $(ARCHSCRIPT)
-EXTRA_LIBS	?=
-
-LINKLIBS	=
-ifeq ($(WINTOOL),y)
-  LIBPATHS	= ${shell for path in $(LINKLIBS); do dir=`dirname $(TOPDIR)/$$path`;echo "-L\"`cygpath -w $$dir`\"";done}
-  LIBPATHS	+= -L"${shell cygpath -w $(BOARDDIR)}"
 else
-  LIBPATHS	= $(addprefix -L$(TOPDIR)/,$(dir $(LINKLIBS)))
-  LIBPATHS	+= -L"$(BOARDDIR)"
+  LIBPATHS += -L"$(TOPDIR)/lib"
+ifeq ($(BOARDMAKE),y)
+  LIBPATHS += -L"$(TOPDIR)/arch/$(CONFIG_ARCH)/src/board"
+endif
+endif
 endif
-LDLIBS		= $(patsubst lib%,-l%,$(basename $(notdir $(LINKLIBS))))

-BOARDDIR	= $(TOPDIR)/arch/$(CONFIG_ARCH)/src/board
+LDLIBS = $(patsubst %.a,%,$(patsubst lib%,-l%,$(LINKLIBS)))
+ifeq ($(BOARDMAKE),y)
+  LDLIBS += -lboard
+endif

-LIBGCC		= "${shell $(CC) $(ARCHCPUFLAGS) -print-libgcc-file-name}"
+LIBGCC = "${shell "$(CC)" $(ARCHCPUFLAGS) -print-libgcc-file-name}"
+GCC_LIBDIR := ${shell dirname $(LIBGCC)}

-VPATH		= chip:common:$(ARCH_SUBDIR)
+VPATH = chip:common:$(ARCH_SUBDIR)

 all: $(HEAD_OBJ) libarch$(LIBEXT)

@@ -100,20 +132,21 @@ $(COBJS): %$(OBJEXT): %.c
 	$(call COMPILE, $<, $@)

 libarch$(LIBEXT): $(OBJS)
-	@( for obj in $(OBJS) ; do \
-		$(call ARCHIVE, $@, $${obj}); \
-	done ; )
+	$(call ARCHIVE, $@, $(OBJS))

 board/libboard$(LIBEXT):
-	@$(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" libboard$(LIBEXT) EXTRADEFINES=$(EXTRADEFINES)

-nuttx: $(HEAD_OBJ) board/libboard$(LIBEXT)
-	@echo "LD: nuttx"
-	@$(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(NUTTX)$(EXEEXT) $(HEAD_OBJ) $(EXTRA_OBJS) \
-		--start-group $(LDLIBS) -lboard $(EXTRA_LIBS) $(LIBGCC) --end-group
-	@$(NM) $(NUTTX)$(EXEEXT) | \
+nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT)
+	$(Q) echo "LD: nuttx"
+	$(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) $(EXTRA_LIBPATHS) \
+		-o $(NUTTX)$(EXEEXT) $(HEAD_OBJ) $(EXTRA_OBJS) \
+		--start-group $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) --end-group
+ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+	$(Q) $(NM) $(NUTTX)$(EXEEXT) | \
 	grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
 	sort > $(TOPDIR)/System.map
+endif

 # This is part of the top-level export target
 # Note that there may not be a head object if layout is handled
@@ -121,37 +154,38 @@ nuttx: $(HEAD_OBJ) board/libboard$(LIBEXT)

 export_head: board/libboard$(LIBEXT) $(HEAD_OBJ)
 ifneq ($(HEAD_OBJ),)
-	@if [ -d "$(EXPORT_DIR)/startup" ]; then \
+	$(Q) if [ -d "$(EXPORT_DIR)/startup" ]; then \
 		cp -f $(HEAD_OBJ) "$(EXPORT_DIR)/startup"; \
 	 else \
 		echo "$(EXPORT_DIR)/startup does not exist"; \
-		exit 1; \
-	 fi
+	exit 1; \
+	fi
 endif

 # Dependencies

 .depend: Makefile chip/Make.defs $(SRCS)
-	@if [ -e board/Makefile ]; then \
-		$(MAKE) -C board TOPDIR="$(TOPDIR)" depend ; \
-	fi
-	@$(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \
-	 $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
-	@touch $@
+ifeq ($(BOARDMAKE),y)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" depend
+endif
+	$(Q) $(MKDEP) --dep-path chip --dep-path common --dep-path $(ARCH_SUBDIR) \
+	 "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep
+	$(Q) touch $@

 depend: .depend

 clean:
-	@if [ -e board/Makefile ]; then \
-		$(MAKE) -C board TOPDIR="$(TOPDIR)" clean ; \
-	fi
-	@rm -f libarch$(LIBEXT) *~ .*.swp
+ifeq ($(BOARDMAKE),y)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" clean
+endif
+	$(call DELFILE, libarch$(LIBEXT))
 	$(call CLEAN)

 distclean: clean
-	@if [ -e board/Makefile ]; then \
-		$(MAKE) -C board TOPDIR="$(TOPDIR)" distclean ; \
-	fi
-	@rm -f Make.dep .depend
+ifeq ($(BOARDMAKE),y)
+	$(Q) $(MAKE) -C board TOPDIR="$(TOPDIR)" distclean
+endif
+	$(call DELFILE, Make.dep)
+	$(call DELFILE, .depend)

 -include Make.dep
@@ -0,0 +1,35 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+comment "ARM Configuration Options"
+
+choice
+	prompt "Toolchain Selection"
+	default ARM_TOOLCHAIN_CODESOURCERYW if HOST_WINDOWS
+	default ARM_TOOLCHAIN_GNU_EABI if !HOST_WINDOWS
+
+config ARM_TOOLCHAIN_BUILDROOT
+	bool "Buildroot (Cygwin or Linux)"
+	depends on !WINDOWS_NATIVE
+
+config ARM_TOOLCHAIN_CODESOURCERYL
+	bool "CodeSourcery GNU toolchain under Linux"
+	depends on HOST_LINUX
+
+config ARM_TOOLCHAIN_CODESOURCERYW
+	bool "CodeSourcery GNU toolchain under Windows"
+	depends on HOST_WINDOWS
+
+config ARM_TOOLCHAIN_DEVKITARM
+	bool "devkitARM GNU toolchain"
+	depends on HOST_WINDOWS
+
+config ARM_TOOLCHAIN_GNU_EABI
+	bool "Generic GNU EABI toolchain"
+	---help---
+		This option should work for any modern GNU toolchain (GCC 4.5 or newer)
+		configured for arm-none-eabi.
+
+endchoice
@@ -0,0 +1,146 @@
+############################################################################
+# arch/arm/src/armv/Toolchain.defs
+#
+#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Setup for the selected toolchain
+
+#
+# Handle old-style chip-specific toolchain names in the absence of
+# a new-style toolchain specification, force the selection of a single
+# toolchain and allow the selected toolchain to be overridden by a
+# command-line selection.
+#
+
+ifeq ($(filter y, \
+      $(CONFIG_DM320_BUILDROOT) \
+      $(CONFIG_LPC313X_BUILDROOT) \
+      $(CONFIG_LPC31_BUILDROOT) \
+      $(CONFIG_OLIMEX_LPC2378_BUILDROOT) \
+      $(CONFIG_ARM_TOOLCHAIN_BUILDROOT) \
+    ),y)
+  CONFIG_ARM_TOOLCHAIN ?= BUILDROOT
+endif
+ifeq ($(filter y, \
+      $(CONFIG_DM320_CODESOURCERYL) \
+      $(CONFIG_LPC31_CODESOURCERYL) \
+      $(CONFIG_OLIMEX_LPC2378_CODESOURCERYL) \
+      $(CONFIG_ARM_TOOLCHAIN_CODESOURCERYL) \
+    ),y)
+  CONFIG_ARM_TOOLCHAIN ?= CODESOURCERYL
+endif
+ifeq ($(filter y, \
+      $(CONFIG_DM320_CODESOURCERYW) \
+      $(CONFIG_LPC31_CODESOURCERYW) \
+      $(CONFIG_OLIMEX_LPC2378_CODESOURCERYW) \
+      $(CONFIG_ARM_TOOLCHAIN_CODESOURCERYW) \
+    ),y)
+  CONFIG_ARM_TOOLCHAIN ?= CODESOURCERYW
+endif
+ifeq ($(filter y, \
+      $(CONFIG_DM320_DEVKITARM) \
+      $(CONFIG_LPC31_DEVKITARM) \
+      $(CONFIG_OLIMEX_LPC2378_DEVKITARM) \
+      $(CONFIG_ARM_TOOLCHAIN_DEVKITARM) \
+    ),y)
+  CONFIG_ARM_TOOLCHAIN ?= DEVKITARM
+endif
+ifeq ($(filter y, \
+      $(CONFIG_ARM_TOOLCHAIN_GNU_EABI) \
+    ),y)
+  CONFIG_ARM_TOOLCHAIN ?= GNU_EABI
+endif
+
+#
+# Supported toolchains
+#
+# TODO - It's likely that all of these toolchains now support the
+#        CortexM4.  Since they are all GCC-based, we could almost
+#        certainly simplify this further.
+#
+# Each toolchain definition should set:
+#
+#  CROSSDEV         The GNU toolchain triple (command prefix)
+#  ARCROSSDEV       If required, an alternative prefix used when 
+#                   invoking ar and nm.
+#  ARCHCPUFLAGS     CPU-specific flags selecting the instruction set
+#                   FPU options, etc.
+#  MAXOPTIMIZATION  The maximum optimization level that results in
+#                   reliable code generation.
+#
+
+# NuttX buildroot under Linux or Cygwin
+
+ifeq ($(CONFIG_ARM_TOOLCHAIN),BUILDROOT)
+  CROSSDEV = arm-nuttx-elf-
+  ARCROSSDEV = arm-nuttx-elf-
+  MAXOPTIMIZATION = -Os
+endif
+
+# CodeSourcery under Linux
+
+ifeq ($(CONFIG_ARM_TOOLCHAIN),CODESOURCERYL)
+  CROSSDEV = arm-none-eabi-
+  ARCROSSDEV = arm-none-eabi-
+  MAXOPTIMIZATION = -O2
+endif
+
+# CodeSourcery under Windows
+
+ifeq ($(CONFIG_ARM_TOOLCHAIN),CODESOURCERYW)
+  CROSSDEV = arm-none-eabi-
+  ARCROSSDEV = arm-none-eabi-
+  MAXOPTIMIZATION = -O2
+  ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+    WINTOOL = y
+  endif
+endif
+
+# devkitARM under Windows
+
+ifeq ($(CONFIG_ARM_TOOLCHAIN),DEVKITARM)
+  CROSSDEV = arm-eabi-
+  ARCROSSDEV = arm-eabi-
+  ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+    WINTOOL = y
+  endif
+endif
+
+# Generic GNU EABI toolchain on OS X, Linux or any typical Posix system
+
+ifeq ($(CONFIG_ARM_TOOLCHAIN),GNU_EABI)
+  CROSSDEV = arm-none-eabi-
+  ARCROSSDEV = arm-none-eabi-
+  MAXOPTIMIZATION = -O3
+endif  
+
@@ -0,0 +1,257 @@
+/****************************************************************************
+ * arch/arm/src/arm/up_elf.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdlib.h>
+#include <elf32.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/elf.h>
+#include <nuttx/arch.h>
+#include <nuttx/binfmt/elf.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arch_checkarch
+ *
+ * Description:
+ *   Given the ELF header in 'hdr', verify that the ELF file is appropriate
+ *   for the current, configured architecture.  Every architecture that uses
+ *   the ELF loader must provide this function.
+ *
+ * Input Parameters:
+ *   hdr - The ELF header read from the ELF file.
+ *
+ * Returned Value:
+ *   True if the architecture supports this ELF file.
+ *
+ ****************************************************************************/
+
+bool arch_checkarch(FAR const Elf32_Ehdr *ehdr)
+{
+  /* Make sure it's an ARM executable */
+
+  if (ehdr->e_machine != EM_ARM)
+    {
+      bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+      return -ENOEXEC;
+    }
+
+  /* Make sure that 32-bit objects are supported */
+
+  if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
+    {
+      bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+      return -ENOEXEC;
+    }
+
+  /* Verify endian-ness */
+
+#ifdef CONFIG_ENDIAN_BIG
+  if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB)
+#else
+  if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
+#endif
+    {
+      bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+      return -ENOEXEC;
+    }
+
+  /* Make sure the entry point address is properly aligned */
+
+  if ((ehdr->e_entry & 3) != 0)
+    {
+      bdbg("Entry point is not properly aligned: %08x\n", ehdr->e_entry);
+      return -ENOEXEC
+    }
+
+  /* TODO:  Check ABI here. */
+  return OK;
+}
+
+/****************************************************************************
+ * Name: arch_relocate and arch_relocateadd
+ *
+ * Description:
+ *   Perform on architecture-specific ELF relocation.  Every architecture
+ *   that uses the ELF loader must provide this function.
+ *
+ * Input Parameters:
+ *   rel - The relocation type
+ *   sym - The ELF symbol structure containing the fully resolved value.
+ *   addr - The address that requires the relocation.
+ *
+ * Returned Value:
+ *   Zero (OK) if the relocation was successful.  Otherwise, a negated errno
+ *   value indicating the cause of the relocation failure.
+ *
+ ****************************************************************************/
+
+int arch_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
+                  uintptr_t addr)
+{
+  int32_t offset;
+
+  switch (ELF32_R_TYPE(rel->r_info))
+    {
+    case R_ARM_NONE:
+      {
+        /* No relocation */
+      }
+      break;
+
+    case R_ARM_PC24:
+    case R_ARM_CALL:
+    case R_ARM_JUMP24:
+      {
+        bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
+              ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr),
+              sym, (long)sym->st_value);
+
+        offset = (*(uint32_t*)addr & 0x00ffffff) << 2;
+        if (offset & 0x02000000)
+          {
+            offset -= 0x04000000;
+          }
+
+        offset += sym->st_value - addr;
+        if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
+          {
+            bdbg("  ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+                 ELF32_R_TYPE(rel->r_info), offset);
+
+            return -EINVAL;
+          }
+
+        offset >>= 2;
+
+        *(uint32_t*)addr &= 0xff000000;
+        *(uint32_t*)addr |= offset & 0x00ffffff;
+      }
+      break;
+
+    case R_ARM_ABS32:
+    case R_ARM_TARGET1:  /* New ABI:  TARGET1 always treated as ABS32 */
+      {
+        bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+              (long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value);
+
+        *(uint32_t*)addr += sym->st_value;
+      }
+      break;
+
+    case R_ARM_V4BX:
+      {
+        bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
+              (long)addr, (long)(*(uint32_t*)addr));
+
+         /* Preserve only Rm and the condition code */
+
+        *(uint32_t*)addr &= 0xf000000f;
+
+        /* Change instruction to 'mov pc, Rm' */
+
+        *(uint32_t*)addr |= 0x01a0f000;
+      }
+      break;
+
+    case R_ARM_PREL31:
+      {
+        bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+              (long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value);
+
+        offset           = *(uint32_t*)addr + sym->st_value - addr;
+        *(uint32_t*)addr = offset & 0x7fffffff;
+      }
+      break;
+
+    case R_ARM_MOVW_ABS_NC:
+    case R_ARM_MOVT_ABS:
+      {
+        bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+              ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr),
+              sym, (long)sym->st_value);
+
+        offset = *(uint32_t*)addr;
+        offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
+        offset = (offset ^ 0x8000) - 0x8000;
+
+        offset += sym->st_value;
+        if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
+          {
+            offset >>= 16;
+          }
+
+        *(uint32_t*)addr &= 0xfff0f000;
+        *(uint32_t*)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff);
+      }
+      break;
+
+    default:
+      bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+      return -EINVAL;
+    }
+
+  return OK;
+}
+
+int arch_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
+                     uintptr_t addr)
+{
+  bdbg("RELA relocation not supported\n");
+  return -ENOSYS;
+}
+
@@ -0,0 +1,51 @@
+#
+# For a description of the syntax of this configuration file,
+# see misc/tools/kconfig-language.txt.
+#
+
+comment "ARMV7M Configuration Options"
+
+choice
+	prompt "Toolchain Selection"
+	default ARMV7M_TOOLCHAIN_CODESOURCERYW if HOST_WINDOWS
+	default ARMV7M_TOOLCHAIN_GNU_EABI if !HOST_WINDOWS
+
+config ARMV7M_TOOLCHAIN_ATOLLIC
+	bool "Atollic Lite/Pro for Windows"
+	depends on HOST_WINDOWS
+
+config ARMV7M_TOOLCHAIN_BUILDROOT
+	bool "Buildroot (Cygwin or Linux)"
+	depends on !WINDOWS_NATIVE
+
+config ARMV7M_TOOLCHAIN_CODEREDL
+	bool "CodeRed for Linux"
+	depends on HOST_LINUX
+
+config ARMV7M_TOOLCHAIN_CODEREDW
+	bool "CodeRed for Windows"
+	depends on HOST_WINDOWS
+
+config ARMV7M_TOOLCHAIN_CODESOURCERYL
+	bool "CodeSourcery GNU toolchain under Linux"
+	depends on HOST_LINUX
+
+config ARMV7M_TOOLCHAIN_CODESOURCERYW
+	bool "CodeSourcery GNU toolchain under Windows"
+	depends on HOST_WINDOWS
+
+config ARMV7M_TOOLCHAIN_DEVKITARM
+	bool "devkitARM GNU toolchain"
+	depends on HOST_WINDOWS
+
+config ARMV7M_TOOLCHAIN_GNU_EABI
+	bool "Generic GNU EABI toolchain"
+	---help---
+		This option should work for any modern GNU toolchain (GCC 4.5 or newer)
+		configured for arm-none-eabi.
+
+config ARMV7M_TOOLCHAIN_RAISONANCE
+	bool "STMicro Raisonance for Windows"
+	depends on HOST_WINDOWS
+
+endchoice
@@ -0,0 +1,266 @@
+############################################################################
+# arch/arm/src/armv7-m/Toolchain.defs
+#
+#   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Setup for the selected toolchain
+
+#
+# Handle old-style chip-specific toolchain names in the absence of
+# a new-style toolchain specification, force the selection of a single
+# toolchain and allow the selected toolchain to be overridden by a
+# command-line selection.
+#
+
+ifeq ($(filter y, \
+      $(CONFIG_LPC43_ATOLLIC_LITE) \
+      $(CONFIG_STM32_ATOLLIC_LITE) \
+      $(CONFIG_LPC43_ATOLLIC_PRO) \
+      $(CONFIG_STM32_ATOLLIC_PRO) \
+      $(CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC) \
+    ),y)
+  CONFIG_ARMV7M_TOOLCHAIN ?= ATOLLIC
+endif
+ifeq ($(filter y, \
+      $(CONFIG_KINETIS_BUILDROOT) \
+      $(CONFIG_LM3S_BUILDROOT) \
+      $(CONFIG_LPC17_BUILDROOT) \
+      $(CONFIG_LPC43_BUILDROOT) \
+      $(CONFIG_SAM3U_BUILDROOT) \
+      $(CONFIG_STM32_BUILDROOT) \
+      $(CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT) \
+    ),y)
+  CONFIG_ARMV7M_TOOLCHAIN ?= BUILDROOT
+endif
+ifeq ($(filter y, \
+      $(CONFIG_LPC17_CODEREDL) \
+      $(CONFIG_ARMV7M_TOOLCHAIN_CODEREDL) \
+    ),y)
+  CONFIG_ARMV7M_TOOLCHAIN ?= CODEREDL
+endif
+ifeq ($(filter y, \
+      $(CONFIG_LPC17_CODEREDW) \
+      $(CONFIG_LPC43_CODEREDW) \
+      $(CONFIG_ARMV7M_TOOLCHAIN_CODEREDW) \
+    ),y)
+  CONFIG_ARMV7M_TOOLCHAIN ?= CODEREDW
+endif
+ifeq ($(filter y, \
+      $(CONFIG_KINETIS_CODESOURCERYL) \
+      $(CONFIG_LM3S_CODESOURCERYL) \
+      $(CONFIG_LPC17_CODESOURCERYL) \
+      $(CONFIG_LPC43_CODESOURCERYL) \
+      $(CONFIG_SAM3U_CODESOURCERYL) \
+      $(CONFIG_STM32_CODESOURCERYL) \
+      $(CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL) \
+    ),y)
+  CONFIG_ARMV7M_TOOLCHAIN ?= CODESOURCERYL
+endif
+ifeq ($(filter y, \
+      $(CONFIG_KINETIS_CODESOURCERYW) \
+      $(CONFIG_LM3S_CODESOURCERYW) \
+      $(CONFIG_LPC17_CODESOURCERYW) \
+      $(CONFIG_LPC43_CODESOURCERYW) \
+      $(CONFIG_SAM3U_CODESOURCERYW) \
+      $(CONFIG_STM32_CODESOURCERYW) \
+      $(CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW) \
+    ),y)
+  CONFIG_ARMV7M_TOOLCHAIN ?= CODESOURCERYW
+endif
+ifeq ($(filter y, \
+      $(CONFIG_KINETIS_DEVKITARM) \
+      $(CONFIG_LM3S_DEVKITARM) \
+      $(CONFIG_LPC17_DEVKITARM) \
+      $(CONFIG_LPC43_DEVKITARM) \
+      $(CONFIG_SAM3U_DEVKITARM) \
+      $(CONFIG_STM32_DEVKITARM) \
+      $(CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM) \
+    ),y)
+  CONFIG_ARMV7M_TOOLCHAIN ?= DEVKITARM
+endif
+ifeq ($(filter y, \
+      $(CONFIG_ARMV7M_TOOLCHAIN_GNU_EABI) \
+    ),y)
+  CONFIG_ARMV7M_TOOLCHAIN ?= GNU_EABI
+endif
+ifeq ($(filter y, \
+      $(CONFIG_STM32_RAISONANCE) \
+      $(CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE) \
+    ),y)
+  CONFIG_ARMV7M_TOOLCHAIN ?= RAISONANCE
+endif
+
+#
+# Supported toolchains
+#
+# TODO - It's likely that all of these toolchains now support the
+#        CortexM4.  Since they are all GCC-based, we could almost
+#        certainly simplify this further.
+#
+# Each toolchain definition should set:
+#
+#  CROSSDEV         The GNU toolchain triple (command prefix)
+#  ARCROSSDEV       If required, an alternative prefix used when 
+#                   invoking ar and nm.
+#  ARCHCPUFLAGS     CPU-specific flags selecting the instruction set
+#                   FPU options, etc.
+#  MAXOPTIMIZATION  The maximum optimization level that results in
+#                   reliable code generation.
+#
+
+# Atollic toolchain under Windows
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),ATOLLIC)
+  CROSSDEV = arm-atollic-eabi-
+  ARCROSSDEV = arm-atollic-eabi-
+  ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+    WINTOOL = y
+  endif
+  ifeq ($(CONFIG_ARCH_CORTEXM4),y)
+    ifeq ($(CONFIG_ARCH_FPU),y)
+      ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+    else
+      ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfloat-abi=soft
+    endif
+  else ifeq ($(CONFIG_ARCH_CORTEXM3),y)
+    ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+  endif
+endif
+
+# NuttX buildroot under Linux or Cygwin
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),BUILDROOT)
+  # OABI
+  # CROSSDEV = arm-nuttx-elf-
+  # ARCROSSDEV = arm-nuttx-elf-
+  # ARCHCPUFLAGS = -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
+  # EABI
+  CROSSDEV = arm-nuttx-eabi-
+  ARCROSSDEV = arm-nuttx-eabi-
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+  MAXOPTIMIZATION = -Os
+endif
+
+# Code Red RedSuite under Linux
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODEREDL)
+  CROSSDEV = arm-none-eabi-
+  ARCROSSDEV = arm-none-eabi-
+  ifeq ($(CONFIG_ARCH_CORTEXM4),y)
+    ifeq ($(CONFIG_ARCH_FPU),y)
+      ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+    else
+      ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfloat-abi=soft
+    endif
+  else ifeq ($(CONFIG_ARCH_CORTEXM3),y)
+    ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+  endif
+endif
+
+# Code Red RedSuite under Windows
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODEREDW)
+  CROSSDEV = arm-none-eabi-
+  ARCROSSDEV = arm-none-eabi-
+  ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+    WINTOOL = y
+  endif
+  ifeq ($(CONFIG_ARCH_CORTEXM4),y)
+    ifeq ($(CONFIG_ARCH_FPU),y)
+      ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+    else
+      ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfloat-abi=soft
+    endif
+  else ifeq ($(CONFIG_ARCH_CORTEXM3),y)
+    ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+  endif
+endif
+
+# CodeSourcery under Linux
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODESOURCERYL)
+  CROSSDEV = arm-none-eabi-
+  ARCROSSDEV = arm-none-eabi-
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+  MAXOPTIMIZATION = -O2
+endif
+
+# CodeSourcery under Windows
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),CODESOURCERYW)
+  CROSSDEV = arm-none-eabi-
+  ARCROSSDEV = arm-none-eabi-
+  ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+    WINTOOL = y
+  endif
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+
+# devkitARM under Windows
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),DEVKITARM)
+  CROSSDEV = arm-eabi-
+  ARCROSSDEV = arm-eabi-
+  ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+    WINTOOL = y
+  endif
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
+
+# Generic GNU EABI toolchain on OS X, Linux or any typical Posix system
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),GNU_EABI)
+  CROSSDEV = arm-none-eabi-
+  ARCROSSDEV = arm-none-eabi-
+  MAXOPTIMIZATION = -O3
+  ifeq ($(CONFIG_ARCH_CORTEXM4),y)
+    ifeq ($(CONFIG_ARCH_FPU),y)
+      ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfpu=fpv4-sp-d16 -mfloat-abi=hard
+    else
+      ARCHCPUFLAGS = -mcpu=cortex-m4 -mthumb -march=armv7e-m -mfloat-abi=soft
+    endif
+  else ifeq ($(CONFIG_ARCH_CORTEXM3),y)
+    ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+  endif
+endif  
+
+# Raisonance RIDE7 under Windows
+
+ifeq ($(CONFIG_ARMV7M_TOOLCHAIN),RAISONANCE)
+  CROSSDEV = arm-none-eabi-
+  ARCROSSDEV = arm-none-eabi-
+  ifneq ($(CONFIG_WINDOWS_NATIVE),y)
+    WINTOOL = y
+  endif
+  ARCHCPUFLAGS = -mcpu=cortex-m3 -mthumb -mfloat-abi=soft
+endif
@@ -0,0 +1,450 @@
+/****************************************************************************
+ * arch/arm/src/armv7-m/up_elf.c
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdlib.h>
+#include <elf32.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/elf.h>
+#include <nuttx/arch.h>
+#include <nuttx/binfmt/elf.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arch_checkarch
+ *
+ * Description:
+ *   Given the ELF header in 'hdr', verify that the ELF file is appropriate
+ *   for the current, configured architecture.  Every architecture that uses
+ *   the ELF loader must provide this function.
+ *
+ * Input Parameters:
+ *   hdr - The ELF header read from the ELF file.
+ *
+ * Returned Value:
+ *   True if the architecture supports this ELF file.
+ *
+ ****************************************************************************/
+
+bool arch_checkarch(FAR const Elf32_Ehdr *ehdr)
+{
+  /* Make sure it's an ARM executable */
+
+  if (ehdr->e_machine != EM_ARM)
+    {
+      bdbg("Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+      return -ENOEXEC;
+    }
+
+  /* Make sure that 32-bit objects are supported */
+
+  if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
+    {
+      bdbg("Need 32-bit objects: e_ident[EI_CLASS]=%02x\n", ehdr->e_ident[EI_CLASS]);
+      return -ENOEXEC;
+    }
+
+  /* Verify endian-ness */
+
+#ifdef CONFIG_ENDIAN_BIG
+  if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB)
+#else
+  if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
+#endif
+    {
+      bdbg("Wrong endian-ness: e_ident[EI_DATA]=%02x\n", ehdr->e_ident[EI_DATA]);
+      return -ENOEXEC;
+    }
+
+  /* TODO:  Check ABI here. */
+  return OK;
+}
+
+/****************************************************************************
+ * Name: arch_relocate and arch_relocateadd
+ *
+ * Description:
+ *   Perform on architecture-specific ELF relocation.  Every architecture
+ *   that uses the ELF loader must provide this function.
+ *
+ * Input Parameters:
+ *   rel - The relocation type
+ *   sym - The ELF symbol structure containing the fully resolved value.
+ *   addr - The address that requires the relocation.
+ *
+ * Returned Value:
+ *   Zero (OK) if the relocation was successful.  Otherwise, a negated errno
+ *   value indicating the cause of the relocation failure.
+ *
+ ****************************************************************************/
+
+int arch_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
+                  uintptr_t addr)
+{
+  int32_t offset;
+  uint32_t upper_insn;
+  uint32_t lower_insn;
+
+  switch (ELF32_R_TYPE(rel->r_info))
+    {
+    case R_ARM_NONE:
+      {
+        /* No relocation */
+      }
+      break;
+
+    case R_ARM_PC24:
+    case R_ARM_CALL:
+    case R_ARM_JUMP24:
+      {
+        bvdbg("Performing PC24 [%d] link at addr %08lx [%08lx] to sym '%s' st_value=%08lx\n",
+              ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr),
+              sym, (long)sym->st_value);
+
+        offset = (*(uint32_t*)addr & 0x00ffffff) << 2;
+        if (offset & 0x02000000)
+          {
+            offset -= 0x04000000;
+          }
+
+        offset += sym->st_value - addr;
+        if (offset & 3 || offset <= (int32_t) 0xfe000000 || offset >= (int32_t) 0x02000000)
+          {
+            bdbg("  ERROR: PC24 [%d] relocation out of range, offset=%08lx\n",
+                 ELF32_R_TYPE(rel->r_info), offset);
+
+            return -EINVAL;
+          }
+
+        offset >>= 2;
+
+        *(uint32_t*)addr &= 0xff000000;
+        *(uint32_t*)addr |= offset & 0x00ffffff;
+      }
+      break;
+
+    case R_ARM_ABS32:
+    case R_ARM_TARGET1:  /* New ABI:  TARGET1 always treated as ABS32 */
+      {
+        bvdbg("Performing ABS32 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+              (long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value);
+
+        *(uint32_t*)addr += sym->st_value;
+      }
+      break;
+
+    case R_ARM_THM_CALL:
+    case R_ARM_THM_JUMP24:
+      {
+        uint32_t S;
+        uint32_t J1;
+        uint32_t J2;
+
+        /* Thumb BL and B.W instructions. Encoding:
+         *
+         * upper_insn:
+         *
+         *  1   1   1   1   1   1
+         *  5   4   3   2   1   0   9   8   7   6   5   4   3   2   1   0
+         * +----------+---+-------------------------------+--------------+
+         * |1   1   1 |OP1|     OP2                       |              | 32-Bit Instructions
+         * +----------+---+--+-----+----------------------+--------------+
+         * |1   1   1 | 1   0|  S  |              imm10                  | BL Instruction
+         * +----------+------+-----+-------------------------------------+
+         *
+         * lower_insn:
+         *
+         *  1   1   1   1   1   1
+         *  5   4   3   2   1   0   9   8   7   6   5   4   3   2   1   0
+         * +---+---------------------------------------------------------+
+         * |OP |                                                         | 32-Bit Instructions
+         * +---+--+---+---+---+------------------------------------------+
+         * |1   1 |J1 | 1 |J2 |                 imm11                    | BL Instruction
+         * +------+---+---+---+------------------------------------------+
+         *
+         * The branch target is encoded in these bits:
+         *
+         *   S     = upper_insn[10]
+         *   imm10 = upper_insn[0:9]
+         *   imm11 = lower_insn[0:10]
+         *   J1    = lower_insn[13]
+         *   J2    = lower_insn[11]
+         */
+
+        upper_insn = (uint32_t)(*(uint16_t*)addr);
+        lower_insn = (uint32_t)(*(uint16_t*)(addr + 2));
+
+        bvdbg("Performing THM_JUMP24 [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
+              ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
+              sym, (long)sym->st_value);
+
+        /* Extract the 25-bit offset from the 32-bit instruction:
+         *
+         *   offset[24]    = S
+         *   offset[23]    = ~(J1 ^ S)
+         *   offset[22]    = ~(J2 ^ S)]
+         *   offset[12:21] = imm10
+         *   offset[1:11]  = imm11
+         *   offset[0]     = 0
+         */
+
+        S   = (upper_insn >> 10) & 1;
+        J1  = (lower_insn >> 13) & 1;
+        J2  = (lower_insn >> 11) & 1;
+
+        offset = (S << 24) |                       /* S -   > offset[24] */
+                 ((~(J1 ^ S) & 1) << 23) |         /* J1    -> offset[23] */
+                 ((~(J2 ^ S) & 1) << 22) |         /* J2    -> offset[22] */
+                 ((upper_insn & 0x03ff) << 12) |   /* imm10 -> offset[12:21] */
+                 ((lower_insn & 0x07ff) << 1);     /* imm11 -> offset[1:11] */
+                                                   /* 0     -> offset[0] */
+
+        /* Sign extend */
+
+        if (offset & 0x01000000)
+          {
+            offset -= 0x02000000;
+          }
+
+        /* And perform the relocation */
+
+        bvdbg("  S=%d J1=%d J2=%d offset=%08lx branch target=%08lx\n",
+              S, J1, J2, (long)offset, offset + sym->st_value - addr);
+
+        offset += sym->st_value - addr;
+
+        /* Is this a function symbol?  If so, then the branch target must be
+         * an odd Thumb address
+         */
+
+        if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0)
+          {
+            bdbg("  ERROR: JUMP24 [%d] requires odd offset, offset=%08lx\n",
+                 ELF32_R_TYPE(rel->r_info), offset);
+
+            return -EINVAL;
+          }
+
+        /* Check the range of the offset */
+
+        if (offset <= (int32_t)0xff000000 || offset >= (int32_t)0x01000000)
+          {
+            bdbg("  ERROR: JUMP24 [%d] relocation out of range, branch taget=%08lx\n",
+                 ELF32_R_TYPE(rel->r_info), offset);
+
+            return -EINVAL;
+          }
+
+        /* Now, reconstruct the 32-bit instruction using the new, relocated
+         * branch target.
+         */
+
+        S  = (offset >> 24) & 1;
+        J1 = S ^ (~(offset >> 23) & 1);
+        J2 = S ^ (~(offset >> 22) & 1);
+ 
+        upper_insn = ((upper_insn & 0xf800) | (S << 10) | ((offset >> 12) & 0x03ff));
+        *(uint16_t*)addr = (uint16_t)upper_insn;
+
+        lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) | ((offset >> 1) & 0x07ff));
+        *(uint16_t*)(addr + 2) = (uint16_t)lower_insn;
+
+        bvdbg("  S=%d J1=%d J2=%d insn [%04x %04x]\n",
+              S, J1, J2, (int)upper_insn, (int)lower_insn);
+      }
+      break;
+
+    case R_ARM_V4BX:
+      {
+        bvdbg("Performing V4BX link at addr=%08lx [%08lx]\n",
+              (long)addr, (long)(*(uint32_t*)addr));
+
+         /* Preserve only Rm and the condition code */
+
+        *(uint32_t*)addr &= 0xf000000f;
+
+        /* Change instruction to 'mov pc, Rm' */
+
+        *(uint32_t*)addr |= 0x01a0f000;
+      }
+      break;
+
+    case R_ARM_PREL31:
+      {
+        bvdbg("Performing PREL31 link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+              (long)addr, (long)(*(uint32_t*)addr), sym, (long)sym->st_value);
+
+        offset           = *(uint32_t*)addr + sym->st_value - addr;
+        *(uint32_t*)addr = offset & 0x7fffffff;
+      }
+      break;
+
+    case R_ARM_MOVW_ABS_NC:
+    case R_ARM_MOVT_ABS:
+      {
+        bvdbg("Performing MOVx_ABS [%d] link at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+              ELF32_R_TYPE(rel->r_info), (long)addr, (long)(*(uint32_t*)addr),
+              sym, (long)sym->st_value);
+
+        offset = *(uint32_t*)addr;
+        offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
+        offset = (offset ^ 0x8000) - 0x8000;
+
+        offset += sym->st_value;
+        if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
+          {
+            offset >>= 16;
+          }
+
+        *(uint32_t*)addr &= 0xfff0f000;
+        *(uint32_t*)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff);
+      }
+      break;
+
+    case R_ARM_THM_MOVW_ABS_NC:
+    case R_ARM_THM_MOVT_ABS:
+      {
+        /* Thumb BL and B.W instructions. Encoding:
+         *
+         * upper_insn:
+         *
+         *  1   1   1   1   1   1
+         *  5   4   3   2   1   0   9   8   7   6   5   4   3   2   1   0
+         * +----------+---+-------------------------------+--------------+
+         * |1   1   1 |OP1|     OP2                       |              | 32-Bit Instructions
+         * +----------+---+--+-----+----------------------+--------------+
+         * |1   1   1 | 1   0|  i  | 1  0   1   1   0   0 |    imm4      | MOVT Instruction
+         * +----------+------+-----+----------------------+--------------+
+         *
+         * lower_insn:
+         *
+         *  1   1   1   1   1   1
+         *  5   4   3   2   1   0   9   8   7   6   5   4   3   2   1   0
+         * +---+---------------------------------------------------------+
+         * |OP |                                                         | 32-Bit Instructions
+         * +---+----------+--------------+-------------------------------+
+         * |0  |   imm3   |      Rd      |            imm8               | MOVT Instruction
+         * +---+----------+--------------+-------------------------------+
+         *
+         * The 16-bit immediate value is encoded in these bits:
+         *
+         *   i    = imm16[11]    = upper_insn[10]
+         *   imm4 = imm16[12:15] = upper_insn[3:0]
+         *   imm3 = imm16[8:10]  = lower_insn[14:12]
+         *   imm8 = imm16[0:7]   = lower_insn[7:0]
+         */
+
+        upper_insn = (uint32_t)(*(uint16_t*)addr);
+        lower_insn = (uint32_t)(*(uint16_t*)(addr + 2));
+
+        bvdbg("Performing THM_MOVx [%d] link at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
+              ELF32_R_TYPE(rel->r_info), (long)addr, (int)upper_insn, (int)lower_insn,
+              sym, (long)sym->st_value);
+
+        /* Extract the 16-bit offset from the 32-bit instruction */
+
+        offset = ((upper_insn & 0x000f) << 12) | /* imm4 -> imm16[8:10] */
+                 ((upper_insn & 0x0400) << 1) |  /* i    -> imm16[11] */
+                 ((lower_insn & 0x7000) >> 4) |  /* imm3 -> imm16[8:10] */
+                  (lower_insn & 0x00ff);         /* imm8 -> imm16[0:7] */
+
+        /* Sign extend */
+
+        offset = (offset ^ 0x8000) - 0x8000;
+
+        /* And perform the relocation */
+
+        bvdbg("  offset=%08lx branch target=%08lx\n",
+              (long)offset, offset + sym->st_value);
+
+        offset += sym->st_value;
+
+        /* Update the immediate value in the instruction.  For MOVW we want the bottom
+         * 16-bits; for MOVT we want the top 16-bits.
+         */
+
+        if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
+          {
+            offset >>= 16;
+          }
+
+        upper_insn = ((upper_insn & 0xfbf0) | ((offset & 0xf000) >> 12) | ((offset & 0x0800) >> 1));
+        *(uint16_t*)addr = (uint16_t)upper_insn;
+
+        lower_insn = ((lower_insn & 0x8f00) | ((offset & 0x0700) << 4) | (offset & 0x00ff));
+        *(uint16_t*)(addr + 2) = (uint16_t)lower_insn;
+
+        bvdbg("  insn [%04x %04x]\n",
+             (int)upper_insn, (int)lower_insn);
+      }
+      break;
+
+    default:
+      bdbg("Unsupported relocation: %d\n", ELF32_R_TYPE(rel->r_info));
+      return -EINVAL;
+    }
+
+  return OK;
+}
+
+int arch_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
+                     uintptr_t addr)
+{
+  bdbg("RELA relocation not supported\n");
+  return -ENOSYS;
+}
+
@@ -134,9 +134,9 @@ exception_common:

 #if CONFIG_ARCH_INTERRUPTSTACK > 3
 	ldr		sp, =g_intstackbase
-	push	r1						/* Save the MSP on the interrupt stack */
+	push	{r1}					/* Save the MSP on the interrupt stack */
 	bl		up_doirq				/* R0=IRQ, R1=register save area on stack */
-	pop		r1						/* Recover R1=main stack pointer */
+	pop		{r1}					/* Recover R1=main stack pointer */
 #else
 	msr	 msp, r1					/* We are using the main stack pointer */
 	bl		up_doirq				/* R0=IRQ, R1=register save area on stack */
@@ -57,9 +57,7 @@

 /* Debug output from this file may interfere with context switching! */

-#undef DEBUG_HARDFAULTS         /* Define to debug hard faults */
-
-#ifdef DEBUG_HARDFAULTS
+#ifdef CONFIG_DEBUG_HARDFAULT
 # define hfdbg(format, arg...) lldbg(format, ##arg)
 #else
 # define hfdbg(x...)
@@ -0,0 +1,416 @@
+/************************************************************************************
+ * nuttx/arch/arm/src/armv7-m/up_memcpy.S
+ *
+ * armv7m-optimised memcpy, contributed by Mike Smith.  Apparently in the public
+ * domain and is re-released here under the modified BSD license:
+ *
+ * Obtained via a posting on the Stellaris forum:
+ *  http://e2e.ti.com/support/microcontrollers/\
+ *       stellaris_arm_cortex-m3_microcontroller/f/473/t/44360.aspx
+ *
+ * Posted by rocksoft on Jul 24, 2008 10:19 AM
+ *
+ *   Hi,
+ *
+ *   I recently finished a "memcpy" replacement and thought it might be useful for
+ *   others...
+ *
+ *   I've put some instructions and the code here:
+ *
+ *   http://www.rock-software.net/downloads/memcpy/
+ *
+ *   Hope it works for you as well as it did for me.
+ *
+ *   Liam.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Symbols
+ ************************************************************************************/
+
+	.global		memcpy
+
+	.syntax		unified
+	.thumb
+	.cpu		cortex-m3
+	.file		"up_memcpy.S"
+
+/************************************************************************************
+ * .text
+ ************************************************************************************/
+
+	.text
+
+/************************************************************************************
+ * Private Constant Data
+ ************************************************************************************/
+
+/* We have 16 possible alignment combinations of src and dst, this jump table
+ * directs the copy operation
+ *
+ * Bits:  Src=00, Dst=00 - Long to Long copy
+ * Bits:  Src=00, Dst=01 - Long to Byte before half word
+ * Bits:  Src=00, Dst=10 - Long to Half word
+ * Bits:  Src=00, Dst=11 - Long to Byte before long word
+ * Bits:  Src=01, Dst=00 - Byte before half word to long
+ * Bits:  Src=01, Dst=01 - Byte before half word to byte before half word -
+ *                         Same alignment
+ * Bits:  Src=01, Dst=10 - Byte before half word to half word
+ * Bits:  Src=01, Dst=11 - Byte before half word to byte before long word
+ * Bits:  Src=10, Dst=00 - Half word to long word
+ * Bits:  Src=10, Dst=01 - Half word to byte before half word
+ * Bits:  Src=10, Dst=10 - Half word to half word - Same Alignment
+ * Bits:  Src=10, Dst=11 - Half word to byte before long word
+ * Bits:  Src=11, Dst=00 - Byte before long word to long word
+ * Bits:  Src=11, Dst=01 - Byte before long word to byte before half word
+ * Bits:  Src=11, Dst=11 - Byte before long word to half word
+ * Bits:  Src=11, Dst=11 - Byte before long word to Byte before long word -
+ *                         Same alignment
+ */
+
+MEM_DataCopyTable:
+	.byte	(MEM_DataCopy0 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy1 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy2 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy3 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy4 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy5 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy6 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy7 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy8 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy9 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy10 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy11 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy12 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy13 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy14 - MEM_DataCopyJump) >> 1
+	.byte	(MEM_DataCopy15 - MEM_DataCopyJump) >> 1
+
+	.align 2
+
+MEM_LongCopyTable:
+	.byte	(MEM_LongCopyEnd - MEM_LongCopyJump) >> 1	/* 0 bytes left */
+	.byte	0					/* 4 bytes left */
+	.byte	(1 * 10) >> 1		/* 8 bytes left */
+	.byte	(2 * 10) >> 1		/* 12 bytes left */
+	.byte	(3 * 10) >> 1		/* 16 bytes left */
+	.byte	(4 * 10) >> 1		/* 20 bytes left */
+	.byte	(5 * 10) >> 1		/* 24 bytes left */
+	.byte	(6 * 10) >> 1		/* 28 bytes left */
+	.byte	(7 * 10) >> 1		/* 32 bytes left */
+	.byte	(8 * 10) >> 1		/* 36 bytes left */
+
+	.align 2
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+/************************************************************************************
+ * Name: memcpy
+ *
+ * Description:
+ *   Optimised "general" copy routine
+ *
+ * Input Parameters:
+ *   r0 = destination, r1 = source, r2 = length
+ *
+ ************************************************************************************/
+
+	.thumb_func
+memcpy:
+	push	{r14}
+
+	/* This allows the inner workings to "assume" a minimum amount of bytes */
+	/* Quickly check for very short copies */
+
+	cmp		r2, #4
+	blt		MEM_DataCopyBytes
+
+	and		r14, r0, #3		 		/* Get destination alignment bits */
+	bfi		r14, r1, #2, #2	 		/* Get source alignment bits */
+	ldr		r3, =MEM_DataCopyTable	/* Jump table base */
+	tbb		[r3, r14]		   		/* Perform jump on src/dst alignment bits */
+MEM_DataCopyJump:
+
+	.align 4
+
+/* Bits:  Src=01, Dst=01 - Byte before half word to byte before half word - Same alignment
+ * 3 bytes to read for long word aligning
+ */
+
+MEM_DataCopy5:
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x01
+
+/* Bits:  Src=10, Dst=10 - Half word to half word - Same Alignment
+ * 2 bytes to read for long word aligning
+ */
+
+MEM_DataCopy10:
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x01
+
+/* Bits:  Src=11, Dst=11 - Byte before long word to Byte before long word - Same alignment
+ * 1 bytes to read for long word aligning
+ */
+
+MEM_DataCopy15:
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x01
+
+/* Bits:  Src=00, Dst=00 - Long to Long copy */
+
+MEM_DataCopy0:
+	/* Save regs that may be used by memcpy */
+
+	push	{r4-r12}
+
+	/* Check for short word-aligned copy */
+
+	cmp		r2, #0x28
+	blt		MEM_DataCopy0_2
+
+	/* Bulk copy loop */
+
+MEM_DataCopy0_1:
+	ldmia	r1!, {r3-r12}
+	stmia	r0!, {r3-r12}
+	sub		r2, r2, #0x28
+	cmp		r2, #0x28
+	bge		MEM_DataCopy0_1
+
+	/* Copy remaining long words */
+
+MEM_DataCopy0_2:
+	/* Copy remaining long words */
+
+	ldr		r14, =MEM_LongCopyTable
+	lsr		r11, r2, #0x02
+	tbb		[r14, r11]
+
+	/* longword copy branch table anchor */
+
+MEM_LongCopyJump:
+	ldr.w	r3, [r1], #0x04		/* 4 bytes remain */
+	str.w	r3, [r0], #0x04
+	b		MEM_LongCopyEnd
+	ldmia.w	r1!, {r3-r4}		/* 8 bytes remain */
+	stmia.w	r0!, {r3-r4}
+	b		MEM_LongCopyEnd
+	ldmia.w	r1!, {r3-r5}		/* 12 bytes remain */
+	stmia.w	r0!, {r3-r5}
+	b		MEM_LongCopyEnd
+	ldmia.w	r1!, {r3-r6}		/* 16 bytes remain */
+	stmia.w	r0!, {r3-r6}
+	b		MEM_LongCopyEnd
+	ldmia.w	r1!, {r3-r7}		/* 20 bytes remain */
+	stmia.w	r0!, {r3-r7}
+	b		MEM_LongCopyEnd
+	ldmia.w	r1!, {r3-r8}		/* 24 bytes remain */
+	stmia.w	r0!, {r3-r8}
+	b		MEM_LongCopyEnd
+	ldmia.w	r1!, {r3-r9}		/* 28 bytes remain */
+	stmia.w	r0!, {r3-r9}
+	b		MEM_LongCopyEnd
+	ldmia.w	r1!, {r3-r10}		/* 32 bytes remain */
+	stmia.w	r0!, {r3-r10}
+	b		MEM_LongCopyEnd
+	ldmia.w	r1!, {r3-r11}		/* 36 bytes remain */
+	stmia.w	r0!, {r3-r11}
+
+MEM_LongCopyEnd:
+	pop		{r4-r12}
+	and		r2, r2, #0x03		/* All the longs have been copied */
+
+	/* Deal with up to 3 remaining bytes */
+
+MEM_DataCopyBytes:
+	/* Deal with up to 3 remaining bytes */
+
+	cmp		r2, #0x00
+	it		eq
+	popeq	{pc}
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	subs	r2, r2, #0x01
+	it		eq
+	popeq	{pc}
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	subs	r2, r2, #0x01
+	it		eq
+	popeq	{pc}
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	pop		{pc}
+
+ .align 4
+
+/* Bits:  Src=01, Dst=11 - Byte before half word to byte before long word
+ * 3 bytes to read for long word aligning the source
+ */
+
+MEM_DataCopy7:
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x01
+
+/* Bits:  Src=10, Dst=00 - Half word to long word
+ * 2 bytes to read for long word aligning the source
+ */
+
+MEM_DataCopy8:
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x01
+
+/* Bits:  Src=11, Dst=01 - Byte before long word to byte before half word
+ * 1 byte to read for long word aligning the source
+ */
+
+MEM_DataCopy13:
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x01
+
+/* Bits:  Src=00, Dst=10 - Long to Half word */
+
+MEM_DataCopy2:
+	cmp		r2, #0x28
+	blt		MEM_DataCopy2_1
+
+	/* Save regs */
+
+	push	{r4-r12}
+
+	/* Bulk copy loop */
+
+MEM_DataCopy2_2:
+	ldmia	r1!, {r3-r12}
+
+	strh	r3, [r0], #0x02
+
+	lsr		r3, r3, #0x10
+	bfi		r3, r4, #0x10, #0x10
+	lsr		r4, r4, #0x10
+	bfi		r4, r5, #0x10, #0x10
+	lsr		r5, r5, #0x10
+	bfi		r5, r6, #0x10, #0x10
+	lsr		r6, r6, #0x10
+	bfi		r6, r7, #0x10, #0x10
+	lsr		r7, r7, #0x10
+	bfi		r7, r8, #0x10, #0x10
+	lsr		r8, r8, #0x10
+	bfi		r8, r9, #0x10, #0x10
+	lsr		r9, r9, #0x10
+	bfi		r9, r10, #0x10, #0x10
+	lsr		r10, r10, #0x10
+	bfi		r10, r11, #0x10, #0x10
+	lsr		r11, r11, #0x10
+	bfi		r11, r12, #0x10, #0x10
+	stmia	r0!, {r3-r11}
+	lsr		r12, r12, #0x10
+	strh	r12, [r0], #0x02
+
+	sub		r2, r2, #0x28
+	cmp		r2, #0x28
+	bge		MEM_DataCopy2_2
+	pop		{r4-r12}
+
+MEM_DataCopy2_1: /* Read longs and write 2 x half words */
+	cmp		r2, #4
+	blt		MEM_DataCopyBytes
+	ldr		r3, [r1], #0x04
+	strh	r3, [r0], #0x02
+	lsr		r3, r3, #0x10
+	strh	r3, [r0], #0x02
+	sub		r2, r2, #0x04
+	b		MEM_DataCopy2
+
+/* Bits:  Src=01, Dst=00 - Byte before half word to long
+ * Bits:  Src=01, Dst=10 - Byte before half word to half word
+ * 3 bytes to read for long word aligning the source
+ */
+
+MEM_DataCopy4:
+MEM_DataCopy6:
+	/* Read B and write B */
+
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x01
+
+/* Bits:  Src=10, Dst=01 - Half word to byte before half word
+ * Bits:  Src=10, Dst=11 - Half word to byte before long word
+ * 2 bytes to read for long word aligning the source
+ */
+
+MEM_DataCopy9:
+MEM_DataCopy11:
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x01
+
+/* Bits:  Src=11, Dst=00 -chm Byte before long word to long word
+ * Bits:  Src=11, Dst=11 - Byte before long word to half word
+ * 1 byte to read for long word aligning the source
+ */
+
+MEM_DataCopy12:
+MEM_DataCopy14:
+	/* Read B and write B */
+
+	ldrb	r3, [r1], #0x01
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x01
+
+/* Bits:  Src=00, Dst=01 - Long to Byte before half word
+ * Bits:  Src=00, Dst=11 - Long to Byte before long word
+ */
+
+MEM_DataCopy1: /* Read longs, write B->H->B */
+MEM_DataCopy3:
+	cmp		r2, #4
+	blt		MEM_DataCopyBytes
+	ldr		r3, [r1], #0x04
+	strb	r3, [r0], #0x01
+	lsr		r3, r3, #0x08
+	strh	r3, [r0], #0x02
+	lsr		r3, r3, #0x10
+	strb	r3, [r0], #0x01
+	sub		r2, r2, #0x04
+	b		MEM_DataCopy3
+
+	.size	memcpy, .-memcpy
+	.end
@@ -0,0 +1,379 @@
+/****************************************************************************
+ * Driver for Calypso keypad hardware
+ *
+ *   Copyright (C) 2011 Stefan Richter. All rights reserved.
+ *   Author: Stefan Richter <ichgeh@l--putt.de>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/fs/fs.h>
+
+#include <stdint.h>
+#include <semaphore.h>
+#include <errno.h>
+#include <unistd.h>
+#include <sched.h>
+
+#include <arch/calypso/defines.h>
+#include <arch/calypso/memory.h>
+#include <arch/calypso/timer.h>
+
+/****************************************************************************
+ * HW access
+ ****************************************************************************/
+
+#define BASE_ADDR_ARMIO 0xfffe4800
+#define ARMIO_REG(x)    ((void *)BASE_ADDR_ARMIO + (x))
+
+enum armio_reg
+{
+  LATCH_IN = 0x00,
+  LATCH_OUT = 0x02,
+  IO_CNTL = 0x04,
+  CNTL_REG = 0x06,
+  LOAD_TIM = 0x08,
+  KBR_LATCH_REG = 0x0a,
+  KBC_REG = 0x0c,
+  BUZZ_LIGHT_REG = 0x0e,
+  LIGHT_LEVEL = 0x10,
+  BUZZER_LEVEL = 0x12,
+  GPIO_EVENT_MODE = 0x14,
+  KBD_GPIO_INT = 0x16,
+  KBD_GPIO_MASKIT = 0x18,
+  GPIO_DEBOUNCING = 0x1a,
+  GPIO_LATCH = 0x1c,
+};
+
+#define KBD_INT     (1 << 0)
+#define GPIO_INT    (1 << 1)
+
+/****************************************************************************
+ * Decoder functions for matrix and power button
+ ****************************************************************************/
+
+static int btn_dec(uint32_t * btn_state, uint8_t col, uint8_t reg,
+                   char *buf, size_t buflen, size_t * len)
+{
+  uint8_t diff = (*btn_state ^ reg) & 0x1f;
+
+  while (diff)
+    {
+      uint8_t val = diff & ~(diff - 1);
+      uint8_t sc = val >> 1;
+      sc |= sc << 2;
+      sc += col;
+      sc += (sc & 0x20) ? 0x26 : 0x3f;
+
+      if (reg & val)
+        {
+          sc |= 0x20;
+        }
+
+      /* Check for space in buffer and dispatch */
+
+      if (*len < buflen)
+        {
+          buf[(*len)++] = sc;
+        }
+      else
+        {
+          break;
+        }
+
+      /* Only change diff if dispatched/buffer not full */
+
+      diff ^= val;
+    }
+
+  /* Store new state of the buttons (but only if they where dispatch) */
+
+  *btn_state >>= 5;
+#ifdef INCLUDE_ALL_COLS
+  *btn_state |= (reg ^ diff) << 20;
+#else
+  *btn_state |= (reg ^ diff) << 15;
+#endif
+  return diff;
+}
+
+static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len)
+{
+  if (reg)
+    {
+      /* Check for pressed power button. If pressed, ignore other
+       * buttons since it collides with an entire row.
+       */
+
+      if (~*state & 0x80000000)
+        {
+          buf[0] = 'z';
+          *len = 1;
+          *state |= 0x80000000;
+        }
+
+        return 1; // break loop in caller
+    }
+  else
+    {
+      /* Check for released power button. */
+
+      if (*state & 0x80000000)
+        {
+          buf[0] = 'Z';
+          *len = 1;
+
+          *state &= 0x7fffffff;
+
+          /* Don't scan others when released; might trigger
+           * false keystrokes otherwise
+           */
+
+           return 1;
+        }
+    }
+
+  return 0; // continue with other columns
+}
+
+/****************************************************************************
+ * Keypad: Fileops Prototypes and Structures
+ ****************************************************************************/
+
+typedef FAR struct file file_t;
+
+static int keypad_open(file_t * filep);
+static int keypad_close(file_t * filep);
+static ssize_t keypad_read(file_t * filep, FAR char *buffer, size_t buflen);
+#ifndef CONFIG_DISABLE_POLL
+static int keypad_poll(file_t * filep, FAR struct pollfd *fds, bool setup);
+#endif
+
+static const struct file_operations keypad_ops =
+{
+  keypad_open,                  /* open */
+  keypad_close,                 /* close */
+  keypad_read,                  /* read */
+  0,                            /* write */
+  0,                            /* seek */
+  0,                            /* ioctl */
+#ifndef CONFIG_DISABLE_POLL
+  keypad_poll                   /* poll */
+#endif
+};
+
+static sem_t kbdsem;
+
+/****************************************************************************
+ * Keypad: Fileops
+ ****************************************************************************/
+
+static int keypad_open(file_t * filep)
+{
+  register uint16_t reg;
+
+  /* Unmask keypad interrupt */
+
+  reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
+  writew(reg & ~KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
+
+  return OK;
+}
+
+static int keypad_close(file_t * filep)
+{
+  register uint16_t reg;
+
+  /* Mask keypad interrupt */
+
+  reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
+  writew(reg | KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
+
+  return OK;
+}
+
+static ssize_t keypad_read(file_t * filep, FAR char *buf, size_t buflen)
+{
+  static uint32_t btn_state = 0;
+  register uint16_t reg;
+  uint16_t col, col_mask;
+  size_t len = 0;
+
+  if (buf == NULL || buflen < 1)
+    {
+      /* Well... nothing to do */
+
+      return -EINVAL;
+    }
+
+retry:
+  col = 1;
+  col_mask = 0x1e;
+
+  if (!btn_state)
+    {
+      /* Drive all cols low such that all buttons cause events */
+
+      writew(0, ARMIO_REG(KBC_REG));
+
+      /* No button currently pressed, use IRQ */
+
+      reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
+      writew(reg & ~KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
+      sem_wait(&kbdsem);
+    }
+  else
+    {
+      writew(0x1f, ARMIO_REG(KBC_REG));
+      usleep(80000);
+    }
+
+  /* Scan columns */
+
+#ifdef INCLUDE_ALL_COLS
+  while (col <= 6)
+    {
+#else
+  while (col <= 5)
+    {
+#endif
+      /* Read keypad latch and immediately set new column since
+       * synchronization takes about 5usec. For the 1st round, the
+       * interrupt has prepared this and the context switch takes
+       * long enough to serve as a delay.
+       */
+
+      reg = readw(ARMIO_REG(KBR_LATCH_REG));
+      writew(col_mask, ARMIO_REG(KBC_REG));
+
+      /* Turn pressed buttons into 1s */
+
+      reg = 0x1f & ~reg;
+
+      if (col == 1)
+        {
+          /* Power/End switch */
+
+          if (pwr_btn_dec(&btn_state, reg, buf, &len))
+            {
+              break;
+            }
+        }
+      else
+        {
+          /* Non-power switches */
+
+          if (btn_dec(&btn_state, col, reg, buf, buflen, &len))
+            {
+              break;
+            }
+        }
+
+      /* Select next column and respective mask */
+
+      col_mask = 0x1f & ~(1 << col++);
+
+      /* We have to wait for synchronization of the inputs. The
+       * processing is too fast if no/few buttons are processed.
+       */
+
+      usleep(5);
+
+      /* XXX: usleep seems to suffer hugh overhead. Better this!?
+       * If nothing else can be done, it's overhead still wastes
+       * time 'usefully'.
+       */
+      /* sched_yield(); up_udelay(2); */
+    }
+
+  /* If we don't have anything to return, retry to avoid EOF */
+
+  if (!len)
+    {
+      goto retry;
+    }
+
+  return len;
+}
+
+/****************************************************************************
+ * Keypad interrupt handler
+ *   mask interrupts
+ *   prepare column drivers for scan
+ *   posts keypad semaphore
+ ****************************************************************************/
+
+inline int calypso_kbd_irq(int irq, uint32_t * regs)
+{
+  register uint16_t reg;
+
+  /* Mask keypad interrupt */
+
+  reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
+  writew(reg | KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
+
+  /* Turn off column drivers */
+
+  writew(0x1f, ARMIO_REG(KBC_REG));
+
+  /* Let the userspace know */
+
+  sem_post(&kbdsem);
+
+  return 0;
+}
+
+/****************************************************************************
+ * Initialize device, add /dev/... nodes
+ ****************************************************************************/
+
+void up_keypad(void)
+{
+  /* Semaphore; helps leaving IRQ ctx as soon as possible */
+
+  sem_init(&kbdsem, 0, 0);
+
+  /* Drive cols low in idle state such that all buttons cause events */
+
+  writew(0, ARMIO_REG(KBC_REG));
+
+  (void)register_driver("/dev/keypad", &keypad_ops, 0444, NULL);
+}
+
+int keypad_kbdinit(void)
+{
+  calypso_armio();
+  up_keypad();
+
+  return OK;
+}
@@ -0,0 +1,53 @@
+/****************************************************************************
+ * arch/arm/src/common/arm-elf.h
+ *
+ *   Copyright (C) 2012 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_ARM_ELF_H
+#define __ARCH_ARM_SRC_ARM_ELF_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_ARM_ELF_H */
@@ -41,36 +41,40 @@ endif

 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c \
-		  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
-		  up_initialize.c up_initialstate.c up_interruptcontext.c \
-		  up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
-		  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
-		  up_schedulesigaction.c up_sigdeliver.c up_systemreset.c \
-		  up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \
-		  up_stackcheck.c
+			  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
+			  up_initialize.c up_initialstate.c up_interruptcontext.c \
+			  up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
+			  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
+			  up_schedulesigaction.c up_sigdeliver.c up_systemreset.c \
+			  up_unblocktask.c up_usestack.c up_doirq.c up_hardfault.c up_svcall.c \
+			  up_stackcheck.c

 ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y)
 CMN_ASRCS	+= up_exception.S
 CMN_CSRCS	+= up_vectors.c
 endif

+ifeq ($(CONFIG_ARCH_MEMCPY),y)
+CMN_ASRCS	+= up_memcpy.S
+endif
+
 ifeq ($(CONFIG_DEBUG_STACK),y)
 CMN_CSRCS	+= up_checkstack.c
 endif

+ifeq ($(CONFIG_ELF),y)
+CMN_CSRCS += up_elf.c
+endif
+
 ifeq ($(CONFIG_ARCH_FPU),y)
 CMN_ASRCS	+= up_fpu.S
 endif

-ifeq ($(CONFIG_ARCH_MEMCPY),y)
-CMN_ASRCS	+= memcpy.S
-endif
-
 CHIP_ASRCS	= 
 CHIP_CSRCS	= stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c \
-		  stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c \
-		  stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c \
-		  stm32_spi.c stm32_sdio.c stm32_tim.c stm32_i2c.c stm32_waste.c
+			  stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq.c \
+			  stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c \
+			  stm32_spi.c stm32_sdio.c stm32_tim.c stm32_i2c.c stm32_waste.c

 ifeq ($(CONFIG_USBDEV),y)
 ifeq ($(CONFIG_STM32_USB),y)
@@ -835,14 +835,6 @@ struct eth_rxdesc_s
 * Public Functions
 ****************************************************************************************************/

-#undef EXTERN
-#if defined(__cplusplus)
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
 #endif /* __ASSEMBLY__ */
 #endif /* STM32_NETHERNET > 0 */
 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_ETH_H */
@@ -110,6 +110,7 @@
 #  define FLASH_ACR_HLFCYA          (1 << 3)                /* FLASH half cycle access */
 #  define FLASH_ACR_PRTFBE          (1 << 4)                /* FLASH prefetch enable */
 #elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
+#  define FLASH_ACR_PRFTEN          (1 << 8)                /* FLASH prefetch enable */
 #  define FLASH_ACR_ICEN            (1 << 9)                /* Bit 9: Instruction cache enable */
 #  define FLASH_ACR_DCEN            (1 << 10)               /* Bit 10: Data cache enable */
 #  define FLASH_ACR_ICRST           (1 << 11)               /* Bit 11: Instruction cache reset */
@@ -6,6 +6,8 @@
 *   Copyright (C) 2012 Michael Smith. All Rights reserved.
 *   Author: Gregory Nutt <gnutt@nuttx.org>
 *           Uros Platise <uros.platise@isotel.eu>
+ *           Michael Smith
+ *           Freddie Chopin <freddie_chopin@op.pl>
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
@@ -49,6 +51,87 @@
 * Pre-processor Definitions
 ************************************************************************************/

+/* Alternate Pin Functions: */
+
+/* ADC */
+
+#define GPIO_ADC1_IN0       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN3       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC1_IN4       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC1_IN5       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC1_IN6       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC1_IN7       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC1_IN8       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC1_IN9       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN10      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC1_IN11      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC1_IN12      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC1_IN13      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC1_IN14      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC1_IN15      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+
+/* CEC */
+#if defined(CONFIG_STM32_CEC_REMAP)
+#  define GPIO_CEC          (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+#else
+#  define GPIO_CEC          (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#endif
+
+/* DAC
+ * Note from RM0041, 11.2: "Once the DAC channelx is enabled, the corresponding
+ * GPIO pin (PA4 or PA5) is automatically connected to the analog converter
+ * output (DAC_OUTx). In order to avoid parasitic consumption, the PA4 or PA5
+ * pin should first be configured to analog (AIN)."
+ */
+
+#define GPIO_DAC_OUT1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+
+/* FSMC */
+
+/* TODO - VL devices in 100- and 144-pin packages have FSMC */
+
+/* I2C */
+
+#if defined(CONFIG_STM32_I2C1_REMAP)
+#  define GPIO_I2C1_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#  define GPIO_I2C1_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#else
+#  define GPIO_I2C1_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+#  define GPIO_I2C1_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
+#endif
+#define GPIO_I2C1_SMBA      (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_I2C2_SCL       (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_I2C2_SDA       (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_I2C2_SMBA      (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+
+/* SPI */
+
+#if defined(CONFIG_STM32_SPI1_REMAP)
+#  define GPIO_SPI1_NSS     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
+#  define GPIO_SPI1_SCK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#  define GPIO_SPI1_MISO    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
+#  define GPIO_SPI1_MOSI    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+#else
+#  define GPIO_SPI1_NSS     (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
+#  define GPIO_SPI1_SCK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
+#  define GPIO_SPI1_MISO    (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
+#  define GPIO_SPI1_MOSI    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#endif
+
+#define GPIO_SPI2_NSS       (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_SPI2_SCK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#define GPIO_SPI2_MISO      (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_SPI2_MOSI      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+
+#define GPIO_SPI3_NSS       (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN15)
+#define GPIO_SPI3_SCK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
+#define GPIO_SPI3_MISO      (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN4)
+#define GPIO_SPI3_MOSI      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+
 /* TIMERS */

 #if defined(CONFIG_STM32_TIM1_FULL_REMAP)
@@ -186,6 +269,77 @@
 #  define GPIO_TIM4_CH4OUT  (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
 #endif

+#define GPIO_TIM5_CH1IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH1OUT    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH2IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH2OUT    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH3IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM5_CH3OUT    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM5_CH4IN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM5_CH4OUT    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+
+#if defined(CONFIG_STM32_TIM12_REMAP)
+#  define GPIO_TIM12_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN12)
+#  define GPIO_TIM12_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#  define GPIO_TIM12_CH2IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
+#  define GPIO_TIM12_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
+#else
+#  define GPIO_TIM12_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#  define GPIO_TIM12_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN4)
+#  define GPIO_TIM12_CH2IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+#  define GPIO_TIM12_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN5)
+#endif
+
+#if defined(CONFIG_STM32_TIM13_REMAP)
+#  define GPIO_TIM13_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#  define GPIO_TIM13_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+#else
+#  define GPIO_TIM13_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
+#  define GPIO_TIM13_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
+#endif
+
+#if defined(CONFIG_STM32_TIM14_REMAP)
+#  define GPIO_TIM14_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+#  define GPIO_TIM14_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+#else
+#  define GPIO_TIM14_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
+#  define GPIO_TIM14_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
+#endif
+
+#if defined(CONFIG_STM32_TIM15_REMAP)
+#  define GPIO_TIM15_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN14)
+#  define GPIO_TIM15_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
+#  define GPIO_TIM15_CH2IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN15)
+#  define GPIO_TIM15_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+#else
+#  define GPIO_TIM15_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#  define GPIO_TIM15_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
+#  define GPIO_TIM15_CH2IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#  define GPIO_TIM15_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+#endif
+#define GPIO_TIM15_BKIN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_TIM15_CH1N     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
+
+#if defined(CONFIG_STM32_TIM16_REMAP)
+#  define GPIO_TIM16_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#  define GPIO_TIM16_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
+#else
+#  define GPIO_TIM16_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN8)
+#  define GPIO_TIM16_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
+#endif
+#define GPIO_TIM16_BKIN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN5)
+#define GPIO_TIM16_CH1N     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
+
+#if defined(CONFIG_STM32_TIM17_REMAP)
+#  define GPIO_TIM17_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#  define GPIO_TIM17_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#else
+#  define GPIO_TIM17_CH1IN  (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN9)
+#  define GPIO_TIM17_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
+#endif
+#define GPIO_TIM17_BKIN     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_TIM17_CH1N     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
+
 /* USART */

 #if defined(CONFIG_STM32_USART1_REMAP)
@@ -230,38 +384,10 @@
 #  define GPIO_USART3_RTS   (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
 #endif

-/* SPI */
+#define GPIO_UART4_TX       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN10)
+#define GPIO_UART4_RX       (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN11)

-#if defined(CONFIG_STM32_SPI1_REMAP)
-#  define GPIO_SPI1_NSS     (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
-#  define GPIO_SPI1_SCK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
-#  define GPIO_SPI1_MISO    (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN4)
-#  define GPIO_SPI1_MOSI    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
-#else
-#  define GPIO_SPI1_NSS     (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN4)
-#  define GPIO_SPI1_SCK     (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN5)
-#  define GPIO_SPI1_MISO    (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN6)
-#  define GPIO_SPI1_MOSI    (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
-#endif
-
-#define GPIO_SPI2_NSS       (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
-#define GPIO_SPI2_SCK       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN13)
-#define GPIO_SPI2_MISO      (GPIO_INPUT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
-#define GPIO_SPI2_MOSI      (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN15)
-
-/* I2C */
-
-#if defined(CONFIG_STM32_I2C1_REMAP)
-#  define GPIO_I2C1_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
-#  define GPIO_I2C1_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
-#else
-#  define GPIO_I2C1_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
-#  define GPIO_I2C1_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
-#endif
-#define GPIO_I2C1_SMBA    (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
-
-#define GPIO_I2C2_SCL     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_I2C2_SDA     (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
-#define GPIO_I2C2_SMBA    (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+#define GPIO_UART5_TX       (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
+#define GPIO_UART5_RX       (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTD|GPIO_PIN2)

 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F100_PINMAP_H */
@@ -129,7 +129,7 @@


 #if 0 /* Needs further investigation */
-#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
 #define GPIO_DAC_OUT2           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
 #endif

@@ -50,53 +50,53 @@

 /* ADC */

-#define GPIO_ADC1_IN0       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ADC1_IN1       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ADC1_IN2       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ADC1_IN3       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ADC1_IN4       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
-#define GPIO_ADC1_IN5       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
-#define GPIO_ADC1_IN6       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
-#define GPIO_ADC1_IN7       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_ADC1_IN8       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_ADC1_IN9       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_ADC1_IN10      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
-#define GPIO_ADC1_IN11      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
-#define GPIO_ADC1_IN12      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_ADC1_IN13      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
-#define GPIO_ADC1_IN14      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_ADC1_IN15      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_ADC1_IN0       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC1_IN1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC1_IN2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC1_IN3       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC1_IN4       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC1_IN5       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC1_IN6       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC1_IN7       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC1_IN8       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC1_IN9       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC1_IN10      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC1_IN11      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC1_IN12      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC1_IN13      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC1_IN14      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC1_IN15      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)

-#define GPIO_ADC2_IN0       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ADC2_IN1       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ADC2_IN2       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ADC2_IN3       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ADC2_IN4       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
-#define GPIO_ADC2_IN5       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
-#define GPIO_ADC2_IN6       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
-#define GPIO_ADC2_IN7       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_ADC2_IN8       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
-#define GPIO_ADC2_IN9       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
-#define GPIO_ADC2_IN10      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
-#define GPIO_ADC2_IN11      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
-#define GPIO_ADC2_IN12      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_ADC2_IN13      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
-#define GPIO_ADC2_IN14      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
-#define GPIO_ADC2_IN15      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)
+#define GPIO_ADC2_IN0       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC2_IN1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC2_IN2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC2_IN3       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC2_IN4       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_ADC2_IN5       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
+#define GPIO_ADC2_IN6       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_ADC2_IN7       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_ADC2_IN8       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_ADC2_IN9       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1)
+#define GPIO_ADC2_IN10      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC2_IN11      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC2_IN12      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC2_IN13      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC2_IN14      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN4)
+#define GPIO_ADC2_IN15      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN5)

-#define GPIO_ADC3_IN0       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_ADC3_IN1       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_ADC3_IN2       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_ADC3_IN3       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_ADC3_IN4       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN6)
-#define GPIO_ADC3_IN5       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN7)
-#define GPIO_ADC3_IN6       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN8)
-#define GPIO_ADC3_IN7       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN9)
-#define GPIO_ADC3_IN8       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN10)
-#define GPIO_ADC3_IN10      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
-#define GPIO_ADC3_IN11      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
-#define GPIO_ADC3_IN12      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
-#define GPIO_ADC3_IN13      (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)
+#define GPIO_ADC3_IN0       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_ADC3_IN1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_ADC3_IN2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_ADC3_IN3       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_ADC3_IN4       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN6)
+#define GPIO_ADC3_IN5       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN7)
+#define GPIO_ADC3_IN6       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN8)
+#define GPIO_ADC3_IN7       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN9)
+#define GPIO_ADC3_IN8       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN10)
+#define GPIO_ADC3_IN10      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN0)
+#define GPIO_ADC3_IN11      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN1)
+#define GPIO_ADC3_IN12      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN2)
+#define GPIO_ADC3_IN13      (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN3)

 /* DAC - "Once the DAC channelx is enabled, the corresponding GPIO pin
 * (PA4 or PA5) is automatically connected to the analog converter output
@@ -104,8 +104,8 @@
 * should first be configured to analog (AIN)."
 */

-#define GPIO_DAC_OUT1       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTF|GPIO_PIN10)
-#define GPIO_DAC_OUT2       (GPIO_ALT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PIN10)
+#define GPIO_DAC_OUT1       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT2       (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)

 /* TIMERS */

@@ -85,7 +85,7 @@
 #endif

 #if 0 /* Needs further investigation */
-#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
 #define GPIO_DAC_OUT2           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
 #endif

@@ -85,7 +85,7 @@
 #endif

 #if 0 /* Needs further investigation */
-#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUTz|GPIO_PORTA|GPIO_PIN4)
+#define GPIO_DAC_OUT1           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
 #define GPIO_DAC_OUT2           (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
 #endif

@@ -59,6 +59,7 @@
 #define STM32_AFIO_EXTICR2_OFFSET    0x000c  /* External interrupt configuration register 2 */
 #define STM32_AFIO_EXTICR3_OFFSET    0x0010  /* External interrupt configuration register 3 */
 #define STM32_AFIO_EXTICR4_OFFSET    0x0014  /* External interrupt configuration register 4 */
+#define STM32_AFIO_MAPR2_OFFSET      0x001c  /* AF remap and debug I/O configuration register 2 */

 /* Register Addresses ***************************************************************/

@@ -373,5 +374,27 @@
 #define AFIO_EXTICR4_EXTI15_SHIFT    (12)      /* Bits 15-12: EXTI 15 configuration */
 #define AFIO_EXTICR4_EXTI15_MASK     (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI15_SHIFT)

+/* AF remap and debug I/O configuration register 2 */
+
+#ifdef CONFIG_STM32_VALUELINE
+#  define AFIO_MAPR2_TIM15_REMAP         (1 << 0)   /* Bit 0: TIM15 remapping */
+#  define AFIO_MAPR2_TIM16_REMAP         (1 << 1)   /* Bit 1: TIM16 remapping */
+#  define AFIO_MAPR2_TIM17_REMAP         (1 << 2)   /* Bit 2: TIM17 remapping */
+#  define AFIO_MAPR2_CEC_REMAP           (1 << 3)   /* Bit 3: CEC remapping */
+#  define AFIO_MAPR2_TIM1_DMA_REMAP      (1 << 4)   /* Bit 4: TIM1 DMA remapping */
+#else
+#  define AFIO_MAPR2_TIM9_REMAP          (1 << 5)   /* Bit 5: TIM9 remapping */
+#  define AFIO_MAPR2_TIM10_REMAP         (1 << 6)   /* Bit 6: TIM10 remapping */
+#  define AFIO_MAPR2_TIM11_REMAP         (1 << 7)   /* Bit 7: TIM11 remapping */
+#endif
+#define AFIO_MAPR2_TIM13_REMAP           (1 << 8)   /* Bit 8: TIM13 remapping */
+#define AFIO_MAPR2_TIM14_REMAP           (1 << 9)   /* Bit 9: TIM14 remapping */
+#define AFIO_MAPR2_FSMC_NADV             (1 << 10)  /* Bit 10: NADV connect/disconnect */
+#ifdef CONFIG_STM32_VALUELINE
+#  define AFIO_MAPR2_TIM67_DAC_DMA_REMAP (1 << 11)  /* Bit 11: TIM67_DAC DMA remapping */
+#  define AFIO_MAPR2_TIM12_REMAP         (1 << 12)  /* Bit 12: TIM12 remapping */
+#  define AFIO_MAPR2_MISC_REMAP          (1 << 13)  /* Bit 13: Miscellaneous features remapping */
+#endif
+
 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_GPIO_H */

@@ -60,7 +60,9 @@
 #define STM32_TIM5_BASE      0x40000c00     /* 0x40000c00 - 0x40000fff: TIM5 timer */
 #define STM32_TIM6_BASE      0x40001000     /* 0x40001000 - 0x400013ff: TIM6 timer */
 #define STM32_TIM7_BASE      0x40001400     /* 0x40001400 - 0x400007ff: TIM7 timer */
-                                            /* 0x40001800 - 0x40000fff: Reserved */
+#define STM32_TIM12_BASE     0x40001800     /* 0x40001800 - 0x40001bff: TIM12 timer */
+#define STM32_TIM13_BASE     0x40001c00     /* 0x40001c00 - 0x40001fff: TIM13 timer */
+#define STM32_TIM14_BASE     0x40002000     /* 0x40002000 - 0x400023ff: TIM14 timer */
 #define STM32_RTC_BASE       0x40002800     /* 0x40002800 - 0x40002bff: RTC */
 #define STM32_WWDG_BASE      0x40002c00     /* 0x40002C00 - 0x40002fff: Window watchdog (WWDG) */
 #define STM32_IWDG_BASE      0x40003000     /* 0x40003000 - 0x400033ff: Independent watchdog (IWDG) */
@@ -83,8 +85,8 @@
 #define STM32_BKP_BASE       0x40006c00     /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */
 #define STM32_PWR_BASE       0x40007000     /* 0x40007000 - 0x400073ff: Power control PWR */
 #define STM32_DAC_BASE       0x40007400     /* 0x40007400 - 0x400077ff: DAC */
-                                            /* 0x40007800 - 0x4000ffff: Reserved */
-
+#define STM32_CEC_BASE       0x40007800     /* 0x40007800 - 0x40007bff: CEC */
+                                            /* 0x40007c00 - 0x4000ffff: Reserved */
 /* APB2 bus */

 #define STM32_AFIO_BASE      0x40010000     /* 0x40010000 - 0x400103ff: AFIO */
@@ -102,44 +104,49 @@
 #define STM32_SPI1_BASE      0x40013000     /* 0x40013000 - 0x400133ff: SPI1 */
 #define STM32_TIM8_BASE      0x40013400     /* 0x40013400 - 0x400137ff: TIM8 timer */
 #define STM32_USART1_BASE    0x40013800     /* 0x40013800 - 0x40013bff: USART1 */
-#define STM32_ADC3_BASE      0x40012800     /* 0x40012800 - 0x40013fff: ADC3 */
-                                            /* 0x40014000 - 0x40017fff: Reserved */
+#define STM32_ADC3_BASE      0x40012800     /* 0x40012800 - 0x40013c00: ADC3 */
+                                            /* 0x40013c00 - 0x40013fff: Reserved */
+#define STM32_TIM15_BASE     0x40014400     /* 0x40014400 - 0x400147ff: TIM15 */
+#define STM32_TIM16_BASE     0x40014400     /* 0x40014400 - 0x400147ff: TIM16 */
+#define STM32_TIM17_BASE     0x40014800     /* 0x40014800 - 0x40014bff: TIM17 */
+                                            /* 0x40014c00 - 0x4001ffff: Reserved */
+
 /* AHB bus */

-#define STM32_SDIO_BASE     0x40018000     /* 0x40018000 - 0x400183ff: SDIO  */
-                                           /* 0x40018400 - 0x40017fff: Reserved */
-#define STM32_DMA1_BASE     0x40020000     /* 0x40020000 - 0x400203ff: DMA1  */
-#define STM32_DMA2_BASE     0x40020400     /* 0x40020000 - 0x400207ff: DMA2  */
-                                           /* 0x40020800 - 0x40020fff: Reserved */
-#define STM32_RCC_BASE      0x40021000     /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
-                                           /* 0x40021400 - 0x40021fff:  Reserved */
-#define STM32_OTGFS_BASE    0x50000000     /* 0x50000000 - 0x500003ff: USB OTG FS */
-#define STM32_FLASHIF_BASE  0x40022000     /* 0x40022000 - 0x400223ff: Flash memory interface */
-#define STM32_CRC_BASE      0x40028000     /* 0x40023000 - 0x400233ff: CRC */
-                                           /* 0x40023400 - 0x40027fff: Reserved */
-#define STM32_ETHERNET_BASE 0x40028000     /* 0x40028000 - 0x40029fff: Ethernet */
-                                           /* 0x40030000 - 0x4fffffff: Reserved */
+#define STM32_SDIO_BASE      0x40018000     /* 0x40018000 - 0x400183ff: SDIO  */
+                                            /* 0x40018400 - 0x40017fff: Reserved */
+#define STM32_DMA1_BASE      0x40020000     /* 0x40020000 - 0x400203ff: DMA1  */
+#define STM32_DMA2_BASE      0x40020400     /* 0x40020000 - 0x400207ff: DMA2  */
+                                            /* 0x40020800 - 0x40020fff: Reserved */
+#define STM32_RCC_BASE       0x40021000     /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
+                                            /* 0x40021400 - 0x40021fff:  Reserved */
+#define STM32_OTGFS_BASE     0x50000000     /* 0x50000000 - 0x500003ff: USB OTG FS */
+#define STM32_FLASHIF_BASE   0x40022000     /* 0x40022000 - 0x400223ff: Flash memory interface */
+#define STM32_CRC_BASE       0x40028000     /* 0x40023000 - 0x400233ff: CRC */
+                                            /* 0x40023400 - 0x40027fff: Reserved */
+#define STM32_ETHERNET_BASE  0x40028000     /* 0x40028000 - 0x40029fff: Ethernet */
+                                            /* 0x40030000 - 0x4fffffff: Reserved */

 /* Peripheral BB base */

-#define STM32_PERIPHBB_BASE 0x42000000
+#define STM32_PERIPHBB_BASE  0x42000000

 /* Flexible SRAM controller (FSMC) */

-#define STM32_FSMC_BANK1    0x60000000     /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
-#define STM32_FSMC_BANK2    0x70000000     /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
-#define STM32_FSMC_BANK3    0x80000000     /* 0x80000000-0x8fffffff: 256Mb  NAND FLASH */
-#define STM32_FSMC_BANK4    0x90000000     /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
-#define STM32_IS_EXTSRAM(a) ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)
+#define STM32_FSMC_BANK1     0x60000000     /* 0x60000000-0x6fffffff: 256Mb NOR/SRAM */
+#define STM32_FSMC_BANK2     0x70000000     /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
+#define STM32_FSMC_BANK3     0x80000000     /* 0x80000000-0x8fffffff: 256Mb  NAND FLASH */
+#define STM32_FSMC_BANK4     0x90000000     /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
+#define STM32_IS_EXTSRAM(a)  ((((uint32_t)(a)) & STM32_REGION_MASK) == STM32_FSMC_BANK1)

-#define STM32_FSMC_BASE     0xa0000000     /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */
+#define STM32_FSMC_BASE      0xa0000000     /* 0xa0000000-0xbfffffff: 512Mb FSMC register block */

 /* Other registers -- see armv7-m/nvic.h for standard Cortex-M3 registers in this
 * address range
 */

-#define STM32_SCS_BASE      0xe000e000
-#define STM32_DEBUGMCU_BASE 0xe0042000
+#define STM32_SCS_BASE       0xe000e000
+#define STM32_DEBUGMCU_BASE  0xe0042000

 #endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_MEMORYMAP_H */

@@ -163,7 +163,9 @@
 #  define RCC_CFGR_PLLMUL_CLKx14    (12 << RCC_CFGR_PLLMUL_SHIFT) /* 1100: PLL input clock x 14 */
 #  define RCC_CFGR_PLLMUL_CLKx15    (13 << RCC_CFGR_PLLMUL_SHIFT) /* 1101: PLL input clock x 15 */
 #  define RCC_CFGR_PLLMUL_CLKx16    (14 << RCC_CFGR_PLLMUL_SHIFT) /* 111x: PLL input clock x 16 */
-#define RCC_CFGR_USBPRE             (1 << 22) /* Bit 22: USB prescaler */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_CFGR_USBPRE           (1 << 22) /* Bit 22: USB prescaler */
+#endif
 #define RCC_CFGR_MCO_SHIFT          (24)      /* Bits 26-24: Microcontroller Clock Output */
 #define RCC_CFGR_MCO_MASK           (0x0f << RCC_CFGR_MCO_SHIFT)
 #  define RCC_CFGR_NOCLK            (0 << RCC_CFGR_MCO_SHIFT)  /* 0xx: No clock */
@@ -207,12 +209,22 @@
 #define TCC_APB2RSTR_IOPFRST        (1 << 7)  /* Bit 7: IO port F reset */
 #define TCC_APB2RSTR_IOPGRST        (1 << 8)  /* Bit 8: IO port G reset */
 #define RCC_APB2RSTR_ADC1RST        (1 << 9)  /* Bit 9: ADC 1 interface reset */
-#define RCC_APB2RSTR_ADC2RST        (1 << 10) /* Bit 10: ADC 2 interface reset */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2RSTR_ADC2RST      (1 << 10) /* Bit 10: ADC 2 interface reset */
+#endif
 #define RCC_APB2RSTR_TIM1RST        (1 << 11) /* Bit 11: TIM1 Timer reset */
 #define RCC_APB2RSTR_SPI1RST        (1 << 12) /* Bit 12: SPI 1 reset */
-#define RCC_APB2RSTR_TIM8RST        (1 << 13) /* Bit 13: TIM8 Timer reset */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2RSTR_TIM8RST      (1 << 13) /* Bit 13: TIM8 Timer reset */
+#endif
 #define RCC_APB2RSTR_USART1RST      (1 << 14) /* Bit 14: USART1 reset */
-#define RCC_APB2RSTR_ADC3RST        (1 << 15) /* Bit 15: ADC3 interface reset */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2RSTR_ADC3RST      (1 << 15) /* Bit 15: ADC3 interface reset */
+#else
+#  define RCC_APB2RSTR_TIM15RST     (1 << 16) /* Bit 16: TIM15 reset */
+#  define RCC_APB2RSTR_TIM16RST     (1 << 17) /* Bit 17: TIM16 reset */
+#  define RCC_APB2RSTR_TIM17RST     (1 << 18) /* Bit 18: TIM17 reset */
+#endif

 /* APB1 Peripheral reset register */

@@ -222,6 +234,11 @@
 #define RCC_APB1RSTR_TIM5RST        (1 << 3)  /* Bit 3: Timer 5 reset */
 #define RCC_APB1RSTR_TIM6RST        (1 << 4)  /* Bit 4: Timer 6 reset */
 #define RCC_APB1RSTR_TIM7RST        (1 << 5)  /* Bit 5: Timer 7 reset */
+#ifdef CONFIG_STM32_VALUELINE
+#  define RCC_APB1RSTR_TIM12RST     (1 << 6) /* Bit 6: TIM12 reset */
+#  define RCC_APB1RSTR_TIM13RST     (1 << 7) /* Bit 7: TIM13 reset */
+#  define RCC_APB1RSTR_TIM14RST     (1 << 8) /* Bit 8: TIM14 reset */
+#endif
 #define RCC_APB1RSTR_WWDGRST        (1 << 11) /* Bit 11: Window Watchdog reset */
 #define RCC_APB1RSTR_SPI2RST        (1 << 14) /* Bit 14: SPI 2 reset */
 #define RCC_APB1RSTR_SPI3RST        (1 << 15) /* Bit 15: SPI 3 reset */
@@ -231,12 +248,17 @@
 #define RCC_APB1RSTR_UART5RST       (1 << 20) /* Bit 18: UART 5 reset */
 #define RCC_APB1RSTR_I2C1RST        (1 << 21) /* Bit 21: I2C 1 reset */
 #define RCC_APB1RSTR_I2C2RST        (1 << 22) /* Bit 22: I2C 2 reset */
-#define RCC_APB1RSTR_USBRST         (1 << 23) /* Bit 23: USB reset */
-#define RCC_APB1RSTR_CAN1RST        (1 << 25) /* Bit 25: CAN1 reset */
-#define RCC_APB1RSTR_CAN2RST        (1 << 26) /* Bit 26: CAN2 reset */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB1RSTR_USBRST       (1 << 23) /* Bit 23: USB reset */
+#  define RCC_APB1RSTR_CAN1RST      (1 << 25) /* Bit 25: CAN1 reset */
+#  define RCC_APB1RSTR_CAN2RST      (1 << 26) /* Bit 26: CAN2 reset */
+#endif
 #define RCC_APB1RSTR_BKPRST         (1 << 27) /* Bit 27: Backup interface reset */
 #define RCC_APB1RSTR_PWRRST         (1 << 28) /* Bit 28: Power interface reset */
 #define RCC_APB1RSTR_DACRST         (1 << 29) /* Bit 29: DAC interface reset */
+#ifdef CONFIG_STM32_VALUELINE
+#  define RCC_APB1RSTR_CECRST       (1 << 30) /* Bit 30: CEC reset */
+#endif

 /* AHB Peripheral Clock enable register */

@@ -246,7 +268,9 @@
 #define RCC_AHBENR_FLITFEN          (1 << 4)  /* Bit 4: FLITF clock enable */
 #define RCC_AHBENR_CRCEN            (1 << 6)  /* Bit 6: CRC clock enable */
 #define RCC_AHBENR_FSMCEN           (1 << 8)  /* Bit 8: FSMC clock enable */
-#define RCC_AHBENR_SDIOEN           (1 << 10) /* Bit 10: SDIO clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_AHBENR_SDIOEN         (1 << 10) /* Bit 10: SDIO clock enable */
+#endif
 #ifdef CONFIG_STM32_CONNECTIVITYLINE
 #  define RCC_AHBENR_ETHMACEN       (1 << 14) /* Bit 14: Ethernet MAC clock enable */
 #  define RCC_AHBENR_ETHMACTXEN     (1 << 15) /* Bit 15: Ethernet MAC TX clock enable */
@@ -272,12 +296,22 @@
 #define RCC_APB2ENR_IOPFEN          (1 << 7)  /* Bit 7: I/O port F clock enable */
 #define RCC_APB2ENR_IOPGEN          (1 << 8)  /* Bit 8: I/O port G clock enable */
 #define RCC_APB2ENR_ADC1EN          (1 << 9)  /* Bit 9: ADC 1 interface clock enable */
-#define RCC_APB2ENR_ADC2EN          (1 << 10) /* Bit 10: ADC 2 interface clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2ENR_ADC2EN        (1 << 10) /* Bit 10: ADC 2 interface clock enable */
+#endif
 #define RCC_APB2ENR_TIM1EN          (1 << 11) /* Bit 11: TIM1 Timer clock enable */
 #define RCC_APB2ENR_SPI1EN          (1 << 12) /* Bit 12: SPI 1 clock enable */
-#define RCC_APB2ENR_TIM8EN          (1 << 13) /* Bit 13: TIM8 Timer clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2ENR_TIM8EN        (1 << 13) /* Bit 13: TIM8 Timer clock enable */
+#endif
 #define RCC_APB2ENR_USART1EN        (1 << 14) /* Bit 14: USART1 clock enable */
-#define RCC_APB2ENR_ADC3EN          (1 << 15) /* Bit 14: ADC3 interface clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB2ENR_ADC3EN        (1 << 15) /* Bit 14: ADC3 interface clock enable */
+#else
+#  define RCC_APB2ENR_TIM15EN       (1 << 16) /* Bit 16: TIM15 clock enable */
+#  define RCC_APB2ENR_TIM16EN       (1 << 17) /* Bit 17: TIM16 clock enable */
+#  define RCC_APB2ENR_TIM17EN       (1 << 18) /* Bit 18: TIM17 clock enable */
+#endif

 /* APB1 Peripheral Clock enable register */

@@ -287,6 +321,11 @@
 #define RCC_APB1ENR_TIM5EN          (1 << 3)  /* Bit 3: Timer 5 clock enable */
 #define RCC_APB1ENR_TIM6EN          (1 << 4)  /* Bit 4: Timer 6 clock enable */
 #define RCC_APB1ENR_TIM7EN          (1 << 5)  /* Bit 5: Timer 7 clock enable */
+#ifdef CONFIG_STM32_VALUELINE
+#  define RCC_APB1ENR_TIM12EN       (1 << 6)  /* Bit 6: Timer 12 clock enable */
+#  define RCC_APB1ENR_TIM13EN       (1 << 7)  /* Bit 7: Timer 13 clock enable */
+#  define RCC_APB1ENR_TIM14EN       (1 << 8)  /* Bit 8: Timer 14 clock enable */
+#endif
 #define RCC_APB1ENR_WWDGEN          (1 << 11) /* Bit 11: Window Watchdog clock enable */
 #define RCC_APB1ENR_SPI2EN          (1 << 14) /* Bit 14: SPI 2 clock enable */
 #define RCC_APB1ENR_SPI3EN          (1 << 15) /* Bit 15: SPI 3 clock enable */
@@ -296,12 +335,17 @@
 #define RCC_APB1ENR_UART5EN         (1 << 20) /* Bit 20: UART 5 clock enable */
 #define RCC_APB1ENR_I2C1EN          (1 << 21) /* Bit 21: I2C 1 clock enable */
 #define RCC_APB1ENR_I2C2EN          (1 << 22) /* Bit 22: I2C 2 clock enable */
-#define RCC_APB1ENR_USBEN           (1 << 23) /* Bit 23: USB clock enable */
-#define RCC_APB1ENR_CAN1EN          (1 << 25) /* Bit 25: CAN1 clock enable */
-#define RCC_APB1ENR_CAN2EN          (1 << 26) /* Bit 25: CAN2 clock enable */
+#ifndef CONFIG_STM32_VALUELINE
+#  define RCC_APB1ENR_USBEN         (1 << 23) /* Bit 23: USB clock enable */
+#  define RCC_APB1ENR_CAN1EN        (1 << 25) /* Bit 25: CAN1 clock enable */
+#  define RCC_APB1ENR_CAN2EN        (1 << 26) /* Bit 25: CAN2 clock enable */
+#endif
 #define RCC_APB1ENR_BKPEN           (1 << 27) /* Bit 27: Backup interface clock enable */
 #define RCC_APB1ENR_PWREN           (1 << 28) /* Bit 28: Power interface clock enable */
 #define RCC_APB1ENR_DACEN           (1 << 29) /* Bit 29: DAC interface clock enable */
+#ifdef CONFIG_STM32_VALUELINE
+#  define RCC_APB1ENR_CECEN         (1 << 30) /* Bit 30: CEC clock enable */
+#endif

 /* Backup domain control register */

@@ -331,7 +375,7 @@

 #if defined(CONFIG_STM32_VALUELINE) || defined(CONFIG_STM32_CONNECTIVITYLINE)

-/* Clock configuration register 2 (For connectivity line only) */
+/* Clock configuration register 2 (For value line and connectivity line only) */

 #define RCC_CFGR2_PREDIV1_SHIFT     (0)
 #define RCC_CFGR2_PREDIV1_MASK      (0x0f << RCC_CFGR2_PREDIV1_SHIFT)
@@ -352,6 +396,10 @@
 #  define RCC_CFGR2_PREDIV1d15      (14 << RCC_CFGR2_PREDIV1_SHIFT)
 #  define RCC_CFGR2_PREDIV1d16      (15 << RCC_CFGR2_PREDIV1_SHIFT)

+#endif
+
+#ifdef CONFIG_STM32_CONNECTIVITYLINE
+
 #define RCC_CFGR2_PREDIV2_SHIFT     (4)
 #define RCC_CFGR2_PREDIV2_MASK      (0x0f << RCC_CFGR2_PREDIV2_SHIFT)
 #  define RCC_CFGR2_PREDIV2d1       (0 << RCC_CFGR2_PREDIV2_SHIFT)
@@ -49,15 +49,77 @@
 * definition that provides the number of supported vectors.
 */

-#ifdef CONFIG_ARMV7M_CMNVECTOR
+#  ifdef CONFIG_ARMV7M_CMNVECTOR

-/* Reserve 60 interrupt table entries for I/O interrupts. */
+/* Reserve 61 interrupt table entries for I/O interrupts. */

-#  define ARMV7M_PERIPHERAL_INTERRUPTS 60
+#    define ARMV7M_PERIPHERAL_INTERRUPTS 61

 #else
-#  error This target requires CONFIG_ARMV7M_CMNVECTOR
-#endif /* CONFIG_ARMV7M_CMNVECTOR */
+
+VECTOR(stm32_wwdg, STM32_IRQ_WWDG)                /* Vector 16+0:  Window Watchdog interrupt */
+VECTOR(stm32_pvd, STM32_IRQ_PVD)                  /* Vector 16+1:  PVD through EXTI Line detection interrupt */
+VECTOR(stm32_tamper, STM32_IRQ_TAMPER)            /* Vector 16+2:  Tamper interrupt */
+VECTOR(stm32_rtc, STM32_IRQ_RTC)                  /* Vector 16+3:  RTC Wakeup through EXTI line interrupt */
+VECTOR(stm32_flash, STM32_IRQ_FLASH)              /* Vector 16+4:  Flash global interrupt */
+VECTOR(stm32_rcc, STM32_IRQ_RCC)                  /* Vector 16+5:  RCC global interrupt */
+VECTOR(stm32_exti0, STM32_IRQ_EXTI0)              /* Vector 16+6:  EXTI Line 0 interrupt */
+VECTOR(stm32_exti1, STM32_IRQ_EXTI1)              /* Vector 16+7:  EXTI Line 1 interrupt */
+VECTOR(stm32_exti2, STM32_IRQ_EXTI2)              /* Vector 16+8:  EXTI Line 2 interrupt */
+VECTOR(stm32_exti3, STM32_IRQ_EXTI3)              /* Vector 16+9:  EXTI Line 3 interrupt */
+VECTOR(stm32_exti4, STM32_IRQ_EXTI4)              /* Vector 16+10: EXTI Line 4 interrupt */
+VECTOR(stm32_dma1ch1, STM32_IRQ_DMA1CH1)          /* Vector 16+11: DMA1 Channel 1 global interrupt */
+VECTOR(stm32_dma1ch2, STM32_IRQ_DMA1CH2)          /* Vector 16+12: DMA1 Channel 2 global interrupt */
+VECTOR(stm32_dma1ch3, STM32_IRQ_DMA1CH3)          /* Vector 16+13: DMA1 Channel 3 global interrupt */
+VECTOR(stm32_dma1ch4, STM32_IRQ_DMA1CH4)          /* Vector 16+14: DMA1 Channel 4 global interrupt */
+VECTOR(stm32_dma1ch5, STM32_IRQ_DMA1CH5)          /* Vector 16+15: DMA1 Channel 5 global interrupt */
+VECTOR(stm32_dma1ch6, STM32_IRQ_DMA1CH6)          /* Vector 16+16: DMA1 Channel 6 global interrupt */
+VECTOR(stm32_dma1ch7, STM32_IRQ_DMA1CH7)          /* Vector 16+17: DMA1 Channel 7 global interrupt */
+VECTOR(stm32_adc1, STM32_IRQ_ADC1)                /* Vector 16+18: ADC1 global interrupt */
+UNUSED(STM32_IRQ_RESERVED0)                       /* Vector 16+19: Reserved 0 */
+UNUSED(STM32_IRQ_RESERVED1)                       /* Vector 16+20: Reserved 1 */
+UNUSED(STM32_IRQ_RESERVED2)                       /* Vector 16+21: Reserved 2 */
+UNUSED(STM32_IRQ_RESERVED3)                       /* Vector 16+22: Reserved 3 */
+VECTOR(stm32_exti95, STM32_IRQ_EXTI95)            /* Vector 16+23: EXTI Line[9:5] interrupts */
+VECTOR(stm32_tim1brk, STM32_IRQ_TIM1BRK)          /* Vector 16+24: TIM1 Break interrupt; TIM15 global interrupt */
+VECTOR(stm32_tim1up, STM32_IRQ_TIM1UP)            /* Vector 16+25: TIM1 Update interrupt; TIM16 global interrupt */
+VECTOR(stm32_tim1trgcom, STM32_IRQ_TIM1TRGCOM)    /* Vector 16+26: TIM1 Trigger and Commutation interrupts; TIM17 global interrupt */
+VECTOR(stm32_tim1cc, STM32_IRQ_TIM1CC)            /* Vector 16+27: TIM1 Capture Compare interrupt */
+VECTOR(stm32_tim2, STM32_IRQ_TIM2)                /* Vector 16+28: TIM2 global interrupt */
+VECTOR(stm32_tim3, STM32_IRQ_TIM3)                /* Vector 16+29: TIM3 global interrupt */
+VECTOR(stm32_tim4, STM32_IRQ_TIM4)                /* Vector 16+30: TIM4 global interrupt */
+VECTOR(stm32_i2c1ev, STM32_IRQ_I2C1EV)            /* Vector 16+31: I2C1 event interrupt */
+VECTOR(stm32_i2c1er, STM32_IRQ_I2C1ER)            /* Vector 16+32: I2C1 error interrupt */
+VECTOR(stm32_i2c2ev, STM32_IRQ_I2C2EV)            /* Vector 16+33: I2C2 event interrupt */
+VECTOR(stm32_i2c2er, STM32_IRQ_I2C2ER)            /* Vector 16+34: I2C2 error interrupt */
+VECTOR(stm32_spi1, STM32_IRQ_SPI1)                /* Vector 16+35: SPI1 global interrupt */
+VECTOR(stm32_spi2, STM32_IRQ_SPI2)                /* Vector 16+36: SPI2 global interrupt */
+VECTOR(stm32_usart1, STM32_IRQ_USART1)            /* Vector 16+37: USART1 global interrupt */
+VECTOR(stm32_usart2, STM32_IRQ_USART2)            /* Vector 16+38: USART2 global interrupt */
+VECTOR(stm32_usart3, STM32_IRQ_USART3)            /* Vector 16+39: USART3 global interrupt */
+VECTOR(stm32_exti1510, STM32_IRQ_EXTI1510)        /* Vector 16+40: EXTI Line[15:10] interrupts */
+VECTOR(stm32_rtcalr, STM32_IRQ_RTCALR)            /* Vector 16+41: RTC alarms (A and B) through EXTI line interrupt */
+VECTOR(stm32_cec, STM32_IRQ_CEC)                  /* Vector 16+42: CEC global interrupt */
+VECTOR(stm32_tim12, STM32_IRQ_TIM12)              /* Vector 16+43: TIM12 global interrupt */
+VECTOR(stm32_tim13, STM32_IRQ_TIM13)              /* Vector 16+44: TIM13 global interrupt */
+VECTOR(stm32_tim14, STM32_IRQ_TIM14)              /* Vector 16+45: TIM14 global interrupt */
+UNUSED(STM32_IRQ_RESERVED4)                       /* Vector 16+46: Reserved 4 */
+UNUSED(STM32_IRQ_RESERVED5)                       /* Vector 16+47: Reserved 5 */
+VECTOR(stm32_fsmc, STM32_IRQ_FSMC)                /* Vector 16+48: FSMC global interrupt */
+UNUSED(STM32_IRQ_RESERVED6)                       /* Vector 16+49: Reserved 6 */
+VECTOR(stm32_tim5, STM32_IRQ_TIM5)                /* Vector 16+50: TIM5 global interrupt */
+VECTOR(stm32_spi3, STM32_IRQ_SPI3)                /* Vector 16+51: SPI3 global interrupt */
+VECTOR(stm32_uart4, STM32_IRQ_UART4)              /* Vector 16+52: USART2 global interrupt */
+VECTOR(stm32_uart5, STM32_IRQ_UART5)              /* Vector 16+53: USART5 global interrupt */
+VECTOR(stm32_tim6, STM32_IRQ_TIM6)                /* Vector 16+54: TIM6 global interrupt */
+VECTOR(stm32_tim7, STM32_IRQ_TIM7)                /* Vector 16+55: TIM7 global interrupt */
+VECTOR(stm32_dma2ch1, STM32_IRQ_DMA2CH1)          /* Vector 16+56: DMA2 Channel 1 global interrupt */
+VECTOR(stm32_dma2ch2, STM32_IRQ_DMA2CH2)          /* Vector 16+57: DMA2 Channel 2 global interrupt */
+VECTOR(stm32_dma2ch3, STM32_IRQ_DMA2CH3)          /* Vector 16+58: DMA2 Channel 3 global interrupt */
+VECTOR(stm32_dma2ch45, STM32_IRQ_DMA2CH45)        /* Vector 16+59: DMA2 Channel 4 and 5 global interrupt */
+VECTOR(stm32_dma2ch5, STM32_IRQ_DMA2CH5)          /* Vector 16+60: DMA2 Channel 5 global interrupt */
+
+#  endif /* CONFIG_ARMV7M_CMNVECTOR */

 #elif defined(CONFIG_STM32_CONNECTIVITYLINE)

@@ -222,7 +222,7 @@
 #define GPIO_ETH_MII_TX_EN_2  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
 #define GPIO_ETH_PPS_OUT_1    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
 #define GPIO_ETH_PPS_OUT_2    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
-#define GPIO_ETH_RMII_CRS_DV  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULLGPIO_PORTA|GPIO_PIN7)
+#define GPIO_ETH_RMII_CRS_DV  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
 #define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
 #define GPIO_ETH_RMII_RXD0    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
 #define GPIO_ETH_RMII_RXD1    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
@@ -222,7 +222,7 @@
 #define GPIO_ETH_MII_TX_EN_2  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN11)
 #define GPIO_ETH_PPS_OUT_1    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN5)
 #define GPIO_ETH_PPS_OUT_2    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN8)
-#define GPIO_ETH_RMII_CRS_DV  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULLGPIO_PORTA|GPIO_PIN7)
+#define GPIO_ETH_RMII_CRS_DV  (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN7)
 #define GPIO_ETH_RMII_REF_CLK (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
 #define GPIO_ETH_RMII_RXD0    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN4)
 #define GPIO_ETH_RMII_RXD1    (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN5)
@@ -720,10 +720,10 @@ static int adc_timinit(FAR struct stm32_dev_s *priv)

      case 4: /* TimerX TRGO event */
        {
-#warning "TRGO support not yet implemented"
-
+          /* TODO: TRGO support not yet implemented */
          /* Set the event TRGO */

+          ccenable = 0;
          egr      = GTIM_EGR_TG;

          /* Set the duty cycle by writing to the CCR register for this channel */
@@ -1128,7 +1128,7 @@ static void adc_reset(FAR struct adc_dev_s *dev)
  avdbg("intf: ADC%d\n", priv->intf);
  flags = irqsave();

-  /* Enable  ADC reset state */
+  /* Enable ADC reset state */

  adc_rccreset(priv, true);

@@ -1326,6 +1326,10 @@ static int adc_setup(FAR struct adc_dev_s *dev)
  ret = irq_attach(priv->irq, priv->isr);
  if (ret == OK)
    {
+      /* Make sure that the ADC device is in the powered up, reset state */
+
+      adc_reset(dev);
+
      /* Enable the ADC interrupt */

      avdbg("Enable the ADC interrupt: irq=%d\n", priv->irq);
@@ -281,7 +281,7 @@

 #if defined(ADC1_HAVE_TIMER) || defined(ADC2_HAVE_TIMER) || defined(ADC3_HAVE_TIMER)
 #  define ADC_HAVE_TIMER 1
-#  if defined(CONFIG_STM32_STM32F10XX) && defined(CONFIG_STM32_FORCEPOWER)
+#  if defined(CONFIG_STM32_STM32F10XX) && !defined(CONFIG_STM32_FORCEPOWER)
 #    warning "CONFIG_STM32_FORCEPOWER must be defined to enable the timer(s)"
 #  endif
 #else
@@ -2594,6 +2594,17 @@ static int stm32_phyinit(FAR struct stm32_ethmac_s *priv)
    }
  up_mdelay(PHY_RESET_DELAY);

+  /* Perform any necessary, board-specific PHY initialization */
+
+#ifdef CONFIG_STM32_PHYINIT
+  ret = stm32_phy_boardinitialize(0);
+  if (ret < 0)
+    {
+      ndbg("Failed to initialize the PHY: %d\n", ret);
+      return ret;
+    }
+#endif
+
  /* Special workaround for the Davicom DM9161 PHY is required. */

 #ifdef CONFIG_PHY_DM9161
@@ -66,14 +66,13 @@ extern "C" {
 * Function: stm32_ethinitialize
 *
 * Description:
- *   Initialize the Ethernet driver for one interface.  If the STM32 chip
- *   supports multiple Ethernet controllers, then board specific logic
- *   must implement up_netinitialize() and call this function to initialize
- *   the desired interfaces.
+ *   Initialize the Ethernet driver for one interface.  If the STM32 chip supports
+ *   multiple Ethernet controllers, then board specific logic must implement
+ *   up_netinitialize() and call this function to initialize the desired interfaces.
 *
 * Parameters:
- *   intf - In the case where there are multiple EMACs, this value
- *          identifies which EMAC is to be initialized.
+ *   intf - In the case where there are multiple EMACs, this value identifies which
+ *   EMAC is to be initialized.
 *
 * Returned Value:
 *   OK on success; Negated errno on failure.
@@ -86,6 +85,30 @@ extern "C" {
 EXTERN int stm32_ethinitialize(int intf);
 #endif

+/************************************************************************************
+ * Function: stm32_phy_boardinitialize
+ *
+ * Description:
+ *   Some boards require specialized initialization of the PHY before it can be used.
+ *   This may include such things as configuring GPIOs, resetting the PHY, etc.  If
+ *   CONFIG_STM32_PHYINIT is defined in the configuration then the board specific
+ *   logic must provide stm32_phyinitialize();  The STM32 Ethernet driver will call
+ *   this function one time before it first uses the PHY.
+ *
+ * Parameters:
+ *   intf - Always zero for now.
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_STM32_PHYINIT
+EXTERN int stm32_phy_boardinitialize(int intf);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }
@@ -67,6 +67,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_USART1_2STOP
 #  define STM32_CONSOLE_TX       GPIO_USART1_TX
 #  define STM32_CONSOLE_RX       GPIO_USART1_RX
+#  ifdef CONFIG_USART1_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_USART1_RS485_DIR
+#    if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_USART2_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_USART2_BASE
 #  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
@@ -76,6 +84,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_USART2_2STOP
 #  define STM32_CONSOLE_TX       GPIO_USART2_TX
 #  define STM32_CONSOLE_RX       GPIO_USART2_RX
+#  ifdef CONFIG_USART2_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_USART2_RS485_DIR
+#    if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_USART3_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_USART3_BASE
 #  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
@@ -85,6 +101,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_USART3_2STOP
 #  define STM32_CONSOLE_TX       GPIO_USART3_TX
 #  define STM32_CONSOLE_RX       GPIO_USART3_RX
+#  ifdef CONFIG_USART3_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_USART3_RS485_DIR
+#    if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_UART4_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_UART4_BASE
 #  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
@@ -94,6 +118,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_UART4_2STOP
 #  define STM32_CONSOLE_TX       GPIO_UART4_TX
 #  define STM32_CONSOLE_RX       GPIO_UART4_RX
+#  ifdef CONFIG_UART4_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_UART4_RS485_DIR
+#    if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_UART5_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_UART5_BASE
 #  define STM32_APBCLOCK         STM32_PCLK1_FREQUENCY
@@ -103,6 +135,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_UART5_2STOP
 #  define STM32_CONSOLE_TX       GPIO_UART5_TX
 #  define STM32_CONSOLE_RX       GPIO_UART5_RX
+#  ifdef CONFIG_UART5_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_UART5_RS485_DIR
+#    if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #elif defined(CONFIG_USART6_SERIAL_CONSOLE)
 #  define STM32_CONSOLE_BASE     STM32_USART6_BASE
 #  define STM32_APBCLOCK         STM32_PCLK2_FREQUENCY
@@ -112,6 +152,14 @@
 #  define STM32_CONSOLE_2STOP    CONFIG_USART6_2STOP
 #  define STM32_CONSOLE_TX       GPIO_USART6_TX
 #  define STM32_CONSOLE_RX       GPIO_USART6_RX
+#  ifdef CONFIG_USART6_RS485
+#    define STM32_CONSOLE_RS485_DIR GPIO_USART6_RS485_DIR
+#    if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
+#      define STM32_CONSOLE_RS485_DIR_POLARITY false
+#    else
+#      define STM32_CONSOLE_RS485_DIR_POLARITY true
+#    endif
+#  endif
 #endif

 /* CR1 settings */
@@ -230,10 +278,19 @@ void up_lowputc(char ch)
  /* Wait until the TX data register is empty */

  while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) == 0);
+#if STM32_CONSOLE_RS485_DIR
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
+#endif

  /* Then send the character */

  putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_DR_OFFSET);
+
+#if STM32_CONSOLE_RS485_DIR
+  while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TC) == 0);
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
+#endif
+
 #endif
 }

@@ -328,7 +385,14 @@ void stm32_lowsetup(void)

 #ifdef STM32_CONSOLE_TX
  stm32_configgpio(STM32_CONSOLE_TX);
-  stm32_configgpio(STM32_CONSOLE_TX);
+#endif
+#ifdef STM32_CONSOLE_RX
+  stm32_configgpio(STM32_CONSOLE_RX);
+#endif
+
+#if STM32_CONSOLE_RS485_DIR
+  stm32_configgpio(STM32_CONSOLE_RS485_DIR);
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
 #endif

  /* Enable and configure the selected console device */
@@ -382,7 +446,14 @@ void stm32_lowsetup(void)

 #ifdef STM32_CONSOLE_TX
  stm32_configgpio(STM32_CONSOLE_TX);
-  stm32_configgpio(STM32_CONSOLE_TX);
+#endif
+#ifdef STM32_CONSOLE_RX
+  stm32_configgpio(STM32_CONSOLE_RX);
+#endif
+
+#if STM32_CONSOLE_RS485_DIR
+  stm32_configgpio(STM32_CONSOLE_RS485_DIR);
+  stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
 #endif

  /* Enable and configure the selected console device */
@@ -3651,10 +3651,14 @@ static int stm32_epout_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
  regval  = stm32_getreg(regaddr);
  if ((regval & OTGFS_DOEPCTL_USBAEP) == 0)
    {
-      regval &= ~(OTGFS_DOEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | OTGFS_DIEPCTL_TXFNUM_MASK);
+      if (regval & OTGFS_DOEPCTL_NAKSTS)
+        {
+          regval |= OTGFS_DOEPCTL_CNAK;
+        }
+      
+      regval &= ~(OTGFS_DOEPCTL_MPSIZ_MASK | OTGFS_DOEPCTL_EPTYP_MASK);
      regval |= mpsiz;
      regval |= (eptype << OTGFS_DOEPCTL_EPTYP_SHIFT);
-      regval |= (eptype << OTGFS_DIEPCTL_TXFNUM_SHIFT);
      regval |= (OTGFS_DOEPCTL_SD0PID | OTGFS_DOEPCTL_USBAEP);
      stm32_putreg(regval, regaddr);

@@ -3743,6 +3747,11 @@ static int stm32_epin_configure(FAR struct stm32_ep_s *privep, uint8_t eptype,
  regval  = stm32_getreg(regaddr);
  if ((regval & OTGFS_DIEPCTL_USBAEP) == 0)
    {
+      if (regval & OTGFS_DIEPCTL_NAKSTS)
+        {
+          regval |= OTGFS_DIEPCTL_CNAK;
+        }
+      
      regval &= ~(OTGFS_DIEPCTL_MPSIZ_MASK | OTGFS_DIEPCTL_EPTYP_MASK | OTGFS_DIEPCTL_TXFNUM_MASK);
      regval |= mpsiz;
      regval |= (eptype << OTGFS_DIEPCTL_EPTYP_SHIFT);
@@ -3900,7 +3909,7 @@ static void stm32_epout_disable(FAR struct stm32_ep_s *privep)
 * Name: stm32_epin_disable
 *
 * Description:
- *   Diable an IN endpoint will no longer be used
+ *   Disable an IN endpoint when it will no longer be used
 *
 *******************************************************************************/

@@ -3912,6 +3921,17 @@ static void stm32_epin_disable(FAR struct stm32_ep_s *privep)

  usbtrace(TRACE_EPDISABLE, privep->epphy);

+  /* After USB reset, the endpoint will already be deactivated by the
+   * hardware. Trying to disable again will just hang in the wait.
+   */
+
+  regaddr = STM32_OTGFS_DIEPCTL(privep->epphy);
+  regval  = stm32_getreg(regaddr);
+  if ((regval & OTGFS_DIEPCTL_USBAEP) == 0)
+    {
+      return;
+    }
+
  /* Make sure that there is no pending IPEPNE interrupt (because we are
   * to poll this bit below).
   */
@@ -51,6 +51,7 @@

 #include <nuttx/arch.h>
 #include <nuttx/kmalloc.h>
+#include <nuttx/clock.h>
 #include <nuttx/usb/usb.h>
 #include <nuttx/usb/usbhost.h>

@@ -149,8 +150,8 @@

 #define STM32_READY_DELAY         200000 /* In loop counts */
 #define STM32_FLUSH_DELAY         200000 /* In loop counts */
-#define STM32_SETUP_DELAY         5000   /* In frames */
-#define STM32_DATANAK_DELAY       5000   /* In frames */
+#define STM32_SETUP_DELAY         (5000 / MSEC_PER_TICK) /* 5 seconds in system ticks */
+#define STM32_DATANAK_DELAY       (5000 / MSEC_PER_TICK) /* 5 seconds in system ticks */

 /* Ever-present MIN/MAX macros */

@@ -305,7 +306,9 @@ static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv,
 /* Control/data transfer logic *************************************************/

 static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx);
+#if 0 /* Not used */
 static inline uint16_t stm32_getframe(void);
+#endif
 static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
                                FAR const struct usb_ctrlreq_s *req);
 static int stm32_ctrl_senddata(FAR struct stm32_usbhost_s *priv,
@@ -1182,14 +1185,18 @@ static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx)
 * Name: stm32_getframe
 *
 * Description:
- *   Get the current frame number.
+ *   Get the current frame number.  The frame number (FRNUM) field increments
+ *   when a new SOF is transmitted on the USB, and is cleared to 0 when it
+ *   reaches 0x3fff.
 *
 *******************************************************************************/

+#if 0 /* Not used */
 static inline uint16_t stm32_getframe(void)
 {
  return (uint16_t)(stm32_getreg(STM32_OTGFS_HFNUM) & OTGFS_HFNUM_FRNUM_MASK);
 }
+#endif

 /*******************************************************************************
 * Name: stm32_ctrl_sendsetup
@@ -1203,14 +1210,14 @@ static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,
                                FAR const struct usb_ctrlreq_s *req)
 {
  FAR struct stm32_chan_s *chan;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
  int ret;

  /* Loop while the device reports NAK (and a timeout is not exceeded */

  chan  = &priv->chan[priv->ep0out];
-  start = stm32_getframe();
+  start = clock_systimer();

  do
    {
@@ -1258,7 +1265,7 @@ static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv,

     /* Get the elapsed time (in frames) */

-     elapsed = stm32_getframe() - start;
+     elapsed = clock_systimer() - start;
    }
  while (elapsed < STM32_SETUP_DELAY);

@@ -1367,8 +1374,8 @@ static int stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
                             FAR uint8_t *buffer, size_t buflen)
 {
  FAR struct stm32_chan_s *chan;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
  int ret = OK;

  /* Loop until the transfer completes (i.e., buflen is decremented to zero)
@@ -1379,7 +1386,7 @@ static int stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
  chan->buffer = buffer;
  chan->buflen = buflen;

-  start = stm32_getframe();
+  start = clock_systimer();
  while (chan->buflen > 0)
    {
      /* Set up for the wait BEFORE starting the transfer */
@@ -1447,7 +1454,7 @@ static int stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
           * buffer pointer and buffer size will be unaltered.
           */

-          elapsed = stm32_getframe() - start;
+          elapsed = clock_systimer() - start;
          if (ret != -EAGAIN ||                       /* Not a NAK condition OR */
              elapsed >= STM32_DATANAK_DELAY ||       /* Timeout has elapsed OR */
              chan->buflen != buflen)                 /* Data has been partially transferred */
@@ -1474,8 +1481,8 @@ static int stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
                              FAR uint8_t *buffer, size_t buflen)
 {
  FAR struct stm32_chan_s *chan;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
  size_t xfrlen;
  int ret = OK;

@@ -1484,7 +1491,7 @@ static int stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
   */

  chan         = &priv->chan[chidx];
-  start        = stm32_getframe();
+  start        = clock_systimer();

  while (buflen > 0)
    {
@@ -1569,7 +1576,7 @@ static int stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx,
           * buffer pointer and buffer size will be unaltered.
           */

-          elapsed = stm32_getframe() - start;
+          elapsed = clock_systimer() - start;
          if (ret != -EAGAIN ||                       /* Not a NAK condition OR */
              elapsed >= STM32_DATANAK_DELAY ||       /* Timeout has elapsed OR */
              chan->buflen != xfrlen)                 /* Data has been partially transferred */
@@ -3540,8 +3547,8 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr,
 {
  struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr;
  uint16_t buflen;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
  int retries;
  int ret;

@@ -3573,7 +3580,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr,

      /* Get the start time.  Loop again until the timeout expires */

-      start = stm32_getframe();
+      start = clock_systimer();
      do
        {
          /* Handle the IN data phase (if any) */
@@ -3606,7 +3613,7 @@ static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr,

          /* Get the elapsed time (in frames) */

-          elapsed = stm32_getframe() - start;
+          elapsed = clock_systimer() - start;
        }
      while (elapsed < STM32_DATANAK_DELAY);
    }
@@ -3623,8 +3630,8 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr,
 {
  struct stm32_usbhost_s *priv = (struct stm32_usbhost_s *)drvr;
  uint16_t buflen;
-  uint16_t start;
-  uint16_t elapsed;
+  uint32_t start;
+  uint32_t elapsed;
  int retries;
  int ret;

@@ -3658,7 +3665,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr,

      /* Get the start time.  Loop again until the timeout expires */

-      start = stm32_getframe();
+      start = clock_systimer();
      do
        {
          /* Handle the data OUT phase (if any) */
@@ -3693,7 +3700,7 @@ static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr,

          /* Get the elapsed time (in frames) */

-          elapsed = stm32_getframe() - start;
+          elapsed = clock_systimer() - start;
        }
      while (elapsed < STM32_DATANAK_DELAY);
    }
@@ -607,6 +607,7 @@ static FAR struct stm32_lowerhalf_s *stm32_tim2lower(int tim)
 #endif
 #ifdef CONFIG_STM32_TIM3_QE
    case 3:
+      return &g_tim3lower;
 #endif
 #ifdef CONFIG_STM32_TIM4_QE
    case 4:
@@ -96,6 +96,19 @@
 #    endif
 #  endif

+/* Currently RS-485 support cannot be enabled when RXDMA is in use due to lack
+ * of testing - RS-485 support was developed on STM32F1x
+ */
+
+#  if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \
+      (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \
+      (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \
+      (defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \
+      (defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) || \
+      (defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485))
+#    error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
+#  endif
+
 /* For the F4, there are alternate DMA channels for USART1 and 6.
 * Logic in the board.h file make the DMA channel selection by defining
 * the following in the board.h file.
@@ -219,6 +232,11 @@ struct up_dev_s
  uint32_t          rxdmanext; /* Next byte in the DMA buffer to be read */
  char       *const rxfifo;    /* Receive DMA buffer */
 #endif
+
+#ifdef HAVE_RS485
+  const uint32_t    rs485_dir_gpio; /* U[S]ART RS-485 DIR GPIO pin configuration */
+  const bool        rs485_dir_polarity; /* U[S]ART RS-485 DIR pin state for TX enabled */
+#endif
 };

 /****************************************************************************
@@ -415,6 +433,15 @@ static struct up_dev_s g_usart1priv =
  .rxfifo        = g_usart1rxfifo,
 #endif
  .vector        = up_interrupt_usart1,
+
+#ifdef CONFIG_USART1_RS485
+  .rs485_dir_gpio = GPIO_USART1_RS485_DIR,
+#  if (CONFIG_USART1_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif

@@ -468,6 +495,15 @@ static struct up_dev_s g_usart2priv =
  .rxfifo        = g_usart2rxfifo,
 #endif
  .vector        = up_interrupt_usart2,
+
+#ifdef CONFIG_USART2_RS485
+  .rs485_dir_gpio = GPIO_USART2_RS485_DIR,
+#  if (CONFIG_USART2_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif

@@ -521,6 +557,15 @@ static struct up_dev_s g_usart3priv =
  .rxfifo        = g_usart3rxfifo,
 #endif
  .vector        = up_interrupt_usart3,
+
+#ifdef CONFIG_USART3_RS485
+  .rs485_dir_gpio = GPIO_USART3_RS485_DIR,
+#  if (CONFIG_USART3_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif

@@ -570,6 +615,15 @@ static struct up_dev_s g_uart4priv =
  .rxfifo        = g_uart4rxfifo,
 #endif
  .vector        = up_interrupt_uart4,
+
+#ifdef CONFIG_UART4_RS485
+  .rs485_dir_gpio = GPIO_UART4_RS485_DIR,
+#  if (CONFIG_UART4_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif

@@ -619,6 +673,15 @@ static struct up_dev_s g_uart5priv =
  .rxfifo        = g_uart5rxfifo,
 #endif
  .vector         = up_interrupt_uart5,
+
+#ifdef CONFIG_UART5_RS485
+  .rs485_dir_gpio = GPIO_UART5_RS485_DIR,
+#  if (CONFIG_UART5_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif

@@ -672,6 +735,15 @@ static struct up_dev_s g_usart6priv =
  .rxfifo        = g_usart6rxfifo,
 #endif
  .vector         = up_interrupt_usart6,
+
+#ifdef CONFIG_USART6_RS485
+  .rs485_dir_gpio = GPIO_USART6_RS485_DIR,
+#  if (CONFIG_USART6_RS485_DIR_POLARITY == 0)
+  .rs485_dir_polarity = false,
+#  else
+  .rs485_dir_polarity = true,
+#  endif
+#endif
 };
 #endif

@@ -744,8 +816,8 @@ static void up_restoreusartint(struct up_dev_s *priv, uint16_t ie)
  /* And restore the interrupt state (see the interrupt enable/usage table above) */

  cr = up_serialin(priv, STM32_USART_CR1_OFFSET);
-  cr &= ~(USART_CR1_RXNEIE|USART_CR1_TXEIE|USART_CR1_PEIE);
-  cr |= (ie & (USART_CR1_RXNEIE|USART_CR1_TXEIE|USART_CR1_PEIE));
+  cr &= ~(USART_CR1_USED_INTS);
+  cr |= (ie & (USART_CR1_USED_INTS));
  up_serialout(priv, STM32_USART_CR1_OFFSET, cr);

  cr = up_serialin(priv, STM32_USART_CR3_OFFSET);
@@ -772,7 +844,7 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
       * USART_CR1_IDLEIE    4  USART_SR_IDLE   Idle Line Detected             (not used)
       * USART_CR1_RXNEIE    5  USART_SR_RXNE   Received Data Ready to be Read
       * "              "       USART_SR_ORE    Overrun Error Detected
-       * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete          (not used)
+       * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete          (used only for RS-485)
       * USART_CR1_TXEIE     7  USART_SR_TXE    Transmit Data Register Empty
       * USART_CR1_PEIE      8  USART_SR_PE     Parity Error
       *
@@ -791,7 +863,7 @@ static inline void up_disableusartint(struct up_dev_s *priv, uint16_t *ie)
       * overlap.  This logic would fail if we needed the break interrupt!
       */

-      *ie = (cr1 & (USART_CR1_RXNEIE|USART_CR1_TXEIE|USART_CR1_PEIE)) | (cr3 & USART_CR3_EIE);
+      *ie = (cr1 & (USART_CR1_USED_INTS)) | (cr3 & USART_CR3_EIE);
    }

  /* Disable all interrupts */
@@ -946,6 +1018,14 @@ static int up_setup(struct uart_dev_s *dev)
      stm32_configgpio(priv->rts_gpio);
    }

+#if HAVE_RS485
+  if (priv->rs485_dir_gpio != 0)
+    {
+      stm32_configgpio(priv->rs485_dir_gpio);
+      stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
+    }
+#endif
+
  /* Configure CR2 */
  /* Clear CLKEN, CPOL, CPHA, LBCL, and interrupt enable bits */

@@ -1217,7 +1297,7 @@ static int up_interrupt_common(struct up_dev_s *priv)
       * USART_CR1_IDLEIE    4  USART_SR_IDLE   Idle Line Detected              (not used)
       * USART_CR1_RXNEIE    5  USART_SR_RXNE   Received Data Ready to be Read
       * "              "       USART_SR_ORE    Overrun Error Detected
-       * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete           (not used)
+       * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete           (used only for RS-485)
       * USART_CR1_TXEIE     7  USART_SR_TXE    Transmit Data Register Empty
       * USART_CR1_PEIE      8  USART_SR_PE     Parity Error
       *
@@ -1232,6 +1312,21 @@ static int up_interrupt_common(struct up_dev_s *priv)
       * being used.
       */

+#ifdef HAVE_RS485
+      /* Transmission of whole buffer is over - TC is set, TXEIE is cleared.
+       * Note - this should be first, to have the most recent TC bit value from
+       * SR register - sending data affects TC, but without refresh we will not
+       * know that...
+       */
+
+      if ((priv->sr & USART_SR_TC) != 0 && (priv->ie & USART_CR1_TCIE) != 0 &&
+          (priv->ie & USART_CR1_TXEIE) == 0)
+        {
+          stm32_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity);
+          up_restoreusartint(priv, priv->ie & ~USART_CR1_TCIE);
+        }
+#endif
+
      /* Handle incoming, receive bytes. */

      if ((priv->sr & USART_SR_RXNE) != 0 && (priv->ie & USART_CR1_RXNEIE) != 0)
@@ -1265,13 +1360,14 @@ static int up_interrupt_common(struct up_dev_s *priv)

      if ((priv->sr & USART_SR_TXE) != 0 && (priv->ie & USART_CR1_TXEIE) != 0)
        {
-           /* Transmit data regiser empty ... process outgoing bytes */
+           /* Transmit data register empty ... process outgoing bytes */

           uart_xmitchars(&priv->dev);
           handled = true;
        }
    }
-    return OK;
+
+  return OK;
 }

 /****************************************************************************
@@ -1611,6 +1707,10 @@ static bool up_dma_rxavailable(struct uart_dev_s *dev)
 static void up_send(struct uart_dev_s *dev, int ch)
 {
  struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
+#ifdef HAVE_RS485
+  if (priv->rs485_dir_gpio != 0)
+    stm32_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity);
+#endif
  up_serialout(priv, STM32_USART_DR_OFFSET, (uint32_t)ch);
 }

@@ -1631,7 +1731,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
   *
   * Enable             Bit Status          Meaning                      Usage
   * ------------------ --- --------------- ---------------------------- ----------
-   * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete        (not used)
+   * USART_CR1_TCIE      6  USART_SR_TC     Transmission Complete        (used only for RS-485)
   * USART_CR1_TXEIE     7  USART_SR_TXE    Transmit Data Register Empty
   * USART_CR3_CTSIE    10  USART_SR_CTS    CTS flag                     (not used)
   */
@@ -1642,7 +1742,20 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
      /* Set to receive an interrupt when the TX data register is empty */

 #ifndef CONFIG_SUPPRESS_SERIAL_INTS
-      up_restoreusartint(priv, priv->ie | USART_CR1_TXEIE);
+      uint16_t ie = priv->ie | USART_CR1_TXEIE;
+
+      /* If RS-485 is supported on this U[S]ART, then also enable the
+       * transmission complete interrupt.
+       */
+
+#  ifdef HAVE_RS485
+      if (priv->rs485_dir_gpio != 0)
+        {
+          ie |= USART_CR1_TCIE;
+        }
+#  endif
+
+      up_restoreusartint(priv, ie);

      /* Fake a TX interrupt here by just calling uart_xmitchars() with
       * interrupts disabled (note this may recurse).
@@ -1657,6 +1770,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)

      up_restoreusartint(priv, priv->ie & ~USART_CR1_TXEIE);
    }
+
  irqrestore(flags);
 }

@@ -223,6 +223,20 @@
 #  undef SERIAL_HAVE_ONLY_DMA
 #endif

+/* Is RS-485 used? */
+
+#if defined(CONFIG_USART1_RS485) || defined(CONFIG_USART2_RS485) || \
+    defined(CONFIG_USART3_RS485) || defined(CONFIG_UART4_RS485)  || \
+    defined(CONFIG_UART5_RS485) || defined(CONFIG_USART6_RS485)
+#  define HAVE_RS485 1
+#endif
+
+#ifdef HAVE_RS485
+#  define USART_CR1_USED_INTS    (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE | USART_CR1_TCIE)
+#else
+#  define USART_CR1_USED_INTS    (USART_CR1_RXNEIE | USART_CR1_TXEIE | USART_CR1_PEIE)
+#endif
+
 /************************************************************************************
 * Public Types
 ************************************************************************************/
@@ -92,7 +92,11 @@ static inline void rcc_reset(void)
  putreg32(regval, STM32_RCC_CR);

  regval  = getreg32(STM32_RCC_CFGR);       /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
-  regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK|RCC_CFGR_USBPRE);
+  regval &= ~(RCC_CFGR_PLLSRC|RCC_CFGR_PLLXTPRE|RCC_CFGR_PLLMUL_MASK
+#ifndef CONFIG_STM32_VALUELINE
+              |RCC_CFGR_USBPRE
+#endif
+              );
  putreg32(regval, STM32_RCC_CFGR);

  putreg32(0, STM32_RCC_CIR);               /* Disable all interrupts */
@@ -224,6 +228,27 @@ static inline void rcc_enableapb1(void)
 #endif
 #endif

+#ifdef CONFIG_STM32_TIM12
+  /* Timer 12 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM12EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM13
+  /* Timer 13 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM13EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM14
+  /* Timer 14 clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB1ENR_TIM14EN;
+#endif
+#endif
+
 #ifdef CONFIG_STM32_WWDG
  /* Window Watchdog clock enable */

@@ -315,6 +340,13 @@ static inline void rcc_enableapb1(void)

  regval |= RCC_APB1ENR_DACEN;
 #endif
+
+#ifdef CONFIG_STM32_CEC
+  /* CEC clock enable */
+
+  regval |= RCC_APB1ENR_CECEN;
+#endif
+
  putreg32(regval, STM32_RCC_APB1ENR);
 }

@@ -404,6 +436,28 @@ static inline void rcc_enableapb2(void)

  regval |= RCC_APB2ENR_ADC3EN;
 #endif
+
+#ifdef CONFIG_STM32_TIM15
+  /* TIM15 Timer clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM15EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM16
+  /* TIM16 Timer clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM16EN;
+#endif
+#endif
+
+#ifdef CONFIG_STM32_TIM17
+  /* TIM17 Timer clock enable */
+#ifdef CONFIG_STM32_FORCEPOWER
+  regval |= RCC_APB2ENR_TIM17EN;
+#endif
+#endif
+
  putreg32(regval, STM32_RCC_APB2ENR);
 }

@@ -631,7 +631,11 @@ static void stm32_stdclockconfig(void)

      /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */

+#ifdef STM32_FLASH_PREFETCH
+      regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
+#else
      regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
+#endif
      putreg32(regval, STM32_FLASH_ACR);

      /* Select the main PLL as system clock source */
@@ -633,7 +633,11 @@ static void stm32_stdclockconfig(void)
 
      /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */

+#ifdef STM32_FLASH_PREFETCH
+      regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
+#else
      regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
+#endif
      putreg32(regval, STM32_FLASH_ACR);

      /* Select the main PLL as system clock source */