mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
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Merge commit '0f2decb70f505b108999fcdb80e89d7aae6760ce' into nuttx-merge-0f2decb
This commit is contained in:
px4dev
@@ -0,0 +1,243 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/include/syscall.h
|
||||
*
|
||||
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Reference: "ELF for the ARM® Architecture," ARM IHI 0044D, current through
|
||||
* ABI release 2.08, October 28, 2009, ARM Limited.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_ELF_H
|
||||
#define __ARCH_ARM_INCLUDE_ELF_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* 4.3.1 ELF Identification. Should have:
|
||||
*
|
||||
* e_machine = EM_ARM
|
||||
* e_ident[EI_CLASS] = ELFCLASS32
|
||||
* e_ident[EI_DATA] = ELFDATA2LSB (little endian) or ELFDATA2MSB (big endian)
|
||||
*/
|
||||
|
||||
#if 0 /* Defined in include/elf32.h */
|
||||
#define EM_ARM 40
|
||||
#endif
|
||||
|
||||
/* Table 4-2, ARM-specific e_flags */
|
||||
|
||||
#define EF_ARM_EABI_MASK 0xff000000
|
||||
#define EF_ARM_EABI_UNKNOWN 0x00000000
|
||||
#define EF_ARM_EABI_VER1 0x01000000
|
||||
#define EF_ARM_EABI_VER2 0x02000000
|
||||
#define EF_ARM_EABI_VER3 0x03000000
|
||||
#define EF_ARM_EABI_VER4 0x04000000
|
||||
#define EF_ARM_EABI_VER5 0x05000000
|
||||
|
||||
#define EF_ARM_BE8 0x00800000
|
||||
|
||||
/* Table 4-4, Processor specific section types */
|
||||
|
||||
#define SHT_ARM_EXIDX 0x70000001 /* Exception Index table */
|
||||
#define SHT_ARM_PREEMPTMAP 0x70000002 /* BPABI DLL dynamic linking pre-emption map */
|
||||
#define SHT_ARM_ATTRIBUTES 0x70000003 /* Object file compatibility attributes */
|
||||
#define SHT_ARM_DEBUGOVERLAY 0x70000004
|
||||
#define SHT_ARM_OVERLAYSECTION 0x70000005
|
||||
|
||||
/* 4.7.1 Relocation codes
|
||||
*
|
||||
* S (when used on its own) is the address of the symbol.
|
||||
* A is the addend for the relocation.
|
||||
* P is the address of the place being relocated (derived from r_offset).
|
||||
* Pa is the adjusted address of the place being relocated, defined as (P & 0xFFFFFFFC).
|
||||
* T is 1 if the target symbol S has type STT_FUNC and the symbol addresses a Thumb instruction;
|
||||
* it is 0 otherwise.
|
||||
* B(S) is the addressing origin of the output segment defining the symbol S.
|
||||
* GOT_ORG is the addressing origin of the Global Offset Table
|
||||
* GOT(S) is the address of the GOT entry for the symbol S.
|
||||
*/
|
||||
|
||||
#define R_ARM_NONE 0 /* No relocation */
|
||||
#define R_ARM_PC24 1 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_ABS32 2 /* Data (S + A) | T */
|
||||
#define R_ARM_REL32 3 /* Data ((S + A) | T) - P */
|
||||
#define R_ARM_LDR_PC_G0 4 /* ARM S + A - P */
|
||||
#define R_ARM_ABS16 5 /* Data S + A */
|
||||
#define R_ARM_ABS12 6 /* ARM S + A */
|
||||
#define R_ARM_THM_ABS5 7 /* Thumb16 S + A */
|
||||
#define R_ARM_ABS8 8 /* Data S + A */
|
||||
#define R_ARM_SBREL32 9 /* Data ((S + A) | T) - B(S) */
|
||||
#define R_ARM_THM_CALL 10 /* Thumb32 ((S + A) | T) - P */
|
||||
#define R_ARM_THM_PC8 11 /* Thumb16 S + A - Pa */
|
||||
#define R_ARM_BREL_ADJ 12 /* Data ?B(S) + A */
|
||||
#define R_ARM_TLS_DESC 13 /* Data */
|
||||
#define R_ARM_THM_SWI8 14 /* Obsolete */
|
||||
#define R_ARM_XPC25 15 /* Obsolete */
|
||||
#define R_ARM_THM_XPC22 16 /* Obsolete */
|
||||
#define R_ARM_TLS_DTPMOD32 17 /* Data Module[S] */
|
||||
#define R_ARM_TLS_DTPOFF32 18 /* Data S + A - TLS */
|
||||
#define R_ARM_TLS_TPOFF32 19 /* Data S + A - tp */
|
||||
#define R_ARM_COPY 20 /* Miscellaneous */
|
||||
#define R_ARM_GLOB_DAT 21 /* Data (S + A) | T */
|
||||
#define R_ARM_JUMP_SLOT 22 /* Data (S + A) | T */
|
||||
#define R_ARM_RELATIVE 23 /* Data B(S) + A */
|
||||
#define R_ARM_GOTOFF32 24 /* Data ((S + A) | T) - GOT_ORG */
|
||||
#define R_ARM_BASE_PREL 25 /* Data B(S) + A - P */
|
||||
#define R_ARM_GOT_BREL 26 /* Data GOT(S) + A - GOT_ORG */
|
||||
#define R_ARM_PLT32 27 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_CALL 28 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_JUMP24 29 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_THM_JUMP24 30 /* Thumb32 ((S + A) | T) - P */
|
||||
#define R_ARM_BASE_ABS 31 /* Data B(S) + A */
|
||||
#define R_ARM_ALU_PCREL_7_0 32 /* Obsolete */
|
||||
#define R_ARM_ALU_PCREL_15_8 33 /* Obsolete */
|
||||
#define R_ARM_ALU_PCREL_23_15 34 /* Obsolete */
|
||||
#define R_ARM_LDR_SBREL_11_0_NC 35 /* ARM S + A - B(S) */
|
||||
#define R_ARM_ALU_SBREL_19_12_NC 36 /* ARM S + A - B(S) */
|
||||
#define R_ARM_ALU_SBREL_27_20_CK 37 /* ARM S + A - B(S) */
|
||||
#define R_ARM_TARGET1 38 /* Miscellaneous (S + A) | T or ((S + A) | T) - P */
|
||||
#define R_ARM_SBREL31 39 /* Data ((S + A) | T) - B(S) */
|
||||
#define R_ARM_V4BX 40 /* Miscellaneous */
|
||||
#define R_ARM_TARGET2 41 /* Miscellaneous */
|
||||
#define R_ARM_PREL31 42 /* Data ((S + A) | T) - P */
|
||||
#define R_ARM_MOVW_ABS_NC 43 /* ARM (S + A) | T */
|
||||
#define R_ARM_MOVT_ABS 44 /* ARM S + A */
|
||||
#define R_ARM_MOVW_PREL_NC 45 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_MOVT_PREL 46 /* ARM S + A - P */
|
||||
#define R_ARM_THM_MOVW_ABS_NC 47 /* Thumb32 (S + A) | T */
|
||||
#define R_ARM_THM_MOVT_ABS 48 /* Thumb32 S + A */
|
||||
#define R_ARM_THM_MOVW_PREL_NC 49 /* Thumb32 ((S + A) | T) - P */
|
||||
#define R_ARM_THM_MOVT_PREL 50 /* Thumb32 S + A - P */
|
||||
#define R_ARM_THM_JUMP19 51 /* Thumb32 ((S + A) | T) - P */
|
||||
#define R_ARM_THM_JUMP6 52 /* Thumb16 S + A - P */
|
||||
#define R_ARM_THM_ALU_PREL_11_0 53 /* Thumb32 ((S + A) | T) - Pa */
|
||||
#define R_ARM_THM_PC12 54 /* Thumb32 S + A - Pa */
|
||||
#define R_ARM_ABS32_NOI 55 /* Data S + A */
|
||||
#define R_ARM_REL32_NOI 56 /* Data S + A - P */
|
||||
#define R_ARM_ALU_PC_G0_NC 57 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_ALU_PC_G0 58 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_ALU_PC_G1_NC 59 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_ALU_PC_G1 60 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_ALU_PC_G2 61 /* ARM ((S + A) | T) - P */
|
||||
#define R_ARM_LDR_PC_G1 62 /* ARM S + A - P */
|
||||
#define R_ARM_LDR_PC_G2 63 /* ARM S + A - P */
|
||||
#define R_ARM_LDRS_PC_G0 64 /* ARM S + A - P */
|
||||
#define R_ARM_LDRS_PC_G1 65 /* ARM S + A - P */
|
||||
#define R_ARM_LDRS_PC_G2 66 /* ARM S + A - P */
|
||||
#define R_ARM_LDC_PC_G0 67 /* ARM S + A - P */
|
||||
#define R_ARM_LDC_PC_G1 68 /* ARM S + A - P */
|
||||
#define R_ARM_LDC_PC_G2 69 /* ARM S + A - P */
|
||||
#define R_ARM_ALU_SB_G0_NC 70 /* ARM ((S + A) | T) - B(S) */
|
||||
#define R_ARM_ALU_SB_G0 71 /* ARM ((S + A) | T) - B(S) */
|
||||
#define R_ARM_ALU_SB_G1_NC 72 /* ARM ((S + A) | T) - B(S) */
|
||||
#define R_ARM_ALU_SB_G1 73 /* ARM ((S + A) | T) - B(S) */
|
||||
#define R_ARM_ALU_SB_G2 74 /* ARM ((S + A) | T) - B(S) */
|
||||
#define R_ARM_LDR_SB_G0 75 /* ARM S + A - B(S) */
|
||||
#define R_ARM_LDR_SB_G1 76 /* ARM S + A - B(S) */
|
||||
#define R_ARM_LDR_SB_G2 77 /* ARM S + A - B(S) */
|
||||
#define R_ARM_LDRS_SB_G0 78 /* ARM S + A - B(S) */
|
||||
#define R_ARM_LDRS_SB_G1 79 /* ARM S + A - B(S) */
|
||||
#define R_ARM_LDRS_SB_G2 80 /* ARM S + A - B(S) */
|
||||
#define R_ARM_LDC_SB_G0 81 /* ARM S + A - B(S) */
|
||||
#define R_ARM_LDC_SB_G1 82 /* ARM S + A - B(S) */
|
||||
#define R_ARM_LDC_SB_G2 83 /* ARM S + A - B(S) */
|
||||
#define R_ARM_MOVW_BREL_NC 84 /* ARM ((S + A) | T) - B(S) */
|
||||
#define R_ARM_MOVT_BREL 85 /* ARM S + A - B(S) */
|
||||
#define R_ARM_MOVW_BREL 86 /* ARM ((S + A) | T) - B(S) */
|
||||
#define R_ARM_THM_MOVW_BREL_NC 87 /* Thumb32 ((S + A) | T) - B(S) */
|
||||
#define R_ARM_THM_MOVT_BREL 88 /* Thumb32 S + A - B(S) */
|
||||
#define R_ARM_THM_MOVW_BREL 89 /* Thumb32 ((S + A) | T) - B(S) */
|
||||
#define R_ARM_TLS_GOTDESC 90 /* Data */
|
||||
#define R_ARM_TLS_CALL 91 /* ARM */
|
||||
#define R_ARM_TLS_DESCSEQ 92 /* ARM TLS relaxation */
|
||||
#define R_ARM_THM_TLS_CALL 93 /* Thumb32 */
|
||||
#define R_ARM_PLT32_ABS 94 /* Data PLT(S) + A */
|
||||
#define R_ARM_GOT_ABS 95 /* Data GOT(S) + A */
|
||||
#define R_ARM_GOT_PREL 96 /* Data GOT(S) + A - P */
|
||||
#define R_ARM_GOT_BREL12 97 /* ARM GOT(S) + A - GOT_ORG */
|
||||
#define R_ARM_GOTOFF12 98 /* ARM S + A - GOT_ORG */
|
||||
#define R_ARM_GOTRELAX 99 /* Miscellaneous */
|
||||
#define R_ARM_GNU_VTENTRY 100 /* Data */
|
||||
#define R_ARM_GNU_VTINHERIT 101 /* Data */
|
||||
#define R_ARM_THM_JUMP11 102 /* Thumb16 S + A - P */
|
||||
#define R_ARM_THM_JUMP8 103 /* Thumb16 S + A - P */
|
||||
#define R_ARM_TLS_GD32 104 /* Data GOT(S) + A - P */
|
||||
#define R_ARM_TLS_LDM32 105 /* Data GOT(S) + A - P */
|
||||
#define R_ARM_TLS_LDO32 106 /* Data S + A - TLS */
|
||||
#define R_ARM_TLS_IE32 107 /* Data GOT(S) + A - P */
|
||||
#define R_ARM_TLS_LE32 108 /* Data S + A - tp */
|
||||
#define R_ARM_TLS_LDO12 109 /* ARM S + A - TLS */
|
||||
#define R_ARM_TLS_LE12 110 /* ARM S + A - tp */
|
||||
#define R_ARM_TLS_IE12GP 111 /* ARM GOT(S) + A - GOT_ORG */
|
||||
#define R_ARM_ME_TOO 128 /* Obsolete */
|
||||
#define R_ARM_THM_TLS_DESCSEQ16 129 /* Thumb16 */
|
||||
#define R_ARM_THM_TLS_DESCSEQ32 130 /* Thumb32 */
|
||||
|
||||
/* 5.2.1 Platform architecture compatibility data */
|
||||
|
||||
#define PT_ARM_ARCHEXT_FMTMSK 0xff000000
|
||||
#define PT_ARM_ARCHEXT_PROFMSK 0x00ff0000
|
||||
#define PT_ARM_ARCHEXT_ARCHMSK 0x000000ff
|
||||
|
||||
#define PT_ARM_ARCHEXT_FMT_OS 0x00000000
|
||||
#define PT_ARM_ARCHEXT_FMT_ABI 0x01000000
|
||||
|
||||
#define PT_ARM_ARCHEXT_PROF_NONE 0x00000000
|
||||
#define PT_ARM_ARCHEXT_PROF_ARM 0x00410000
|
||||
#define PT_ARM_ARCHEXT_PROF_RT 0x00520000
|
||||
#define PT_ARM_ARCHEXT_PROF_MC 0x004d0000
|
||||
#define PT_ARM_ARCHEXT_PROF_CLASSIC 0x00530000
|
||||
|
||||
#define PT_ARM_ARCHEXT_ARCH_UNKNOWN 0x00
|
||||
#define PT_ARM_ARCHEXT_ARCHv4 0x01
|
||||
#define PT_ARM_ARCHEXT_ARCHv4T 0x02
|
||||
#define PT_ARM_ARCHEXT_ARCHv5T 0x03
|
||||
#define PT_ARM_ARCHEXT_ARCHv5TE 0x04
|
||||
#define PT_ARM_ARCHEXT_ARCHv5TEJ 0x05
|
||||
#define PT_ARM_ARCHEXT_ARCHv6 0x06
|
||||
#define PT_ARM_ARCHEXT_ARCHv6KZ 0x07
|
||||
#define PT_ARM_ARCHEXT_ARCHv6T2 0x08
|
||||
#define PT_ARM_ARCHEXT_ARCHv6K 0x09
|
||||
#define PT_ARM_ARCHEXT_ARCHv7 0x0a
|
||||
#define PT_ARM_ARCHEXT_ARCHv6M 0x0b
|
||||
#define PT_ARM_ARCHEXT_ARCHv6SM 0x0c
|
||||
#define PT_ARM_ARCHEXT_ARCHv7EM 0x0d
|
||||
|
||||
/* Table 5-6, ARM-specific dynamic array tags */
|
||||
|
||||
#define DT_ARM_RESERVED1 0x70000000
|
||||
#define DT_ARM_SYMTABSZ 0x70000001
|
||||
#define DT_ARM_PREEMPTMAP 0x70000002
|
||||
#define DT_ARM_RESERVED2 0x70000003
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_ELF_H */
|
||||
@@ -45,37 +45,42 @@
|
||||
****************************************************************************/
|
||||
|
||||
#define CHAR_BIT 8
|
||||
#define SCHAR_MIN (-128)
|
||||
#define SCHAR_MAX 127
|
||||
#define UCHAR_MAX 0xff
|
||||
#define SCHAR_MIN (-SCHAR_MAX - 1)
|
||||
#define SCHAR_MAX 127
|
||||
#define UCHAR_MAX 255
|
||||
|
||||
/* These could be different on machines where char is unsigned */
|
||||
|
||||
#ifdef __CHAR_UNSIGNED__
|
||||
#define CHAR_MIN 0
|
||||
#define CHAR_MAX UCHAR_MAX
|
||||
#else
|
||||
#define CHAR_MIN SCHAR_MIN
|
||||
#define CHAR_MAX SCHAR_MAX
|
||||
#endif
|
||||
|
||||
#define SHRT_MIN 0x8000
|
||||
#define SHRT_MAX 0x7fff
|
||||
#define USHRT_MAX 0xffff
|
||||
#define SHRT_MIN (-SHRT_MAX - 1)
|
||||
#define SHRT_MAX 32767
|
||||
#define USHRT_MAX 65535U
|
||||
|
||||
#define INT_MIN 0x80000000
|
||||
#define INT_MAX 0x7fffffff
|
||||
#define UINT_MAX 0xffffffff
|
||||
#define INT_MIN (-INT_MAX - 1)
|
||||
#define INT_MAX 2147483647
|
||||
#define UINT_MAX 4294967295U
|
||||
|
||||
/* These change on 32-bit and 64-bit platforms */
|
||||
|
||||
#define LONG_MAX 0x80000000
|
||||
#define LONG_MIN 0x7fffffff
|
||||
#define ULONG_MAX 0xffffffff
|
||||
#define LONG_MIN (-LONG_MAX - 1)
|
||||
#define LONG_MAX 2147483647L
|
||||
#define ULONG_MAX 4294967295UL
|
||||
|
||||
#define LLONG_MAX 0x8000000000000000
|
||||
#define LLONG_MIN 0x7fffffffffffffff
|
||||
#define ULLONG_MAX 0xffffffffffffffff
|
||||
#define LLONG_MIN (-LLONG_MAX - 1)
|
||||
#define LLONG_MAX 9223372036854775807LL
|
||||
#define ULLONG_MAX 18446744073709551615ULL
|
||||
|
||||
/* A pointer is 4 bytes */
|
||||
|
||||
#define PTR_MIN 0x80000000
|
||||
#define PTR_MAX 0x7fffffff
|
||||
#define UPTR_MAX 0xffffffff
|
||||
#define PTR_MIN (-PTR_MAX - 1)
|
||||
#define PTR_MAX 2147483647
|
||||
#define UPTR_MAX 4294967295U
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LIMITS_H */
|
||||
|
||||
@@ -59,12 +59,11 @@
|
||||
/* STM32 F100 Value Line ************************************************************/
|
||||
|
||||
#if defined(CONFIG_ARCH_CHIP_STM32F100C8) || defined(CONFIG_ARCH_CHIP_STM32F100CB) \
|
||||
|| defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB) \
|
||||
|| defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB)
|
||||
|| defined(CONFIG_ARCH_CHIP_STM32F100R8) || defined(CONFIG_ARCH_CHIP_STM32F100RB)
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -72,15 +71,110 @@
|
||||
# define STM32_NFSMC 0 /* FSMC */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM 3 /* 16-bit general timers TIM2,3,4 with DMA */
|
||||
# define STM32_NBTIM 0 /* No basic timers */
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
|
||||
// TODO: there are also 3 additional timers (15-17) that don't fit any existing category
|
||||
# define STM32_NDMA 1 /* DMA1 */
|
||||
# define STM32_NSPI 2 /* SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S (?) */
|
||||
# define STM32_NI2S 0 /* No I2S */
|
||||
# define STM32_NUSART 3 /* USART1-3 */
|
||||
# define STM32_NI2C 2 /* I2C1-2 */
|
||||
# define STM32_NCAN 0 /* No CAN */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
|
||||
# define STM32_NGPIO 64 /* GPIOA-D */
|
||||
# define STM32_NADC 1 /* ADC1 */
|
||||
# define STM32_NDAC 2 /* DAC 1-2 */
|
||||
# define STM32_NCRC 1 /* CRC1 */
|
||||
# define STM32_NETHERNET 0 /* No ethernet */
|
||||
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F100V8) || defined(CONFIG_ARCH_CHIP_STM32F100VB)
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# define CONFIG_STM32_MEDIUMDENSITY 1 /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
|
||||
# define STM32_NFSMC 0 /* FSMC */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM 3 /* 16-bit general timers TIM2,3,4 with DMA */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
|
||||
// TODO: there are also 3 additional timers (15-17) that don't fit any existing category
|
||||
# define STM32_NDMA 1 /* DMA1 */
|
||||
# define STM32_NSPI 2 /* SPI1-2 */
|
||||
# define STM32_NI2S 0 /* No I2S */
|
||||
# define STM32_NUSART 3 /* USART1-3 */
|
||||
# define STM32_NI2C 2 /* I2C1-2 */
|
||||
# define STM32_NCAN 0 /* No CAN */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
|
||||
# define STM32_NGPIO 80 /* GPIOA-E */
|
||||
# define STM32_NADC 1 /* ADC1 */
|
||||
# define STM32_NDAC 2 /* DAC 1-2 */
|
||||
# define STM32_NCRC 1 /* CRC1 */
|
||||
# define STM32_NETHERNET 0 /* No ethernet */
|
||||
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
/* STM32 F100 High-density value Line ************************************************************/
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F100RC) || defined(CONFIG_ARCH_CHIP_STM32F100RD) \
|
||||
|| defined(CONFIG_ARCH_CHIP_STM32F100RE)
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
|
||||
# define STM32_NFSMC 0 /* FSMC */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
|
||||
// TODO: there are also 6 additional timers (12-17) that don't fit any existing category
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NSPI 3 /* SPI1-3 */
|
||||
# define STM32_NI2S 0 /* No I2S */
|
||||
# define STM32_NUSART 5 /* USART1-5 */
|
||||
# define STM32_NI2C 2 /* I2C1-2 */
|
||||
# define STM32_NCAN 0 /* No CAN */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
|
||||
# define STM32_NGPIO 64 /* GPIOA-D */
|
||||
# define STM32_NADC 1 /* ADC1 */
|
||||
# define STM32_NDAC 2 /* DAC 1-2 */
|
||||
# define STM32_NCRC 1 /* CRC1 */
|
||||
# define STM32_NETHERNET 0 /* No ethernet */
|
||||
# define STM32_NRNG 0 /* No random number generator (RNG) */
|
||||
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F100VC) || defined(CONFIG_ARCH_CHIP_STM32F100VD) \
|
||||
|| defined(CONFIG_ARCH_CHIP_STM32F100VE)
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# define CONFIG_STM32_VALUELINE 1 /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
|
||||
# define STM32_NFSMC 1 /* FSMC */
|
||||
# define STM32_NATIM 1 /* One advanced timer TIM1 */
|
||||
# define STM32_NGTIM 4 /* 16-bit general timers TIM2,3,4,5 with DMA */
|
||||
# define STM32_NBTIM 2 /* 2 basic timers: TIM6, TIM7 */
|
||||
// TODO: there are also 6 additional timers (12-17) that don't fit any existing category
|
||||
# define STM32_NDMA 2 /* DMA1-2 */
|
||||
# define STM32_NSPI 3 /* SPI1-3 */
|
||||
# define STM32_NI2S 0 /* No I2S */
|
||||
# define STM32_NUSART 5 /* USART1-5 */
|
||||
# define STM32_NI2C 2 /* I2C1-2 */
|
||||
# define STM32_NCAN 0 /* No CAN */
|
||||
# define STM32_NSDIO 0 /* No SDIO */
|
||||
# define STM32_NUSBOTG 0 /* No USB OTG FS/HS */
|
||||
# define STM32_NGPIO 80 /* GPIOA-E */
|
||||
# define STM32_NADC 1 /* ADC1 */
|
||||
# define STM32_NDAC 2 /* DAC 1-2 */
|
||||
@@ -96,9 +190,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -129,9 +223,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F103VCT6) || defined(CONFIG_ARCH_CHIP_STM32F103VET6)
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -162,9 +256,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# define CONFIG_STM32_HIGHDENSITY 1 /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -192,9 +286,9 @@
|
||||
/* STM32 F105/F107 Connectivity Line *******************************************************/
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F105VBT7)
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -221,9 +315,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
|
||||
# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -251,9 +345,9 @@
|
||||
/* STM32 F2 Family ******************************************************************/
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F207IG) /* UFBGA-176 1024Kb FLASH 128Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */
|
||||
@@ -283,9 +377,9 @@
|
||||
/* STM23 F4 Family ******************************************************************/
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F405RG) /* LQFP 64 10x10x1.4 1024Kb FLASH 192Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -314,9 +408,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F405VG) /* LQFP 100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -345,9 +439,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F405ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -376,9 +470,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F407VE) /* LQFP-100 512Kb FLASH 192Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -407,9 +501,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F407VG) /* LQFP-100 14x14x1.4 1024Kb FLASH 192Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -438,9 +532,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZE) /* LQFP-144 512Kb FLASH 192Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -469,9 +563,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F407ZG) /* LQFP 144 20x20x1.4 1024Kb FLASH 192Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -500,9 +594,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F407IE) /* LQFP 176 24x24x1.4 512Kb FLASH 192Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
@@ -531,9 +625,9 @@
|
||||
|
||||
#elif defined(CONFIG_ARCH_CHIP_STM32F407IG) /* BGA 176; LQFP 176 24x24x1.4 1024Kb FLASH 192Kb SRAM */
|
||||
# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F101x and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
|
||||
# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
|
||||
# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
|
||||
# undef CONFIG_STM32_VALUELINE /* STM32F100x */
|
||||
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
|
||||
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
|
||||
|
||||
@@ -61,11 +61,13 @@
|
||||
* External interrupts (vectors >= 16)
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_VALUELINE) && defined(CONFIG_STM32_MEDIUMDENSITY)
|
||||
/* Value line devices */
|
||||
|
||||
#if defined(CONFIG_STM32_VALUELINE)
|
||||
# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
|
||||
# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
|
||||
# define STM32_IRQ_TAMPER (18) /* 2: Tamper interrupt */
|
||||
# define STM32_IRQ_RTC (19) /* 3: RTC global interrupt */
|
||||
# define STM32_IRQ_RTC (19) /* 3: RTC Wakeup through EXTI line interrupt */
|
||||
# define STM32_IRQ_FLASH (20) /* 4: Flash global interrupt */
|
||||
# define STM32_IRQ_RCC (21) /* 5: RCC global interrupt */
|
||||
# define STM32_IRQ_EXTI0 (22) /* 6: EXTI Line 0 interrupt */
|
||||
@@ -80,12 +82,18 @@
|
||||
# define STM32_IRQ_DMA1CH5 (31) /* 15: DMA1 Channel 5 global interrupt */
|
||||
# define STM32_IRQ_DMA1CH6 (32) /* 16: DMA1 Channel 6 global interrupt */
|
||||
# define STM32_IRQ_DMA1CH7 (33) /* 17: DMA1 Channel 7 global interrupt */
|
||||
# define STM32_IRQ_ADC12 (34) /* 18: ADC1 and ADC2 global interrupt */
|
||||
/* 19-22: reserved */
|
||||
# define STM32_IRQ_ADC1 (34) /* 18: ADC1 global interrupt */
|
||||
# define STM32_IRQ_RESERVED0 (35) /* 19: Reserved 0 */
|
||||
# define STM32_IRQ_RESERVED1 (36) /* 20: Reserved 1 */
|
||||
# define STM32_IRQ_RESERVED2 (37) /* 21: Reserved 2 */
|
||||
# define STM32_IRQ_RESERVED3 (38) /* 22: Reserved 3 */
|
||||
# define STM32_IRQ_EXTI95 (39) /* 23: EXTI Line[9:5] interrupts */
|
||||
# define STM32_IRQ_TIM1BRK (40) /* 24: TIM1 Break interrupt */
|
||||
# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt (TIM16 global interrupt) */
|
||||
# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts (TIM17 global interrupt) */
|
||||
# define STM32_IRQ_TIM15 (40) /* TIM15 global interrupt */
|
||||
# define STM32_IRQ_TIM1UP (41) /* 25: TIM1 Update interrupt */
|
||||
# define STM32_IRQ_TIM16 (41) /* TIM16 global interrupt */
|
||||
# define STM32_IRQ_TIM1TRGCOM (42) /* 26: TIM1 Trigger and Commutation interrupts */
|
||||
# define STM32_IRQ_TIM17 (42) /* TIM17 global interrupt */
|
||||
# define STM32_IRQ_TIM1CC (43) /* 27: TIM1 Capture Compare interrupt */
|
||||
# define STM32_IRQ_TIM2 (44) /* 28: TIM2 global interrupt */
|
||||
# define STM32_IRQ_TIM3 (45) /* 29: TIM3 global interrupt */
|
||||
@@ -100,29 +108,30 @@
|
||||
# define STM32_IRQ_USART2 (54) /* 38: USART2 global interrupt */
|
||||
# define STM32_IRQ_USART3 (55) /* 39: USART3 global interrupt */
|
||||
# define STM32_IRQ_EXTI1510 (56) /* 40: EXTI Line[15:10] interrupts */
|
||||
# define STM32_IRQ_RTCALR (57) /* 41: RTC alarm through EXTI line interrupt */
|
||||
# define STM32_IRQ_RTCALR (57) /* 41: RTC alarms (A and B) through EXTI line interrupt */
|
||||
# define STM32_IRQ_CEC (58) /* 42: CEC global interrupt */
|
||||
# if defined(CONFIG_STM32_HIGHDENSITY)
|
||||
# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */
|
||||
# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */
|
||||
# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */
|
||||
/* 46-47: reserved */
|
||||
# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */
|
||||
/* 49: reserved */
|
||||
# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
|
||||
# define STM32_IRQ_SPI3 (67) /* 51: SPI1 global interrupt */
|
||||
# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
|
||||
# define STM32_IRQ_UART5 (69) /* 53: USART3 global interrupt */
|
||||
# else
|
||||
/* 43-53: reserved */
|
||||
# endif
|
||||
# define STM32_IRQ_TIM12 (59) /* 43: TIM12 global interrupt */
|
||||
# define STM32_IRQ_TIM13 (60) /* 44: TIM13 global interrupt */
|
||||
# define STM32_IRQ_TIM14 (61) /* 45: TIM14 global interrupt */
|
||||
# define STM32_IRQ_RESERVED4 (62) /* 46: Reserved 4 */
|
||||
# define STM32_IRQ_RESERVED5 (63) /* 47: Reserved 5 */
|
||||
# define STM32_IRQ_FSMC (64) /* 48: FSMC global interrupt */
|
||||
# define STM32_IRQ_RESERVED6 (65) /* 49: Reserved 6 */
|
||||
# define STM32_IRQ_TIM5 (66) /* 50: TIM5 global interrupt */
|
||||
# define STM32_IRQ_SPI3 (67) /* 51: SPI3 global interrupt */
|
||||
# define STM32_IRQ_UART4 (68) /* 52: USART2 global interrupt */
|
||||
# define STM32_IRQ_UART5 (69) /* 53: USART5 global interrupt */
|
||||
# define STM32_IRQ_TIM6 (70) /* 54: TIM6 global interrupt */
|
||||
# define STM32_IRQ_TIM7 (71) /* 55: TIM7 global interrupt */
|
||||
# define STM32_IRQ_DMA2CH1 (72) /* 56: DMA2 Channel 1 global interrupt */
|
||||
# define STM32_IRQ_DMA2CH2 (73) /* 57: DMA2 Channel 2 global interrupt */
|
||||
# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
|
||||
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 global interrupt */
|
||||
# define NR_IRQS (76)
|
||||
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */
|
||||
# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */
|
||||
# define NR_IRQS (77)
|
||||
|
||||
/* Connectivity Line Devices */
|
||||
|
||||
#elif defined(CONFIG_STM32_CONNECTIVITYLINE)
|
||||
# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
|
||||
# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
|
||||
@@ -193,6 +202,9 @@
|
||||
# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
|
||||
# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
|
||||
# define NR_IRQS (84)
|
||||
|
||||
/* Medium and High Density Devices */
|
||||
|
||||
#else
|
||||
# define STM32_IRQ_WWDG (16) /* 0: Window Watchdog interrupt */
|
||||
# define STM32_IRQ_PVD (17) /* 1: PVD through EXTI Line detection interrupt */
|
||||
|
||||
Reference in New Issue
Block a user