From d8b6b2a5ad706f740cda9e9b2d685eeb481e5ee2 Mon Sep 17 00:00:00 2001 From: Peter van der Perk Date: Sat, 1 Jun 2024 19:35:17 +0200 Subject: [PATCH] [BACKPORT] fmu-v6xrt: Fix flash configuration Fixes correct dummy cycle count of 20 --- boards/px4/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/boards/px4/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c b/boards/px4/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c index 6ae7589d60..dfdf13da6d 100644 --- a/boards/px4/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c +++ b/boards/px4/fmu-v6xrt/src/imxrt_flexspi_nor_flash.c @@ -104,9 +104,10 @@ const struct flexspi_nor_config_s g_flash_fast_config = { .busyBitPolarity = 0u, .lookupTable = { - /* Read */// EEH+11H+32bit addr+20dummy cycles+ 4Bytes read data //200Mhz 18 dummy=10+8 + /* Read */// EEH+11H+32bit addr+20dummy cycles+ 4Bytes read data + /* Macronix manual says 20 dummy cycles @ 200Mhz, FlexSPI peripheral Operand value needs to be 2N in DDR mode hence 0x28 */ [0 + 0] = FLEXSPI_LUT_SEQ(CMD_DDR, FLEXSPI_8PAD, 0xEE, CMD_DDR, FLEXSPI_8PAD, 0x11), //0x871187ee, - [0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x04),//0xb3048b20, + [0 + 1] = FLEXSPI_LUT_SEQ(RADDR_DDR, FLEXSPI_8PAD, 0x20, DUMMY_DDR, FLEXSPI_8PAD, 0x28),//0xb3288b20, [0 + 2] = FLEXSPI_LUT_SEQ(READ_DDR, FLEXSPI_8PAD, 0x04, STOP_EXE, FLEXSPI_1PAD, 0x00), //0xa704, /* Read status */