mirror of
https://gitee.com/mirrors_PX4/PX4-Autopilot.git
synced 2026-04-28 17:24:09 +08:00
invensense/mpu6000 refactor to be consistent with new icm20602, icm20608g, etc
- always check FIFO count before transfer even with data ready - interupt pin set active low and latch - relax retry timeout if configure failed - improve configured empty rate (sample rate) rounding - check FIFO count as part of full transfer and reset or adjust timing if necessary
This commit is contained in:
Daniel Agar
parent
279d06ee50
commit
d55c3d80f3
@ -39,6 +39,7 @@ px4_add_module(
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MPU6000.cpp
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MPU6000.hpp
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mpu6000_main.cpp
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InvenSense_MPU6000_registers.hpp
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DEPENDS
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drivers_accelerometer
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drivers_gyroscope
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@ -40,6 +40,8 @@
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#pragma once
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#include <cstdint>
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// TODO: move to a central header
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static constexpr uint8_t Bit0 = (1 << 0);
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static constexpr uint8_t Bit1 = (1 << 1);
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@ -52,25 +54,33 @@ static constexpr uint8_t Bit7 = (1 << 7);
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namespace InvenSense_MPU6000
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{
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static constexpr uint32_t SPI_SPEED = 20 * 1000 * 1000;
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static constexpr uint32_t SPI_SPEED = 1 * 1000 * 1000;
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static constexpr uint32_t SPI_SPEED_SENSOR = 10 * 1000 * 1000; // 20MHz for reading sensor and interrupt registers
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static constexpr uint8_t DIR_READ = 0x80;
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static constexpr uint8_t WHOAMI = 0x68;
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static constexpr float TEMPERATURE_SENSITIVITY = 326.8f; // LSB/C
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static constexpr float ROOM_TEMPERATURE_OFFSET = 25.f; // C
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enum class Register : uint8_t {
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CONFIG = 0x1A,
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GYRO_CONFIG = 0x1B,
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ACCEL_CONFIG = 0x1C,
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FIFO_EN = 0x23,
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I2C_MST_CTRL = 0x24,
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INT_PIN_CFG = 0x37,
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INT_ENABLE = 0x38,
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INT_STATUS = 0x3A,
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INT_ENABLE = 0x38,
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TEMP_OUT_H = 0x41,
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TEMP_OUT_L = 0x42,
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SIGNAL_PATH_RESET = 0x68,
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USER_CTRL = 0x6A,
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PWR_MGMT_1 = 0x6B,
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@ -112,6 +122,14 @@ enum FIFO_EN_BIT : uint8_t {
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ACCEL_FIFO_EN = Bit3,
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};
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// INT_PIN_CFG
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enum INT_PIN_CFG_BIT : uint8_t {
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INT_LEVEL = Bit7,
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INT_RD_CLEAR = Bit4,
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};
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// INT_ENABLE
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enum INT_ENABLE_BIT : uint8_t {
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FIFO_OFLOW_EN = Bit4,
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@ -124,22 +142,34 @@ enum INT_STATUS_BIT : uint8_t {
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DATA_RDY_INT = Bit0,
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};
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// SIGNAL_PATH_RESET
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enum SIGNAL_PATH_RESET_BIT : uint8_t {
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GYRO_RESET = Bit2,
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ACCEL_RESET = Bit1,
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TEMP_RESET = Bit0,
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};
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// USER_CTRL
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enum USER_CTRL_BIT : uint8_t {
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FIFO_EN = Bit6,
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FIFO_RESET = Bit2,
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FIFO_EN = Bit6,
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I2C_MST_EN = Bit5,
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I2C_IF_DIS = Bit4,
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FIFO_RESET = Bit2,
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SIG_COND_RESET = Bit0,
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};
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// PWR_MGMT_1
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enum PWR_MGMT_1_BIT : uint8_t {
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DEVICE_RESET = Bit7,
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SLEEP = Bit6,
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CLKSEL_2 = Bit2,
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CLKSEL_1 = Bit1,
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CLKSEL_0 = Bit0,
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CLKSEL_2 = Bit2,
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CLKSEL_1 = Bit1,
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CLKSEL_0 = Bit0,
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};
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namespace FIFO
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{
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static constexpr size_t SIZE = 1024;
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@ -34,43 +34,83 @@
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#include "MPU6000.hpp"
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using namespace time_literals;
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using namespace InvenSense_MPU6000;
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static constexpr int16_t combine(uint8_t msb, uint8_t lsb) { return (msb << 8u) | lsb; }
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static constexpr uint32_t GYRO_RATE{8000}; // 8 kHz gyro
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static constexpr uint32_t ACCEL_RATE{1000}; // 1 kHz accel
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static constexpr uint32_t FIFO_INTERVAL{1000}; // 1000 us / 1000 Hz interval
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static constexpr uint32_t FIFO_GYRO_SAMPLES{FIFO_INTERVAL / (1000000 / GYRO_RATE)};
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static constexpr uint32_t FIFO_ACCEL_SAMPLES{FIFO_INTERVAL / (1000000 / ACCEL_RATE)};
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static constexpr int16_t combine(uint8_t msb, uint8_t lsb)
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{
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return (msb << 8u) | lsb;
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}
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MPU6000::MPU6000(I2CSPIBusOption bus_option, int bus, uint32_t device, enum Rotation rotation, int bus_frequency,
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spi_mode_e spi_mode, spi_drdy_gpio_t drdy_gpio) :
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SPI(MODULE_NAME, nullptr, bus, device, spi_mode, bus_frequency),
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I2CSPIDriver(MODULE_NAME, px4::device_bus_to_wq(get_device_id()), bus_option, bus),
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_drdy_gpio(drdy_gpio),
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_px4_accel(get_device_id(), ORB_PRIO_VERY_HIGH, rotation),
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_px4_gyro(get_device_id(), ORB_PRIO_VERY_HIGH, rotation)
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_px4_accel(get_device_id(), ORB_PRIO_HIGH, rotation),
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_px4_gyro(get_device_id(), ORB_PRIO_HIGH, rotation)
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{
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set_device_type(DRV_IMU_DEVTYPE_MPU6000);
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_px4_accel.set_device_type(DRV_IMU_DEVTYPE_MPU6000);
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_px4_gyro.set_device_type(DRV_IMU_DEVTYPE_MPU6000);
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_px4_accel.set_update_rate(1000000 / FIFO_INTERVAL);
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_px4_gyro.set_update_rate(1000000 / FIFO_INTERVAL);
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ConfigureSampleRate(_px4_gyro.get_max_rate_hz());
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}
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MPU6000::~MPU6000()
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{
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perf_free(_transfer_perf);
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perf_free(_bad_register_perf);
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perf_free(_bad_transfer_perf);
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perf_free(_fifo_empty_perf);
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perf_free(_fifo_overflow_perf);
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perf_free(_fifo_reset_perf);
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perf_free(_drdy_interval_perf);
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}
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int MPU6000::init()
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{
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int ret = SPI::init();
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if (ret != PX4_OK) {
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DEVICE_DEBUG("SPI::init failed (%i)", ret);
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return ret;
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}
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return Reset() ? 0 : -1;
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}
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bool MPU6000::Reset()
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{
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_state = STATE::RESET;
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ScheduleClear();
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ScheduleNow();
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return true;
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}
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void MPU6000::exit_and_cleanup()
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{
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DataReadyInterruptDisable();
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I2CSPIDriverBase::exit_and_cleanup();
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}
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void MPU6000::print_status()
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{
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I2CSPIDriverBase::print_status();
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PX4_INFO("FIFO empty interval: %d us (%.3f Hz)", _fifo_empty_interval_us,
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static_cast<double>(1000000 / _fifo_empty_interval_us));
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perf_print_counter(_transfer_perf);
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perf_print_counter(_bad_register_perf);
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perf_print_counter(_bad_transfer_perf);
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perf_print_counter(_fifo_empty_perf);
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perf_print_counter(_fifo_overflow_perf);
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perf_print_counter(_fifo_reset_perf);
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perf_print_counter(_drdy_interval_perf);
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_px4_accel.print_status();
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_px4_gyro.print_status();
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}
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int MPU6000::probe()
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{
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const uint8_t whoami = RegisterRead(Register::WHO_AM_I);
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@ -83,126 +123,232 @@ int MPU6000::probe()
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return PX4_OK;
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}
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void MPU6000::exit_and_cleanup()
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void MPU6000::RunImpl()
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{
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if (_drdy_gpio != 0) {
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// Disable data ready callback
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px4_arch_gpiosetevent(_drdy_gpio, false, false, false, nullptr, nullptr);
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RegisterClearBits(Register::INT_ENABLE, INT_ENABLE_BIT::DATA_RDY_INT_EN);
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}
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switch (_state) {
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case STATE::RESET:
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// PWR_MGMT_1: Device Reset
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RegisterWrite(Register::PWR_MGMT_1, PWR_MGMT_1_BIT::DEVICE_RESET);
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_reset_timestamp = hrt_absolute_time();
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_state = STATE::WAIT_FOR_RESET;
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ScheduleDelayed(100_ms);
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break;
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I2CSPIDriverBase::exit_and_cleanup();
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}
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case STATE::WAIT_FOR_RESET:
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int MPU6000::init()
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{
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int ret = SPI::init();
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// The reset value is 0x00 for all registers other than the registers below
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// Document Number: RM-MPU-6000A-00 Page 8 of 46
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if ((RegisterRead(Register::WHO_AM_I) == WHOAMI)
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&& (RegisterRead(Register::PWR_MGMT_1) == 0x40)) {
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if (ret != PX4_OK) {
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DEVICE_DEBUG("SPI::init failed (%i)", ret);
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return ret;
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}
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// SIGNAL_PATH_RESET: ensure the reset is performed properly
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RegisterWrite(Register::SIGNAL_PATH_RESET,
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SIGNAL_PATH_RESET_BIT::GYRO_RESET | SIGNAL_PATH_RESET_BIT::ACCEL_RESET | SIGNAL_PATH_RESET_BIT::TEMP_RESET);
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if (!Reset()) {
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DEVICE_DEBUG("reset failed");
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return PX4_ERROR;
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}
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// if reset succeeded then configure
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_state = STATE::CONFIGURE;
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ScheduleDelayed(100_ms);
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Start();
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} else {
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// RESET not complete
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if (hrt_elapsed_time(&_reset_timestamp) > 100_ms) {
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PX4_DEBUG("Reset failed, retrying");
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_state = STATE::RESET;
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ScheduleDelayed(100_ms);
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return PX4_OK;
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}
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} else {
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PX4_DEBUG("Reset not complete, check again in 10 ms");
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ScheduleDelayed(10_ms);
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}
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}
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bool MPU6000::Reset()
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{
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// PWR_MGMT_1: Device Reset
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// CLKSEL[2:0] must be set to 001 to achieve full gyroscope performance.
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RegisterWrite(Register::PWR_MGMT_1, PWR_MGMT_1_BIT::DEVICE_RESET);
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usleep(2000);
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break;
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// PWR_MGMT_1: CLKSEL[2:0] must be set to 001 to achieve full gyroscope performance.
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RegisterWrite(Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0);
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usleep(100);
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case STATE::CONFIGURE:
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if (Configure()) {
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// if configure succeeded then start reading from FIFO
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_state = STATE::FIFO_READ;
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// ACCEL_CONFIG: Accel 16 G range
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RegisterSetBits(Register::ACCEL_CONFIG, ACCEL_CONFIG_BIT::AFS_SEL_16G);
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_px4_accel.set_scale(CONSTANTS_ONE_G / 2048);
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_px4_accel.set_range(16.0f * CONSTANTS_ONE_G);
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if (DataReadyInterruptConfigure()) {
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_data_ready_interrupt_enabled = true;
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// GYRO_CONFIG: Gyro 2000 degrees/second
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RegisterSetBits(Register::GYRO_CONFIG, GYRO_CONFIG_BIT::FS_SEL_2000_DPS);
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_px4_gyro.set_scale(math::radians(1.0f / 16.4f));
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_px4_gyro.set_range(math::radians(2000.0f));
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// backup schedule as a watchdog timeout
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ScheduleDelayed(10_ms);
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// reset done once data is ready
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const bool reset_done = !(RegisterRead(Register::PWR_MGMT_1) & PWR_MGMT_1_BIT::DEVICE_RESET);
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const bool clksel_done = (RegisterRead(Register::PWR_MGMT_1) & PWR_MGMT_1_BIT::CLKSEL_0);
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const bool data_ready = (RegisterRead(Register::INT_STATUS) & INT_STATUS_BIT::DATA_RDY_INT);
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} else {
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_data_ready_interrupt_enabled = false;
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ScheduleOnInterval(_fifo_empty_interval_us, _fifo_empty_interval_us);
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}
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return reset_done && clksel_done && data_ready;
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}
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FIFOReset();
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void MPU6000::ResetFIFO()
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{
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perf_count(_fifo_reset_perf);
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} else {
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PX4_DEBUG("Configure failed, retrying");
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// try again in 10 ms
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ScheduleDelayed(10_ms);
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}
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// FIFO_EN: disable FIFO
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RegisterWrite(Register::FIFO_EN, 0);
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RegisterClearBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN | USER_CTRL_BIT::FIFO_RESET);
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break;
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// USER_CTRL: reset FIFO then re-enable
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RegisterSetBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_RESET);
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up_udelay(1); // bit auto clears after one clock cycle of the internal 20 MHz clock
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RegisterSetBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN);
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case STATE::FIFO_READ: {
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hrt_abstime timestamp_sample = 0;
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// CONFIG:
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RegisterSetBits(Register::CONFIG, CONFIG_BIT::DLPF_CFG_BYPASS_DLPF);
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if (_data_ready_interrupt_enabled && (hrt_elapsed_time(×tamp_sample) < (_fifo_empty_interval_us / 2))) {
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// re-schedule as watchdog timeout
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ScheduleDelayed(10_ms);
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// FIFO_EN: enable both gyro and accel
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_data_ready_count = 0;
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RegisterWrite(Register::FIFO_EN, FIFO_EN_BIT::XG_FIFO_EN | FIFO_EN_BIT::YG_FIFO_EN | FIFO_EN_BIT::ZG_FIFO_EN |
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FIFO_EN_BIT::ACCEL_FIFO_EN);
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up_udelay(10);
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}
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timestamp_sample = _fifo_watermark_interrupt_timestamp;
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uint8_t MPU6000::RegisterRead(Register reg)
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{
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uint8_t cmd[2] {};
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cmd[0] = static_cast<uint8_t>(reg) | DIR_READ;
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transfer(cmd, cmd, sizeof(cmd));
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return cmd[1];
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}
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} else {
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// use the time now roughly corresponding with the last sample we'll pull from the FIFO
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timestamp_sample = hrt_absolute_time();
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}
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void MPU6000::RegisterWrite(Register reg, uint8_t value)
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{
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uint8_t cmd[2] { (uint8_t)reg, value };
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transfer(cmd, cmd, sizeof(cmd));
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}
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const uint16_t fifo_count = FIFOReadCount();
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const uint8_t samples = (fifo_count / sizeof(FIFO::DATA) / SAMPLES_PER_TRANSFER) *
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SAMPLES_PER_TRANSFER; // round down to nearest
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void MPU6000::RegisterSetBits(Register reg, uint8_t setbits)
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{
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uint8_t val = RegisterRead(reg);
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bool failure = false;
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if (!(val & setbits)) {
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val |= setbits;
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RegisterWrite(reg, val);
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if (samples > FIFO_MAX_SAMPLES) {
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// not technically an overflow, but more samples than we expected or can publish
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perf_count(_fifo_overflow_perf);
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failure = true;
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FIFOReset();
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} else if (samples >= SAMPLES_PER_TRANSFER) {
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// require at least SAMPLES_PER_TRANSFER (we want at least 1 new accel sample per transfer)
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if (!FIFORead(timestamp_sample, samples)) {
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failure = true;
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_px4_accel.increase_error_count();
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_px4_gyro.increase_error_count();
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}
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} else if (samples == 0) {
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failure = true;
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perf_count(_fifo_empty_perf);
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}
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if (failure || hrt_elapsed_time(&_last_config_check_timestamp) > 10_ms) {
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// check registers incrementally
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if (RegisterCheck(_register_cfg[_checked_register], true)) {
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_last_config_check_timestamp = timestamp_sample;
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_checked_register = (_checked_register + 1) % size_register_cfg;
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} else {
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// register check failed, force reconfigure
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PX4_DEBUG("Health check failed, reconfiguring");
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_state = STATE::CONFIGURE;
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ScheduleNow();
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}
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} else {
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// periodically update temperature (1 Hz)
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if (hrt_elapsed_time(&_temperature_update_timestamp) > 1_s) {
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UpdateTemperature();
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_temperature_update_timestamp = timestamp_sample;
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}
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}
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}
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break;
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}
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}
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void MPU6000::RegisterClearBits(Register reg, uint8_t clearbits)
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void MPU6000::ConfigureAccel()
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{
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uint8_t val = RegisterRead(reg);
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const uint8_t AFS_SEL = RegisterRead(Register::ACCEL_CONFIG) & (Bit4 | Bit3); // [4:3] AFS_SEL[1:0]
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if (val & clearbits) {
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val &= !clearbits;
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RegisterWrite(reg, val);
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switch (AFS_SEL) {
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case AFS_SEL_2G:
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_px4_accel.set_scale(CONSTANTS_ONE_G / 16384);
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_px4_accel.set_range(2 * CONSTANTS_ONE_G);
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break;
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case AFS_SEL_4G:
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_px4_accel.set_scale(CONSTANTS_ONE_G / 8192);
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_px4_accel.set_range(4 * CONSTANTS_ONE_G);
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break;
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case AFS_SEL_8G:
|
||||
_px4_accel.set_scale(CONSTANTS_ONE_G / 4096);
|
||||
_px4_accel.set_range(8 * CONSTANTS_ONE_G);
|
||||
break;
|
||||
|
||||
case AFS_SEL_16G:
|
||||
_px4_accel.set_scale(CONSTANTS_ONE_G / 2048);
|
||||
_px4_accel.set_range(16 * CONSTANTS_ONE_G);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void MPU6000::ConfigureGyro()
|
||||
{
|
||||
const uint8_t GYRO_FS_SEL = RegisterRead(Register::GYRO_CONFIG) & (Bit4 | Bit3); // [4:3] FS_SEL[1:0]
|
||||
|
||||
switch (GYRO_FS_SEL) {
|
||||
case FS_SEL_250_DPS:
|
||||
_px4_gyro.set_scale(math::radians(1.f / 131.f));
|
||||
_px4_gyro.set_range(math::radians(250.f));
|
||||
break;
|
||||
|
||||
case FS_SEL_500_DPS:
|
||||
_px4_gyro.set_scale(math::radians(1.f / 65.5f));
|
||||
_px4_gyro.set_range(math::radians(500.f));
|
||||
break;
|
||||
|
||||
case FS_SEL_1000_DPS:
|
||||
_px4_gyro.set_scale(math::radians(1.f / 32.8f));
|
||||
_px4_gyro.set_range(math::radians(1000.f));
|
||||
break;
|
||||
|
||||
case FS_SEL_2000_DPS:
|
||||
_px4_gyro.set_scale(math::radians(1.f / 16.4f));
|
||||
_px4_gyro.set_range(math::radians(2000.f));
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void MPU6000::ConfigureSampleRate(int sample_rate)
|
||||
{
|
||||
if (sample_rate == 0) {
|
||||
sample_rate = 1000; // default to 1 kHz
|
||||
}
|
||||
|
||||
// round down to nearest FIFO sample dt * SAMPLES_PER_TRANSFER
|
||||
const float min_interval = SAMPLES_PER_TRANSFER * FIFO_SAMPLE_DT;
|
||||
_fifo_empty_interval_us = math::max(roundf((1e6f / (float)sample_rate) / min_interval) * min_interval, min_interval);
|
||||
|
||||
_fifo_gyro_samples = math::min((float)_fifo_empty_interval_us / (1e6f / GYRO_RATE), (float)FIFO_MAX_SAMPLES);
|
||||
|
||||
// recompute FIFO empty interval (us) with actual gyro sample limit
|
||||
_fifo_empty_interval_us = _fifo_gyro_samples * (1e6f / GYRO_RATE);
|
||||
|
||||
_fifo_accel_samples = math::min(_fifo_empty_interval_us / (1e6f / ACCEL_RATE), (float)FIFO_MAX_SAMPLES);
|
||||
|
||||
_px4_accel.set_update_rate(1e6f / _fifo_empty_interval_us);
|
||||
_px4_gyro.set_update_rate(1e6f / _fifo_empty_interval_us);
|
||||
}
|
||||
|
||||
bool MPU6000::Configure()
|
||||
{
|
||||
bool success = true;
|
||||
|
||||
for (const auto ® : _register_cfg) {
|
||||
if (!RegisterCheck(reg)) {
|
||||
success = false;
|
||||
}
|
||||
}
|
||||
|
||||
ConfigureAccel();
|
||||
ConfigureGyro();
|
||||
|
||||
return success;
|
||||
}
|
||||
|
||||
int MPU6000::DataReadyInterruptCallback(int irq, void *context, void *arg)
|
||||
{
|
||||
MPU6000 *dev = reinterpret_cast<MPU6000 *>(arg);
|
||||
dev->DataReady();
|
||||
static_cast<MPU6000 *>(arg)->DataReady();
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -210,143 +356,226 @@ void MPU6000::DataReady()
|
||||
{
|
||||
perf_count(_drdy_interval_perf);
|
||||
|
||||
_data_ready_count++;
|
||||
|
||||
if (_data_ready_count >= 8) {
|
||||
_time_data_ready = hrt_absolute_time();
|
||||
|
||||
_data_ready_count = 0;
|
||||
|
||||
// make another measurement
|
||||
if (_data_ready_count.fetch_add(1) >= (_fifo_gyro_samples - 1)) {
|
||||
_data_ready_count.store(0);
|
||||
_fifo_watermark_interrupt_timestamp = hrt_absolute_time();
|
||||
_fifo_read_samples.store(_fifo_gyro_samples);
|
||||
ScheduleNow();
|
||||
}
|
||||
}
|
||||
|
||||
void MPU6000::Start()
|
||||
bool MPU6000::DataReadyInterruptConfigure()
|
||||
{
|
||||
ResetFIFO();
|
||||
|
||||
if (_drdy_gpio == 0) {
|
||||
ScheduleOnInterval(FIFO_INTERVAL, FIFO_INTERVAL);
|
||||
|
||||
} else {
|
||||
// Setup data ready on rising edge
|
||||
px4_arch_gpiosetevent(_drdy_gpio, true, false, true, &MPU6000::DataReadyInterruptCallback, this);
|
||||
RegisterSetBits(Register::INT_ENABLE, INT_ENABLE_BIT::DATA_RDY_INT_EN);
|
||||
return false;
|
||||
}
|
||||
|
||||
// Setup data ready on falling edge
|
||||
return px4_arch_gpiosetevent(_drdy_gpio, false, true, true, &MPU6000::DataReadyInterruptCallback, this) == 0;
|
||||
}
|
||||
|
||||
void MPU6000::RunImpl()
|
||||
bool MPU6000::DataReadyInterruptDisable()
|
||||
{
|
||||
// use timestamp from the data ready interrupt if available,
|
||||
// otherwise use the time now roughly corresponding with the last sample we'll pull from the FIFO
|
||||
const hrt_abstime timestamp_sample = (hrt_elapsed_time(&_time_data_ready) < FIFO_INTERVAL) ? _time_data_ready :
|
||||
hrt_absolute_time();
|
||||
if (_drdy_gpio == 0) {
|
||||
return false;
|
||||
}
|
||||
|
||||
return px4_arch_gpiosetevent(_drdy_gpio, false, false, false, nullptr, nullptr) == 0;
|
||||
}
|
||||
|
||||
bool MPU6000::RegisterCheck(const register_config_t ®_cfg, bool notify)
|
||||
{
|
||||
bool success = true;
|
||||
|
||||
const uint8_t reg_value = RegisterRead(reg_cfg.reg);
|
||||
|
||||
if (reg_cfg.set_bits && ((reg_value & reg_cfg.set_bits) != reg_cfg.set_bits)) {
|
||||
PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not set)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.set_bits);
|
||||
success = false;
|
||||
}
|
||||
|
||||
if (reg_cfg.clear_bits && ((reg_value & reg_cfg.clear_bits) != 0)) {
|
||||
PX4_DEBUG("0x%02hhX: 0x%02hhX (0x%02hhX not cleared)", (uint8_t)reg_cfg.reg, reg_value, reg_cfg.clear_bits);
|
||||
success = false;
|
||||
}
|
||||
|
||||
if (!success) {
|
||||
RegisterSetAndClearBits(reg_cfg.reg, reg_cfg.set_bits, reg_cfg.clear_bits);
|
||||
|
||||
if (notify) {
|
||||
perf_count(_bad_register_perf);
|
||||
_px4_accel.increase_error_count();
|
||||
_px4_gyro.increase_error_count();
|
||||
}
|
||||
}
|
||||
|
||||
return success;
|
||||
}
|
||||
|
||||
uint8_t MPU6000::RegisterRead(Register reg)
|
||||
{
|
||||
uint8_t cmd[2] {};
|
||||
cmd[0] = static_cast<uint8_t>(reg) | DIR_READ;
|
||||
set_frequency(SPI_SPEED); // low speed for regular registers
|
||||
transfer(cmd, cmd, sizeof(cmd));
|
||||
return cmd[1];
|
||||
}
|
||||
|
||||
void MPU6000::RegisterWrite(Register reg, uint8_t value)
|
||||
{
|
||||
uint8_t cmd[2] { (uint8_t)reg, value };
|
||||
set_frequency(SPI_SPEED); // low speed for regular registers
|
||||
transfer(cmd, cmd, sizeof(cmd));
|
||||
}
|
||||
|
||||
void MPU6000::RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t clearbits)
|
||||
{
|
||||
const uint8_t orig_val = RegisterRead(reg);
|
||||
uint8_t val = orig_val;
|
||||
|
||||
if (setbits) {
|
||||
val |= setbits;
|
||||
}
|
||||
|
||||
if (clearbits) {
|
||||
val &= ~clearbits;
|
||||
}
|
||||
|
||||
RegisterWrite(reg, val);
|
||||
}
|
||||
|
||||
uint16_t MPU6000::FIFOReadCount()
|
||||
{
|
||||
// read FIFO count
|
||||
uint8_t fifo_count_buf[3] {};
|
||||
fifo_count_buf[0] = static_cast<uint8_t>(Register::FIFO_COUNTH) | DIR_READ;
|
||||
set_frequency(SPI_SPEED_SENSOR);
|
||||
|
||||
if (transfer(fifo_count_buf, fifo_count_buf, sizeof(fifo_count_buf)) != PX4_OK) {
|
||||
return;
|
||||
perf_count(_bad_transfer_perf);
|
||||
return 0;
|
||||
}
|
||||
|
||||
const size_t fifo_count = combine(fifo_count_buf[1], fifo_count_buf[2]);
|
||||
const int samples = (fifo_count / sizeof(FIFO::DATA) / 2) * 2; // round down to nearest 2
|
||||
return combine(fifo_count_buf[1], fifo_count_buf[2]);
|
||||
}
|
||||
|
||||
if (samples < 1) {
|
||||
perf_count(_fifo_empty_perf);
|
||||
return;
|
||||
bool MPU6000::FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples)
|
||||
{
|
||||
perf_begin(_transfer_perf);
|
||||
|
||||
} else if (samples < 8) {
|
||||
// don't transfer fewer than 8 samples (1 accel + 8 gyro)
|
||||
return;
|
||||
|
||||
} else if (samples > 16) {
|
||||
// not technically an overflow, but more samples than we expected
|
||||
perf_count(_fifo_overflow_perf);
|
||||
ResetFIFO();
|
||||
return;
|
||||
}
|
||||
|
||||
// Transfer data
|
||||
FIFOTransferBuffer buffer{};
|
||||
const size_t transfer_size = math::min(samples * sizeof(FIFO::DATA) + 1, FIFO::SIZE);
|
||||
|
||||
perf_begin(_transfer_perf);
|
||||
set_frequency(SPI_SPEED_SENSOR);
|
||||
|
||||
if (transfer((uint8_t *)&buffer, (uint8_t *)&buffer, transfer_size) != PX4_OK) {
|
||||
perf_end(_transfer_perf);
|
||||
return;
|
||||
perf_count(_bad_transfer_perf);
|
||||
return false;
|
||||
}
|
||||
|
||||
perf_end(_transfer_perf);
|
||||
|
||||
ProcessGyro(timestamp_sample, buffer, samples);
|
||||
return ProcessAccel(timestamp_sample, buffer, samples);
|
||||
}
|
||||
|
||||
void MPU6000::FIFOReset()
|
||||
{
|
||||
perf_count(_fifo_reset_perf);
|
||||
|
||||
// FIFO_EN: disable FIFO
|
||||
RegisterWrite(Register::FIFO_EN, 0);
|
||||
|
||||
// USER_CTRL: reset FIFO
|
||||
RegisterSetAndClearBits(Register::USER_CTRL, USER_CTRL_BIT::FIFO_RESET, USER_CTRL_BIT::FIFO_EN);
|
||||
|
||||
// reset while FIFO is disabled
|
||||
_data_ready_count.store(0);
|
||||
_fifo_watermark_interrupt_timestamp = 0;
|
||||
_fifo_read_samples.store(0);
|
||||
|
||||
// FIFO_EN: enable both gyro and accel
|
||||
// USER_CTRL: re-enable FIFO
|
||||
for (const auto &r : _register_cfg) {
|
||||
if ((r.reg == Register::FIFO_EN) || (r.reg == Register::USER_CTRL)) {
|
||||
RegisterSetAndClearBits(r.reg, r.set_bits, r.clear_bits);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
bool MPU6000::ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples)
|
||||
{
|
||||
PX4Accelerometer::FIFOSample accel;
|
||||
accel.timestamp_sample = timestamp_sample;
|
||||
accel.samples = samples / 8;
|
||||
accel.dt = FIFO_INTERVAL / FIFO_ACCEL_SAMPLES;
|
||||
accel.dt = _fifo_empty_interval_us / _fifo_accel_samples;
|
||||
|
||||
bool bad_data = false;
|
||||
|
||||
// FIFO contains 8 duplicated accel samples per gyro sample
|
||||
int accel_samples = 0;
|
||||
|
||||
for (int i = 0; i < samples; i = i + 8) {
|
||||
const FIFO::DATA &fifo_sample = buffer.f[i];
|
||||
int16_t accel_x = combine(fifo_sample.ACCEL_XOUT_H, fifo_sample.ACCEL_XOUT_L);
|
||||
int16_t accel_y = combine(fifo_sample.ACCEL_YOUT_H, fifo_sample.ACCEL_YOUT_L);
|
||||
int16_t accel_z = combine(fifo_sample.ACCEL_ZOUT_H, fifo_sample.ACCEL_ZOUT_L);
|
||||
|
||||
// sensor's frame is +x forward, +y left, +z up
|
||||
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
||||
accel.x[accel_samples] = accel_x;
|
||||
accel.y[accel_samples] = (accel_y == INT16_MIN) ? INT16_MAX : -accel_y;
|
||||
accel.z[accel_samples] = (accel_z == INT16_MIN) ? INT16_MAX : -accel_z;
|
||||
accel_samples++;
|
||||
}
|
||||
|
||||
accel.samples = accel_samples;
|
||||
|
||||
_px4_accel.updateFIFO(accel);
|
||||
|
||||
return !bad_data;
|
||||
}
|
||||
|
||||
void MPU6000::ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples)
|
||||
{
|
||||
PX4Gyroscope::FIFOSample gyro;
|
||||
gyro.timestamp_sample = timestamp_sample;
|
||||
gyro.samples = samples;
|
||||
gyro.dt = FIFO_INTERVAL / FIFO_GYRO_SAMPLES;
|
||||
|
||||
// accel data is duplicated 8 times
|
||||
for (int i = 0; i < accel.samples; i++) {
|
||||
const FIFO::DATA &fifo_sample = buffer.f[i];
|
||||
|
||||
// coordinate convention (x forward, y right, z down)
|
||||
accel.x[i] = combine(fifo_sample.ACCEL_XOUT_H, fifo_sample.ACCEL_XOUT_L);
|
||||
accel.y[i] = -combine(fifo_sample.ACCEL_YOUT_H, fifo_sample.ACCEL_YOUT_L);
|
||||
accel.z[i] = -combine(fifo_sample.ACCEL_ZOUT_H, fifo_sample.ACCEL_ZOUT_L);
|
||||
}
|
||||
gyro.dt = _fifo_empty_interval_us / _fifo_gyro_samples;
|
||||
|
||||
for (int i = 0; i < samples; i++) {
|
||||
const FIFO::DATA &fifo_sample = buffer.f[i];
|
||||
|
||||
// coordinate convention (x forward, y right, z down)
|
||||
gyro.x[i] = combine(fifo_sample.GYRO_XOUT_H, fifo_sample.GYRO_XOUT_L);
|
||||
gyro.y[i] = -combine(fifo_sample.GYRO_YOUT_H, fifo_sample.GYRO_YOUT_L);
|
||||
gyro.z[i] = -combine(fifo_sample.GYRO_ZOUT_H, fifo_sample.GYRO_ZOUT_L);
|
||||
}
|
||||
const int16_t gyro_x = combine(fifo_sample.GYRO_XOUT_H, fifo_sample.GYRO_XOUT_L);
|
||||
const int16_t gyro_y = combine(fifo_sample.GYRO_YOUT_H, fifo_sample.GYRO_YOUT_L);
|
||||
const int16_t gyro_z = combine(fifo_sample.GYRO_ZOUT_H, fifo_sample.GYRO_ZOUT_L);
|
||||
|
||||
|
||||
// Temperature
|
||||
if (hrt_elapsed_time(&_time_last_temperature_update) > 1_s) {
|
||||
// read current temperature
|
||||
uint8_t temperature_buf[3] {};
|
||||
temperature_buf[0] = static_cast<uint8_t>(Register::TEMP_OUT_H) | DIR_READ;
|
||||
|
||||
if (transfer(temperature_buf, temperature_buf, sizeof(temperature_buf)) != PX4_OK) {
|
||||
return;
|
||||
}
|
||||
|
||||
const int16_t TEMP_OUT = combine(temperature_buf[1], temperature_buf[2]);
|
||||
|
||||
static constexpr float RoomTemp_Offset = 25.0f; // Room Temperature Offset 25°C
|
||||
static constexpr float Temp_Sensitivity = 326.8f; // Sensitivity 326.8 LSB/°C
|
||||
|
||||
const float TEMP_degC = ((TEMP_OUT - RoomTemp_Offset) / Temp_Sensitivity) + 25.0f;
|
||||
|
||||
_px4_accel.set_temperature(TEMP_degC);
|
||||
_px4_gyro.set_temperature(TEMP_degC);
|
||||
// sensor's frame is +x forward, +y left, +z up
|
||||
// flip y & z to publish right handed with z down (x forward, y right, z down)
|
||||
gyro.x[i] = gyro_x;
|
||||
gyro.y[i] = (gyro_y == INT16_MIN) ? INT16_MAX : -gyro_y;
|
||||
gyro.z[i] = (gyro_z == INT16_MIN) ? INT16_MAX : -gyro_z;
|
||||
}
|
||||
|
||||
_px4_gyro.updateFIFO(gyro);
|
||||
_px4_accel.updateFIFO(accel);
|
||||
}
|
||||
|
||||
void MPU6000::print_status()
|
||||
void MPU6000::UpdateTemperature()
|
||||
{
|
||||
I2CSPIDriverBase::print_status();
|
||||
perf_print_counter(_transfer_perf);
|
||||
perf_print_counter(_fifo_empty_perf);
|
||||
perf_print_counter(_fifo_overflow_perf);
|
||||
perf_print_counter(_fifo_reset_perf);
|
||||
perf_print_counter(_drdy_interval_perf);
|
||||
// read current temperature
|
||||
uint8_t temperature_buf[3] {};
|
||||
temperature_buf[0] = static_cast<uint8_t>(Register::TEMP_OUT_H) | DIR_READ;
|
||||
set_frequency(SPI_SPEED_SENSOR);
|
||||
|
||||
_px4_accel.print_status();
|
||||
_px4_gyro.print_status();
|
||||
if (transfer(temperature_buf, temperature_buf, sizeof(temperature_buf)) != PX4_OK) {
|
||||
perf_count(_bad_transfer_perf);
|
||||
return;
|
||||
}
|
||||
|
||||
const int16_t TEMP_OUT = combine(temperature_buf[1], temperature_buf[2]);
|
||||
const float TEMP_degC = ((TEMP_OUT - ROOM_TEMPERATURE_OFFSET) / TEMPERATURE_SENSITIVITY) + ROOM_TEMPERATURE_OFFSET;
|
||||
|
||||
if (PX4_ISFINITE(TEMP_degC)) {
|
||||
_px4_accel.set_temperature(TEMP_degC);
|
||||
_px4_gyro.set_temperature(TEMP_degC);
|
||||
}
|
||||
}
|
||||
|
||||
@ -48,9 +48,10 @@
|
||||
#include <lib/drivers/gyroscope/PX4Gyroscope.hpp>
|
||||
#include <lib/ecl/geo/geo.h>
|
||||
#include <lib/perf/perf_counter.h>
|
||||
#include <px4_platform_common/atomic.h>
|
||||
#include <px4_platform_common/i2c_spi_buses.h>
|
||||
|
||||
using InvenSense_MPU6000::Register;
|
||||
using namespace InvenSense_MPU6000;
|
||||
|
||||
class MPU6000 : public device::SPI, public I2CSPIDriver<MPU6000>
|
||||
{
|
||||
@ -75,6 +76,13 @@ protected:
|
||||
void custom_method(const BusCLIArguments &cli) override;
|
||||
void exit_and_cleanup() override;
|
||||
private:
|
||||
// Sensor Configuration
|
||||
static constexpr float FIFO_SAMPLE_DT{125.f};
|
||||
static constexpr uint32_t SAMPLES_PER_TRANSFER{8}; // ensure at least 1 new accel sample per transfer
|
||||
static constexpr float GYRO_RATE{1e6f / FIFO_SAMPLE_DT}; // 8 kHz gyro
|
||||
static constexpr float ACCEL_RATE{GYRO_RATE / 8.f}; // 1 kHz accel
|
||||
|
||||
static constexpr uint32_t FIFO_MAX_SAMPLES{math::min(FIFO::SIZE / sizeof(FIFO::DATA), sizeof(PX4Gyroscope::FIFOSample::x) / sizeof(PX4Gyroscope::FIFOSample::x[0]))};
|
||||
|
||||
// Transfer data
|
||||
struct FIFOTransferBuffer {
|
||||
@ -82,19 +90,41 @@ private:
|
||||
FIFO::DATA f[FIFO_MAX_SAMPLES] {};
|
||||
};
|
||||
// ensure no struct padding
|
||||
static_assert(sizeof(FIFOTransferBuffer) == (sizeof(uint8_t) + FIFO_MAX_SAMPLES *sizeof(FIFO::DATA)));
|
||||
static_assert(sizeof(FIFOTransferBuffer) == (1 + FIFO_MAX_SAMPLES *sizeof(FIFO::DATA)));
|
||||
|
||||
struct register_config_t {
|
||||
Register reg;
|
||||
uint8_t set_bits{0};
|
||||
uint8_t clear_bits{0};
|
||||
};
|
||||
|
||||
int probe() override;
|
||||
|
||||
bool Configure();
|
||||
void ConfigureAccel();
|
||||
void ConfigureGyro();
|
||||
void ConfigureSampleRate(int sample_rate);
|
||||
|
||||
static int DataReadyInterruptCallback(int irq, void *context, void *arg);
|
||||
void DataReady();
|
||||
bool DataReadyInterruptConfigure();
|
||||
bool DataReadyInterruptDisable();
|
||||
|
||||
bool RegisterCheck(const register_config_t ®_cfg, bool notify = false);
|
||||
|
||||
uint8_t RegisterRead(Register reg);
|
||||
void RegisterWrite(Register reg, uint8_t value);
|
||||
void RegisterSetBits(Register reg, uint8_t setbits);
|
||||
void RegisterClearBits(Register reg, uint8_t clearbits);
|
||||
void RegisterSetAndClearBits(Register reg, uint8_t setbits, uint8_t clearbits);
|
||||
void RegisterSetBits(Register reg, uint8_t setbits) { RegisterSetAndClearBits(reg, setbits, 0); }
|
||||
void RegisterClearBits(Register reg, uint8_t clearbits) { RegisterSetAndClearBits(reg, 0, clearbits); }
|
||||
|
||||
void ResetFIFO();
|
||||
uint16_t FIFOReadCount();
|
||||
bool FIFORead(const hrt_abstime ×tamp_sample, uint16_t samples);
|
||||
void FIFOReset();
|
||||
|
||||
bool ProcessAccel(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
|
||||
void ProcessGyro(const hrt_abstime ×tamp_sample, const FIFOTransferBuffer &buffer, const uint8_t samples);
|
||||
void UpdateTemperature();
|
||||
|
||||
const spi_drdy_gpio_t _drdy_gpio;
|
||||
|
||||
@ -102,12 +132,45 @@ private:
|
||||
PX4Gyroscope _px4_gyro;
|
||||
|
||||
perf_counter_t _transfer_perf{perf_alloc(PC_ELAPSED, MODULE_NAME": transfer")};
|
||||
perf_counter_t _fifo_empty_perf{perf_alloc(PC_COUNT, MODULE_NAME": fifo empty")};
|
||||
perf_counter_t _fifo_overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": fifo overflow")};
|
||||
perf_counter_t _fifo_reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": fifo reset")};
|
||||
perf_counter_t _drdy_interval_perf{perf_alloc(PC_INTERVAL, MODULE_NAME": drdy interval")};
|
||||
perf_counter_t _bad_register_perf{perf_alloc(PC_COUNT, MODULE_NAME": bad register")};
|
||||
perf_counter_t _bad_transfer_perf{perf_alloc(PC_COUNT, MODULE_NAME": bad transfer")};
|
||||
perf_counter_t _fifo_empty_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO empty")};
|
||||
perf_counter_t _fifo_overflow_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO overflow")};
|
||||
perf_counter_t _fifo_reset_perf{perf_alloc(PC_COUNT, MODULE_NAME": FIFO reset")};
|
||||
perf_counter_t _drdy_interval_perf{perf_alloc(PC_INTERVAL, MODULE_NAME": DRDY interval")};
|
||||
|
||||
hrt_abstime _time_data_ready{0};
|
||||
hrt_abstime _time_last_temperature_update{0};
|
||||
int _data_ready_count{0};
|
||||
hrt_abstime _reset_timestamp{0};
|
||||
hrt_abstime _last_config_check_timestamp{0};
|
||||
hrt_abstime _fifo_watermark_interrupt_timestamp{0};
|
||||
hrt_abstime _temperature_update_timestamp{0};
|
||||
|
||||
px4::atomic<uint8_t> _data_ready_count{0};
|
||||
px4::atomic<uint8_t> _fifo_read_samples{0};
|
||||
bool _data_ready_interrupt_enabled{false};
|
||||
|
||||
enum class STATE : uint8_t {
|
||||
RESET,
|
||||
WAIT_FOR_RESET,
|
||||
CONFIGURE,
|
||||
FIFO_READ,
|
||||
};
|
||||
|
||||
STATE _state{STATE::RESET};
|
||||
|
||||
uint16_t _fifo_empty_interval_us{1000}; // default 1000 us / 1000 Hz transfer interval
|
||||
uint8_t _fifo_gyro_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / GYRO_RATE))};
|
||||
uint8_t _fifo_accel_samples{static_cast<uint8_t>(_fifo_empty_interval_us / (1000000 / ACCEL_RATE))};
|
||||
|
||||
uint8_t _checked_register{0};
|
||||
static constexpr uint8_t size_register_cfg{7};
|
||||
register_config_t _register_cfg[size_register_cfg] {
|
||||
// Register | Set bits, Clear bits
|
||||
{ Register::PWR_MGMT_1, PWR_MGMT_1_BIT::CLKSEL_0, PWR_MGMT_1_BIT::DEVICE_RESET | PWR_MGMT_1_BIT::SLEEP },
|
||||
{ Register::ACCEL_CONFIG, ACCEL_CONFIG_BIT::AFS_SEL_16G, 0 },
|
||||
{ Register::GYRO_CONFIG, GYRO_CONFIG_BIT::FS_SEL_2000_DPS, 0 },
|
||||
{ Register::USER_CTRL, USER_CTRL_BIT::FIFO_EN | USER_CTRL_BIT::I2C_IF_DIS, USER_CTRL_BIT::I2C_MST_EN},
|
||||
{ Register::FIFO_EN, FIFO_EN_BIT::XG_FIFO_EN | FIFO_EN_BIT::YG_FIFO_EN | FIFO_EN_BIT::ZG_FIFO_EN | FIFO_EN_BIT::ACCEL_FIFO_EN, FIFO_EN_BIT::TEMP_FIFO_EN },
|
||||
{ Register::INT_PIN_CFG, INT_PIN_CFG_BIT::INT_LEVEL, 0 },
|
||||
{ Register::INT_ENABLE, INT_ENABLE_BIT::DATA_RDY_INT_EN, 0 }
|
||||
};
|
||||
};
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user