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NuttX stm32f7 fully re-enable dcache with write back (#12435)

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- fixes https://github.com/PX4/Firmware/issues/12216
 - includes latest PX4/NuttX and apps update 7.29+
This commit is contained in:
Daniel Agar
2019-07-10 19:08:12 -04:00
committed by GitHub
parent dc10a68539
commit d4cd1d0d2e
33 changed files with 14 additions and 564 deletions
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src/drivers/px4io/px4io_serial.h
+1 -1
View File
@@ -252,7 +252,7 @@ private:
/**
* IO Buffer storage
*/
static uint8_t _io_buffer_storage[];
static uint8_t _io_buffer_storage[] __attribute__((aligned(ARMV7M_DCACHE_LINESIZE)));
};
#else
src/drivers/px4io/px4io_serial_f7.cpp
+7 -9
View File
@@ -57,12 +57,10 @@
#define rCR3 REG(STM32_USART_CR3_OFFSET)
#define rGTPR REG(STM32_USART_GTPR_OFFSET)
#define CACHE_LINE_SIZE 32
#define DMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1)
#define DMA_ALIGN_UP(n) (((n) + DMA_BUFFER_MASK) & ~DMA_BUFFER_MASK)
#define ROUND_UP_TO_POW2_CT(size, alignment) (((uintptr_t)((size) + ((alignment) - 1u))) & (~((uintptr_t)((alignment) - 1u))))
#define ALIGNED_IO_BUFFER_SIZE ROUND_UP_TO_POW2_CT(sizeof(IOPacket), CACHE_LINE_SIZE)
uint8_t PX4IO_serial_f7::_io_buffer_storage[ALIGNED_IO_BUFFER_SIZE + CACHE_LINE_SIZE];
uint8_t PX4IO_serial_f7::_io_buffer_storage[DMA_ALIGN_UP(sizeof(IOPacket))];
PX4IO_serial_f7::PX4IO_serial_f7() :
_tx_dma(nullptr),
@@ -119,9 +117,9 @@ int
PX4IO_serial_f7::init()
{
/* initialize base implementation */
int r;
int r = PX4IO_serial::init((IOPacket *)&_io_buffer_storage[0]);
if ((r = PX4IO_serial::init((IOPacket *)ROUND_UP_TO_POW2_CT((uintptr_t)_io_buffer_storage, CACHE_LINE_SIZE))) != 0) {
if (r != 0) {
return r;
}
@@ -289,7 +287,7 @@ PX4IO_serial_f7::_bus_exchange(IOPacket *_packet)
/* Clean _current_packet, so DMA can see the data */
up_clean_dcache((uintptr_t)_current_packet,
(uintptr_t)_current_packet + ALIGNED_IO_BUFFER_SIZE);
(uintptr_t)_current_packet + DMA_ALIGN_UP(sizeof(IOPacket)));
/* start TX DMA - no callback if we also expect a reply */
/* DMA setup time ~3µs */
@@ -459,7 +457,7 @@ PX4IO_serial_f7::_do_interrupt()
if (_rx_dma_status == _dma_status_waiting) {
/* Invalidate _current_packet, so we get fresh data from RAM */
up_invalidate_dcache((uintptr_t)_current_packet,
(uintptr_t)_current_packet + ALIGNED_IO_BUFFER_SIZE);
(uintptr_t)_current_packet + DMA_ALIGN_UP(sizeof(IOPacket)));
/* verify that the received packet is complete */
size_t length = sizeof(*_current_packet) - stm32_dmaresidual(_rx_dma);