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NuttX stm32f7 fully re-enable dcache with write back (#12435)
- fixes https://github.com/PX4/Firmware/issues/12216 - includes latest PX4/NuttX and apps update 7.29+
This commit is contained in:
Daniel Agar
@@ -39,7 +39,6 @@ if ((${PX4_PLATFORM} MATCHES "nuttx") AND NOT ${PX4_BOARD} MATCHES "io")
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board_dma_alloc.c
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board_fat_dma_alloc.c
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board_gpio_init.c
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board_dcache_control.c
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)
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if (${CONFIG_ARCH_CHIP} MATCHES "kinetis")
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@@ -1,178 +0,0 @@
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/****************************************************************************
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*
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* Copyright (C) 2019 PX4 Development Team. All rights reserved.
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* Author: @author David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name PX4 nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/**
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* @file board_dcache_control.c
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* Support for parameter based control of dcache for the
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* ARM 1259864 Data corruption eratta
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*/
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#include <px4_config.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "nvic.h"
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#include <nuttx/cache.h>
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#include "up_arch.h"
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#include <parameters/param.h>
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#define CPUID_REVISION_SHIFT 0
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#define CPUID_REVISION_MASK (0xf << CPUID_REVISION_SHIFT)
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#define CPUID_REVISION(cpuid) (((cpuid) & CPUID_REVISION_MASK) >> CPUID_REVISION_SHIFT)
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#define CPUID_PARTNO_SHIFT 4
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#define CPUID_PARTNO_MASK (0xfff << CPUID_PARTNO_SHIFT)
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#define CPUID_PARTNO(cpuid) (((cpuid) & CPUID_PARTNO_MASK) >> CPUID_PARTNO_SHIFT)
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# define CPUID_CORTEX_M7 0xc27
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#define CPUID_VARIANT_SHIFT 20
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#define CPUID_VARIANT_MASK (0xf << CPUID_VARIANT_SHIFT)
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#define CPUID_VARIANT(cpuid) (((cpuid) & CPUID_VARIANT_MASK) >> CPUID_VARIANT_SHIFT)
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#define CPUID_IMPLEMENTER_SHIFT 24
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#define CPUID_IMPLEMENTER_MASK (0xff << CPUID_IMPLEMENTER_SHIFT)
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#define CPUID_IMPLEMENTER(cpuid) (((cpuid) & CPUID_IMPLEMENTER_MASK) >> CPUID_IMPLEMENTER_SHIFT)
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#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
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/************************************************************************************
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* Name: board_configure_dcache
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*
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* Description:
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* Called at various points in start up to disable the dcache if the
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* 1259864 Data corruption in a sequence of Write-Through stores and loads
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* errata is preset.
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*
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* Input Parameters:
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* stage - 0 - early init no OS;
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* 1 - OS and file system are runnting;
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*
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* Returned Value:
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************************************************************************************/
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void board_configure_dcache(int stage)
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{
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/* 1259864 Data corruption in a sequence of Write-Through stores and loads
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* Fault Status: Present in r0p1, r0p2, r1p0 and r1p1. Fixed in r1p2
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*/
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uint32_t cpuid = getreg32(NVIC_CPUID_BASE);
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bool erratta = CPUID_PARTNO(cpuid) == CPUID_CORTEX_M7 && (CPUID_VARIANT(cpuid) == 0 || (CPUID_VARIANT(cpuid) == 1
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&& CPUID_REVISION(cpuid) < 2));
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/* On boot we should default to disabled on effected HW */
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if (erratta && stage == 0) {
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up_disable_dcache();
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return;
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}
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/* Based on a param We can enable the dcache */
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if (stage != 0) {
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int32_t dcache = board_get_dcache_setting();
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switch (dcache) {
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default:
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case 0:
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erratta ? up_disable_dcache() : up_enable_dcache();
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break;
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case 1:
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up_disable_dcache();
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break;
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case 2:
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up_enable_dcache();
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break;
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return;
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}
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}
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}
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/************************************************************************************
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* Name: board_dcache_info
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*
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* Description:
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* Called to retrieve dcache info and optionally set dcache to on or off.
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*
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* Input Parameters:
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* action - -1 Provide info only.
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* pmesg - if non null return the chipid revision and patch level
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* will indicate if the dcache eratta is present.
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* state - if non null return the state of the dcache
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* true on, false is off.
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*
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* Returned Value:
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* 0 - success
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*
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************************************************************************************/
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int board_dcache_info(int action, char **pmesg, bool *pstate)
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{
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uint32_t cpuid = getreg32(NVIC_CPUID_BASE);
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static char mesg[] = "r?p? has dcache eratta!";
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bool erratta = (CPUID_PARTNO(cpuid) == CPUID_CORTEX_M7 && (CPUID_VARIANT(cpuid) == 0 || (CPUID_VARIANT(cpuid) == 1
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&& CPUID_REVISION(cpuid) < 2)));
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mesg[1] = '0' + CPUID_VARIANT(cpuid);
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mesg[3] = '0' + CPUID_REVISION(cpuid);
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if (!erratta) {
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mesg[5] = 'O';
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mesg[6] = 'K';
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mesg[7] = '\0';
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}
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if (action == 0) {
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up_disable_dcache();
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}
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if (action == 1) {
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up_enable_dcache();
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}
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if (pmesg) {
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*pmesg = mesg;
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}
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if (pstate) {
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*pstate = getreg32(NVIC_CFGCON) & NVIC_CFGCON_DC ? true : false;
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}
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return 0;
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}
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#endif
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@@ -117,67 +117,3 @@ __EXPORT void board_gpio_init(const uint32_t list[], int count);
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************************************************************************************/
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__EXPORT int board_determine_hw_info(void);
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#if defined(CONFIG_ARMV7M_DCACHE) && defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
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/************************************************************************************
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* Name: board_configure_dcache
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*
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* Description:
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* Called at various points in start up to disable the dcache if the
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* 1259864 Data corruption in a sequence of Write-Through stores and loads
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* errata is preset.
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*
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* Input Parameters:
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* stage - 0 - early init no OS;
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* 1 - OS and file system are runnting;
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*
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* Returned Value:
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* None
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************************************************************************************/
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void board_configure_dcache(int stage);
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/************************************************************************************
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* Name: board_get_dcache_setting
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*
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* Description:
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* Called to retrieve the parameter setting to enable/disable
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* the dcache.
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*
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* Input Parameters:
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* None
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*
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* Returned Value:
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* -1 - Not set - if Eratta exits turn dcache off else leave it on
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* 0 - if Eratta exits turn dcache off else leave it on
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* 1 - Force it off
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* 2 - Force it on
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*
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************************************************************************************/
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int board_get_dcache_setting(void);
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/************************************************************************************
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* Name: board_dcache_info
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*
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* Description:
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* Called to retrieve dcache info and optionally set dcache to on or off.
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*
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* Input Parameters:
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* action - -1 Provide info only.
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* pmesg - if non null return the chipid revision and patch level
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* will indicate if the dcache eratta is present.
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* state - if non null return the state of the dcache
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* true on, false is off.
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*
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* Returned Value:
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* 0 - success
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*
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************************************************************************************/
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int board_dcache_info(int action, char **pmesg, bool *pstate);
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#else
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# define board_configure_dcache(stage)
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# define board_get_dcache_setting()
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# define board_dcache_info(action, pmesg, pstate)
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#endif
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